TWI751659B - Power supply device for increasing switch life - Google Patents

Abstract

A power supply device for increasing the switch life includes a transformer, an output stage circuit, a first resistor, a second resistor, a power switch element, a PWM (Pulse Width Modulation) IC (Integrated Circuit), and a control circuit. The transformer includes a main coil and a secondary coil. The main coil receives an input voltage. The output stage circuit generates an output voltage. The power switch element receives a PWM voltage through the first resistor. The power switch element selectively couples the main coil through the second resistor to a ground voltage according to the PWM voltage. The control circuit includes a subtractor, a first switch element, and a second switch element. The control circuit controls the switching discharge time of the power switch element according to a constant voltage and the PWM voltage.

Description

Power Supply for Extending Switch Life

The present invention relates to a power supply, in particular to a power supply which can prolong the life of a switch.

In conventional power supplies, the power switches are usually designed to have extremely short switching discharge times to support high frequency operation of the power supplies. However, because the switching speed of the power switch is too fast, it is easy to shorten the life of its components and cause problems such as electromagnetic interference. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the previous technology.

In a preferred embodiment, the present invention provides a power supply for extending switch life, comprising: a transformer including a main coil and a secondary coil, wherein the main coil is used for receiving an input potential, and the secondary coil is used for receiving an input potential. It is used to generate an induced potential; an output stage circuit generates an output potential according to the induced potential; a first resistor; a second resistor; a power switch, which receives a pulse width modulation through the first resistor variable potential, wherein the power switch selectively couples the main coil to a ground potential through the second resistor according to the pulse width modulation potential; a pulse width modulation integrated circuit generates the a pulse width modulated potential and a constant potential; and a control circuit including a subtractor, a first switch, and a second switch, wherein the control circuit is based on the constant potential and the pulse width modulated potential bit to control the switching discharge time of one of the power switches.

In order to make the objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are given in the following, and are described in detail as follows in conjunction with the accompanying drawings.

Certain terms are used throughout the specification and claims to refer to particular elements. It should be understood by those skilled in the art that hardware manufacturers may refer to the same element by different nouns. This specification and the scope of the patent application do not use the difference in name as a way to distinguish elements, but use the difference in function of the elements as a criterion for distinguishing. The words "including" and "including" mentioned in the entire specification and the scope of the patent application are open-ended terms, so they should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. Furthermore, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting means. Second device.

FIG. 1 is a schematic diagram of a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in FIG. 1 , the power supply 100 includes: a transformer 110 , an output stage circuit 120 , a first resistor R1 , a second resistor R2 , a power switch 130 , and a PWM integrated circuit circuit 140 , and a control circuit 150 . It should be noted that, although not shown in FIG. 1, the power supply 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The transformer 110 includes a primary coil 111 and a secondary coil 112 , wherein the primary coil 111 can be located on one side of the transformer 110 , and the secondary coil 112 can be located on the opposite side of the transformer 110 . The primary coil 111 can receive an input potential VIN, and in response to the input potential VIN, the secondary coil 112 can generate an induced potential VS. The input potential VIN can come from an external input power source. For example, the input potential VIN can be approximately a DC potential or an AC potential, and its RMS value can be from 90V to 264V, but it is not limited thereto. The output stage circuit 120 can generate an output potential VOUT according to the induced potential VS. For example, the output potential VOUT can be a DC potential, and its potential level can be from 18V to 22V, but it is not limited thereto. The power switch 130 can receive a PWM potential VM through the first resistor R1, wherein the power switch 130 can selectively couple the main coil 111 through the second resistor R2 according to the PWM potential VM Connect to a ground potential VSS (eg 0V). For example, if the PWM potential VM is at a high logic level (ie, logic "1"), the power switch 130 couples the main coil 111 to the ground potential VSS through the second resistor R2 (ie, The power switch 130 can be approximated as a short-circuit path); on the contrary, if the PWM potential VM is at a low logic level (ie, logic "0"), the power switch 130 will not pass the main coil 111 through the first The two resistors R2 are coupled to the ground potential VSS (ie, the power switch 130 can approximate an open path). The PWM integrated circuit 140 can generate the PWM potential VM and a constant potential VK. The control circuit 150 includes a subtractor 152, a first switch 154, and a second switch 156, wherein the control circuit 150 can control one of the power switches 130 to switch according to the constant potential VK and the pulse width modulated potential VM discharge time. By adjusting the switching discharge time of the power switch 130, the discharge operation of the power switch 130 can be properly buffered. Therefore, the service life of the power switch 130 of the power supply 100 can be effectively extended.

The following embodiments will introduce the detailed structure and operation of the power supply 100 . It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 is a schematic diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has an input node NIN and an output node NOUT, and includes a transformer 210, an output stage circuit 220, a first resistor R1, a second resistor R2, A power switch 230 , a pulse width modulation integrated circuit 240 , and a control circuit 250 . The input node NIN of the power supply 200 can receive an input potential VIN from an external input power source, and the output node NOUT of the power supply 200 can output an output potential VOUT to an electronic device (not shown).

The transformer 210 includes a main coil 211 and a secondary coil 212 , wherein the transformer 210 can have a built-in magnetizing inductor LM. The magnetizing inductor LM may be an inherent component that is incidental to the manufacture of the transformer 210, and is not an external independent component. Both the main coil 211 and the magnetizing inductor LM can be located on the same side of the transformer 210 , and the secondary coil 212 can be located on the opposite side of the transformer 210 . The main coil 211 has a first end and a second end, wherein the first end of the main coil 211 is coupled to the input node NIN, and the second end of the main coil 211 is coupled to a first node N1. The magnetizing inductor LM has a first end and a second end, wherein the first end of the magnetizing inductor LM is coupled to the input node NIN, and the second end of the magnetizing inductor LM is coupled to the first node N1. The secondary coil 212 has a first end and a second end, wherein the first end of the secondary coil 212 is coupled to a second node N2 to output an induced potential VS, and the second end of the secondary coil 212 is coupled to A common node NCM.

The input stage circuit 220 includes a diode D1 and a first capacitor C1. The diode D1 has an anode and a cathode, wherein the anode of the diode D1 is coupled to the second node N2 to receive the induced potential VS, and the cathode of the diode D1 is coupled to the output node NOUT. The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the output node NOUT, and the second terminal of the first capacitor C1 is coupled to the common node NCM.

The power switch 230 includes a first transistor M1. The first transistor M1 can be an N-type MOSFET. The first transistor M1 has a control terminal (eg, a gate), a first terminal (eg, a source), and a second terminal (eg, a drain), wherein the control of the first transistor M1 The terminal is coupled to a third node N3, the first terminal of the first transistor M1 is coupled to a fourth node N4, and the second terminal of the first transistor M1 is coupled to the first node N1. A first parasitic capacitor CP1 can be built in the first transistor M1. The first parasitic capacitor CP1 has a first end and a second end, wherein the first end of the first parasitic capacitor CP1 is coupled to the third node N3, and the second end of the first parasitic capacitor CP1 is coupled to the ground Potential VSS. It must be understood that the total parasitic capacitance between the control terminal and the first terminal of the first transistor M1 can be modeled as the aforementioned first parasitic capacitor CP1, which is not an external independent component.

The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is used for receiving a pulse width modulation potential VM, and the second end of the first resistor R1 is used for receiving a pulse width modulation potential VM. is coupled to the third node N3. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the fourth node N4, and the second end of the second resistor R2 is coupled to a Ground potential VSS (eg 0V). It must be noted that because the resistance value of the second resistor R2 is not large, the first parasitic capacitor CP1 of the first transistor M1 can be approximately coupled between the third node N3 and the ground potential VSS. In other embodiments, the first parasitic capacitor CP1 of the first transistor M1 can also be coupled between the third node N3 and the fourth node N4 instead.

The PWM integrated circuit 240 can generate the PWM potential VM and a constant potential VK, wherein the constant potential VK can be higher than or equal to the PWM potential VM. In addition, the PWM potential VM can be maintained at a fixed potential when the power supply 200 is initialized, and can provide a periodic clock waveform after the power supply 200 enters a normal use stage.

The control circuit 250 includes a subtractor 252, a first switch 254, a second switch 256, a second capacitor C2, a third resistor R3, a fourth resistor R4, and an inductor L1.

The subtractor 252 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the subtractor 252 is used for receiving the constant potential VK, and the second input terminal of the subtractor 252 is used for receiving The PWM potential VM, and the output terminal of the subtractor 252 is used to output a difference potential VD, which is equal to the constant potential VK minus the PWM potential VM. That is, the operation of the subtractor 252 can be described as the following equation (1):

……………………………………(1) 其中「VD」代表差值電位VD，「VK」代表恆定電位VK，而「VM」代表脈衝寬度調變電位VM。

………………………………(1) “VD” represents the difference potential VD, “VK” represents the constant potential VK, and “VM” represents the pulse width modulation potential VM.

The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is used for receiving the difference potential VD, and the second terminal of the second capacitor C2 is coupled to a fifth node N5. The third resistor R3 has a first end and a second end, wherein the first end of the third resistor R3 is coupled to the fifth node N5, and the second end of the third resistor R3 is coupled to a The sixth node N6.

The first switch 254 includes a second transistor M2. The second transistor M2 can be an N-type MOSFET. The second transistor M2 has a control terminal (eg, a gate), a first terminal (eg, a source), and a second terminal (eg, a drain), wherein the control of the second transistor M2 The terminal is coupled to the sixth node N6, the first terminal of the second transistor M2 is coupled to a seventh node N7, and the second terminal of the second transistor M2 is coupled to the third node N3. A second parasitic capacitor CP2 can be built in the second transistor M2. The second parasitic capacitor CP2 has a first terminal and a second terminal, wherein the first terminal of the second parasitic capacitor CP2 is coupled to the third node N3, and the second terminal of the second parasitic capacitor CP2 is coupled to the third node N3. Seven node N7. It must be understood that the total parasitic capacitance between the second terminal and the first terminal of the second transistor M2 can be modeled as the aforementioned second parasitic capacitor CP2, which is not an external independent component.

The fourth resistor R4 has a first end and a second end, wherein the first end of the fourth resistor R4 is coupled to the fifth node N5, and the second end of the fourth resistor R4 is coupled to a The eighth node N8. The inductor L1 has a first end and a second end, wherein the first end of the inductor L1 is coupled to the seventh node N7, and the second end of the inductor L1 is coupled to the ground potential VSS. In some embodiments, the resistance value of the third resistor R3 is less than or equal to half of the resistance value of the fourth resistor R4.

The second switch 256 includes a third transistor M3. The third transistor M3 can be an N-type MOSFET. The third transistor M3 has a control terminal (eg, a gate), a first terminal (eg, a source), and a second terminal (eg, a drain), wherein the control of the third transistor M3 The terminal is coupled to the eighth node N8, the first terminal of the third transistor M3 is coupled to the seventh node N7, and the second terminal of the third transistor M3 is coupled to the third node N3. A third parasitic capacitor CP3 can be built in the third transistor M3. The third parasitic capacitor CP3 has a first terminal and a second terminal, wherein the first terminal of the third parasitic capacitor CP3 is coupled to the third node N3, and the second terminal of the third parasitic capacitor CP3 is coupled to the third node N3. Seven node N7. It must be understood that the total parasitic capacitance between the second terminal and the first terminal of the third transistor M3 can be modeled as the aforementioned third parasitic capacitor CP3, which is not an external independent component.

FIG. 3 shows a potential waveform diagram of the power supply 200 according to an embodiment of the present invention, wherein the horizontal axis represents time, and the vertical axis represents the potential level of a control potential VC at the third node N3. In response to the change of the control potential VC, the power supply 200 can operate in a first stage T1, a second stage T2, a third stage T3, a fourth stage T4, and a fifth stage T5 in sequence. The principle can be as follows: as described below.

During the first phase T1, the PWM potential VM is at a high logic level, and the control potential VC is at the highest potential level. At this time, the first transistor M1 is fully turned on, and the magnetizing inductor LM is storing electromagnetic energy.

During the second phase T2, the PWM potential VM is ready to be switched from a high logic level to a low logic level, and the control potential VC starts to decrease gradually from the highest potential level. At this time, since the PWM potential VM is relatively high, the difference potential VD of the subtractor 252 is not enough to enable the second transistor M2 and the third transistor M3. Therefore, the first parasitic capacitor CP1 of the first transistor M1 is mainly discharged through the first resistor R1.

During the third phase T3, both the PWM potential VM and the control potential VC continue to decrease. At this time, since the PWM potential VM is relatively middle, the difference potential VD of the subtractor 252 can enable the second transistor M2, but is still insufficient to enable the third transistor M3. Therefore, the first parasitic capacitor CP1 of the first transistor M1 is mainly discharged through a first buffer circuit 460 . FIG. 4 is a schematic diagram of the first buffer circuit 460 according to an embodiment of the present invention. As shown in FIG. 4, the first buffer circuit 460 is composed of a first on-resistor RM2, a second parasitic capacitor CP2, and an inductor L1, wherein the first on-resistor RM2 can represent the second transistor M2 The equivalent resistance value produced when enabled.

During the fourth phase T4, both the PWM potential VM and the control potential VC are still continuously decreasing. At this time, since the PWM potential VM is relatively low, the difference potential VD of the subtractor 252 can enable the second transistor M2 and the third transistor M3 at the same time. Therefore, the first parasitic capacitor CP1 of the first transistor M1 is mainly discharged through a second buffer circuit 570 . FIG. 5 is a schematic diagram illustrating a second buffer circuit 570 according to an embodiment of the present invention. As shown in FIG. 5, the second buffer circuit 570 is composed of a first on-resistor RM2, a second on-resistor RM3, a second parasitic capacitor CP2, a third parasitic capacitor CP3, and an inductor L1, wherein The second on-resistor RM3 can represent an equivalent resistance value generated when the third transistor M3 is enabled.

During the fifth stage T5, the PWM potential VM has dropped to a low logic level, and the control potential VC has the lowest potential level. At this time, the first transistor M1 is completely turned off, and both the second transistor M2 and the third transistor M3 are disabled at the same time. Under this design, the power switch 230 of the power supply 200 can perform at least three stages of buffer discharge operations (eg, the second stage T2 , the third stage T3 , and the fourth stage T4 ), which helps to prolong power switching the service life of the device 230.

In some embodiments, the component parameters of the power supply 200 may be as follows. The capacitance value of the first capacitor C1 may be between 544 μF and 816 μF, preferably about 680 μF. The capacitance value of the second capacitor C2 may be between 9nF and 11nF, preferably about 10nF. The capacitance value of the first parasitic capacitor CP1 may be between 640pF and 960pF, preferably about 800pF. The capacitance value of the second parasitic capacitor CP2 may be between 120pF and 180pF, preferably about 150pF. The capacitance value of the third parasitic capacitor CP3 may be between 120pF and 180pF, preferably about 150pF. The inductance value of the inductor L1 may be between 1.8 μH and 2.2 μH, preferably about 2 μH. The inductance value of the magnetizing inductor LM may be between 240 μH and 360 μH, preferably about 300 μH. The resistance value of the first resistor R1 may be between 9.9Ω and 10.1Ω, preferably about 10Ω. The resistance value of the second resistor R2 can be between 0.9KΩ and 1.1KΩ, preferably about 1KΩ. The resistance value of the third resistor R3 may be between 14.85Ω and 15.15Ω, preferably about 15Ω. The resistance value of the fourth resistor R4 may be between 39.6Ω and 40.4Ω, preferably about 40Ω. The resistance value of the first on-resistor RM2 may be between 79.2mΩ and 80.8mΩ, preferably about 80mΩ. The resistance value of the second on-resistor RM3 may be between 79.2mΩ and 80.8mΩ, preferably about 80mΩ. The turns ratio of the primary coil 211 to the secondary coil 212 may be between 1 and 100, preferably about 10. The constant potential VK may be approximately equal to 15V. The switching frequency of the PWM potential VM may be approximately 65kHz, and the high logic level thereof may be approximately equal to 15V. The above parameter ranges are obtained according to multiple experimental results, which help maximize the switching life of the power supply 200 .

The present invention provides a novel power supply including a control circuit to adjust the switching discharge time of the power switch. According to the actual measurement results, the use of the above-designed power supply can effectively prolong the service life of the power switch, so it is very suitable for use in various types of devices.

It should be noted that the potential, current, resistance value, inductance value, capacitance value and other component parameters mentioned above are not limitations of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the states shown in FIGS. 1-5. The present invention may include only any one or more of the features of any one or more of the embodiments of Figures 1-5. In other words, not all the features shown in the figures need to be simultaneously implemented in the power supply of the present invention. Although the embodiments of the present invention use MOSFETs as an example, the present invention is not limited to this, and those skilled in the art can use other types of transistors, such as junction field effect transistors, or fins type field effect transistor, etc., without affecting the effect of the present invention.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., do not have a sequential relationship with each other, and are only used to mark and distinguish two identical different elements of the name.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100,200: Power Supply 110, 210: Transformers 111, 211: Main coil 112,212: Secondary coil 120,220: Output stage circuit 130,230: Power switch 140, 240: Pulse Width Modulation Integrated Circuits 150,250: Control circuit 152,252: Subtractor 154,254: First switcher 156,256: Second switcher 460: First buffer circuit 570: Second buffer circuit C1: first capacitor C2: Second capacitor CP1: first parasitic capacitor CP2: Second Parasitic Capacitor CP3: Third Parasitic Capacitor D1: Diode L1: Inductor LM: magnetizing inductor M1: first transistor M2: second transistor M3: The third transistor N1: the first node N2: second node N3: The third node N4: Fourth Node N5: Fifth node N6: sixth node N7: seventh node N8: Eighth Node NCM: Common Node NIN: input node NOUT: output node R1: first resistor R2: Second resistor R3: Third resistor R4: Fourth resistor RM2: first on-resistor RM3: Second on-resistor T1: Phase 1 T2: Phase 2 T3: Stage Three T4: Stage Four T5: Stage 5 VC: control potential VD: difference potential VIN: input potential VK: constant potential VM: PWM potential VOUT: output potential VS: induced potential VSS: ground potential

FIG. 1 is a schematic diagram of a power supply according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing a power supply according to an embodiment of the present invention. FIG. 3 shows a potential waveform diagram of a power supply according to an embodiment of the present invention. FIG. 4 is a schematic diagram illustrating a first buffer circuit according to an embodiment of the present invention. FIG. 5 is a schematic diagram illustrating a second buffer circuit according to an embodiment of the present invention.

100: Power supply

110: Transformer

111: main coil

112: Secondary coil

120: Output stage circuit

130: Power switch

140: Pulse width modulation integrated circuit

150: Control circuit

152: Subtractor

154: First Switcher

156: Second switcher

R1: first resistor

R2: Second resistor

VIN: input potential

VK: constant potential

VM: PWM potential

VOUT: output potential

VS: induced potential

VSS: ground potential

Claims (7)

A power supply for prolonging switch life, comprising: a transformer including a main coil and a secondary coil, wherein the main coil is used for receiving an input potential, and the secondary coil is used for generating an induced potential; an output stage The circuit generates an output potential according to the induced potential; a first resistor; a second resistor; a power switch, which receives a pulse width modulation potential through the first resistor, wherein the power switch is The main coil is selectively coupled to a ground potential through the second resistor according to the PWM potential; a PWM integrated circuit generates the PWM potential and a constant potential ; and a control circuit including a subtractor, a first switch, and a second switch, wherein the control circuit controls a switch of the power switch according to the constant potential and the PWM potential discharge time; wherein the transformer has a built-in magnetizing inductor, the main coil has a first end and a second end, the first end of the main coil is coupled to an input node to receive the input potential, the main coil has The second end of the coil is coupled to a first node, the magnetizing inductor has a first end and a second end, the first end of the magnetizing inductor is coupled to the input node, the magnetizing inductor the second end is coupled to the first node, the secondary coil has a first end and a second end, the first end of the secondary coil is coupled to a second node to output the induced potential, and the second end of the secondary coil is coupled to a common node; The output stage circuit includes: a diode with an anode and a cathode, wherein the anode of the diode is coupled to the second node to receive the induced potential, and the cathode of the diode is coupled to an output node to output the output potential; and a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the output node, and the first capacitor The second end of a capacitor is coupled to the common node; wherein the power switch includes: a first transistor having a control end, a first end, and a second end, wherein the first transistor The control terminal is coupled to a third node, the first terminal of the first transistor is coupled to a fourth node, and the second terminal of the first transistor is coupled to the first node; wherein a first parasitic capacitor is built in the first transistor, the first parasitic capacitor has a first terminal and a second terminal, and the first terminal of the first parasitic capacitor is coupled to the third node , and the second end of the first parasitic capacitor is coupled to the ground potential. The power supply of claim 1, wherein the first resistor has a first end and a second end, the first end of the first resistor is used for receiving the PWM potential, the The second end of the first resistor is coupled to the third node, the second resistor has a first end and a second end, and the first end of the second resistor is coupled to the fourth node node, and the second end of the second resistor is coupled to the ground potential. The power supply of claim 1, wherein the subtractor has a first input terminal, a second input terminal, and an output terminal, the first input terminal of the subtractor is used for receiving the constant potential, the The second input terminal of the subtractor is used for receiving the PWM potential, and the output terminal of the subtractor is used for outputting a difference potential, which is equal to the constant potential minus the PWM voltage bit. The power supply of claim 3, wherein the control circuit further comprises: a second capacitor having a first end and a second end, wherein the first end of the second capacitor is used for receiving the difference value potential, and the second end of the second capacitor is coupled to a fifth node; and a third resistor having a first end and a second end, wherein the first end of the third resistor The terminal is coupled to the fifth node, and the second terminal of the third resistor is coupled to a sixth node. The power supply of claim 4, wherein the first switch comprises: a second transistor having a control end, a first end, and a second end, wherein the control of the second transistor The terminal is coupled to the sixth node, the first terminal of the second transistor is coupled to a seventh node, and the second terminal of the second transistor is coupled to the third node; wherein A second parasitic capacitor is built in the second transistor, the second parasitic capacitor has a first terminal and a second terminal, the first terminal of the second parasitic capacitor is coupled to the third node, and the second parasitic capacitor has a first terminal and a second terminal. The second end of the second parasitic capacitor is coupled to the seventh node. The power supply of claim 5, wherein the control circuit further comprises: a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the fifth node, and the second end of the fourth resistor is coupled to an eighth node; and an inductor having a first end and a second end, wherein the first end of the inductor is coupled to the seventh node, and the second end of the inductor is coupled to the ground potential. The power supply of claim 6, wherein the second switch comprises: a third transistor having a control end, a first end, and a second end, wherein the control of the third transistor The terminal is coupled to the eighth node, the first terminal of the third transistor is coupled to the seventh node, and the second terminal of the third transistor is coupled to the third node; wherein The third transistor has a built-in third parasitic capacitor, the third parasitic capacitor has a first terminal and a second terminal, the first terminal of the third parasitic capacitor is coupled to the third node, and the The second end of the third parasitic capacitor is coupled to the seventh node.

Images