TW202343946A - Power supply device - Google Patents

Abstract

A power supply device includes a bridge rectifier, a first capacitor, a transformer, an output stage circuit, a power switch element, a PWM (Pulse Width Modulation) IC (Integrated Circuit), and a control circuit. The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The transformer includes a main coil and a secondary coil. The main coil receives the rectified voltage. The secondary coil generates an induced voltage. The output stage circuit generates an output voltage and an output current according to the induced voltage. A parasitic capacitor is built in the power switch element. The control circuit monitors the power switch element and the output stage circuit. If the power switch element is opened and the output current is equal to 0, the control circuit will fully discharge the parasitic capacitor of the power switch element.

Description

power supply

The present invention relates to a power supply, and in particular to a power supply that can reduce switching losses.

In traditional power supplies, the non-ideal parasitic capacitance of the power switch often produces a ringing effect, which not only causes greater switching losses, but also causes the overall conversion efficiency of the power supply to decrease. In addition, in a high-pressure environment, the aforementioned switching loss will further increase. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.

In a preferred embodiment, the present invention proposes a power supply including: a bridge rectifier that generates a rectified potential according to a first input potential and a second input potential, wherein the first input potential and the second input potential An absolute value of a potential difference between potentials is greater than a critical value; a first capacitor stores the rectified potential; a transformer includes a main coil and a secondary coil, wherein the transformer has a built-in exciting inductor, the main The coil receives the rectified potential, and the secondary coil generates an induced potential; an output stage circuit generates an output potential and an output current according to the induced potential; a power switch modulates the potential according to a pulse width. Selectively coupling the main coil and the exciting inductor to a ground potential, wherein the power switch has a built-in parasitic capacitor; a pulse width modulation integrated circuit generates the pulse width modulation potential; and a control circuit that monitors the power switch and the output stage circuit, wherein if the power switch is in an off state and the output current is equal to 0, the control circuit can completely discharge the parasitic capacitor of the power switch. .

In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode has an anode and a cathode, wherein the second diode The anode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode has an anode and a cathode , wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; wherein the first capacitor has a first One terminal and a second terminal, the first terminal of the first capacitor is coupled to the first node, and the second terminal of the first capacitor is coupled to the ground potential.

In some embodiments, the main coil has a first end and a second end, the first end of the main coil is coupled to the first node to receive the rectified potential, and the second end of the main coil is coupled to a second node, the exciting inductor has a first end and a second end, the first end of the exciting inductor is coupled to the first node, the second end of the exciting inductor is coupled to the second node, the secondary coil has a first end and a second end, the first end of the secondary coil is coupled to a third node to output the induced potential, and the secondary coil The second end is coupled to a common node.

In some embodiments, the output stage circuit includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the third node to receive the induced potential, The cathode of the fifth diode is coupled to an output node to output the output potential; and a second capacitor has a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node; wherein the output current flows through the fifth diode.

In some embodiments, the power switch includes: a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the second node, and The second terminal of the first resistor is coupled to a fourth node; and a first transistor has a control terminal, a first terminal, and a second terminal, wherein the first transistor The control terminal is used to receive the pulse width modulation potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the third Four nodes; wherein the parasitic capacitor has a first end and a second end, the first end of the parasitic capacitor is coupled to the fourth node to output a capacitive potential, and the second end of the parasitic capacitor is coupled to this ground potential.

In some embodiments, the control circuit includes: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the first node, and the sixth diode the cathode of the body is coupled to a fifth node; a second resistor has a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the fifth node, The second end of the second resistor is coupled to a sixth node; a third resistor has a first end and a second end, wherein the first end of the third resistor is coupled is connected to the sixth node, and the second end of the third resistor is coupled to the ground potential; and a Zener diode having an anode and a cathode, wherein the anode of the Zener diode is coupled to the ground potential, and the cathode of the Zener diode is coupled to the sixth node.

In some embodiments, the control circuit further includes: a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the first node, and the seventh diode The cathode of the pole body is coupled to a seventh node; a fourth resistor has a first end and a second end, wherein the first end of the fourth resistor is coupled to the seventh node , and the second terminal of the fourth resistor is coupled to an eighth node to output a divided voltage potential; and a fifth resistor has a first terminal and a second terminal, wherein the fifth resistor has a first terminal and a second terminal. The first end of the resistor is coupled to the eighth node, and the second end of the fifth resistor is coupled to the ground potential.

In some embodiments, the control circuit further includes: a comparator having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the comparator is used to receive the divided voltage potential. , the negative input terminal of the comparator is used to receive the capacitor potential, and the output terminal of the comparator is used to output a comparison potential.

In some embodiments, the control circuit further includes: a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the sixth node, and the third capacitor has a first terminal and a second terminal. The second terminal of the three capacitors is coupled to a ninth node; a second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to connected to the ninth node, the first terminal of the second transistor is coupled to a tenth node, and the second terminal of the second transistor is coupled to the second node; and a first An inductor has a first end and a second end, wherein the first end of the first inductor is coupled to the tenth node, and the second end of the first inductor is coupled to the ground potential.

In some embodiments, the control circuit further includes: a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the comparison potential, the first terminal of the third transistor is coupled to an eleventh node, and the second terminal of the third transistor is coupled to the output node; a sixth resistor has a first One end and a second end, wherein the first end of the sixth resistor is coupled to the eleventh node, and the second end of the sixth resistor is coupled to a twelfth node; and a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the twelfth node, and the second end of the second inductor is coupled to the common node; wherein the second inductor and the first inductor are coupled to each other.

In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are listed below and described in detail with reference to the accompanying drawings.

Certain words are used in the specification and patent claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the patent application do not use differences in names as a way to distinguish components, but differences in functions of components as a criterion for distinction. The words "include" and "include" mentioned throughout the specification and the scope of the patent application are open-ended terms, and therefore should be interpreted as "include but not limited to." The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupling" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connections. Two devices.

Figure 1 is a schematic diagram of a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in Figure 1, the power supply 100 includes: a bridge rectifier 110, a first capacitor C1, a transformer 120, an output stage circuit 130, a power switch 140, and a pulse width modulation integrated circuit ( Pulse Width Modulation Integrated Circuit (PWM IC) 150, and a control circuit 160. It should be noted that, although not shown in FIG. 1 , the power supply 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2, wherein one of the first input potential VIN1 and the second input potential VIN2 can have any frequency and any amplitude. AC voltage. For example, the frequency of the AC voltage can be about 50Hz or 60Hz, and the root mean square value of the AC voltage can be about 90V to 264V, but it is not limited thereto. The first capacitor C1 can receive and store the rectified potential VR. The transformer 120 includes a primary coil 121 and a secondary coil 122, wherein the transformer 120 may have a built-in magnetizing inductor LM. The primary coil 121 and the exciting inductor LM may be located on the same side of the transformer 120 , while the secondary coil 122 may be located on the opposite side of the transformer 120 . The primary coil 121 can receive the rectified potential VR, and in response to the rectified potential VR, the secondary coil 122 can generate an induced potential VS. The output stage circuit 130 is coupled to the secondary coil 122 and can generate an output potential VOUT and an output current IOUT according to the induced potential VS. For example, the output potential VOUT may be a DC potential, and its potential level may be from 18V to 22V, but is not limited thereto. The power switch 140 can selectively couple the main coil 121 and the exciting inductor LM to a ground potential VSS (eg, 0V) according to a pulse width modulation potential VA. For example, if the pulse width modulation potential VA is a high logic level (ie, logic “1”), the power switch 140 can couple both the main coil 121 and the exciting inductor LM to the ground potential VSS (ie, logic “1”). That is, the power switch 140 can be approximated as a short-circuit path); on the contrary, if the pulse width modulation potential VA is a low logic level (that is, logic "0"), the power switch 140 will not switch the main coil 121 and magnetizing inductor LM are coupled to ground potential VSS (ie, power switch 140 may approximate an open path). The power switch 140 may have a built-in parasitic capacitor CP. It must be understood that the total parasitic capacitance between the two terminals of the power switch 140 can be simulated as the aforementioned parasitic capacitor CP, which is not an external independent component. The pulse width modulation integrated circuit 150 can generate the pulse width modulation potential VA. The control circuit 160 can monitor the operating status of the power switch 140 and the output stage circuit 130 . If the power switch 140 is in the off state and the output current IOUT of the output stage circuit 130 is equal to 0, the control circuit 160 can completely discharge the parasitic capacitor CP of the power switch 140 . Under this design, once a ringing effect occurs between the magnetizing inductor LM of the transformer 120 and the parasitic capacitor CP of the power switch 140, the control circuit 160 can quickly eliminate this non-ideal characteristic. Therefore, the present invention can effectively reduce the switching loss of the power switch 140 and greatly improve the conversion efficiency of the power supply 100. It should be noted that even if the power supply 100 is used in a high-voltage environment, its operating efficiency will not be affected. That is, the absolute value of the potential difference between the first input potential VIN1 and the second input potential VIN2 can be greater than a critical value (for example: 220V), but is not limited thereto.

The following embodiments will introduce the detailed structure and operation of the power supply 100 . It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the invention.

Figure 2 is a schematic diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first capacitor C1, and a transformer 220 , an output stage circuit 230, a power switch 240, a pulse width modulation integrated circuit 250, and a control circuit 260. The first input node NIN1 and the second input node NIN2 of the power supply 200 can be used to receive a first input potential VIN1 and a second input potential VIN2. The output node NOUT of the power supply 200 can be used to output an output potential VOUT.

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 To output the rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the first node N1 to receive and store the rectified potential VR, and the second terminal of the first capacitor C1 is coupled to ground potential VSS.

The transformer 220 includes a primary coil 221 and a secondary coil 222, wherein the transformer 220 may have a built-in magnetizing inductor LM. The exciting inductor LM may be an inherent component produced when the transformer 220 is manufactured, and is not an external independent component. The main coil 221 and the exciting inductor LM can be located on the same side of the transformer 220 (for example, the primary side), while the secondary coil 222 can be located on the opposite side of the transformer 220 (for example, the secondary side, which can be connected to the primary side). isolated). The main coil 221 has a first end and a second end, wherein the first end of the main coil 221 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the main coil 221 is coupled to a first node N1. Two nodes N2. The exciting inductor LM has a first end and a second end, wherein the first end of the exciting inductor LM is coupled to the first node N1, and the second end of the exciting inductor LM is coupled to the second node N2 . The secondary coil 222 has a first end and a second end, wherein the first end of the secondary coil 222 is coupled to a third node N3 to output an induced potential VS, and the second end of the secondary coil 222 is coupled to A common node NCM. For example, the common node NCM can be regarded as another ground potential, which can be the same as or different from the aforementioned ground potential VSS.

The output stage circuit 230 includes a fifth diode D5 and a second capacitor C2. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the third node N3 to receive the induced potential VS, and the cathode of the fifth diode D5 is coupled to the output Node NOUT. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C1 is coupled to the common node NCM. In addition, an output current IOUT may flow through the fifth diode D5.

The power switch 240 includes a first resistor R1 and a first transistor M1. For example, the first transistor M1 may be an N-type MOSFET. The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to the second node N2, and the second terminal of the first resistor R1 is coupled to a The fourth node N4. The first transistor M1 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the first transistor M1 The terminal is used to receive a pulse width modulation potential VA, the first terminal of the first transistor M1 is coupled to the ground potential VSS, and the second terminal of the first transistor M1 is coupled to the fourth node N4 . For example, if the pulse width modulation potential VA is a high logic level, the first transistor M1 will be enabled, causing the power switch 240 to present a conductive state; conversely, if the pulse width modulation potential VA is If the logic level is low, the first transistor M1 will be disabled, causing the power switch 240 to be in an off state. The power switch 240 may have a built-in parasitic capacitor CP. It must be understood that the total parasitic capacitance between the first terminal and the second terminal of the first transistor M1 can be simulated as the aforementioned parasitic capacitor CP, which is not an external independent component. The parasitic capacitor CP has a first end and a second end. The first end of the parasitic capacitor CP is coupled to the fourth node N4 to output a capacitance potential VC, and the second end of the parasitic capacitor CP is coupled to the ground. Potential VSS.

The pulse width modulation integrated circuit 250 can generate the pulse width modulation potential VA. For example, the PWM potential VA can be maintained at a fixed potential when the power supply 200 is initialized, and can provide a periodic clock waveform after the power supply 200 enters the normal use stage.

The control circuit 260 includes a comparator 265, a sixth diode D6, a seventh diode D7, a Zener diode DZ, a second transistor M2, a third transistor M3, a first inductor L1, a second inductor L2, a third capacitor C3, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a Sixth resistor R6. For example, the second transistor M2 and the third transistor M3 may each be an N-type MOSFET. Both the first inductor L1 and the second inductor L2 may be coupled to each other. For example, the first inductor L1 and the second inductor L2 may be formed on the same iron core (not shown), but are not limited thereto.

The sixth diode D6 has an anode and a cathode, wherein the anode of the sixth diode D6 is coupled to the first node N1, and the cathode of the sixth diode D6 is coupled to a fifth node N5. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to the fifth node N5, and the second terminal of the second resistor R2 is coupled to a The sixth node N6. The third resistor R3 has a first terminal and a second terminal, wherein the first terminal of the third resistor R3 is coupled to the sixth node N6, and the second terminal of the third resistor R3 is coupled to the ground. Potential VSS. The Zener diode DZ has an anode and a cathode, wherein the anode of the Zener diode DZ is coupled to the ground potential VSS, and the cathode of the Zener diode DZ is coupled to the sixth node N6.

The seventh diode D7 has an anode and a cathode, wherein the anode of the seventh diode D7 is coupled to the first node N1, and the cathode of the seventh diode D7 is coupled to a seventh node N7. The fourth resistor R4 has a first terminal and a second terminal, wherein the first terminal of the fourth resistor R4 is coupled to the seventh node N7, and the second terminal of the fourth resistor R4 is coupled to a The eighth node N8 outputs a divided voltage potential VD. The fifth resistor R5 has a first terminal and a second terminal, wherein the first terminal of the fifth resistor R5 is coupled to the eighth node N8, and the second terminal of the fifth resistor R5 is coupled to the ground. Potential VSS.

The comparator 265 can be implemented with an operational amplifier (Operational Amplifier). In detail, the comparator 265 has a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the comparator 265 is used to receive the divided voltage potential VD, and the negative input terminal of the comparator 265 is used to receive the divided voltage potential VD. In receiving the capacitor potential VC, the output terminal of the comparator 265 is used to output a comparison potential VM. For example, if the divided voltage potential VD is higher than or equal to the capacitor potential VC, the comparison potential VM will be a high logic level; conversely, if the divided voltage potential VD is lower than the capacitor potential VC, the comparison potential VM will be a low logic level. Logic level.

The third capacitor C3 has a first terminal and a second terminal, wherein the first terminal of the third capacitor C3 is coupled to the sixth node N6, and the second terminal of the third capacitor C3 is coupled to a ninth node. N9. The second transistor M2 has a control terminal (for example, a gate), a first terminal (for example, a source), and a second terminal (for example, a drain), wherein the control terminal of the second transistor M2 The terminal is coupled to the ninth node N9, the first terminal of the second transistor M2 is coupled to a tenth node N10, and the second terminal of the second transistor M2 is coupled to the second node N2. The first inductor L1 has a first terminal and a second terminal, wherein the first terminal of the first inductor L1 is coupled to the tenth node N10, and the second terminal of the first inductor L1 is coupled to the ground. Potential VSS.

The third transistor M3 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the third transistor M3 The terminal is used to receive the comparison potential VM, the first terminal of the third transistor M3 is coupled to an eleventh node N11, and the second terminal of the third transistor M3 is coupled to the output node NOUT. The sixth resistor R6 has a first terminal and a second terminal, wherein the first terminal of the sixth resistor R6 is coupled to the eleventh node N11, and the second terminal of the sixth resistor R6 is coupled to A twelfth node N12. The second inductor L2 has a first terminal and a second terminal, wherein the first terminal of the second inductor L2 is coupled to the twelfth node N12 , and the second terminal of the second inductor L2 is coupled to Common node NCM.

It must be noted that the power supply 200 can be used in a high-voltage environment. For example, the absolute value of the potential difference between the first input potential VIN1 and the second input potential VIN2 may be greater than a critical value, such as 200V or 220V. Under high voltage conditions, since the potential level of the rectifier potential VR is high enough, the Zener diode DZ will undergo reverse collapse, which can be regarded as a stable voltage source to enable the second transistor M2.

Figure 3 shows a signal waveform diagram of a traditional power supply operating under high voltage conditions, in which the horizontal axis represents time and the vertical axis represents potential level or current value. Under the traditional design, when the power switch is in the off state and the output current IOUT is equal to 0, the capacitance potential VC of the parasitic capacitor of the power switch still cannot drop to 0, which will result in a large switching loss.

Figure 4 shows a signal waveform diagram of the power supply 200 operating under high voltage conditions according to an embodiment of the present invention, in which the horizontal axis represents time and the vertical axis represents potential level or current value. According to the measurement results in Figure 4, when the pulse width modulation potential VA is at a low logic level and the power switch 240 is in the off state, the power supply 200 will operate in a first phase T1, a first phase, and a first phase T1. The operating principles of the second stage T2 and the third stage T3 can be described as follows.

During the first phase T1, the output current IOUT has not yet dropped to 0. At this time, the energy stored in the secondary coil 222 will be transmitted back to the primary coil 221 to maintain the capacitance potential VC of the parasitic capacitor CP at a higher level.

During the second stage T2, the output current IOUT has dropped to 0, and the capacitor potential VC is higher than the divided voltage potential VD. Therefore, the comparator 265 will output the comparison potential VM of a low logic level to disable the third transistor M3. At this time, the parasitic capacitor CP will resonate with the magnetizing inductor LM and the first inductor L1, and most of the resonance energy is stored in the first inductor L1.

During the third stage T3, the output current IOUT has dropped to 0, and the capacitor potential VC is lower than or equal to the divided voltage potential VD. Therefore, the comparator 265 will output the comparison potential VM of a high logic level to enable the third transistor M3. Because the second inductor L2 and the first inductor L1 are coupled to each other, the energy previously stored in the first inductor L1 will be indirectly transferred to the second inductor L2, and then quickly released through the second inductor L2 to the common node NCM. Under this design, the parasitic capacitor CP of the power switch 240 can be completely discharged, and the capacitance potential VC of the parasitic capacitor CP can drop to 0 (or the ground potential VSS), so that the switching loss of the power supply 200 can be greatly reduced.

In some embodiments, component parameters of the power supply 200 may be as follows. The inductance value of the magnetizing inductor LM can be between 270μH and 330μH, preferably 300μH. The inductance value of the first inductor L1 can be between 414μH and 506μH, preferably 460μH. The inductance value of the second inductor L2 can be between 41.4μH and 50.6μH, preferably 46μH. The capacitance value of the first capacitor C1 can be between 96 μF and 144 μF, preferably 120 μF. The capacitance value of the second capacitor C2 can be between 544μF and 816μF, preferably 680μF. The capacitance value of the third capacitor C3 can be between 0.8nF and 1.2nF, preferably 1nF. The capacitance value of the parasitic capacitor CP can be between 320pF and 480pF, preferably 400pF. The resistance value of the first resistor R1 can be between 17.1Ω and 18.9Ω, preferably 18Ω. The resistance value of the second resistor R2 can be between 9.45KΩ and 8.55KΩ, preferably 9KΩ. The resistance value of the third resistor R3 can be between 0.95KΩ and 1.05KΩ, preferably 1KΩ. The resistance value of the fourth resistor R4 can be between 10.45KΩ and 11.55KΩ, preferably 11KΩ. The resistance value of the fifth resistor R5 can be between 3.8KΩ and 4.2KΩ, preferably 4KΩ. The resistance value of the sixth resistor R6 can be between 95Ω and 105Ω, preferably 100Ω. The turns ratio of the primary coil 221 to the secondary coil 222 can be between 1 and 10, preferably 6. The above parameter range is obtained based on multiple experimental results, which helps to minimize the switching loss of the power supply 200 while maximizing the conversion efficiency of the power supply 200 .

The present invention proposes a novel power supply that includes a control circuit to reduce switching losses. According to actual measurement results, using the power supply designed as mentioned above can almost completely eliminate the non-ideal characteristics between the transformer and the power switch, and does not affect its efficiency even in high-voltage environments. Since the present invention can effectively improve the conversion efficiency of the power supply, it is very suitable for application in various electronic devices.

It is worth noting that the above-mentioned potential, current, resistance value, inductance value, capacitance value, and other component parameters are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the state shown in Figures 1-4. The present invention may only include any one or multiple features of any one or multiple embodiments of Figures 1-4. In other words, not all features shown in the figures need to be implemented in the power supply of the present invention at the same time. Although the embodiment of the present invention uses a metal oxide semi-field effect transistor as an example, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fins. type field effect transistor, etc., without affecting the effect of the present invention.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other. They are only used to distinguish two items with the same Different components with names.

Although the present invention is disclosed above in terms of preferred embodiments, they are not intended to limit the scope of the present invention. Anyone skilled in the art can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100,200:Power supply 110,210: Bridge rectifier 120,220:Transformer 121,221: Main coil 122,222: Secondary coil 130,230: Output stage circuit 140,240:Power switcher 150,250: Pulse width modulation integrated circuit 160,260:Control circuit 265: Comparator C1: first capacitor C2: Second capacitor C3: The third capacitor CP: parasitic capacitor D1: first diode D2: Second diode D3: The third diode D4: The fourth diode D5: The fifth diode D6: The sixth diode D7: The seventh diode DZ: Zener diode IOUT: output current L1: first inductor L2: Second inductor LM: Magnetizing inductor M1: the first transistor M2: Second transistor M3: The third transistor N1: first node N2: second node N3: The third node N4: fourth node N5: fifth node N6: The sixth node N7: The seventh node N8: The eighth node N9: Ninth node N10: tenth node N11: The eleventh node N12: Twelfth node NCM: common node NIN1: first input node NIN2: second input node NOUT: output node R1: first resistor R2: second resistor R3: The third resistor R4: The fourth resistor R5: fifth resistor R6: The sixth resistor T1: first stage T2: The second stage T3: The third stage VA: pulse width modulation potential VC: capacitor potential VD: voltage dividing potential VIN1: first input potential VIN2: second input potential VM: comparison potential VOUT: output potential VR: rectifier potential VS: induced potential VSS: ground potential

Figure 1 is a schematic diagram of a power supply according to an embodiment of the present invention. Figure 2 is a schematic diagram of a power supply according to an embodiment of the present invention. Figure 3 shows the signal waveform diagram of a traditional power supply operating under high voltage conditions. Figure 4 shows a signal waveform diagram of a power supply operating under high voltage conditions according to an embodiment of the present invention.

100:Power supply

110: Bridge rectifier

120:Transformer

121: Main coil

122: Secondary coil

130:Output stage circuit

140:Power switcher

150: Pulse width modulation integrated circuit

160:Control circuit

C1: first capacitor

CP: parasitic capacitor

IOUT: output current

LM: Magnetizing inductor

VA: pulse width modulation potential

VIN1: first input potential

VIN2: second input potential

VOUT: output potential

VR: rectifier potential

VS: induced potential

VSS: ground potential

Claims (10)

A power supply including: A bridge rectifier generates a rectified potential based on a first input potential and a second input potential, wherein an absolute value of a potential difference between the first input potential and the second input potential is greater than a critical value; a first capacitor to store the rectified potential; A transformer includes a primary coil and a secondary coil, wherein the transformer has a built-in exciting inductor, the primary coil receives the rectified potential, and the secondary coil generates an induced potential; An output stage circuit generates an output potential and an output current according to the induced potential; A power switch that selectively couples the main coil and the exciting inductor to a ground potential based on a pulse width modulation potential, wherein the power switch has a built-in parasitic capacitor; a pulse width modulation integrated circuit to generate the pulse width modulation potential; and A control circuit monitors the power switch and the output stage circuit, wherein if the power switch is in an off state and the output current is equal to 0, the control circuit can completely discharge the parasitic capacitor of the power switch. The power supply of claim 1, wherein the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the first diode The cathode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the The cathode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; The first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor is coupled to the first node, and the second terminal of the first capacitor is coupled to the ground potential. The power supply of claim 2, wherein the main coil has a first end and a second end, the first end of the main coil is coupled to the first node to receive the rectified potential, and the main coil has a first end and a second end. The second terminal is coupled to a second node, the magnetizing inductor has a first terminal and a second terminal, the first terminal of the magnetizing inductor is coupled to the first node, and the magnetizing inductor has a first terminal and a second terminal. The second end is coupled to the second node, the secondary coil has a first end and a second end, the first end of the secondary coil is coupled to a third node to output the induced potential, and The second end of the secondary coil is coupled to a common node. The power supply of claim 3, wherein the output stage circuit includes: A fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the third node to receive the induced potential, and the cathode of the fifth diode is coupled Connected to an output node to output the output potential; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node; The output current flows through the fifth diode. The power supply of claim 4, wherein the power switch includes: A first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the second node, and the second terminal of the first resistor is coupled to connected to a fourth node; and A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the pulse width modulation potential, the first transistor The first terminal is coupled to the ground potential, and the second terminal of the first transistor is coupled to the fourth node; The parasitic capacitor has a first end and a second end, the first end of the parasitic capacitor is coupled to the fourth node to output a capacitance potential, and the second end of the parasitic capacitor is coupled to the ground potential. The power supply of claim 5, wherein the control circuit includes: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the first node, and the cathode of the sixth diode is coupled to a fifth node; a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the fifth node, and the second terminal of the second resistor is coupled to Connected to a sixth node; A third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the sixth node, and the second terminal of the third resistor is coupled to connected to this ground potential; and A Zener diode has an anode and a cathode, wherein the anode of the Zener diode is coupled to the ground potential, and the cathode of the Zener diode is coupled to the sixth node. Such as the power supply of claim 6, wherein the control circuit further includes: A seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the first node, and the cathode of the seventh diode is coupled to a seventh node; a fourth resistor having a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the seventh node, and the second terminal of the fourth resistor is coupled to Connected to an eighth node to output a divided voltage potential; and A fifth resistor having a first terminal and a second terminal, wherein the first terminal of the fifth resistor is coupled to the eighth node, and the second terminal of the fifth resistor is coupled to connected to this ground potential. Such as the power supply of claim 7, wherein the control circuit further includes: A comparator has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the comparator is used to receive the divided voltage potential, and the negative input terminal of the comparator is used to The capacitor potential is received, and the output terminal of the comparator is used to output a comparison potential. Such as the power supply of claim 8, wherein the control circuit further includes: a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the sixth node, and the second terminal of the third capacitor is coupled to a Ninth node; A second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to the ninth node, and the first terminal of the second transistor terminal is coupled to a tenth node, and the second terminal of the second transistor is coupled to the second node; and A first inductor having a first terminal and a second terminal, wherein the first terminal of the first inductor is coupled to the tenth node, and the second terminal of the first inductor is coupled to connected to this ground potential. Such as the power supply of claim 9, wherein the control circuit further includes: A third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the comparison potential, and the first terminal of the third transistor is coupled to an eleventh node, and the second terminal of the third transistor is coupled to the output node; a sixth resistor having a first terminal and a second terminal, wherein the first terminal of the sixth resistor is coupled to the eleventh node, and the second terminal of the sixth resistor is coupled to a twelfth node; and a second inductor having a first terminal and a second terminal, wherein the first terminal of the second inductor is coupled to the twelfth node, and the second terminal of the second inductor is coupled to the common node; The second inductor and the first inductor are coupled to each other.

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