TWI736951B - Buck integrated circuit - Google Patents

Abstract

A buck integrated circuit is configured to receive a DC power outputted by a DC output terminal of a rectifier circuit, and the buck integrated circuit comprises a transistor switch, a capacitor, an output stage circuit, and a Schmitt comparator. The transistor switch includes a first terminal, a second terminal, and a third terminal, and the first terminal is electrically connected to the DC output terminal. A first end of the capacitor is electrically connected to the second terminal, and a second end of the capacitor is grounded. The output stage circuit is electrically connected the first end of the capacitor and the second terminal. The Schmitt comparator includes a non-inverting input terminal, an inverting input terminal and an output terminal, the inverting input terminal receives a reference voltage, the non-inverting input terminal is electrically connected to the first terminal and the DC output terminal, and the output terminal is electrically connected with the third terminal.

Description

Step-down integrated circuit

The invention relates to an integrated circuit, particularly an integrated circuit with a voltage reduction function.

With the development of electronic technology, various voltage converters have been widely used in electronic devices, such as AC/DC converters or DC converters. Generally speaking, the step-down circuit in the AC/DC converter includes a primary side coil and a secondary side coil. By designing the turns ratio of the primary side coil and the secondary measuring coil, the purpose of stepping down the voltage can be achieved in order to supply low voltage. Voltage electrical appliances. Since the step-down circuit must use a coil, the area of the AC/DC converter increases and the production cost is increased.

In view of this, there is indeed a need for a more streamlined AC/DC converter, which can at least improve the above shortcomings.

The present invention is to provide a step-down integrated circuit, which can extract the energy of the low-voltage part of the DC power so as to supply it to low-power electrical appliances.

According to the step-down integrated circuit disclosed in an embodiment of the present invention, the step-down integrated circuit is used to receive the DC power output from the DC output terminal of the rectifier circuit. The step-down integrated circuit includes a transistor switch, a capacitor, an output stage circuit and a Schmitt comparator. The transistor switch includes a first terminal, a second terminal, and a third terminal. The first terminal is electrically connected to the DC output terminal. The first end of the capacitor is electrically connected to the second terminal, and the second end of the capacitor is grounded. The output stage circuit is electrically connected to the first terminal and the second terminal of the capacitor. The Schmitt comparator includes a non-inverting input terminal, an inverting input terminal and an output terminal. The inverting input terminal receives the reference voltage. The non-inverting input terminal is electrically connected to the first terminal and the DC output terminal. The output terminal is connected to the third The terminals are electrically connected.

According to the step-down integrated circuit disclosed in an embodiment of the present invention, the step-down integrated circuit is used to receive the DC power output from the DC output terminal of the rectifier circuit. The step-down integrated circuit includes a transistor switch, a capacitor, an output stage circuit, a first Schmitt comparator, a second Schmitt comparator, and an inverting or gate circuit. The transistor switch includes a first terminal, a second terminal and a third terminal, and the first terminal is connected to the DC output terminal. The first end of the capacitor is electrically connected to the second terminal, and the second end of the capacitor is grounded. The output stage circuit is electrically connected to the first terminal and the second terminal of the capacitor. The first Schmitt comparator includes a first non-inverting input terminal, a first inverting input terminal, and a first output terminal. The first inverting input terminal receives a first reference voltage. The first non-inverting input terminal is connected to the first output terminal. One terminal is electrically connected to the DC output terminal. The second Schmitt comparator includes a second non-inverting input terminal, a second inverting input terminal, and a second output terminal. The second inverting input terminal receives a second reference voltage. The second non-inverting input terminal is connected to the second output terminal. The two terminals, the first end of the capacitor, and the output stage circuit are electrically connected. The inverting OR circuit includes a first output terminal, a second input terminal, and an output terminal. The first input terminal is electrically connected to the first output terminal of the first Schmitt comparator, and the second input terminal is compared with the second Schmitt comparator. The second output terminal of the device is electrically connected, and the output terminal of the gate circuit is electrically connected to the third terminal.

In the step-down integrated circuit provided by the present invention, the first Schmitt comparator determines the upper limit of the voltage of the extracted DC power, and the second Schmitt comparator determines the upper limit of the voltage supplied to the output stage circuit. Therefore, the step-down integrated circuit can obtain energy from the low-voltage section of the DC power, and then provide a stable DC voltage to low-power electrical appliances through the voltage stabilizing circuit. The circuit architecture of the step-down integrated circuit has the advantages of being chip-based to achieve the goal of miniaturization of the power supply. Compared with the conventional power supply, the cost is lower and the circuit structure is much simpler.

The above description of the disclosure and the following description of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the scope of the patent application of the present invention.

The detailed features and advantages of the present invention will be described in detail in the following embodiments. The content is sufficient to enable anyone familiar with the relevant art to understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, the scope of patent application and the drawings. Anyone who is familiar with relevant skills can easily understand the purpose and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention by any viewpoint.

FIG. 1 is a functional block diagram of the step-down integrated circuit according to the first embodiment of the present invention. As shown in FIG. 1, the step-down integrated circuit 1 is used to receive the DC circuit output by the rectifier circuit 10, and the step-down integrated circuit 1 includes a transistor switch 12, a capacitor C, an output stage circuit 14 and a comparator Circuit 16. The rectifier circuit 10 includes an AC input terminal 101 and a DC output terminal 102. The AC input terminal 101 is used to receive AC power from the mains. The rectifier circuit 10 can be a half-wave rectifier or a full-wave rectifier to convert the AC power from the mains. It is DC power, and finally the DC power is output to the step-down integrated circuit 1 through the DC output terminal 102.

The transistor switch 12 is a high voltage (Ultra high voltage) transistor switch made of a metal oxide semiconductor field effect transistor (MOS), and the upper limit of the voltage is, for example, 500 volts, but it is not limited thereto. The transistor switch 12 has a first terminal 121, a second terminal 122, and a third terminal 123. In this embodiment, the transistor switch 12 is NMOS, so the first terminal 121, the second terminal 122, and the third terminal 123 are respectively Drain, source and gate. The first terminal 121 of the transistor switch 12 is electrically connected to the DC output terminal 102 of the rectifier circuit 10.

The capacitor C has a first terminal and a second terminal. The first terminal of the capacitor C is electrically connected to the second terminal 122 of the transistor switch 12, and the second terminal of the capacitor C is grounded.

The output stage circuit 14 includes an input terminal and an output terminal output. The input terminal input of the output stage circuit 14 is electrically connected to the second terminal 122 of the transistor switch 12, and the output terminal output of the output stage circuit 14 can be used to connect an external electric appliance.

The comparison circuit 16 includes a first comparison signal input terminal Com1, a second comparison signal input terminal Com2, a control signal output terminal Con, a first reference signal input terminal Ref1, and a second reference signal input terminal Ref2. The first comparison signal input terminal Com1 is electrically connected to the first terminal 121 of the transistor switch 12 and the DC output terminal 102 of the rectifier circuit 10. The second comparison signal input terminal Com2 is electrically connected to the second terminal 122 of the transistor switch 12 and the input terminal input of the output stage circuit 14. The control signal output terminal Con is electrically connected to the third terminal 123 of the transistor switch 12. The first reference signal input terminal Ref1 is used to receive the first reference voltage. The second reference signal input terminal Ref2 is used to receive the second reference voltage. Among them, according to the comparison result of the two signals input from the first comparison signal input terminal Com1 and the first reference signal input terminal Ref1, and according to the two signals input from the second comparison signal input terminal Com2 and the second reference signal input terminal Ref2 The comparison result of the signals can determine the level of the control signal output by the control signal output terminal Con.

Figure 2 is a circuit diagram of the step-down integrated circuit of Figure 1. 1 and 2 together, the output stage circuit 14 includes a voltage stabilizing circuit 141 and an inverter circuit 142, wherein the voltage stabilizing circuit 141 is, for example, a transistor series regulator, a transistor shunt regulator or a Zener Diode. The voltage stabilizing circuit 141 has an input end 1411 and an output end 1412. The input end 1411 of the voltage stabilizing circuit 141 is electrically connected to the first end of the capacitor C, the second terminal 12 of the transistor switch 12 and the comparison circuit 16. The inverter circuit 142 is, for example, a CMOS inverter, and the inverter circuit 142 has an input terminal 1421 and an output terminal 1422. The output terminal 1412 of the voltage stabilizing circuit 141 is connected to the input terminal 1421 of the inverter circuit 142.

The comparison circuit 16 includes a first voltage divider circuit 161, a first Schmitt comparator 162, a second voltage divider circuit 163, a second Schmitt comparator 164 and an inverter circuit 165. The first voltage divider circuit 161 includes a first resistor R1 and a second resistor R2, wherein both ends of the first resistor R1 have a first node N1 and a second node N2, respectively. The first node N1 is electrically connected to the DC output terminal 102 of the rectifier circuit 10, and the second node N2 is electrically connected between the first resistor R1 and the second resistor R2.

The first Schmitt comparator 162 includes a first inverting input terminal 1621, a first non-inverting input terminal 1622, and a first output terminal 1623. The first inverting input terminal 1621 is connected to the first reference voltage Vref1, and the first non-inverting input terminal 1622 is electrically connected to the second node N2 of the first voltage divider circuit 161. The function of the first Schmitt comparator 162 is to set the upper limit of the input voltage of the transistor switch 12, where the upper limit of the input voltage of the transistor switch 12 is Vref1*(R1+R2)/R2.

The second voltage divider circuit 163 includes a third resistor R3 and a fourth resistor R4, wherein two ends of the third resistor R3 respectively have a third node N3 and a fourth node N4. The third node N3 is electrically connected to the second terminal 122 of the transistor switch 12, the first terminal of the capacitor C and the input terminal 1411 of the voltage stabilizing circuit 141. The fourth node N4 is electrically connected between the third resistor R3 and the fourth resistor R4.

The second Schmitt comparator 164 includes a second inverting input terminal 1641, a second non-inverting input terminal 1642, and a second output terminal 1643. The second inverting input terminal 1641 is connected to the second reference voltage Vref2. The second non-inverting input terminal 1642 is electrically connected to the fourth node N4 of the second voltage divider circuit 163. The function of the second Schmitt comparator 164 is to set the upper limit of the input voltage of the voltage stabilizing circuit 141, where the upper limit of the input voltage of the voltage stabilizing circuit 141 is Vref2*(R3+R4)/R4.

The NOR gate circuit 165 has a first input terminal 1651, a second input terminal 1652, and an output terminal 1653. The first input terminal 1651 of the inverting OR circuit 165 is electrically connected to the first output terminal 1623 of the first Schmitt comparator 162. The second input terminal 1652 of the inverter circuit 165 is electrically connected to the second output terminal 1643 of the second Schmitt comparator 164. The output terminal 1653 of the NOR circuit 165 is electrically connected to the third terminal 123 of the transistor switch 12.

Comparing FIG. 1 with FIG. 2, the second node N2 of the first voltage divider circuit 161 is the first comparison signal input terminal Com1, and the fourth node N4 of the second voltage divider circuit 163 is the second comparison signal input terminal Com2. An inverting input terminal 1621 is the first reference signal input terminal Ref1, the second inverting input terminal 1641 is the second reference signal input terminal Ref2, and the output terminal 1653 of the inverter circuit 165 is the control signal output terminal Con.

In another embodiment, the transistor switch 12 may be an NPN type BJT, and the first terminal 121, the second terminal 122, and the third terminal 123 are a collector, an emitter, and a base, respectively. The first non-inverting input terminal 1622 is electrically connected to the second node N2 of the first voltage divider circuit 161, and the first inverting input terminal 1621 is connected to the first reference voltage Vref1. The second non-inverting input terminal 1642 is electrically connected to the fourth node N4 of the second voltage divider circuit 163, and the second inverting input terminal 1641 is connected to the second reference voltage Vref2.

3 shows the second terminal 122 of the transistor switch 12 of FIG. 2, the DC output terminal 102 of the rectifier circuit 10, the third terminal 123 of the transistor switch 12, the first input terminal 1651 of the inverter circuit 165, and The signal waveform diagram of the second input terminal 1652 of the inverting OR circuit 165. As shown in FIG. 3, after the AC power is full-wave rectified by the rectifier circuit 10, the DC power is output to the DC output terminal 102. Only when the voltages of the first input terminal 1651 and the second input terminal 1652 of the inverter circuit 165 are both at the low level, the output terminal 1653 of the inverter circuit 165 will output a high level voltage. The third terminal 123 of the transistor switch 12 is connected to the output terminal 1653, so the voltage signal of the output terminal 1653 is the same as the voltage signal of the third terminal 123. When the voltage of the third terminal 123 (the gate electrode in this embodiment) of the transistor switch 12 is at a high level, the transistor switch 12 is in an on state, and the direct current at the DC output terminal 102 passes through the transistor switch 12 at this time. The following circuit operation takes the transistor switch 12 as an NMOS as an example.

As shown in FIG. 3, when the DC power of the DC output terminal 102 is in the first interval 0~T1, since the voltage of the first non-inverting input terminal 1622 is less than the first reference voltage Vref1 of the first inverting input terminal 1621, The first output terminal 1623 of a Schmitt comparator 162 outputs a low-level voltage signal to the first input terminal 1651 of the inverter circuit 165. Since the voltage of the second non-inverting input terminal 1642 is greater than the second reference voltage Vref2 of the second inverting input terminal 1641, the second output terminal 1643 of the second Schmitt comparator 164 outputs a high-level voltage signal to the inverted OR The second input terminal 1652 of the gate circuit 165. Since the input signal of the inverter circuit 165 is a low-level voltage and a high-level voltage, the output terminal 1653 of the inverter circuit 165 outputs a low-level voltage to the third terminal 123 of the transistor switch 12. At this time, the transistor switch 12 is in an off state and the capacitor C is in a discharged state.

When the DC power of the DC output terminal 102 is in the second interval T1~T2, since the voltage of the first non-inverting input terminal 1622 is greater than the first reference voltage Vref1 of the first inverting input terminal 1621, the first Schmitt comparator The first output terminal 1623 of the 162 outputs a high-level voltage signal to the first input terminal 1651 of the inverter circuit 165. Since the voltage of the second non-inverting input terminal 1642 is greater than the second reference voltage Vref2 of the second inverting input terminal 1641, the second output terminal 1643 of the second Schmitt comparator 164 outputs a high-level voltage signal to the inverted OR The second input terminal 1652 of the gate circuit 165. Since the input signals of the inverter circuit 165 are all high-level voltage signals, the output terminal 1653 of the inverter circuit 165 outputs a low-level voltage signal to the third terminal 123 of the transistor switch 12. At this time, the transistor switch 12 is in an off state and the capacitor C is in a discharged state.

When the DC power of the DC output terminal 102 is in the third interval T2~T3, since the voltage of the first non-inverting input terminal 1622 is less than the first reference voltage Vref1 of the first inverting input terminal 1621, the first Schmitt comparator The first output terminal 1623 of the 162 outputs a low-level voltage signal to the first input terminal 1651 of the inverter circuit 165. Since the voltage of the second non-inverting input terminal 1642 is greater than the second reference voltage Vref2 of the second inverting input terminal 1641, the second output terminal 1643 of the second Schmitt comparator 164 outputs a high-level voltage signal to the inverted OR The second input terminal 1652 of the gate circuit 165. Since the input signal of the inverter circuit 165 is a low-level voltage signal and a high-level voltage signal, the output terminal 1653 of the inverter circuit 165 outputs a low-level voltage signal to the third terminal 123 of the transistor switch 12. At this time, the transistor switch 12 is in an off state and the capacitor C is in a discharged state.

When the DC power of the DC output terminal 102 is in the fourth interval T3~T4, since the voltage of the first non-inverting input terminal 1622 is less than the first reference voltage Vref1 of the first inverting input terminal 1621, the first Schmitt comparator The first output terminal 1623 of the 162 outputs a low-level voltage signal to the first input terminal 1651 of the inverter circuit 165. Since the voltage of the second non-inverting input terminal 1642 is less than the second reference voltage Vref2 of the second inverting input terminal 1641, the second output terminal 1643 of the second Schmitt comparator 164 outputs a low-level voltage signal to the inverted OR The second input terminal 1652 of the gate circuit 165. Since the input signals of the inverter circuit 165 are low-level voltage signals, the output terminal 1653 of the inverter circuit 165 outputs a high-level voltage signal to the third terminal 123 of the transistor switch 12. At this time, the transistor switch 12 is in a conducting state and the capacitor C is in a charging state.

In summary, only when the voltage of the node N2 and the voltage of the node N4 are smaller than the first reference voltage Vref1 and the second reference voltage Vref2, the transistor switch 12 will be in the on state. When the transistor switch 12 is in the on state, the capacitor C is charged by the direct current.

In the step-down integrated circuit provided by the present invention, the first Schmitt comparator determines the upper limit of the voltage of the extracted DC power, and the second Schmitt comparator determines the upper limit of the voltage supplied to the output stage circuit. Therefore, the step-down integrated circuit can obtain energy from the low-voltage section of the DC power, and then provide a stable DC voltage to low-power electrical appliances through the voltage stabilizing circuit. The circuit architecture of the step-down integrated circuit has the advantages of being chip-based to achieve the goal of miniaturization of the power supply. Compared with the conventional power supply, the cost is lower and the circuit structure is much simpler.

In summary, although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. All changes and modifications made without departing from the spirit and scope of the present invention fall within the scope of the patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the attached scope of patent application.

10: Rectifier circuit 101: AC input 102: DC output 1: Step-down integrated circuit 12: Transistor switch 121: first terminal 122: second terminal 123: third terminal 14: output stage circuit 141: Voltage stabilizing circuit 1411: Input 1412: output 142: Inverting circuit 1421: Input 1422: output 16: Comparison circuit 161: The first voltage divider circuit 162: First Schmitt Comparator 1621: The first inverting input terminal 1622: The first non-inverting input terminal 1623: first output 163: Second voltage divider circuit 164: Second Schmitt Comparator 1641: second inverting input 1642: second non-inverting input 1643: second output 165: Inverted OR gate circuit 1651: first input 1652: second input 1653: output Com1: The first comparison signal input terminal Com2: The second comparison signal input terminal Ref1: The first reference signal input terminal Ref2: The second reference signal input terminal Con: Control signal output terminal input: input output: output terminal C: Capacitance R1: first resistance R2: second resistor N1: the first node N2: second node R3: third resistor R4: Fourth resistor N3: third node N4: Fourth node Vref1: the first reference voltage Vref2: second reference voltage

FIG. 1 is a functional block diagram of the step-down integrated circuit according to the first embodiment of the present invention. Figure 2 is a circuit diagram of the step-down integrated circuit of Figure 1. Figure 3 shows the second terminal of the transistor switch of Figure 2, the DC output terminal of the rectifier circuit, the third terminal of the transistor switch, the first input terminal of the inverter circuit and the second input of the inverter circuit. Waveform diagram of the signal at the end.

1: Step-down integrated circuit

10: Rectifier circuit

101: AC input

102: DC output

12: Transistor switch

121: first terminal

122: second terminal

123: third terminal

C: Capacitance

14: output stage circuit

input: input

output: output terminal

16: Comparison circuit

Com1: The first comparison signal input terminal

Com2: The second comparison signal input terminal

Ref1: The first reference signal input terminal

Ref2: The second reference signal input terminal

Con: Control signal output terminal

Claims (8)

A step-down integrated circuit for receiving DC power output from a DC output terminal of a rectifier circuit. The step-down integrated circuit includes a transistor switch including a first terminal, a second terminal, and a first terminal. Three terminals, the first terminal is electrically connected to the DC output terminal; a capacitor has a first terminal and a second terminal, the first terminal of the capacitor is electrically connected to the second terminal, the first terminal of the capacitor Two terminals are grounded; an output stage circuit electrically connected to the first terminal and the second terminal of the capacitor; and a Schmitt comparator including a non-inverting input terminal, an inverting input terminal and an output terminal , The inverting input terminal receives a reference voltage, the non-inverting input terminal is electrically connected to the first terminal and the DC output terminal, the output terminal is electrically connected to the third terminal; the output stage circuit includes a voltage regulator Circuit and an inverter circuit. The voltage stabilizing circuit has an input and an output. The input of the voltage stabilizing circuit is electrically connected to the second terminal and the first end of the capacitor. The output terminal is electrically connected with the inverter circuit. The step-down integrated circuit according to claim 1, wherein the transistor switch is a high-resistance piezoelectric crystal switch made of a metal oxide semiconductor field effect transistor. The step-down integrated circuit according to claim 1, further comprising a first resistor and a second resistor, one end of the first resistor is electrically connected to the DC output terminal and the first terminal, and the other of the first resistor One end is electrically connected to one end of the second resistor and the inverting input end. A step-down integrated circuit for receiving DC power output from a DC output terminal of a rectifier circuit. The step-down integrated circuit includes: A transistor switch includes a first terminal, a second terminal, and a third terminal. The first terminal is electrically connected to the DC output terminal; a capacitor having a first terminal and a second terminal. The first end is electrically connected to the second terminal, and the second end of the capacitor is grounded; an output stage circuit is electrically connected to the first end and the second terminal of the capacitor; a first Schmitt comparison The device includes a first non-inverting input terminal, a first inverting input terminal, and a first output terminal. The first inverting input terminal receives a first reference voltage, the first non-inverting input terminal and the first output terminal. The first terminal and the DC output terminal are electrically connected; a second Schmitt comparator includes a second non-inverting input terminal, a second inverting input terminal and a second output terminal, the second inverting The input terminal receives a second reference voltage, the second non-inverting input terminal is connected to the second terminal, the first terminal of the capacitor, and the output stage circuit; and an inverter circuit including a first input Terminal, a second input terminal and an output terminal, the first input terminal is electrically connected to the first output terminal of the first Schmitt comparator, and the second input terminal is electrically connected to the second Schmitt comparator The second output terminal of the inverter is electrically connected, and the output terminal of the inverter circuit is electrically connected to the third terminal. The step-down integrated circuit according to claim 4, wherein the output stage circuit includes a voltage stabilizing circuit and an inverter circuit, the voltage stabilizing circuit has an input terminal and an output terminal, and the input terminal of the voltage stabilizing circuit It is electrically connected to the second terminal, the first end of the capacitor, and the second inverting input end, and the output end of the voltage stabilizing circuit is electrically connected to the inverting circuit. The step-down integrated circuit according to claim 4, wherein the transistor switch is a high-resistance piezoelectric crystal switch made of a metal oxide semiconductor field effect transistor. The step-down integrated circuit according to claim 4, further comprising a first resistor and a second resistor, one end of the first resistor is electrically connected to the DC output terminal and the first terminal, and the other of the first resistor One end is electrically connected to one end of the second resistor and the first inverting input end. The step-down integrated circuit according to claim 4, further comprising a third resistor and a fourth resistor, one end of the third resistor is electrically connected to the second terminal, the first end of the capacitor, and the output stage In the circuit, the other end of the third resistor is electrically connected to one end of the fourth resistor and the second inverting input end.

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