TWI837701B - Boost converter for increasing output stability - Google Patents

Abstract

A boost converter includes a bridge rectifier, a boost inductor, a power switch element, an output stage circuit, and a detection and control circuit. The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The boost inductor receives the rectified voltage. An inductive current flows through the boost inductor. The power switch element selectively couples the boost inductor to a ground voltage according to a clock voltage. The output stage circuit is coupled to the boost inductor, and is configured to generate an output voltage. An output current flows through the output stage circuit. The detection and control circuit determines a current mode of the boost inductor according to the inductive current, and determines a load mode of the output stage circuit according to the output current. The detection and control circuit checks whether the load mode matches with the current mode, so as to generate the clock voltage.

Description

Boost converter to improve output stability

The present invention relates to a boost converter, and more particularly to a boost converter capable of improving output stability.

In traditional boost converters, if the purpose of miniaturization is to be achieved, the operating frequency must be increased. However, this improved method of increasing the operating frequency can easily cause the traditional boost converter to malfunction when switching current modes, thereby reducing its output stability. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.

In a preferred embodiment, the present invention provides a boost converter for improving output stability, comprising: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a boost inductor, receiving the rectified potential, wherein an inductor current flows through the boost inductor; a power switch, selectively coupling the boost inductor to a ground potential according to a clock potential; an output stage circuit; A circuit is provided, coupled to the boost inductor, and generates an output potential, wherein an output current flows through the output stage circuit; and a detection and control circuit determines a current mode of the boost inductor according to the inductor current, and determines a load mode of the output stage circuit according to the output current; wherein the detection and control circuit further confirms whether the load mode matches the current mode, and generates the clock potential accordingly.

In order to make the purpose, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are specifically listed below and described in detail with reference to the accompanying drawings.

Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described herein as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or may be indirectly electrically connected to the second device via other devices or connection means.

FIG. 1 is a schematic diagram of a boost converter 100 according to an embodiment of the present invention. For example, the boost converter 100 may be applied to a desktop computer, a laptop computer, or an all-in-one computer. As shown in FIG. 1 , the boost converter 100 includes: a bridge rectifier 110, a boost inductor LU, a power switch 120, an output stage circuit 130, and a detection and control circuit 140. It should be noted that, although not shown in FIG. 1 , the boost converter 100 may further include other components, such as: a voltage regulator or (and) a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be approximately 50 Hz or 60 Hz, and the RMS value of the AC voltage can be approximately from 90 V to 264 V, but is not limited thereto. The boost inductor LU can receive the rectified potential VR, wherein an inductor current ILM can flow through the boost inductor LU. The power switch 120 can selectively couple the boost inductor LU to a ground potential VSS (e.g., 0 V) according to a clock potential VA. For example, if the clock potential VA is a high logic level (i.e., logic "1"), the power switch 120 can couple the boost inductor LU to the ground potential VSS (i.e., the power switch 120 can be similar to a short circuit path); conversely, if the clock potential VA is a low logic level (i.e., logic "0"), the power switch 120 will not couple the boost inductor LU to the ground potential VSS (i.e., the power switch 120 can be similar to an open circuit path). The output stage circuit 130 is coupled to the boost inductor LU and can generate an output potential VOUT, wherein an output current IOUT can flow through the output stage circuit 130. For example, the output potential VOUT may be a DC potential, and its potential level may be approximately 400V, but is not limited thereto. The detection and control circuit 140 is coupled to the boost inductor LU and the output stage circuit 130, respectively. The detection and control circuit 140 may determine a current mode of the boost inductor LU according to the inductor current ILM, and may determine a load mode of the output stage circuit 130 according to the output current IOUT. In addition, the detection and control circuit 140 may also confirm whether the load mode of the output stage circuit 130 matches the current mode of the boost inductor LU, and may generate and adjust the clock potential VA accordingly. In this design, since the pulse potential VA of the power switch 120 can be dynamically adjusted in response to the current mode and load mode, the probability of mode switching errors in the boost converter 100 can be greatly reduced, thereby effectively improving its overall output stability.

The following embodiments will introduce the detailed structure and operation of the boost converter 100. It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 is a circuit diagram of a boost converter 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the boost converter 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a boost inductor LU, a power switch 220, an output stage circuit 230, and a detection and control circuit 240. The first input node NIN1 and the second input node NIN2 of the boost converter 200 can receive a first input potential VIN1 and a second input potential VIN2 respectively from an external input power source (not shown). The output node NOUT of the boost converter 200 can be used to output an output potential VOUT to an electronic device (not shown).

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The boost inductor LU has a first terminal and a second terminal, wherein the first terminal of the boost inductor LU is coupled to the first node N1 to receive the rectified potential VR, and the second terminal of the boost inductor LU is coupled to a second node N2.

The power switch 220 includes a switching transistor MS. For example, the switching transistor MS may be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The switching transistor MS has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the switching transistor MS is used to receive a clock potential VA, the first terminal of the switching transistor MS is coupled to the ground potential VSS, and the second terminal of the switching transistor MS is coupled to a third node N3. For example, an operating frequency of the clock potential VA may be between 150kHz and 250kHz, which is higher than the traditional 65kHz design, but is not limited thereto.

The output stage circuit 230 includes a fifth diode D5 and an output capacitor CO. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the third node N3, and the cathode of the fifth diode D5 is coupled to the output node NOUT. The output capacitor CO has a first terminal and a second terminal, wherein the first terminal of the output capacitor CO is coupled to the output node NOUT, and the second terminal of the output capacitor CO is coupled to a fourth node N4.

The detection and control circuit 240 includes a microcontroller unit (MCU) 250, a first resistor R1, and a second resistor R2. The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is coupled to the second node N2, and the second end of the first resistor R1 is coupled to the third node N3. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the fourth node N4, and the second end of the second resistor R2 is coupled to the ground potential VSS. It should be noted that the first resistor R1 is coupled in series with the boost inductor LU, wherein an inductor current ILM flows through the boost inductor LU and the first resistor R1 at the same time. In addition, the second resistor R2 is coupled in series with the output capacitor CO, wherein an output current IOUT flows through the output capacitor CO and the second resistor R2 simultaneously. In some embodiments, the first resistor R1 and the second resistor R2 both have very small resistance values (eg, less than 5 ohms).

The microcontroller 250 includes a sampling module 251, an error detection module 252, a counting module 253, a processing module 254, a sensing and comparison module 255, and a clock generation module 256. For example, each module of the microcontroller 250 can be implemented in the form of a hardware circuit or a software program, but is not limited thereto.

The sampling module 251 can detect a first potential difference ΔV1 across the first resistor R1. According to Ohm's law, since the first potential difference ΔV1 is proportional to the inductor current ILM, the sampling module 251 can obtain relevant information of the inductor current ILM according to the first potential difference ΔV1. In some embodiments, a sampling frequency of the sampling module 251 is equal to the switching frequency of the power switch 220. That is, the sampling frequency of the sampling module 251 can be substantially the same as the operating frequency of the clock potential VA.

The error detection module 252 can generate a first bit B1 and a second bit B2 of logical complement according to the first potential difference ΔV1. Specifically, the error detection module 252 can compare the first potential difference ΔV1 with the ground potential VSS (or 0V). For example, if the first potential difference ΔV1 is equal to the ground potential VSS (i.e., ), it means that the inductor current ILM is 0, and the error detection module 252 can generate a first bit B1 with a high logic level and a second bit B2 with a low logic level; on the contrary, if the first potential difference ΔV1 is not equal to the ground potential VSS (that is, ), it may represent that the inductor current ILM is not zero, and the error detection module 252 may generate a first bit B1 with a low logic level and a second bit B2 with a high logic level.

In response to the first bit B1 having a high logic level, the counting module 253 may start to count a zero current time TZ. For example, if the zero current time TZ is equal to 0, the counting module 253 may generate a third bit B3 having a low logic level; conversely, if the zero current time TZ is greater than 0, the counting module 253 may generate a third bit B3 having a high logic level. On the other hand, if the first bit B1 is a low logic level, the counting module 253 will not be activated, and the third bit B3 will not be generated.

The processing module 254 can determine a current mode of the boost inductor LU according to the first bit B1, the second bit B2, and the third bit B3. For example, the current mode can be a discontinuous current mode (DCM), a boundary current mode (BCM), or a continuous current mode (CCM). In some embodiments, the corresponding relationship between the current mode of the boost inductor LU and the first bit B1, the second bit B2, and the third bit B3 can be described in Table 1 below:

The first digit B1 The second bit B2 The third bit B3 Discontinuous Current Mode High logic level Low logic level High logic level Boundary Current Mode High logic level Low logic level Low logic level Continuous Current Mode Low logic level High logic level Not generated Table 1: Correspondence between the current mode of the boost inductor LU and each bit

The sensing and comparison module 255 can detect a second potential difference ΔV2 across the second resistor R2. According to Ohm's law, since the second potential difference ΔV2 is proportional to the output current IOUT, the sensing and comparison module 255 can obtain relevant information of the output current IOUT according to the second potential difference ΔV2. In detail, the sensing and comparison module 255 can compare the second potential difference ΔV2 with a first critical potential VTH1 and a second critical potential VTH2 to determine a load mode of the output stage circuit 230. For example, if the second potential difference ΔV2 is less than the first critical potential VTH1 (that is, ), the sensing and comparison module 255 can determine that the output stage circuit 230 operates in a light load mode; if the second potential difference ΔV2 is between the first critical potential VTH1 and the second critical potential VTH2 (ie, ), the sensing and comparing module 255 can determine that the output stage circuit 230 operates in a medium load mode; and if the second potential difference ΔV2 is greater than the second critical potential VTH2 (ie, ), the sensing and comparison module 255 can determine that the output stage circuit 230 operates in a heavy load mode. In some embodiments, the first critical potential VTH1 and the second critical potential VTH2 can be set according to the following equations (1) and (2):

……………………(1)

……………………(2) Wherein "VTH1" represents the first critical potential VTH1, "VTH2" represents the second critical potential VTH2, "IOUTMAX" represents the maximum value of the output current IOUT, and "R2" represents the resistance value of the second resistor R2.

In addition, the sensing and comparison module 255 can further inform the processing module 254 of the load mode of the output stage circuit 230, so that the processing module 254 can confirm whether the load mode of the output stage circuit 230 matches the current mode of the boost inductor LU. In some embodiments, the operation modes that match each other can be described in Table 2 below:

Load Mode Current mode matching the load mode Light load mode Discontinuous Current Mode Medium load mode Boundary Current Mode Reload Mode Continuous Current Mode Table 2: Mutually matched load mode and current mode

The clock generation module 256 can be controlled by the processing module 254 and the sensing and comparing module 255, and can generate and adjust the clock potential VA. In some embodiments, if the load mode of the output stage circuit 230 matches the current mode of the boost inductor LU, the processing module 254 can control the clock generation module 256 to maintain a duty cycle of the clock potential VA; on the contrary, if the load mode of the output stage circuit 230 and the current mode of the boost inductor LU do not match each other, the processing module 254 can control the clock generation module 256 to change the duty cycle of the clock potential VA. For example, if the load mode is a light load mode but the current mode is a boundary current mode (mismatch), the processing module 254 will be able to control the clock generation module 256 to shorten the duty cycle of the clock potential VA; for another example, if the load mode is a heavy load mode but the current mode is a boundary current mode (mismatch), the processing module 254 will be able to control the clock generation module 256 to increase the duty cycle of the clock potential VA, but it is not limited to this.

In some embodiments, if the output stage circuit 230 changes its load mode, the clock generation module 256 will further provide a delay interval TD to the clock potential VA, wherein the delay interval TD may be greater than or equal to 25 μs. For example, if the output stage circuit 230 switches from the light load mode to the medium load mode, the delay interval TD of the clock potential VA will be between the light load mode and the medium load mode, wherein the clock potential VA is maintained at a low logic level during the delay interval TD to avoid confusion between different load modes. It must be understood that the delay interval TD is only an optional design and may be removed in other embodiments.

Figure 3 shows the waveform of the inductor current ILM of a conventional boost converter when the output current IOUT gradually increases. Ideally, the inductor current ILM should switch from the discontinuous current mode to the boundary current mode and then to the continuous current mode. However, in practice, the inductor current ILM is prone to some malfunctions.

Figure 4 shows the waveform of the inductor current ILM of a conventional boost converter when the output current IOUT gradually decreases. Ideally, the inductor current ILM should switch from the continuous current mode to the boundary current mode and then to the discontinuous current mode. However, in practice, the inductor current ILM is prone to other malfunctions.

FIG. 5 is a waveform diagram showing the inductor current ILM of the boost converter 200 according to an embodiment of the present invention when the output current IOUT gradually increases. As shown in FIG. 5 , the boost inductor LU operates in a discontinuous current mode in a first time interval T1, in a boundary current mode in a second time interval T2, and in a continuous current mode in a third time interval T3. According to the measurement results of FIG. 5 , since almost all switching errors are eliminated, the boost converter 200 can greatly improve its output stability.

FIG. 6 is a waveform diagram showing the inductor current ILM of the boost converter 200 according to an embodiment of the present invention when the output current IOUT gradually decreases. As shown in FIG. 5 , the boost inductor LU operates in a continuous current mode in a fourth time interval T4, in a boundary current mode in a fifth time interval T5, and in a discontinuous current mode in a sixth time interval T6. According to the measurement results of FIG. 6 , since almost all switching errors are eliminated, the boost converter 200 can greatly improve its output stability.

The present invention proposes a novel boost converter, which can correspond to different current modes and load modes. According to actual measurement results, the boost converter designed by the above-mentioned design can effectively improve its output stability, so it is very suitable for application in various devices.

It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The boost converter of the present invention is not limited to the states shown in Figures 1-6. The present invention may include only one or more features of any one or more embodiments of Figures 1-6. In other words, not all of the features shown in the diagrams need to be implemented in the boost converter of the present invention at the same time. Although the embodiments of the present invention use metal oxide semi-conductor field effect transistors as an example, the present invention is not limited to this. People skilled in the art can use other types of transistors, such as junction field effect transistors, or fin field effect transistors, etc., without affecting the effects of the present invention.

Ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to mark and distinguish two different components with the same name.

Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

100,200: Boost converter 110,210: Bridge rectifier 120,220: Power switch 130,230: Output stage circuit 140,240: Detection and control circuit 250: Microcontroller 251: Sampling module 252: Error detection module 253: Counting module 254: Processing module 255: Sensing and comparison module 256: Pulse generation module B1: First bit B2: Second bit B3: Third bit CO: Output capacitor D1: First diode D2: Second diode D3: Third diode D4: Fourth diode D5: Fifth diode ILM: Inductor current IOUT: output current LU: boost inductor MS: switching transistor N1: first node N2: second node N3: third node N4: fourth node NIN1: first input node NIN2: second input node NOUT: output node R1: first resistor R2: second resistor T1: first time interval T2: second time interval T3: third time interval T4: fourth time interval T5: fifth time interval T6: sixth time interval TD: delay interval TZ: zero current time VA: clock potential VIN1: first input potential VIN2: second input potential VOUT: output potential VR: rectified potential VSS: ground potential VTH1: first critical potential VTH2: second critical potential ΔV1: first potential difference ΔV2: second potential difference

FIG. 1 is a schematic diagram of a boost converter according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a boost converter according to an embodiment of the present invention. FIG. 3 is a waveform diagram of an inductor current when the output current of a conventional boost converter gradually increases. FIG. 4 is a waveform diagram of an inductor current when the output current of a conventional boost converter gradually decreases. FIG. 5 is a waveform diagram of an inductor current when the output current of a boost converter according to an embodiment of the present invention gradually increases. FIG. 6 is a waveform diagram of an inductor current when the output current of a boost converter according to an embodiment of the present invention gradually decreases.

100: Boost converter 110: Bridge rectifier 120: Power switch 130: Output stage circuit 140: Detection and control circuit ILM: Inductor current IOUT: Output current LU: Boost inductor VA: Clock potential VIN1: First input potential VIN2: Second input potential VOUT: Output potential VR: Rectification potential VSS: Ground potential

Claims (10)

A boost converter for improving output stability includes: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a boost inductor, receiving the rectified potential, wherein an inductor current flows through the boost inductor; a power switch, selectively coupling the boost inductor to a ground potential according to a clock potential; an output stage circuit, coupled to the boost inductor and generating an output potential, wherein an output current flows through the output stage circuit; and a detection and control circuit, determining the boost inductor according to the inductor current. A current mode of the output stage circuit is detected, and a load mode of the output stage circuit is determined according to the output current; wherein the detection and control circuit further confirms whether the load mode matches the current mode, and generates the clock potential accordingly; wherein the detection and control circuit includes: a first resistor, wherein the first resistor is coupled in series with the boost inductor; and a microcontroller, wherein the microcontroller includes: a sampling module, detecting a first potential difference across the first resistor, wherein a sampling frequency of the sampling module is equal to a switching frequency of the power switch. A boost converter as claimed in claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; wherein the boost inductor has a first end and a second end, the first end of the boost inductor is coupled to the first node to receive the rectified potential, and the second end of the boost inductor is coupled to a second node. A boost converter as claimed in claim 2, wherein the power switch comprises: a switching transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the switching transistor is used to receive the clock potential, the first terminal of the switching transistor is coupled to the ground potential, and the second terminal of the switching transistor is coupled to a third node. A boost converter as claimed in claim 3, wherein the output stage circuit comprises: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the third node, and the cathode of the fifth diode is coupled to an output node to output the output potential; and an output capacitor having a first end and a second end, wherein the first end of the output capacitor is coupled to the output node, and the second end of the output capacitor is coupled to a fourth node. A boost converter as claimed in claim 4, wherein the detection and control circuit comprises: wherein the first resistor has a first end and a second end, the first end of the first resistor is coupled to the second node, and the second end of the first resistor is coupled to the third node; a second resistor, having a first end and a second end, wherein the first end of the second resistor is coupled to the fourth node, and the second end of the second resistor is coupled to the ground potential; wherein the inductor current further flows through the first resistor, and the output current further flows through the second resistor. The boost converter of claim 5, wherein the microcontroller further comprises: an error detection module, which generates a first bit and a second bit of logical complement according to the first potential difference; wherein if the first potential difference is equal to the ground potential, the error detection module will generate the first bit with a high logical level; wherein if the first potential difference is not equal to the ground potential, the error detection module will generate the first bit with a low logical level. The boost converter of claim 6, wherein the microcontroller further comprises: a counting module, wherein in response to the first bit having a high logic level, the counting module starts to count a zero current time; wherein if the zero current time is equal to 0, the counting module will generate a third bit having a low logic level; wherein if the zero current time is greater than 0, the counting module will generate the third bit having a high logic level. The boost converter of claim 7, wherein the microcontroller further comprises: a processing module, which determines the current mode of the boost inductor according to the first bit, the second bit, and the third bit, wherein the current mode is one of a discontinuous current mode, a boundary current mode, or a continuous current mode. The boost converter of claim 5, wherein the microcontroller further comprises: a sensing and comparison module, detecting a second potential difference across the second resistor, and comparing the second potential difference with a first critical potential and a second critical potential; wherein if the second potential difference is less than the first critical potential, the sensing and comparison module determines that the output stage circuit operates in a light load mode; wherein if the second potential difference is between the first critical potential and the second critical potential, the sensing and comparison module determines that the output stage circuit operates in a medium load mode; wherein if the second potential difference is greater than the second critical potential, the sensing and comparison module determines that the output stage circuit operates in a heavy load mode. The boost converter of claim 9, wherein the microcontroller further comprises: a clock generation module, which is controlled by the sensing and comparison module and generates the clock potential; wherein if the output stage circuit changes the load mode, the clock generation module will provide a delay interval to the clock potential, and the delay interval is greater than or equal to 25μs.

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