TWI717838B

TWI717838B - Power supply device

Info

Publication number: TWI717838B
Application number: TW108133527A
Authority: TW
Inventors: 詹子增
Original assignee: 宏碁股份有限公司
Priority date: 2019-09-18
Filing date: 2019-09-18
Publication date: 2021-02-01
Also published as: TW202113529A

Abstract

A power supply device with a target output value includes a power supply module, a first capacitor, a second capacitor, a voltage detector, and a voltage balancer. The power supply module generates an output voltage. The voltage detector controls the voltage balancer to selectively operate in a first mode, a second mode, or a third mode. In the second mode, the voltage balancer decreases the maximum value of the output voltage by a predetermined percentage of the target output value, and increases the minimum value of the output voltage by the predetermined percentage of the target output value. In the third mode, the voltage balancer decreases the maximum value of the output voltage by twice the predetermined percentage of the target output value, and increases the minimum value of the output voltage by twice the predetermined percentage of the target output value.

Description

Power Supplier

本發明係關於一種電源供應器，特別係關於一種可提升輸出穩定度之電源供應器。The present invention relates to a power supply, and more particularly to a power supply capable of improving output stability.

傳統電源供應器之輸出端通常採用並聯之多個電容器以提供輸出電位。然而，因為這些電容器本身之電容值誤差及其等效串聯電阻值(Equivalent Series Resistance，ESR)不一致，往往導致電源供應器之輸出電位可能超出額定輸出值之可接受範圍。有鑑於此，勢必要提出一種全新之解決方案，以克服先前技術所遭遇之困境。The output terminal of the traditional power supply usually uses multiple capacitors connected in parallel to provide the output potential. However, because the capacitance error of these capacitors and their Equivalent Series Resistance (ESR) are inconsistent, the output potential of the power supply may exceed the acceptable range of the rated output value. In view of this, it is necessary to propose a new solution to overcome the difficulties encountered by the previous technology.

在較佳實施例中，本發明提出一種電源供應器，具有一額定輸出值，並包括：一電源供應模組，產生一輸出電位；一第一電容器，具有一第一等效串聯電阻值；一第二電容器，具有一第二等效串聯電阻值，其中該第二電容器係與該第一電容器並聯耦接至該電源供應模組，而該第一電容器和該第二電容器皆用於儲存該輸出電位；一電位偵測器，偵測該輸出電位之一最高電位值和一最低電位值之間之一電位差值，並根據該電位差值來產生一控制電位；以及一電位平衡器，根據該控制電位來選擇性地操作於一第一模式、一第二模式，或是一第三模式；其中在該第一模式中，該電位平衡器不會改變該輸出電位；其中在該第二模式中，該電位平衡器會將該最高電位值降低該額定輸出值之一既定比率，並將該最低電位值提高該額定輸出值之該既定比率；其中在該第三模式中，該電位平衡器會將該最高電位值降低該額定輸出值之該既定比率之2倍，並將該最低電位值提高該額定輸出值之該既定比率之2倍。In a preferred embodiment, the present invention provides a power supply having a rated output value, and including: a power supply module, which generates an output potential; a first capacitor, which has a first equivalent series resistance; A second capacitor having a second equivalent series resistance value, wherein the second capacitor is coupled to the power supply module in parallel with the first capacitor, and the first capacitor and the second capacitor are both used for storage The output potential; a potential detector that detects a potential difference between a highest potential value and a lowest potential value of the output potential, and generates a control potential based on the potential difference; and a potential balancer, according to The control potential is used to selectively operate in a first mode, a second mode, or a third mode; wherein in the first mode, the potential balancer does not change the output potential; wherein in the second mode In mode, the potential balancer will reduce the highest potential value by a predetermined ratio of the rated output value, and increase the lowest potential value by the predetermined ratio of the rated output value; wherein in the third mode, the potential balance The device reduces the maximum potential value by 2 times the predetermined rate of the rated output value, and increases the minimum potential value by 2 times the predetermined rate of the rated output value.

為讓本發明之目的、特徵和優點能更明顯易懂，下文特舉出本發明之具體實施例，並配合所附圖式，作詳細說明如下。In order to make the purpose, features and advantages of the present invention more comprehensible, specific embodiments of the present invention are listed below, with the accompanying drawings, and detailed descriptions are as follows.

在說明書及申請專利範圍當中使用了某些詞彙來指稱特定的元件。本領域技術人員應可理解，硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明書及申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及申請專利範圍當中所提及的「包含」及「包括」一詞為開放式的用語，故應解釋成「包含但不僅限定於」。「大致」一詞則是指在可接受的誤差範圍內，本領域技術人員能夠在一定誤差範圍內解決所述技術問題，達到所述基本之技術效果。此外，「耦接」一詞在本說明書中包含任何直接及間接的電性連接手段。因此，若文中描述一第一裝置耦接至一第二裝置，則代表該第一裝置可直接電性連接至該第二裝置，或經由其它裝置或連接手段而間接地電性連接至該第二裝置。Certain words are used in the specification and the scope of the patent application to refer to specific elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and the scope of patent application do not use differences in names as a way to distinguish elements, but use differences in functions of elements as a criterion. The terms "including" and "including" mentioned in the entire specification and the scope of the patent application are open-ended terms, so they should be interpreted as "including but not limited to". The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the term "coupling" includes any direct and indirect electrical connection means in this specification. Therefore, if it is described that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting means. Two devices.

第1圖係顯示根據本發明一實施例所述之電源供應器100之示意圖。例如，電源供應器100可以應用於桌上型電腦、筆記型電腦，或一體成形電腦。如第1圖所示，電源供應器100包括：一電源供應模組110、一第一電容器C1、一第二電容器C2、一電位偵測器120，以及一電位平衡器130。必須注意的是，雖然未顯示於第1圖中，但電源供應器100更可包括其他元件，例如：一穩壓器或(且)一負回授電路。FIG. 1 shows a schematic diagram of a power supply 100 according to an embodiment of the invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an integrated computer. As shown in FIG. 1, the power supply 100 includes a power supply module 110, a first capacitor C1, a second capacitor C2, a potential detector 120, and a potential balancer 130. It should be noted that although not shown in Figure 1, the power supply 100 may further include other components, such as a voltage regulator or (and) a negative feedback circuit.

電源供應模組110係用於產生一輸出電位VOUT。例如，電源供應模組110可包括一橋式整流器、一輸入電容器、一變壓器、一功率切換器、一輸出級電路，以及一控制器(未顯示)。電源供應模組110具有一第一輸出節點NOUT1和一第二輸出節點NOUT2，其中第一輸出節點NOUT1可用於提供輸出電位VOUT，而第二輸出節點NOUT2可用於提供一接地電位VSS。第一電容器C1具有一第一等效串聯電阻值RE1。第二電容器C2具有一第二等效串聯電阻值RE2。第二電容器C2係與第一電容器C1並聯耦接於第一輸出節點NOUT1和第二輸出節點NOUT2之間，其中第一電容器C1和第二電容器C2皆可用於儲存輸出電位VOUT。詳細而言，第一電容器C1之第一端係耦接至第一輸出節點NOUT1，而第一電容器C1之第二端係耦接至第二輸出節點NOUT2。第二電容器C2之第一端係耦接至第一輸出節點NOUT1，而第二電容器C2之第二端係耦接至第二輸出節點NOUT2。 The power supply module 110 is used to generate an output potential VOUT. For example, the power supply module 110 may include a bridge rectifier, an input capacitor, a transformer, a power switch, an output stage circuit, and a controller (not shown). The power supply module 110 has a first output node NOUT1 and a second output node NOUT2. The first output node NOUT1 can be used to provide an output potential VOUT, and the second output node NOUT2 can be used to provide a ground potential VSS. The first capacitor C1 has a first equivalent series resistance value RE1. The second capacitor C2 has a second equivalent series resistance value RE2. The second capacitor C2 is coupled in parallel with the first capacitor C1 between the first output node NOUT1 and the second output node NOUT2. Both the first capacitor C1 and the second capacitor C2 can be used to store the output potential VOUT. In detail, the first end of the first capacitor C1 is coupled to the first output node NOUT1, and the second end of the first capacitor C1 is coupled to the second output node NOUT2. The first end of the second capacitor C2 is coupled to the first output node NOUT1, and the second end of the second capacitor C2 is coupled to the second output node NOUT2.

第2圖係顯示根據本發明一實施例所述之電源供應器100之輸出電位VOUT之波形圖。在理想情況下，輸出電位VOUT應恆等於電源供應器100之一額定輸出值VA，例如：19V。實際上，由於第一電容器C1和第二電容器C2有電容值誤差且第一等效串聯電阻值RE1與第二等效串聯電阻值RE2不同，故輸出電位VOUT會發生波動並具有一最高電位值VMAX和一最低電位值VMIN。有時候，最高電位值VMAX可能高於額定輸出值VA之105%，或是最低電位值VMIN可能低於額定輸出值VA之95%，此二者均代表電源供應器100之輸出穩定度不足。為解決此一問題，本發明提出一種全新解決方案，請參考下列實施例所述。 FIG. 2 is a waveform diagram of the output potential VOUT of the power supply 100 according to an embodiment of the invention. In an ideal situation, the output potential VOUT should always be equal to one of the rated output values VA of the power supply 100, for example: 19V. In fact, because the first capacitor C1 and the second capacitor C2 have capacitance errors and the first equivalent series resistance value RE1 is different from the second equivalent series resistance value RE2, the output potential VOUT will fluctuate and have a highest potential value. VMAX and a minimum potential value VMIN. Sometimes, the highest potential value VMAX may be higher than 105% of the rated output value VA, or the lowest potential value VMIN may be lower than 95% of the rated output value VA, both of which indicate that the output stability of the power supply 100 is insufficient. In order to solve this problem, the present invention proposes a new solution, please refer to the following embodiments.

電位偵測器120可偵測輸出電位VOUT之最高電位值VMAX和最低電位值VMIN之間之一電位差值VD(亦即，VD=VMAX-VMIN)，並根據電位差值VD來產生一控制電位VC。電位平衡器130係根據控制電位VC來選擇性地操作於一第一模式、一第二模式，或是一第三模式。在一些實施例中，若電位差值VD低於額定輸出值VA之10%(亦即，VD<VA．10%)，則電位平衡器130將操作於第一模式，若電位差值VD介於額定輸出值VA之10%至20%之間(亦即，VA．10%

VD<VA．20%)，則電位平衡器130將操作於第二模式，而若電位差值VD介於額定輸出值VA之20%至30%之間(亦即，

，則電位平衡器130將操作於第三模式。必須注意的是，若電位差值VD高於額定輸出值VA之30%(亦即，

，則電源供應模組110會使用其他過載保護機制，故在此不細加討論。 The potential detector 120 can detect a potential difference VD between the highest potential value VMAX and the lowest potential value VMIN of the output potential VOUT (that is, VD=VMAX-VMIN), and generate a control potential VC according to the potential difference VD . The potential balancer 130 selectively operates in a first mode, a second mode, or a third mode according to the control potential VC. In some embodiments, if the potential difference VD is less than 10% of the rated output value VA (that is, VD<VA.10%), the potential balancer 130 will operate in the first mode. If the potential difference VD is between the rated output value VA, Between 10% and 20% of the output value VA (that is, VA. 10%

VD<VA. 20%), the potential balancer 130 will operate in the second mode, and if the potential difference VD is between 20% and 30% of the rated output value VA (that is,

, The potential balancer 130 will operate in the third mode. It must be noted that if the potential difference VD is higher than 30% of the rated output value VA (that is,

, The power supply module 110 will use other overload protection mechanisms, so it will not be discussed in detail here.

在第一模式中，電位平衡器130不會改變輸出電位VOUT。第3圖係顯示根據本發明一實施例所述之第二模式下之輸出電位VOUT之波形圖。在第二模式中，電位平衡器130會將最高電位值VMAX降低額定輸出值VA之一既定比率P%(亦即，

)，並將最低電位值VMIN提高額定輸出值VA之既定比率P%(亦即，

)。例如，此既定比率P%可為2%、3%，或是4%，但亦不僅限於此。第4圖係顯示根據本發明一實施例所述之第三模式下之輸出電位VOUT之波形圖。在第三模式中，電位平衡器130會將最高電位值VMAX降低額定輸出值VA之既定比率P%之2倍(亦即，

)，並將最低電位值VMIN提高額定輸出值VA之既定比率P%之2倍(亦即，

)。在此設計下，即使最高電位值VMAX太高或是最低電位值VMIN太低，電位偵測器120和電位平衡器130都可以動態地壓縮輸出電位VOUT之電位差值VD，使得最終之輸出電位VOUT能更趨近於額定輸出值VA。因此，電源供應器100之輸出穩定度將能獲得有效提升。 In the first mode, the potential balancer 130 does not change the output potential VOUT. Fig. 3 shows a waveform diagram of the output potential VOUT in the second mode according to an embodiment of the present invention. In the second mode, the potential balancer 130 reduces the maximum potential value VMAX by a predetermined ratio P% of the rated output value VA (that is,

), and increase the minimum potential value VMIN by the predetermined ratio P% of the rated output value VA (that is,

). For example, the predetermined ratio P% can be 2%, 3%, or 4%, but it is not limited to this. FIG. 4 is a waveform diagram of the output potential VOUT in the third mode according to an embodiment of the present invention. In the third mode, the potential balancer 130 reduces the maximum potential value VMAX by 2 times the predetermined rate P% of the rated output value VA (ie,

), and increase the minimum potential value VMIN by 2 times the predetermined ratio P% of the rated output value VA (that is,

). Under this design, even if the highest potential value VMAX is too high or the lowest potential value VMIN is too low, both the potential detector 120 and the potential balancer 130 can dynamically compress the potential difference VD of the output potential VOUT, so that the final output potential VOUT Can be closer to the rated output value VA. Therefore, the output stability of the power supply 100 can be effectively improved.

在一些實施例中，電源供應器100之元件參數可如下列所述。第一電容器C1之電容值可介於544μF至816μF之間，例如：680μF。第一等效串聯電阻值RE1可介於0.05Ω至1Ω之間，例如：0.1Ω。第二電容器C2之電容值可介於544μF至816μF之間，例如：680μF。第二等效串聯電阻值RE2可介於0.05Ω至1Ω之間，例如：0.1Ω。以上元件參數係根據多次實驗結果而得出，其有助於最佳化電源供應器100之輸出穩定度。In some embodiments, the component parameters of the power supply 100 may be as follows. The capacitance value of the first capacitor C1 can be between 544 μF and 816 μF, for example, 680 μF. The first equivalent series resistance value RE1 may be between 0.05Ω and 1Ω, for example, 0.1Ω. The capacitance value of the second capacitor C2 can be between 544 μF and 816 μF, for example, 680 μF. The second equivalent series resistance value RE2 may be between 0.05Ω and 1Ω, for example: 0.1Ω. The above component parameters are obtained based on the results of many experiments, which help to optimize the output stability of the power supply 100.

第5圖係顯示根據本發明另一實施例所述之電源供應器500之示意圖。第5圖和第1圖相似。在第5圖之實施例中，電源供應器500更包括一第一電阻器R1、一第二電阻器R2、一第一二極體D1，以及一第二二極體D2。第一電阻器R1之第一端係耦接至電位偵測器120，而第一電阻器R1之第二端係耦接至第一輸出節點NOUT1。第二電阻器R2之第一端係耦接至電位偵測器120，而第二電阻器R2之第二端係耦接至第一輸出節點NOUT1。第一電阻器R1和第二電阻器R2之每一者之電阻值皆可介於0.9MΩ至1.1MΩ之間，例如：1MΩ。根據實際量測結果，第一電阻器R1和第二電阻器R2可用於避免電位偵測器120汲取過大之輸出電流。第一二極體D1之陽極係耦接至電位平衡器130，而第一二極體D1之陰極係耦接至第一輸出節點NOUT1。第二二極體D2之陽極係耦接至電位平衡器130，而第二二極體D2之陰極係耦接至第二輸出節點NOUT2。根據實際量測結果，第一二極體D1和第二二極體D2可用於避免輸出電流回灌至電位平衡器130。第5圖之電源供應器500之其餘特徵皆與第1圖之電源供應器100類似，故此二實施例均可達成相似之操作效果。FIG. 5 is a schematic diagram of a power supply 500 according to another embodiment of the invention. Figure 5 is similar to Figure 1. In the embodiment of FIG. 5, the power supply 500 further includes a first resistor R1, a second resistor R2, a first diode D1, and a second diode D2. The first end of the first resistor R1 is coupled to the potential detector 120, and the second end of the first resistor R1 is coupled to the first output node NOUT1. The first end of the second resistor R2 is coupled to the potential detector 120, and the second end of the second resistor R2 is coupled to the first output node NOUT1. The resistance value of each of the first resistor R1 and the second resistor R2 can be between 0.9MΩ and 1.1MΩ, for example: 1MΩ. According to the actual measurement result, the first resistor R1 and the second resistor R2 can be used to prevent the potential detector 120 from drawing excessive output current. The anode of the first diode D1 is coupled to the potential balancer 130, and the cathode of the first diode D1 is coupled to the first output node NOUT1. The anode of the second diode D2 is coupled to the potential balancer 130, and the cathode of the second diode D2 is coupled to the second output node NOUT2. According to the actual measurement result, the first diode D1 and the second diode D2 can be used to prevent the output current from flowing back to the potential balancer 130. The remaining features of the power supply 500 in FIG. 5 are similar to those of the power supply 100 in FIG. 1, so the two embodiments can achieve similar operation effects.

以下實施例將介紹電位偵測器120和電位平衡器130之詳細結構及操作方式。必須理解的是，這些圖式和敘述僅為舉例，而非用於限制本發明之範圍。The following embodiments will introduce the detailed structure and operation of the potential detector 120 and the potential balancer 130. It must be understood that these drawings and descriptions are only examples and are not used to limit the scope of the present invention.

第6圖係顯示根據本發明一實施例所述之電位偵測器120之示意圖。在第6圖之實施例中，電位偵測器120包括一偵測單元122、一減法器124，以及一比較器126。偵測單元122可於一段測試時間內偵測出輸出電位VOUT之最高電位值VMAX和最低電位值VMIN。減法器124可將最高電位值VMAX減去最低電位值VMIN，以產生電位差值VD。比較器126可將電位差值VD與一臨界值VTH作比較，以產生控制電位VC。詳細而言，比較器126具有一正輸入端、一負輸入端，以及一輸出端，其中比較器126之正輸入端係用於接收電位差值VD，比較器126之負輸入端係用於接收臨界值VTH，而比較器126之輸出端係用於輸出控制電位VC。臨界值VTH可等於額定輸出值VA之10%或20%。在一些實施例中，係先將臨界值VTH設定為額定輸出值VA之10%，然後再將之改為額定輸出值VA之20%，使得電位平衡器130可根據控制電位VC來判斷現應操作於第一模式、第二模式，或是第三模式。FIG. 6 shows a schematic diagram of the potential detector 120 according to an embodiment of the invention. In the embodiment of FIG. 6, the potential detector 120 includes a detection unit 122, a subtractor 124, and a comparator 126. The detection unit 122 can detect the highest potential value VMAX and the lowest potential value VMIN of the output potential VOUT within a period of testing time. The subtractor 124 may subtract the lowest potential value VMIN from the highest potential value VMAX to generate a potential difference value VD. The comparator 126 can compare the potential difference VD with a threshold value VTH to generate the control potential VC. In detail, the comparator 126 has a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the comparator 126 is used to receive the potential difference VD, and the negative input terminal of the comparator 126 is used to receive The threshold value VTH, and the output terminal of the comparator 126 is used to output the control potential VC. The threshold value VTH can be equal to 10% or 20% of the rated output value VA. In some embodiments, the threshold value VTH is first set to 10% of the rated output value VA, and then changed to 20% of the rated output value VA, so that the potential balancer 130 can determine the current value according to the control potential VC Operate in the first mode, the second mode, or the third mode.

第7圖係顯示根據本發明一實施例所述之電位平衡器130之示意圖。在第7圖之實施例中，電位平衡器130包括一放大器132、一電晶體M1、一第三電阻器R3、一第四電阻器R4、一第三電容器C3，以及一第四電容器C4。放大器132可為一運算放大器。放大器132之正輸入端係耦接至一第一節點N1，放大器132之負輸入端係耦接至一第二節點N2以接收一調整電位VT，而放大器132之輸出端係耦接至一第三節點N3。調整電位VT可根據控制電位VC來決定。第三電阻器R3之第一端係耦接至第一節點N1，而第三電阻器R3之第二端係耦接至第三節點N3。第三電容器C3之第一端係耦接至第一節點N1，而第三電容器C3之第二端係耦接至第一輸出節點NOUT1。電晶體M1可為一N型金氧半場效電晶體。電晶體M1之控制端係耦接至第三節點N3，電晶體M1之第一端係耦接至接地電位VSS，而電晶體M1之第二端係耦接至第一輸出節點NOUT1。第四電阻器R4之第一端係耦接至第二節點N2，而第四電阻器R4之第二端係耦接至第三節點N3。第四電容器C4之第一端係耦接至第三節點N3，而第四電容器C4之第二端係耦接至接地電位VSS。在一些實施例中，調整電位VT可等於接地電位VSS，或是額定輸出值VA之既定比率P%之1倍或2倍(亦即，VA．P%或VA．2．P%)。例如，若電位平衡器130操作於第一模式，則調整電位VT可等於VSS，若電位平衡器130操作於第二模式，則調整電位VT可等於額定輸出值VA之既定比率P%，而若電位平衡器130操作於第三模式，則調整電位VT可等於額定輸出值VA之既定比率P%之2倍。 FIG. 7 shows a schematic diagram of the potential balancer 130 according to an embodiment of the invention. In the embodiment of FIG. 7, the potential balancer 130 includes an amplifier 132, a transistor M1, a third resistor R3, a fourth resistor R4, a third capacitor C3, and a fourth capacitor C4. The amplifier 132 may be an operational amplifier. The positive input terminal of the amplifier 132 is coupled to a first node N1, the negative input terminal of the amplifier 132 is coupled to a second node N2 to receive a tuning potential VT, and the output terminal of the amplifier 132 is coupled to a first node N2. Three node N3. The adjustment potential VT can be determined according to the control potential VC. The first end of the third resistor R3 is coupled to the first node N1, and the second end of the third resistor R3 is coupled to the third node N3. The first end of the third capacitor C3 is coupled to the first node N1, and the second end of the third capacitor C3 is coupled to the first output node NOUT1. The transistor M1 can be an N-type metal oxide half field effect transistor. The control terminal of the transistor M1 is coupled to the third node N3, the first terminal of the transistor M1 is coupled to the ground potential VSS, and the second terminal of the transistor M1 is coupled to the first output node NOUT1. The first end of the fourth resistor R4 is coupled to the second node N2, and the second end of the fourth resistor R4 is coupled to the third node N3. The first terminal of the fourth capacitor C4 is coupled to the third node N3, and the second terminal of the fourth capacitor C4 is coupled to the ground potential VSS. In some embodiments, the adjustment potential VT may be equal to the ground potential VSS, or 1 or 2 times the predetermined ratio P% of the rated output value VA (ie, VA.P% or VA.2.P%). For example, if the potential balancer 130 is operating in the first mode, the adjustment potential VT can be equal to VSS, if the potential balancer 130 is operating in the second mode, the adjustment potential VT can be equal to the predetermined ratio P% of the rated output value VA, and if When the potential balancer 130 operates in the third mode, the adjusted potential VT can be equal to twice the predetermined ratio P% of the rated output value VA.

在另一些實施例中，調整電位VT為具有不同工作週期(Duty Cycle)之脈衝。第8A圖係顯示根據本發明一實施例所述之第一模式下之調整電位VT之波形圖。在第一模式中，調整電位VT之一第一工作週期可等於0。第8B圖係顯示根據本發明一實施例所述之第二模式下之調整電位VT之波形圖。在第二模式中，調整電位VT之一第二工作週期可等於一既定長度TC。第8C圖係顯示根據本發明一實施例所述之第三模式下之調整電位VT之波形圖。在第三模式中，調整電位VT之一第三工作週期可等於前述既定長度TC之2倍。In other embodiments, the adjustment potential VT is pulses with different duty cycles. FIG. 8A shows a waveform diagram of the adjustment potential VT in the first mode according to an embodiment of the present invention. In the first mode, a first duty cycle of the adjustment potential VT may be equal to zero. FIG. 8B is a waveform diagram showing the adjustment potential VT in the second mode according to an embodiment of the present invention. In the second mode, a second duty cycle of the adjustment potential VT can be equal to a predetermined length TC. Fig. 8C is a waveform diagram of the adjustment potential VT in the third mode according to an embodiment of the present invention. In the third mode, a third duty cycle of the adjustment potential VT can be equal to twice the predetermined length TC.

本發明提出一種新穎之電源供應器，其包括一電位偵測器和一電位平衡器，用於自動校正電容器所儲存之輸出電位。根據實際量測結果，使用前述電位偵測器和電位平衡器之電源供應器可大幅提升其輸出穩定度。因此，本發明之電源供應器很適合應用於各種各式高輸出效率之電子裝置當中。The present invention provides a novel power supply, which includes a potential detector and a potential balancer for automatically calibrating the output potential stored in the capacitor. According to the actual measurement results, the power supply using the aforementioned potential detector and potential balancer can greatly improve its output stability. Therefore, the power supply of the present invention is very suitable for use in various electronic devices with high output efficiency.

值得注意的是，以上所述之電位、電流、電阻值、電感值、電容值，以及其餘元件參數均非為本發明之限制條件。設計者可以根據不同需要調整這些設定值。本發明之電源供應器並不僅限於第1-8圖所圖示之狀態。本發明可以僅包括第1-8圖之任何一或複數個實施例之任何一或複數項特徵。換言之，並非所有圖示之特徵均須同時實施於本發明之電源供應器當中。雖然本發明之實施例係使用金氧半場效電晶體為例，但本發明並不僅限於此，本技術領域人士可改用其他種類之電晶體，例如：接面場效電晶體，或是鰭式場效電晶體等等，而不致於影響本發明之效果。It should be noted that the above-mentioned potential, current, resistance value, inductance value, capacitance value, and other component parameters are not the limiting conditions of the present invention. The designer can adjust these settings according to different needs. The power supply of the present invention is not limited to the state shown in Figures 1-8. The present invention may only include any one or more of the features of any one or more of the embodiments in FIGS. 1-8. In other words, not all the features shown in the figures need to be implemented in the power supply of the present invention at the same time. Although the embodiment of the present invention uses metal oxide half field effect transistors as an example, the present invention is not limited to this. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fins. Type field effect transistors, etc., without affecting the effect of the present invention.

在本說明書以及申請專利範圍中的序數，例如「第一」、「第二」、「第三」等等，彼此之間並沒有順序上的先後關係，其僅用於標示區分兩個具有相同名字之不同元件。The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., do not have a sequential relationship between each other, and they are only used to distinguish two having the same Different components of the name.

本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention is disclosed as above in a preferred embodiment, it is not intended to limit the scope of the present invention. Anyone who is familiar with the art can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100、500:電源供應器 110:電源供應模組 120:電位偵測器 122:偵測單元 124:減法器 126:比較器 130:電位平衡器 132:放大器 C1:第一電容器 C2:第二電容器 C3:第三電容器 C4:第四電容器 D1:第一二極體 D2:第二二極體 M1:電晶體 N1:第一節點 N2:第二節點 N3:第三節點 NOUT1:第一輸出節點 NOUT2:第二輸出節點 P%:既定比率 R1:第一電阻器 R2:第二電阻器 R3:第三電阻器 R4:第四電阻器 RE1:第一等效串聯電阻值 RE2:第二等效串聯電阻值 TC:既定長度 VA:額定輸出值 VC:控制電位 VD:輸出電位之電位差值 VOUT:輸出電位 VMAX:輸出電位之最高電位值 VMIN:輸出電位之最低電位值 VT:調整電位 VTH:臨界值 VSS:接地電位 100, 500: power supply 110: Power supply module 120: Potential detector 122: detection unit 124: Subtractor 126: Comparator 130: Potential balancer 132: Amplifier C1: The first capacitor C2: second capacitor C3: third capacitor C4: The fourth capacitor D1: The first diode D2: The second diode M1: Transistor N1: the first node N2: second node N3: third node NOUT1: the first output node NOUT2: second output node P%: established ratio R1: first resistor R2: second resistor R3: third resistor R4: Fourth resistor RE1: The first equivalent series resistance value RE2: Second equivalent series resistance value TC: established length VA: Rated output value VC: control potential VD: Potential difference of output potential VOUT: output potential VMAX: The highest potential value of the output potential VMIN: The lowest potential value of the output potential VT: Adjust potential VTH: critical value VSS: Ground potential

第1圖係顯示根據本發明一實施例所述之電源供應器之示意圖。第2圖係顯示根據本發明一實施例所述之電源供應器之輸出電位之波形圖。第3圖係顯示根據本發明一實施例所述之第二模式下之輸出電位之波形圖。第4圖係顯示根據本發明一實施例所述之第三模式下之輸出電位之波形圖。第5圖係顯示根據本發明另一實施例所述之電源供應器之示意圖。第6圖係顯示根據本發明一實施例所述之電位偵測器之示意圖。第7圖係顯示根據本發明一實施例所述之電位平衡器之示意圖。第8A圖係顯示根據本發明一實施例所述之第一模式下之調整電位之波形圖。第8B圖係顯示根據本發明一實施例所述之第二模式下之調整電位之波形圖。第8C圖係顯示根據本發明一實施例所述之第三模式下之調整電位之波形圖。 Fig. 1 is a schematic diagram of a power supply according to an embodiment of the invention. Figure 2 is a waveform diagram showing the output potential of the power supply according to an embodiment of the invention. Fig. 3 is a waveform diagram of the output potential in the second mode according to an embodiment of the present invention. Figure 4 is a waveform diagram of the output potential in the third mode according to an embodiment of the present invention. Fig. 5 is a schematic diagram of a power supply according to another embodiment of the invention. Fig. 6 shows a schematic diagram of a potential detector according to an embodiment of the invention. Fig. 7 is a schematic diagram of a potential balancer according to an embodiment of the invention. FIG. 8A is a waveform diagram showing the adjustment potential in the first mode according to an embodiment of the present invention. FIG. 8B is a waveform diagram of the adjusted potential in the second mode according to an embodiment of the present invention. Fig. 8C is a waveform diagram showing the adjustment potential in the third mode according to an embodiment of the present invention.

100:電源供應器 100: power supply

110:電源供應模組 110: Power supply module

120:電位偵測器 120: Potential detector

130:電位平衡器 130: Potential balancer

C1:第一電容器 C1: The first capacitor

C2:第二電容器 C2: second capacitor

NOUT1:第一輸出節點 NOUT1: the first output node

NOUT2:第二輸出節點 NOUT2: second output node

P%:既定比率 P%: established ratio

RE1:第一等效串聯電阻值 RE1: The first equivalent series resistance value

RE2:第二等效串聯電阻值 RE2: Second equivalent series resistance value

VA:額定輸出值 VA: Rated output value

VC:控制電位 VC: control potential

VD:輸出電位之電位差值 VD: Potential difference of output potential

VOUT:輸出電位 VOUT: output potential

VMAX:輸出電位之最高電位值 VMAX: The highest potential value of the output potential

VMIN:輸出電位之最低電位值 VMIN: The lowest potential value of the output potential

Claims

A power supply has a rated output value and includes: A power supply module generates an output potential; A first capacitor having a first equivalent series resistance value; A second capacitor having a second equivalent series resistance value, wherein the second capacitor is coupled to the power supply module in parallel with the first capacitor, and the first capacitor and the second capacitor are both used for storage The output potential; A potential detector, which detects a potential difference between a highest potential value and a lowest potential value of the output potential, and generates a control potential according to the potential difference; and A potential balancer selectively operating in a first mode, a second mode, or a third mode according to the control potential; Wherein in the first mode, the potential balancer will not change the output potential; Wherein in the second mode, the potential balancer will reduce the highest potential value by a predetermined ratio of the rated output value, and increase the lowest potential value by the predetermined ratio of the rated output value; Wherein in the third mode, the potential balancer reduces the maximum potential value by 2 times the predetermined ratio of the rated output value, and increases the minimum potential value by 2 times the predetermined ratio of the rated output value.

For example, the power supply described in item 1 of the scope of patent application, wherein if the potential difference is less than 10% of the rated output value, the potential balancer will operate in the first mode, if the potential difference is within the rated output value Between 10% and 20% of the output value, the potential balancer will operate in the second mode, and if the potential difference is between 20% and 30% of the rated output value, the potential balancer will Operate in this third mode.

For the power supply described in item 1 of the scope of patent application, the predetermined ratio is 2%.

The power supply according to claim 1, wherein the first capacitor has a first terminal and a second terminal, and the first terminal of the first capacitor is coupled to a first output node to provide For the output potential, the second terminal of the first capacitor is coupled to a second output node to provide a ground potential, the second capacitor has a first terminal and a second terminal, and the second terminal of the second capacitor One end is coupled to the first output node, and the second end of the second capacitor is coupled to the second output node.

The power supply described in item 4 of the scope of patent application includes: A first resistor has a first end and a second end, wherein the first end of the first resistor is coupled to the potential detector, and the second end of the first resistor is Coupled to the first output node; and A second resistor has a first end and a second end, wherein the first end of the second resistor is coupled to the potential detector, and the second end of the second resistor is Coupled to the first output node.

The power supply described in item 4 of the scope of patent application includes: A first diode has an anode and a cathode, wherein the anode of the first diode is coupled to the potential balancer, and the cathode of the first diode is coupled to the first Output node; and A second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the potential balancer, and the cathode of the second diode is coupled to the second Output node.

The power supply described in item 4 of the scope of patent application, wherein the potential detector includes: A detection unit for detecting the highest potential value and the lowest potential value of the output potential; A subtractor that subtracts the lowest potential value from the highest potential value to generate the potential difference value; and A comparator that compares the potential difference with a critical value to generate the control potential; The critical value is equal to 10% or 20% of the rated output value.

The power supply described in item 4 of the scope of patent application, wherein the potential balancer includes: An amplifier has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the amplifier is coupled to a first node, and the negative input terminal of the amplifier is coupled to a second node Node to receive an adjustment potential, and the output terminal of the amplifier is coupled to a third node; A third resistor has a first end and a second end, wherein the first end of the third resistor is coupled to the first node, and the second end of the third resistor is coupled Connected to the third node; A third capacitor has a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the first node, and the second terminal of the third capacitor is coupled to the The first output node; and A transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the transistor is coupled to the third node, and the first terminal of the transistor is coupled to the Ground potential, and the second terminal of the transistor is coupled to the first output node.

The power supply described in item 8 of the scope of patent application, wherein the potential balancer further includes: A fourth resistor has a first end and a second end, wherein the first end of the fourth resistor is coupled to the second node, and the second end of the fourth resistor is coupled Connected to the third node; and A fourth capacitor has a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the third node, and the second terminal of the fourth capacitor is coupled to the Ground potential.

The power supply described in item 8 of the scope of patent application, wherein the adjustment potential is equal to 1 or 2 times the predetermined ratio of the rated output value.