CN113541512B

CN113541512B - Boost converter

Info

Publication number: CN113541512B
Application number: CN202010284530.9A
Authority: CN
Inventors: 詹子增
Original assignee: Acer Inc
Current assignee: Acer Inc
Priority date: 2020-04-13
Filing date: 2020-04-13
Publication date: 2022-07-26
Anticipated expiration: 2040-04-13
Also published as: CN113541512A

Abstract

A boost converter, comprising: the power switch circuit comprises a voltage division circuit, a first comparator, an adjustable inductance element, a power switch, a second comparator, an output stage circuit and a controller. The voltage divider circuit can receive an input potential. The adjustable inductance element is coupled to the voltage dividing circuit, wherein the total inductance value of the adjustable inductance element is controlled by the first comparator. The output stage circuit is coupled to the adjustable inductive element and the power switch. The output stage circuit includes an adjustable resistive element, wherein the total resistance of the adjustable resistive element is controlled by the second comparator. When the boost converter operates in a first mode, an output potential of the output stage circuit has a higher potential level. When the boost converter operates in a second mode, the output voltage of the output stage circuit has a lower voltage level.

Description

Boost converter

Technical Field

The present invention relates to a boost converter, and more particularly, to a boost converter with high conversion efficiency.

Background

In a conventional boost converter, the output voltage is usually maintained at a higher voltage level regardless of the input voltage. However, the output voltage with a higher voltage level is liable to cause a larger power loss, and results in a lower conversion efficiency of the boost converter. In view of the above, a new solution is needed to overcome the dilemma faced by the prior art.

Disclosure of Invention

In a preferred embodiment, the present invention provides a boost converter comprising: a voltage dividing circuit for generating a divided voltage according to an input voltage; a first comparator for comparing the divided voltage potential with a first reference potential to generate a first control potential; an adjustable inductance element coupled to the voltage divider circuit, wherein the total inductance of the adjustable inductance element is adjusted according to the first control potential; a power switch for selectively coupling the tunable inductive element to a ground potential according to a clock potential; a second comparator for comparing the first control potential with a second reference potential to generate a second control potential; an output stage circuit coupled to the adjustable inductive element and the power switch for generating an output voltage according to a third reference voltage and the second control voltage, wherein the output stage circuit includes an adjustable resistive element, and a total resistance of the adjustable resistive element is adjusted according to the second control voltage; and a controller for generating the clock potential, the first reference potential, the second reference potential, and the third reference potential.

Drawings

Fig. 1 is a schematic diagram illustrating a boost converter according to an embodiment of the invention.

Fig. 2 is a schematic diagram illustrating a boost converter according to an embodiment of the invention.

Wherein the reference numerals are as follows:

100, 200: boost converter

110, 210: voltage divider circuit

120, 220: first comparator

130, 230: adjustable inductance element

140, 240: power switch

150, 250: second comparator

160, 260: output stage circuit

170, 270: adjustable resistance element

180, 280: controller for controlling a motor

C1: first capacitor

C2: second capacitor

D1: diode with a high-voltage source

I4: electric current of

L1: first inductor

L2: second inductor

M1: a first transistor

M2: second transistor

M3: a third transistor

N1: first node

N2: second node

N3: third node

N4: fourth node

NIN: input node

NOUT: output node

R1: a first resistor

R2: second resistor

R3: third resistor

R4: fourth resistor

R5: fifth resistor

VA: clock potential

VC 1: a first control potential

VC 2: second control potential

VD: potential of partial voltage

VIN: input potential

VOUT: output potential

VR 1: first reference potential

VR 2: second reference potential

VR 3: third reference potential

VSS: ground potential

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "substantially" is intended to mean within an acceptable error range, within which a person skilled in the art would be able to solve the technical problem and achieve the essential technical result. In addition, the term "coupled" is used in this specification to include any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 is a schematic diagram illustrating a boost converter 100 according to an embodiment of the invention. For example, the boost converter 100 may be applied to a desktop computer, a tablet computer, a notebook computer, or an all-in-one computer. As shown in fig. 1, the boost converter 100 includes: a voltage divider circuit 110, a first comparator 120, an adjustable inductance element 130, a power switch 140, a second comparator 150, an output stage circuit 160, and a controller 180, wherein the output stage circuit 160 includes an adjustable resistance element 170. It should be noted that although not shown in fig. 1, boost converter 100 may also include other elements, such as: a voltage regulator or (and) a negative feedback circuit.

The voltage divider 110 generates a voltage-dividing potential VD according to an input potential VIN, wherein the voltage-dividing potential VD may be only a specific ratio (e.g., 1% to 20%) of the input potential VIN. The input potential VIN may be derived from an external power source, wherein the input potential VIN may be an ac potential with any frequency and any amplitude. For example, the frequency of the AC potential may be about 50Hz or 60Hz, and the root-mean-square value of the AC potential may be about 110V or 220V. The first comparator 120 compares the divided voltage VD with a first reference voltage VR1 to generate a first control voltage VC 1. The adjustable inductive element 130 may be considered a boost inductor of the boost converter 100. The adjustable inductive element 130 is coupled to the voltage divider circuit 110, wherein the total inductance of the adjustable inductive element 130 can be adjusted according to the first control potential VC 1. The power switch 140 selectively couples the tunable inductive element 130 to a ground potential VSS (e.g., 0V) according to a clock potential VA. For example, if the clock potential VA is at a high logic level (e.g., logic "1"), the power switch 140 couples the tunable inductive element 130 to the ground potential VSS (i.e., the power switch 140 may be similar to a short circuit path); conversely, if the clock potential VA is at a low logic level (e.g., logic "0"), the power switch 140 does not couple the tunable inductive element 130 to the ground potential VSS (i.e., the power switch 110 may be approximated by an open circuit path). The second comparator 150 compares the first control potential VC1 with a second reference potential VR2 to generate a second control potential VC 2. The output stage circuit 160 is coupled to the adjustable inductor 130 and the power switch 140, and generates an output voltage VOUT according to a third reference voltage VR3 and the second control voltage VC 2. The output voltage VOUT may be a dc voltage, wherein the voltage level of the output voltage VOUT is higher than the maximum value of the input voltage VIN. The total resistance of the adjustable resistive element 170 of the output stage circuit 160 can be adjusted according to the second control potential VC 2. The controller 180 may be an integrated circuit chip that is configured to generate the clock level VA, the first reference level VR1, the second reference level VR2, and the third reference level VR 3. For example, the clock level VA may be maintained at a fixed level during initialization of the boost converter 100, and may provide a periodic clock waveform after the boost converter 100 enters a normal use stage. In addition, the first reference voltage level VR1, the second reference voltage level VR2, and the third reference voltage level VR3 can be maintained at a constant voltage level. In some embodiments, if the input voltage VIN is higher than or equal to a threshold voltage, the boost converter 100 will operate in a first mode and the output voltage VOUT will have a higher voltage level; conversely, if the input voltage VIN is lower than the threshold voltage, the boost converter 100 will operate in a second mode and the output voltage VOUT will have a lower voltage level. According to the actual measurement result, the design of the dual output mode can avoid the higher power loss caused by the lower input voltage VIN, so the conversion efficiency of the boost converter 100 can be effectively improved.

The following embodiments will describe the detailed structure and operation of the boost converter 100. It must be understood that these drawings and descriptions are only by way of example and are not intended to limit the scope of the invention.

Fig. 2 is a schematic diagram illustrating a boost converter 200 according to an embodiment of the invention. In the embodiment of fig. 2, the boost converter 200 has an input node NIN and an output node NOUT, and includes a voltage divider circuit 210, a first comparator 220, an adjustable inductive element 230, a power switch 240, a second comparator 250, an output stage circuit 260, and a controller 280, wherein the output stage circuit 260 includes an adjustable resistive element 270. The input node NIN of the boost converter 200 receives an input voltage VIN from an external power source, and the output node NOUT of the boost converter 200 is used for outputting an output voltage VOUT, wherein the voltage level of the output voltage VOUT is higher than the maximum value of the input voltage VIN.

The voltage divider 210 includes a first resistor R1, a second resistor R2, and a first capacitor C1. The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to the input node NIN, and the second terminal of the first resistor R1 is coupled to a first node N1 for outputting a divided voltage VD. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to the first node N1, and the second terminal of the second resistor R2 is coupled to a ground potential VSS. The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the first node N1, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS. The potential level of the divided potential VD may be determined according to a resistance ratio of the first resistor R1 and the second resistor R2. In addition, the first capacitor C1 can stabilize the voltage-dividing potential VD of the first node N1 according to actual measurement results.

The first comparator 220 may be implemented by an operational amplifier. In detail, the first comparator 220 has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the first comparator 220 is used for receiving a first reference potential VR1, the negative input terminal of the first comparator 220 is used for receiving the divided potential VD, and the output terminal of the first comparator 220 is used for outputting a first control potential VC 1. For example, if the first reference potential VR1 is higher than or equal to the divided potential VD, the first control potential VC1 will be a high logic level; conversely, if the first reference potential VR1 is lower than the divided potential VD, the first control potential VC1 may be a low logic level.

The adjustable inductance element 230 includes a first inductor L1, a second inductor L2, and a first transistor M1. The first transistor M1 may be an nmos field effect transistor. The first inductor L1 has a first terminal and a second terminal, wherein the first terminal of the first inductor L1 is coupled to the input node NIN, and the second terminal of the first inductor L1 is coupled to a second node N2. The second inductor L2 has a first terminal and a second terminal, wherein the first terminal of the second inductor L2 is coupled to the input node NIN, and the second terminal of the second inductor L2 is coupled to a third node N3. The first transistor M1 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor M1 is for receiving the first control potential VC1, the first terminal of the first transistor M1 is coupled to the third node N3, and the second terminal of the first transistor M1 is coupled to the second node N2. In some embodiments, if the first transistor M1 is enabled, the second inductor L2 will be coupled in parallel with the first inductor L1; conversely, if the first transistor M1 is disabled, the second inductor L2 will not be coupled in parallel with the first inductor L1. Therefore, the total inductance of the adjustable inductance element 230 can be adjusted by the first comparator 220 using the first control potential VC 1.

The power switch 240 includes a second transistor M2. The second transistor M2 may be an nmos field effect transistor. The second transistor M2 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor M2 is used for receiving a clock potential VA, the first terminal of the second transistor M2 is coupled to the ground potential VSS, and the second terminal of the second transistor M2 is coupled to the second node N2. That is, the second transistor M2 can selectively couple the second node N2 to the ground potential VSS.

The second comparator 250 may be implemented by an operational amplifier. In detail, the second comparator 250 has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the second comparator 250 is for receiving a second reference potential VR2, the negative input terminal of the second comparator 250 is for receiving the first control potential VC1, and the output terminal of the second comparator 250 is for outputting a second control potential VC 2. For example, if the second reference potential VR2 is higher than or equal to the first control potential VC1, the second control potential VC2 will be at a high logic level; conversely, if the second reference potential VR2 is lower than the first control potential VC1, the second control potential VC2 can be a low logic level.

In addition to adjustable resistive element 270, output stage circuit 260 includes a diode D1 and a second capacitor C2. The diode D1 has an anode and a cathode, wherein the anode of the diode D1 is coupled to the second node N2, and the cathode of the diode D2 is coupled to the output node NOUT. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the ground potential VSS.

The adjustable resistance element 270 of the output stage 260 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a third transistor M3. The third transistor M3 may be an nmos fet. The third resistor R3 has a first terminal and a second terminal, wherein the first terminal of the third resistor R3 is coupled to the output node NOUT, and the second terminal of the third resistor R3 is coupled to a fourth node N4 for receiving a third reference potential VR 3. The fourth resistor R4 has a first terminal and a second terminal, wherein the first terminal of the fourth resistor R4 is coupled to the fourth node N4, and the second terminal of the fourth resistor R4 is coupled to the ground potential VSS. The third transistor M3 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor M3 is used for receiving the second control potential VC2, the first terminal of the third transistor M3 is coupled to a fifth node N5, and the second terminal of the third transistor M3 is coupled to the fourth node N4. The fifth resistor R5 has a first terminal and a second terminal, wherein the first terminal of the fifth resistor R5 is coupled to the fifth node N5, and the second terminal of the fifth resistor R5 is coupled to the ground potential VSS. In some embodiments, if the third transistor M3 is enabled, the fifth resistor R5 will be coupled in parallel with the fourth resistor R4; conversely, if the third transistor M3 is disabled, the fifth resistor R5 will not be coupled in parallel with the fourth resistor R4. Therefore, the total resistance of the adjustable resistive element 270 can be adjusted by the second comparator 250 using the second control potential VC 2.

The controller 280 may be an integrated circuit chip that is configured to generate the clock potential VA, the first reference potential VR1, the second reference potential VR2, and the third reference potential VR 3. For example, the clock level VA may be maintained at a fixed level (e.g., the ground level VSS) during initialization of the boost converter 200, and may provide a periodic clock waveform after the boost converter 200 enters a normal operation phase. In addition, the first reference voltage level VR1, the second reference voltage level VR2, and the third reference voltage level VR3 can be maintained at a constant voltage level.

In some embodiments, the boost converter 200 operates in either a first mode or a second mode, and the detailed operation principle thereof may be as follows.

If the input potential VIN is higher than or equal to a threshold potential, the boost converter 200 can operate in a first mode. Since the divided voltage VD is higher than the first reference voltage VR1, the first control voltage VC1 is at a low logic level to disable the first transistor M1, so that the total inductance of the adjustable inductor 230 is substantially equal to the inductance of the first inductor L1 (i.e., the total inductance of the adjustable inductor 230 is relatively large). Furthermore, the second control potential VC2 will be at a high logic level to enable the third transistor M3. Since the fifth resistor R5 is coupled in parallel with the fourth resistor R4, the current I4 through the fourth node N4 will be relatively large. In the first mode, the adjustable inductance device 230 stores more energy, and the output voltage VOUT of the boost converter 200 has a higher voltage level.

If the input voltage VIN is lower than the threshold voltage, the boost converter 200 can operate in a second mode. Since the divided voltage VD is lower than the first reference voltage VR1, the first control voltage VC1 is at a high logic level to enable the first transistor M1, so that the total inductance of the adjustable inductor 230 is substantially equal to the parallel inductance of the first inductor L1 and the second inductor L2 (i.e., the total inductance of the adjustable inductor 230 is relatively small). Furthermore, the second control potential VC2 is at a low logic level to disable the third transistor M3. Because the fifth resistor R5 is not coupled in parallel with the fourth resistor R4, the current I4 through the fourth node N4 will be relatively small. In the second mode, the adjustable inductance device 230 stores less energy, and the output voltage VOUT of the boost converter 200 has a lower voltage level.

In summary, two different operation modes of the boost converter 200 can be described as the following table one:

table one: different modes of operation of the boost converter 200

According to practical measurements, this design can reduce the input power of the boost converter 200 in the second mode, thereby improving the conversion efficiency of the boost converter 200 (since the conversion efficiency is the ratio of the output power to the input power, wherein the output power of the boost converter 200 is substantially constant). For example, the conversion efficiency of the boost converter 200 in the second mode can be improved from about 90% to about 94%, but it is not limited thereto.

In some embodiments, the component parameters of the boost converter 200 may be as follows. The critical potential of the input potential VIN may be about 170V. In the first mode, the input voltage VIN may be between 170V and 240V, and the higher level of the output voltage VOUT may be about 400V. In the second mode, the input voltage VIN may be between 100V and 170V, and the lower level of the output voltage VOUT may be about 250V. The resistance value of the first resistor R1 may be approximately equal to 16k omega. The resistance value of the second resistor R2 may be substantially equal to 1k Ω. The resistance value of the third resistor R3 may be approximately equal to 49k omega. The resistance value of the fourth resistor R4 may be approximately equal to 1k Ω. The resistance value of the fifth resistor R5 may be substantially equal to 1.63k omega. The capacitance of the first capacitor C1 may be 44.65 μ F to 49.35 μ F, preferably 47 μ F. The second capacitor C2 may have a capacitance of 1350 μ F to 1650 μ F, preferably 1500 μ F. The inductance of the first inductor L1 may be between 180 μ H and 220 μ H, preferably 200 μ H. The inductance of the second inductor L2 may be between 180 μ H and 220 μ H, preferably 200 μ H. The switching frequency of the clock potential VA may be about 65 kHz. The first reference potential VR1 may be approximately constant at 10V. The second reference potential VR2 may be constant at about 14V. The third reference potential VR3 may be constant at about 5V. The above parameter ranges are derived from a plurality of experimental results, which help to optimize the conversion efficiency of the boost converter 200.

The present invention provides a novel boost converter, which can be operated in a first mode or a second mode to provide output potentials with different potential levels. According to actual measurement results, the boost converter using the aforementioned design can reduce its overall power loss. In summary, the present invention can effectively improve the conversion efficiency of the boost converter, and thus, is suitable for various electronic devices.

It should be noted that the above-mentioned potential, current, resistance, inductance, capacitance, and other device parameters are not limitations of the present invention. The designer can adjust these settings according to different needs. The boost converter of the present invention is not limited to the states shown in fig. 1-2. The present disclosure may include only any one or more features of any one or more of the embodiments of fig. 1-2. In other words, not all illustrated features need to be implemented in the boost converter of the present invention at the same time. Although the embodiments of the present invention use mosfet as an example, the present invention is not limited thereto, and other kinds of transistors can be used by those skilled in the art, such as: junction field effect transistors, or finfets, etc., without affecting the performance of the present invention.

Ordinal numbers such as "first," "second," "third," etc., in the specification and in the claims, do not have a sequential relationship with each other, but are used merely to identify two different elements having the same name.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A boost converter, comprising:

a voltage division circuit for generating a divided voltage potential according to an input potential;

a first comparator for comparing the divided voltage potential with a first reference potential to generate a first control potential;

an adjustable inductance element coupled to the voltage divider circuit, wherein a total inductance of the adjustable inductance element is adjusted according to the first control potential;

a power switch for selectively coupling the adjustable inductive element to a ground potential according to a clock potential;

a second comparator for comparing the first control potential with a second reference potential to generate a second control potential;

an output stage circuit coupled to the adjustable inductive element and the power switch for generating an output voltage according to a third reference voltage and the second control voltage, wherein the output stage circuit includes an adjustable resistive element, and a total resistance of the adjustable resistive element is adjusted according to the second control voltage; and

a controller for generating the clock potential, the first reference potential, the second reference potential, and the third reference potential.

2. The boost converter of claim 1, wherein if the input voltage is higher than or equal to a threshold voltage, the boost converter is to operate in a first mode and the output voltage has a higher voltage level, and if the input voltage is lower than the threshold voltage, the boost converter is to operate in a second mode and the output voltage has a lower voltage level.

3. The boost converter of claim 1, wherein the voltage divider circuit comprises:

a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to an input node for receiving the input potential, and the second end of the first resistor is coupled to a first node for outputting the divided potential;

a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the first node and the second end of the second resistor is coupled to the ground potential; and

a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the first node and the second terminal of the first capacitor is coupled to the ground potential.

4. The boost converter of claim 1, wherein the first comparator has a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal of the first comparator is for receiving the first reference potential, the negative input terminal of the first comparator is for receiving the divided potential, and the output terminal of the first comparator is for outputting the first control potential.

5. The boost converter of claim 3, wherein the adjustable inductive element comprises:

a first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the input node and the second end of the first inductor is coupled to a second node;

a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the input node and the second end of the second inductor is coupled to a third node; and

a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is for receiving the first control potential, the first terminal of the first transistor is coupled to the third node, and the second terminal of the first transistor is coupled to the second node.

6. The boost converter of claim 5, wherein the power switch comprises:

a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is for receiving the clock potential, the first terminal of the second transistor is coupled to the ground potential, and the second terminal of the second transistor is coupled to the second node.

7. The boost converter of claim 1, wherein the second comparator has a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal of the second comparator is for receiving the second reference potential, the negative input terminal of the second comparator is for receiving the first control potential, and the output terminal of the second comparator is for outputting the second control potential.

8. The boost converter of claim 5, wherein the output stage circuit further comprises:

a diode having an anode and a cathode, wherein the anode of the diode is coupled to the second node and the cathode of the diode is coupled to an output node to output the output potential; and

a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node and the second terminal of the second capacitor is coupled to the ground potential.

9. The boost converter of claim 8, wherein the adjustable resistive element comprises:

a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the output node, and the second end of the third resistor is coupled to a fourth node for receiving the third reference potential; and

a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the fourth node, and the second end of the fourth resistor is coupled to the ground potential.

10. The boost converter of claim 9, wherein the adjustable resistive element further comprises:

a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is for receiving the second control potential, the first terminal of the third transistor is coupled to a fifth node, and the second terminal of the third transistor is coupled to the fourth node; and

a fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is coupled to the fifth node, and the second end of the fifth resistor is coupled to the ground potential.