TWI750656B - Display device - Google Patents

Abstract

The present invention is to provide a display device capable of suppressing a voltage drop in a micro LED in which an anode terminal and a cathode terminal are arranged to face each other. A display device according to one embodiment includes: a substrate; a light-emitting element mounted on the substrate; an anode terminal disposed on the bottom of the light-emitting element; and a cathode terminal disposed on an exit surface of the light-emitting element on the opposite side of the anode terminal; and The cathode terminal is formed of a metallic material.

Description

display device

Embodiments of the present invention relate to a display device.

Although an LED display using a light emitting diode (LED: Light Emitting Diode), which is a self-luminous element, has been known, in recent years, as a display device with a higher definition, a micro-diode element called a micro LED has been developed. The display device (hereinafter, referred to as a micro LED display).

Unlike conventional liquid crystal displays and organic EL (Electro Luminescent) displays, this micro LED display is formed by mounting a plurality of micro LEDs in the form of wafers in the display area, so it is easy to achieve high definition and large size. , while attracting much attention as a next-generation display.

In micro LEDs, there are those in which an anode terminal (anode) and a cathode terminal (cathode) are opposed to each other with a light-emitting layer interposed therebetween. Such a micro LED emits light by applying a voltage to an anode terminal and a cathode terminal.

Generally speaking, the above-mentioned cathode terminal is disposed on the light emitting surface side, and is often formed of a transparent conductive material from the viewpoint of light extraction efficiency. In addition, the above-mentioned cathode terminals are formed continuously across a plurality of pixels, and are connected to the power supply wiring in the outer peripheral portion (non-display area) where the micro LEDs are not arranged.

However, in this case, the voltage drop based on the resistance of the transparent conductive material, the further away from the micro-LED of the above-mentioned power wiring configuration, the higher the voltage applied to the cathode terminal may be. small.

One of the objects of the present disclosure is to provide a display device capable of suppressing a voltage drop in a micro LED in which an anode terminal and a cathode terminal are arranged opposite to each other.

A display device according to an embodiment includes: a substrate; a light-emitting element mounted on the substrate; an anode terminal disposed on the bottom of the light-emitting element; and a cathode terminal disposed between the light-emitting element on the opposite side to the anode terminal an exit surface; and the cathode terminal is formed of a metal material.

According to the display device having the above-described configuration, it is possible to provide a display device capable of suppressing a voltage drop in the micro LEDs in which the anode terminal and the cathode terminal are arranged to face each other.

1: Display device

2: Display panel

3: The first circuit board

4: Second circuit board

5: Panel driver

10: Light-emitting elements

10B: Light-emitting element

10G: Light-emitting element

10R: Light-emitting element

21: 1st main power cord

22: Common power wiring

23: Pixel signal line

24: Initialize the power cord

25: Reset the power cord

31: Insulating substrate

32: Base coat

33: Interlayer insulating film

34: Flattening film

35: Conductive layer

36: Insulation layer

37: Pixel electrode

38: Common electrode

39: Flattening film

40: 1st relay electrode

40B: 1st relay electrode

40G: 1st relay electrode

40R: 1st relay electrode

41: 2nd relay electrode

42: Transparent conductive layer

43: Component insulation layer

44: Flattening film

45: polarizer

AN: Anode terminal

AR: Array substrate

BA: Bending area

BG: output control signal

BCT: output transistor

CA: Cathode terminal

CH1B: Opening

CH1G: Opening

CH1R: Opening

CH2B: Opening

CH2G: Opening

CH2R: Opening

CH3B: Opening

CH3G: Opening

CH3R: Opening

CH4B: Opening

CH4G: Opening

CH4R: Opening

CH5: Opening

CH6: Opening

Cled: element capacitance

Cs1: Holding Capacitor

Cs2: auxiliary capacitor

DA: display area

DRT: Drive Transistor

E1: 1st electrode

E2: 2nd electrode

EX: Short side

EY: long edge

GD: Gate Driver

GE: gate electrode

GI: Gate insulating film

IST: Initialize Transistor

IG: Initialize control signal

MT: Terminal area

NDA: non-display area

PVDD: 1st power supply potential

PVSS: 2nd power supply potential

px: pixel

RG: reset control signal

RST: reset transistor

SC: Semiconductor layer

SG: pixel control signal

SPB: Sub pixel

SPG: Sub pixel

SPR: Sub pixel

SST: Pixel Transistor

Vini: initialization voltage

Vsig: pixel signal

X: 1st direction

Y: 2nd direction

Z: 3rd direction

FIG. 1 is a perspective view schematically showing the configuration of a display device according to an embodiment.

FIG. 2 is a diagram for explaining an example of the circuit configuration of the display device of the embodiment.

FIG. 3 is a diagram schematically showing an example of the cross-sectional structure of the display device of this embodiment.

FIG. 4 is a plan view schematically showing an example of the pixel structure of the display device of this embodiment.

FIG. 5 is a plan view schematically showing an example of the layout of the cathode terminals constituting the display device of this embodiment.

FIG. 6 is a plan view schematically showing another example of the layout of the cathode terminals constituting the display device of this embodiment.

FIG. 7 is a diagram schematically showing an example of a cross-sectional structure of a display device of a comparative example.

Some embodiments will be described with reference to the drawings.

It should be noted that the disclosure is merely an example, and it goes without saying that appropriate modifications to maintain the gist of the invention can be easily conceived by those in the industry. In addition, the drawings are shown more clearly than the actual state in some cases, but they are only an example and are not intended to limit the interpreter of the present invention. In each drawing, the symbol may be omitted for the same or similar elements arranged consecutively. In addition, in this specification and each drawing, the same reference number may be attached|subjected to the component which performs the same or similar function as the description in the previous drawing, and the repeated detailed description may be abbreviate|omitted.

FIG. 1 is a perspective view schematically showing the configuration of the display device 1 of the present embodiment. 1 shows a three-dimensional space defined by a first direction X, a second direction Y perpendicular to the first direction X, and a third direction Z perpendicular to the first direction X and the second direction Y. In addition, although the 1st direction X and the 2nd direction Y are orthogonal to each other, they may cross at an angle other than 90 degrees. In addition, in this embodiment, the 3rd direction Z is defined as upper, and the direction opposite to the 3rd direction Z is defined as lower. In the case of "a second member above the first member" and "a second member below the first member", the second member may be in contact with the first member or may be positioned apart from the first member.

Hereinafter, in this embodiment, the case where the display device 1 is a micro LED display device (micro LED display) using a self-luminous element, that is, a micro LED will be mainly described.

As shown in FIG. 1 , the display device 1 includes a display panel 2 , a first circuit board 3 , a second circuit board 4 , and the like.

The display panel 2 is rectangular in one example. In the illustrated example, the short side EX of the display panel 2 is parallel to the first direction X, and the long side EY of the display panel 2 is parallel to the second direction Y. The third direction Z corresponds to the thickness direction of the display panel 2 . The first direction X can also be read as a direction parallel to the short side EX of the display device 1, and the second direction Y can be read as a direction parallel to the long side EY of the display device 1. direction, and the third direction Z is read as the thickness direction of the display device 1 . The main surface of the display panel 2 is parallel to the X-Y plane defined by the first direction X and the second direction Y. The display panel 2 has a display area DA and a non-display area NDA outside the display area DA. The non-display area NDA has a terminal area MT. In the illustrated example, the non-display area NDA surrounds the display area DA.

The display area DA is an area for displaying an image, and includes, for example, a plurality of pixels PX arranged in a matrix. The pixel PX includes a light-emitting element (micro LED), a switching element (driving transistor) for driving the light-emitting element, and the like.

The terminal area MT is disposed along the short side EX of the display panel 2 and includes terminals for electrically connecting the display panel 2 with external devices and the like.

The first circuit board 3 is mounted on the terminal region MT, and is electrically connected to the display panel 2 . The first circuit board 3 is, for example, a flexible printed circuit board. The first circuit board 3 includes a driver IC chip (hereinafter, referred to as a panel driver) 5 and the like for driving the display panel 2 . In addition, in the example shown in the figure, the panel driver 5 is arranged on the first circuit board 3, but it may be arranged below it. Alternatively, the panel driver 5 may be mounted on other than the first circuit board 3 , and may be mounted on, for example, the second circuit board 4 . The second circuit board 4 is, for example, a flexible printed circuit board. The second circuit board 4 is connected to the first circuit board 3 , for example, below the first circuit board 3 .

The above-mentioned panel driver 5 is connected to a control board (not shown) via, for example, the second circuit board 4 . The panel driver 5 performs control of displaying an image on the display panel 2 by driving a plurality of pixels PX based on, for example, an image signal output from the control substrate.

In addition, the display panel 2 may also have a curved area BA marked with oblique lines. The curved area BA is a curved area when the display device 1 is accommodated in a casing of an electronic device or the like. The bent area BA is located on the side of the terminal area MT in the non-display area NDA. In a state where the bending area BA is bent, the first circuit board 3 and the second circuit board 4 are arranged on the display panel 2 so as to face each other. Below the display panel 2 .

Next, the circuit configuration of the display device 1 will be described with reference to FIG. 2 . As described above, a plurality of pixels PX are arranged in a matrix in the display area DA. A plurality of pixels PX are configured in the same manner. Therefore, in FIG. 2 , one pixel PX among the plurality of pixels PX is represented and illustrated. The pixel PX includes, for example, three sub-pixels (sub-pixels) SPR, SPG, and SPB.

The sub-pixels SPR, SPG, and SPB are configured in the same manner. Therefore, here, for the sake of convenience, the configuration (pixel circuit) of the sub-pixel SPB will be mainly described. As shown in FIG. 2 , the sub-pixel SPB includes a light-emitting element 10 , a driving transistor DRT, a pixel transistor SST, an initialization transistor IST, a holding capacitor Cs1 and a storage capacitor Cs2 . The gate driver GD includes a reset transistor RST. In addition, one output transistor BCT shown in FIG. 2 is arranged with respect to the sub-pixels SPR, SPG, and SPB. In FIG. 2, each transistor is an n-channel transistor. In addition, the element capacitance Cled shown in FIG. 2 is the capacitance between the anode electrode and the cathode electrode of the light-emitting element 10 . In addition, the reset transistor RST, the pixel transistor SST, the initialization transistor IST, and the output transistor BCT may not be constituted by transistors, respectively. The reset transistor RST, the pixel transistor SST, the initialization transistor IST, and the output transistor BCT may function as a reset switch, a pixel switch, and an output switch, respectively. The Vrst line functions as a reset line, and the BG line, the RG line, the IG line, and the SG line each function as a control line.

In the following description, one of the source and drain terminals of the transistor is referred to as the first terminal, and the other is referred to as the second terminal. Moreover, let one terminal which forms an element capacitance be a 1st terminal, and let the other terminal be a 2nd terminal.

The first terminal of the driving transistor DRT is connected to the first terminal of the element capacitor Cled, the first terminal of the holding capacitor Cs1, and the first terminal of the auxiliary capacitor Cs2. The second terminal of the drive transistor DRT is connected to the first terminal of the output transistor BCT. Also, the second drive transistor DRT The terminal is connected to the first terminal of the reset transistor RST via the Vrst line.

The second terminal of the output transistor BCT is connected to the first main power supply line 21 . In addition, the second terminal of the element capacitor Cled is connected to the second main power supply line 22 .

The first terminal of the pixel transistor SST is connected to the gate terminal of the drive transistor DRT, the first terminal of the initialization transistor IST, and the second terminal of the holding capacitor Cs1. The second terminal of the pixel transistor SST is connected to the pixel signal line 23 .

The second terminal of the initialization transistor IST is connected to the initialization power supply line 24 . The second terminal of the auxiliary capacitor Cs2 is connected to the first main power supply line 21 . In addition, the second terminal of the auxiliary capacitor Cs2 may be connected to a constant potential line, and may be connected to a wiring different from the first main power supply line 21 .

Here, the reset transistor RST is provided in the gate driver GD disposed outside the sub-pixel SPB (pixel PX), and the second terminal of the reset transistor RST is connected to the reset power supply line 25 .

Here, the first power supply potential PVDD is supplied to the first main power supply line 21 , and the second power supply potential PVSS is supplied to the second main power supply line 22 . The first power supply potential PVDD corresponds to a voltage for supplying an anode voltage to the light-emitting element 10 , and the second power supply potential PVSS corresponds to a cathode voltage of the light-emitting element 10 . In addition, the second main power supply line 22 may also be referred to as a common power supply wiring (or simply referred to as a power supply wiring).

Further, the pixel signal Vsig is supplied to the pixel signal line 23, the initialization voltage Vini is supplied to the initialization power supply line 24, and the reset power supply line 25 is set to the reset power supply potential Vrst. In addition, the pixel signal Vsig is a signal written to the pixel (here, the sub-pixel SPB) based on the above-mentioned image signal.

The gate terminal of the output transistor BCT is connected to the BG line. The output control signal BG is supplied to the BG line.

The gate terminal of the pixel transistor SST is connected to the SG line. The pixel control signal SG is supplied to the SG line.

The gate terminal of the initialization transistor IST is connected to the IG line. An initialization control signal IG is supplied to the IG line.

The gate terminal of the reset transistor RST is connected to the RG line. A reset control signal RG is supplied to the RG line.

In FIG. 2, it has been explained that the above transistors are all n-channel transistors, but for example, transistors other than the driving transistor DRT can be p-channel transistors, and n-channel transistors and p-channel transistors can also be used. Mixed transistors.

In addition, the display device 1 only needs to include at least one gate driver GD. In the present embodiment, although not shown, the display device 1 includes two gate drivers GD. The gate driver GD is not only disposed on the left side of the pixel PX mentioned in FIG. 2 , but also on the right side of the pixel PX. Therefore, a signal can be given to one pixel PX from the gate drivers GD on both sides. Here, the two-side power supply method is used for the above-mentioned SG line, and the one-side power supply method is used for the other BG lines, IG lines, and Vrst lines.

Here, the configuration of the sub-pixel SPB has been described, but the same applies to the sub-pixel SPR and SPG.

The circuit configuration described in FIG. 2 is an example, and the circuit configuration of the display device 1 may be other configurations as long as it includes at least the driving transistor DRT. For example, a part of the circuit configuration described in FIG. 2 may be omitted, and other configurations may be added.

FIG. 3 schematically shows a cross-sectional structure of the display device 1 . Here, an example in which the above-mentioned minute light-emitting diode elements called micro LEDs are mounted on a substrate as a display element will be described. In addition, in FIG. 3, for the TFT (Thin Film Transistor: thin film transistor) display area DA is displayed.

The array substrate AR of the display panel 2 shown in FIG. 3 includes an insulating substrate 31 . The insulating substrate 31 can be made of any material as long as it can withstand the processing temperature in the TFT step, but mainly a glass substrate such as quartz and alkali-free glass, or a resin substrate such as polyimide can be used. The resin substrate has flexibility, and can constitute the display device 1 as a sheet display. In addition, as a resin substrate, it is not limited to polyimide, and other resin materials can also be used. From the above, it may be appropriate to call the insulating substrate 31 an organic insulating layer or a resin layer.

On the insulating substrate 31, an undercoat layer 32 having a three-layer laminate structure is provided. Although detailed illustration is omitted, the undercoat layer 32 has a _{lower layer formed of silicon oxide (SiO 2} ), a middle layer formed of silicon nitride (SiN), and an upper layer formed of _{silicon oxide (SiO 2 ).} The lower layer of the primer layer 32 is provided to improve the adhesion with the base material, that is, the insulating substrate 31, the middle layer is provided as a barrier film for blocking moisture and impurities from the outside, and the upper layer is provided to prevent the hydrogen atoms contained in the middle layer from diffusing to the surface. A barrier film on the side of the semiconductor layer SC, which will be described later, is provided. In addition, the primer layer 32 may be further laminated, and may have a single-layer structure or a double-layer structure. For example, when the insulating substrate 31 is glass, the silicon nitride film can be directly formed on the insulating substrate 31 because the adhesion of the silicon nitride film is better.

On the insulating substrate 31, a light shielding layer (not shown) is arranged. The position of the light shielding layer is aligned with the part where the TFT is subsequently formed. The light-shielding layer may be formed of a material having light-shielding properties such as a metal layer or a black layer. By the light shielding layer, since the intrusion of light into the back surface of the channel of the TFT can be suppressed, it is possible to suppress the change of the TFT characteristics which may be caused by the light incident from the insulating substrate 31 side. In addition, when the light shielding layer is formed by a conductive layer, a back gate effect can be imparted to the TFT by applying a specific potential to the light shielding layer.

A TFT (eg, a driving transistor DRT) is formed on the above-mentioned undercoat layer 32 . As the TFT, a polysilicon TFT using polysilicon for the semiconductor layer SC is taken as an example. in this embodiment In the above, the semiconductor layer SC is formed using low temperature polysilicon. As the TFT, either NchTFT or PchTFT can be used. Alternatively, NchTFT and PchTFT may be formed simultaneously. Hereinafter, an example in which an NchTFT is used as the driving transistor DRT will be described. The semiconductor layer SC of the NchTFT has a first region, a second region, a channel region between the first region and the second region, and low concentrations respectively provided between the channel region and the first region and between the channel region and the second region impurity region. One of the first and second regions functions as a source region, and the other of the first and second regions functions as a drain region. The gate insulating film GI uses a silicon oxide film, and the gate electrode GE is formed of MoW (molybdenum, tungsten). In addition, the electrode formed on the gate insulating film GI, such as the gate electrode GE, may also be called a 1st wiring or a 1st metal. In addition to the function of the gate electrode of the TFT, the gate electrode GE also has a function of a holding capacitor electrode which will be described later. Here, although a top-gate type TFT is used for description, the TFT may be a bottom-gate type TFT.

An interlayer insulating film 33 is provided on the gate insulating film GI and the gate electrode GE. The interlayer insulating film 33 is formed by sequentially laminating, for example, a silicon nitride film and a silicon oxide film on the gate insulating film GI and the gate electrode GE.

On the interlayer insulating film 33, the first electrode E1 and the second electrode E2 of the TFT are provided. In addition, on the interlayer insulating film 33, the common power supply wiring 22 is provided. The first electrode E1, the second electrode E2, and the common power supply wiring 22 each have a three-layer structure (Ti-based/Al-based/Ti-based), and have a lower layer including Ti (titanium), an alloy containing Ti, and the like. A metal material with Ti as its main component; a middle layer, which contains Al (aluminum), an alloy containing Al, and other metal materials whose main component is Al; and an upper layer, which contains Ti, an alloy containing Ti, and other metals whose main component is Ti Material. In addition, the electrode formed on the interlayer insulating film 33, such as the 1st electrode E1, may also be called 2nd wiring, or 2nd metal. The first electrode E1 is connected to the first region of the semiconductor layer SC, and the second electrode E2 is connected to the second region of the semiconductor layer SC. For example, when the first region of the semiconductor layer SC functions as a source region, the first electrical The electrode E1 is a source electrode, and the second electrode E2 is a drain electrode. The first electrode E1, the interlayer insulating film 33, and the gate electrode (holding capacitor electrode) GE of the TFT together form a holding capacitor Cs1.

The planarizing film 34 is formed on the interlayer insulating film 33 , the first electrode E1 , the second electrode E2 , and the common power supply wiring 22 so as to cover the TFT and the common power supply wiring 22 . As the planarizing film 34, an organic insulating material such as photosensitive acrylic is often used. Compared with inorganic insulating materials formed by CVD (Chemical Vapor Deposition) or the like, the coverage of wiring steps and the flatness of the surface are excellent.

On the planarizing film 34, a conductive layer 35 is provided. Although described later, the conductive layer 35 is not formed in the region where the first electrode E1 of the TFT is in contact with the pixel electrode 37 (anode electrode), and has an opening in this region. On the conductive layer 35, an insulating layer 36 is provided. For example, the insulating layer 36 is formed of a silicon nitride film. On the insulating layer 36, a pixel electrode 37 is disposed. The pixel electrode 37 is in contact with the first electrode E1 of the TFT through the opening formed in the planarizing film 34 and the insulating layer 36 . Accordingly, the pixel electrode 37 is electrically connected to the first electrode E1 of the TFT through the opening. The conductive layer 35 and the pixel electrode 37 are both formed of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In addition, the above-mentioned TFT and the pixel electrode 37 may be collectively referred to as an anode wiring.

The conductive layer 35 is in contact with the common power supply wiring 22 through the opening formed in the planarization film 34 . In a region where the conductive layer 35 is in contact with the common power supply wiring 22 , a common electrode 38 (cathode electrode) is provided on the conductive layer 35 . Accordingly, the common electrode 38 is electrically connected to the common power supply wiring 22 via the conductive layer 35 . The common electrode 38 is formed of a transparent conductive material such as ITO or IZO, like the conductive layer 35 and the pixel electrode 37 .

In addition, the common power supply wiring 22, the conductive layer 35, and the common electrode 38 may be collectively referred to as a cathode wiring.

Furthermore, the pixel electrode 37 and the common electrode 38 are not limited to those formed of transparent conductive materials, and may also be made of light-shielding metal materials such as Al (aluminum), Ti (titanium), Mo (molybdenum), and W (tungsten). Formed by a layered structure of these metal materials.

A planarization film 39 is provided on the insulating layer 36 , the pixel electrode 37 and the common electrode 38 . The planarizing film 39 is formed of an organic insulating material such as photosensitive acrylic. The planarizing film 39 has an opening for electrically connecting the pixel electrode 37 and the first relay electrode 40 (anode relay electrode), and an opening for electrically connecting the common electrode 38 and the second relay electrode 41 (cathode relay electrode) electrode) openings.

In the display device 1, as described above, the two planarizing films 34 and 39 are provided. The planarizing films 34 and 39 have a thickness (film thickness) along the third direction Z compared with the insulating layer formed of an inorganic insulating material, and therefore, at least one of the planarizing films 34 and 39 is made of an inorganic insulating material. Compared with the case of an insulating layer formed of an insulating material, an advantage of excellent buffering properties can be obtained.

In the display area DA, the light-emitting element 10 is mounted. In FIG. 3, although only one light-emitting element 10 is shown, the light-emitting element 10 having the emission colors of R, G, and B is actually provided. The light-emitting element 10 and the first relay electrode 40 are electrically connected through the anode terminal AN. The anode terminal AN is a connecting member such as solder.

The light-emitting element 10 is in contact with the cathode terminal CA at both ends of the output surface opposite to the anode terminal AN arranged at the bottom. More specifically, the light-emitting element 10 and the cathode terminal CA are overlapped and contacted, for example, at an end portion of 1 μm of the output surface. It is desirable that the cathode terminal CA is formed of a metal material such as titanium (Ti), or blackened metal. Accordingly, it can be expected to improve the contrast ratio of the display device 1 in a bright place.

The cathode terminal CA is in contact with the second relay electrode 41 through an opening formed in the element insulating layer 43 to be described later. That is, the second relay electrode electrically connected to the cathode terminal CA 41 is arranged on the same layer as the anode terminal AN (and the first relay electrode 40 electrically connected to the anode terminal AN).

The transparent conductive layer 42 is provided so as to cover the cathode terminal CA and a portion of the emission surface of the light-emitting element 10 that does not overlap with the cathode terminal CA. As the transparent conductive layer 42, a transparent conductive material such as ITO or IZO can be used. In this way, light can be extracted from the light-emitting element 10 by providing the transparent conductive layer 42 as the conductive layer provided on the portion of the light-emitting element 10 that does not overlap with the cathode terminal CA. In addition, in this embodiment, since the transparent conductive layer 42 basically does not function as a cathode terminal, the transparent conductive layer 42 may be omitted. On the other hand, by providing the transparent conductive layer 42, the redundancy can be expected to be improved. In addition, although it will be described later, the transparent conductive layer 42 may have a concave shape at the part where the cathode terminal CA and the cathode terminal CA extending from the adjacent sub-pixels intersect with the cathode terminal CA as shown in FIG. thickness.

An element insulating layer 43 is provided between the planarizing film 39 , the cathode terminal CA, and the transparent conductive layer 42 . The element insulating layer 43 is formed of a resin material filled in the space between the light emitting elements 10 .

A planarization film 44 is provided on the transparent conductive layer 42 , and a polarizer 45 is provided on the planarization film 44 . The planarizing film 44 is formed of an organic insulating material such as photosensitive acrylic. The polarizing plate 45 is bonded on the planarizing film 44 by an adhesive layer not shown.

4 is a plan view for explaining positions of a plurality of openings (contacts) formed in the pixel PX (sub-pixels SPR, SPG, and SPB) of the present embodiment. In addition, in FIG. 4, in order to prevent drawing complexity, only necessary elements are described, and illustration of some elements is abbreviate|omitted.

As shown in FIG. 4 , the pixels PX including the sub-pixels SPR, SPG and SPB share a single conductive layer 35 . In other words, the conductive layer 35 is formed to continuously extend across the plurality of sub-pixels SPR, SPG and SPB.

In the following description, R is added at the end of the symbol to describe the elements included in the sub-pixel SPR. In addition, G is added to the end of the symbol to describe the elements included in the sub-pixel SPG. Furthermore, B is further marked at the end of the symbol to describe the elements included in the sub-pixel SPB.

As shown in FIG. 4 , openings CH1 to CH4 are formed in each of the sub-pixels SPR, SPG, and SPB included in the pixel PX. Moreover, as shown in FIG. 4, opening parts CH5 and CH6 are formed in each pixel PX.

The opening portion CH1R corresponds to a region where the conductive layer 35 is not formed so that the pixel electrode 37R and the first electrode E1R are in contact with the opening portion CH2R described later. In addition, the opening portion CH1G corresponds to a region where the conductive layer 35 is not formed so that the pixel electrode 37G and the first electrode E1G are brought into contact with the opening portion CH2G described later. In addition, the opening portion CH1B corresponds to a region where the conductive layer 35 is not formed so that the pixel electrode 37B and the first electrode E1B are in contact with the opening portion CH2B described later.

The opening portion CH2R is formed in the opening portion of the planarizing film 34 and the insulating layer 36 so that the pixel electrode 37R is in contact with the first electrode E1R. In addition, the opening portion CH2G is formed in the opening portion of the planarizing film 34 and the insulating layer 36 so that the pixel electrode 37G and the first electrode E1G are in contact with each other. In addition, the opening part CH2B is formed in the opening part of the planarization film 34 and the insulating layer 36 so that the pixel electrode 37B and the 1st electrode E1B may contact.

As shown in FIG. 4, the opening part CH1R is formed larger than the opening part CH2R, and the opening part CH1R and the opening part CH2R overlap in plan view. Similarly, the opening portion CH1G is formed larger than the opening portion CH2G, and the opening portion CH1G and the opening portion CH2G overlap in a plan view. Moreover, the opening part CH1B is formed larger than the opening part CH2B, and the opening part CH1B and the opening part CH2B overlap in plan view.

Furthermore, as shown in FIG. 4 , the openings CH1R and CH2R, the openings CH1G and CH2G, and the openings CH1B and CH2B are arranged in a line along the first direction X substantially linearly.

The opening portion CH3R is formed in the opening portion of the planarizing film 34 so that the conductive layer 35 is in contact with the common power supply wiring 22 . Moreover, the opening part CH3G is formed in the opening part of the planarizing film 34 so that the conductive layer 35 and the common power supply wiring 22 may contact. In addition, the opening part CH3B is formed in the opening part of the planarizing film 34 so that the conductive layer 35 and the common power supply wiring 22 may contact.

As shown in FIG. 4 , the openings CH3R, CH3G, and CH3B are arranged in a row along the first direction X substantially linearly.

Furthermore, as shown in FIG. 4 , the openings CH1R and CH2R and the opening CH3R are arranged in a row along the second direction Y substantially linearly. Similarly, the openings CH1G and CH2G and the opening CH3G are arranged substantially linearly along the second direction Y, and the openings CH1B and CH2B and the opening CH3B are arranged substantially linearly arranged along the second direction Y.

The opening portion CH4R is formed in the opening portion of the planarizing film 39 in order to bring the pixel electrode 37R into contact with the first relay electrode 40R. Moreover, the opening part CH4G is formed in the opening part of the planarization film 39 so that the pixel electrode 37G and the 1st relay electrode 40G may contact. The opening portion CH4B is formed in the opening portion of the planarizing film 39 so that the pixel electrode 37B and the first relay electrode 40B are brought into contact with each other.

In the example shown in FIG. 4 , at least one of the openings CH4R, CH4G, and CH4B is formed so as to be arranged in a non-linear arrangement. Specifically, the openings CH4R and CH4B are arranged in a line extending in the first direction X, but the openings CH4G are not arranged in a line extending in the first direction X. In addition, although the openings CH4G and CH4B are arranged in a line extending in the second direction Y, the openings CH4R are not arranged in a line extending in the second direction Y.

The opening portion CH5 is formed in the opening portion of the planarizing film 39 so that the common electrode 38 and the second relay electrode 41 are brought into contact with each other. Moreover, the opening part CH6 is formed in the opening part of the element insulating layer 43 so that the 2nd relay electrode 41 may contact with the cathode terminal CA. In addition, as shown in FIG. 4 , the openings CH5 and CH6 partially overlap in a plan view, but the openings CH5 and CH6 may not overlap in a plan view, or may completely overlap.

As shown in FIG. 4 , when the shape of the pixel PX is a rectangle, and the sub-pixels SPR, SPG, and SPB are arranged in a triangular shape at positions corresponding to three of the four vertices of the rectangle, the opening CH5 is desired. And CH6 is formed at the position corresponding to the remaining 1 vertex.

Here, the layout of the cathode terminal CA provided in the pixel PX will be described with reference to FIG. 5 . In FIG. 5, the layout in which the cathode terminal CA is mainly extended along the 1st direction X is illustrated. In addition, the width or thickness of the cathode terminal CA is set to a value corresponding to the electric power required for the light-emitting element 10 to emit light, and can be set to, for example, a width of 10 μm and a thickness of 50 nm.

Specifically, the cathode terminal CA extends in the first direction X as follows: connecting the end of the emission surface of the green light-emitting element 10G (the side of the rectangular emission surface extending in the second direction Y), and being arranged in the first direction X The end of the output surface of the green light-emitting element 10G included in the other arranged pixel PX (the side of the rectangular output surface extending in the second direction Y). In other words, the cathode terminal CA is along the first direction so as to connect the two ends of the light-emitting element 10G's light-emitting surface and the end of the light-emitting element 10G's light-emitting surface included in another pixel PX adjacent in the first direction X, respectively. X extension.

In addition, the cathode terminal CA extends in the first direction X so as to connect one end of the emission surface of the red light-emitting element 10R (the two sides of the rectangular emission surface extending in the second direction Y are close to the blue emission in the same pixel PX). element 10B), and one end of the light-emitting surface of the blue light-emitting element 10B (one of the two sides of the rectangular light-emitting surface extending along the second direction Y is close to the red light-emitting element 10R in the same pixel PX). In addition, the cathode terminal CA is along the first direction X as follows Extension: connecting the other end of the emitting surface of the light-emitting element 10R (the side of the two sides of the rectangular emitting surface extending along the second direction Y away from the light-emitting element 10B in the same pixel PX), and arranged along the first direction X The end of the emission surface of the blue light-emitting element 10B included in the other pixel PX (the side of the rectangular emission surface extending along the second direction Y). In addition, the cathode terminal CA extends in the first direction X so as to connect the other end of the emission surface of the light-emitting element 10B (out of the two sides of the rectangular emission surface extending in the second direction Y away from the light-emitting element 10R in the same pixel PX) side), and the end of the output surface of the red light-emitting element 10R included in the other pixel PX arranged along the first direction X (the side of the rectangular output surface extending along the second direction Y).

In addition, the cathode terminal CA extends in the second direction Y as follows: connecting the end of the light-emitting element 10B's light-emitting surface (the side of the rectangular light-emitting surface extending in the first direction X), and the end of the light-emitting element 10B extending in the first direction The end of the emission surface of the blue light-emitting element 10B included in the other pixel PX (the side of the rectangular emission surface extending along the first direction X). In other words, the cathode terminal CA is along the second direction so as to connect the two ends of the light-emitting element 10B's light-emitting surface and the end of the light-emitting element 10B's light-emitting surface included in another pixel PX adjacent in the second direction Y, respectively. Y extension.

In addition, a cathode terminal CA extending from the green light-emitting element 10G to another pixel PX adjacent in the first direction X, and a cathode terminal extending from the blue light-emitting element 10B to another pixel PX adjacent to the second direction Y CA crosses in the area|region in which the opening part CH6 is formed in plan view.

As shown in FIG. 5 , when the cathode terminals CA are mainly arranged to extend along the first direction X, although the extraction efficiency of the light from the first direction X is slightly reduced due to the arrangement of the cathode terminals CA, it is possible to obtain an increase in the light extraction efficiency from the first direction X. The advantage of the extraction efficiency of light in 2 directions Y.

Next, another layout of the cathode terminals CA provided in the pixels PX will be described with reference to FIG. 6 . Unlike the case of FIG. 5 , FIG. 6 illustrates a layout in which the cathode terminals CA are mainly arranged to extend along the second direction Y. As shown in FIG.

Specifically, the cathode terminal CA passes between the green light-emitting element 10G and the red light-emitting element 10R included in each of the plurality of pixels PX arranged along the first direction X, and between the opening CH6 and the blue light-emitting element 10B. The first direction X extends.

In addition, the cathode terminal CA extends in the second direction Y so as to connect one end of the emission surface of the light-emitting element 10G (one of the two sides of the rectangular emission surface extending in the first direction X is close to the red light-emitting element 10R in the same pixel PX). side), and an end of the emitting surface of the light-emitting element 10R (the side of the two sides of the rectangular emitting surface extending along the first direction X that is close to the green light-emitting element 10G in the same pixel PX). Furthermore, the cathode terminal CA extends along the second direction Y as follows: connecting the other end of the emitting surface of the light-emitting element 10G (the two sides of the rectangular emitting surface extending along the first direction X are far from the light-emitting element in the same pixel PX). 10R side), and the end of the output surface of the red light-emitting element 10R included in another pixel PX arranged along the second direction Y (the side of the rectangular output surface extending along the first direction X). In addition, the cathode terminal CA extends in the second direction Y so as to connect the other end of the emission surface of the light-emitting element 10R (out of the two sides of the rectangular emission surface extending in the first direction X away from the light-emitting element 10G in the same pixel PX) side), and the end of the output surface of the green light-emitting element 10G included in the other pixel PX arranged along the second direction Y (the side of the rectangular output surface extending along the first direction X).

As shown in FIG. 6 , the cathode terminal CA extending from the green light emitting element 10G to the red light emitting element 10R and the cathode terminal CA extending in the first direction X in the same pixel PX cross in plan view.

The cathode terminal CA extends in the second direction Y as follows, and connects the end of the emission surface of the light-emitting element 10B (the side of the rectangular emission surface extending in the first direction X) and another pixel arranged in the second direction Y. The end portion of the blue light-emitting element 10B included in the PX (the side of the rectangular output surface extending in the first direction X) passes through the opening CH6. In other words, the cathode terminals CA are The two ends of the light-emitting element 10B are connected to the end of the light-emitting element 10B included in the other adjacent pixel PX in the second direction Y, and the second direction passes through the opening CH6. Y extension.

As shown in FIG. 6 , a cathode terminal CA extending from the blue light-emitting element 10B to the blue light-emitting element 10B included in another pixel PX adjacent in the second direction Y and a cathode terminal CA extending in the first direction X Of course it crosses from a top view.

As shown in FIG. 6 , when the cathode terminals CA are mainly arranged to extend along the second direction Y, the extraction efficiency of light from the second direction Y is slightly reduced due to the arrangement of the cathode terminals CA. The advantage of the extraction efficiency of light in the first direction X.

In addition, in the case of the layout shown in FIG. 5, since the cathode terminals CA are in contact around the blue light-emitting element 10B, it may be difficult to extract the blue outgoing light, but in the case of the layout shown in FIG. 6, Since the light-emitting elements 10R, 10G, and 10B of any color are in contact with the cathode terminal CA at two ends, and the cathode terminal CA is not in contact with the surroundings, the possibility that it is difficult to extract the outgoing light of a specific color can be suppressed.

Furthermore, in the case of the layout shown in FIG. 5, since the voltage supply to the cathode terminal CA of the red light-emitting element 10R is performed (bridged) through the cathode terminal CA of the blue light-emitting element 10B, the light-emitting element 10R, emits light. The voltage applied between the elements 10G and 10B may be slightly different, but in the case of the layout shown in FIG. CA supplies voltages equally, so the possibility of applying different voltages as described above can be suppressed.

Hereinafter, the effect of the display device 1 of the present embodiment will be described using a comparative example. In addition, the comparative example is used to illustrate a part of the effects that the display device 1 of the present embodiment can exert, and it is not intended to exclude the common structure between the comparative example and the present embodiment from the scope of the present invention. success or effect.

FIG. 7 schematically shows the cross-sectional structure of the display device 100 of the comparative example. The display device 100 of the comparative example is different from the display device 1 of the present embodiment in that the cathode terminal CA is connected to the power supply wiring in the non-display area NDA outside the display area DA, and the cathode terminal CA is formed of a transparent conductive material.

In the display device 100 of the comparative example, the cathode terminal CA of the light-emitting element 10 included in the pixel PX is formed by a transparent conductive material such as ITO, and the cathode terminal CA is shared by a plurality of pixels PX, and the cathode terminal CA is applied with self The voltage supplied by the power wiring provided in the non-display area NDA. In this case, the voltage of the resistance of ITO drops, and the light-emitting element 10 arranged farther away from the power supply wiring provided in the non-display area NDA (for example, the light-emitting element 10 arranged near the center of the display area DA) is applied to the cathode. The problem that the voltage of terminal CA is smaller.

On the other hand, in the display device 1 of the present embodiment, since the common power supply wiring 22 (cathode wiring) corresponding to the above-mentioned power supply wiring is provided for each pixel PX, the resistance can be reduced, and the generation of the above-mentioned voltage can be suppressed. possibility of decline.

In addition, in the display device 1 of the present embodiment, since the cathode terminal CA is formed of a metal material such as titanium or a blackened metal rather than a transparent conductive material such as ITO, compared with the display device 100 of the comparative example, the The resistance can be reduced, and the possibility of the above-mentioned voltage drop can be further suppressed.

Furthermore, as shown in FIGS. 5 and 6 , the display device 1 of this embodiment can change the light extraction efficiency according to the layout of the cathode terminals CA, thereby obtaining the advantage of being able to meet various needs of users.

According to one of the embodiments described above, it is possible to provide a device capable of suppressing voltage drop in the light-emitting element 10 (micro LED) in which the anode terminal AN and the cathode terminal CA are arranged to face each other. Display device 1.

Above, based on the display device described as an embodiment of the present invention, all display devices implemented by appropriately modifying the design are within the scope of the present invention as long as they include the gist of the present invention.

If you are a business person, you can think of various modifications within the scope of the idea of the present invention, and it should be understood that these modifications also belong to the scope of the present invention. For example, those who appropriately add, delete, or change the design of the components, or add, omit, or change the conditions of the above-mentioned embodiments are included in the scope of the present invention as long as they have the gist of the present invention.

In addition, as for the other functions and effects brought about by the aspects described in the above-mentioned embodiments, those that are clarified from the description of this specification or those that are appropriately conceived by the industry should, of course, be understood to be brought about by the present invention.

This application is based on Japanese Patent Application No. 2019-090813 (filing date: May 13, 2019), and enjoys the priority of this application. This application incorporates all content of that application by reference to that application.

10: Light-emitting elements

22: Common power wiring

31: Insulation layer

32: Base coat

33: Interlayer insulating film

34: Flattening film

35: Conductive layer

36: Insulation layer

37: Pixel electrode

38: Common electrode

39: Flattening film

40: 1st relay electrode

41: 2nd relay electrode

42: Transparent conductive layer

43: Component insulation layer

44: Flattening film

45: polarizer

AN: Anode terminal

AR: Array substrate

CA: Cathode terminal

DA: display area

E1: 1st electrode

E2: 2nd electrode

GE: gate electrode

GI: Gate insulating film

SC: Semiconductor layer

Claims (8)

A display device comprising: a substrate; a light-emitting element mounted on the substrate; an anode terminal disposed at a bottom of the light-emitting element; and a cathode terminal disposed at an output of the light-emitting element on the opposite side of the anode terminal and the cathode terminal is formed of a metal material; the cathode terminal overlaps with the end of the emitting surface and does not overlap with the central portion of the emitting surface. The display device according to claim 1, further comprising: a transparent conductive layer disposed on the cathode terminal and the central portion of the emission surface. The display device of claim 1, comprising: a plurality of pixels each including the light-emitting element, the anode terminal, and the cathode terminal; and a cathode for supplying a voltage applied to the cathode terminal is provided for each pixel wiring. The display device of claim 3, wherein The cathode terminal is electrically connected to the cathode wiring via a cathode relay electrode, and the cathode relay electrode is arranged on the same layer as the anode terminal. The display device according to claim 4, comprising: an anode wiring for supplying a voltage applied to the anode terminal; and the anode terminal is electrically connected to the anode wiring via an anode relay electrode, and the anode relay electrode is connected to the anode terminal. The cathode relay electrodes are arranged on the same layer and do not overlap in plan view. The display device of claim 4, wherein the cathode terminal extends along the first direction as follows: connecting the end of the output surface and the output of the light-emitting element adjacent to the first direction parallel to the short side of the display device The end portion of the surface overlaps with the contact portion that is in contact with the cathode relay electrode in a plan view. The display device of claim 4, wherein the cathode terminal extends along the second direction as follows: connecting the end of the output surface and the output of the light-emitting element adjacent to the second direction parallel to the long side of the display device The end portion of the surface overlaps with the contact portion that is in contact with the cathode relay electrode in a plan view. The display device of claim 4, wherein the pixels are rectangular, and The red, green and blue light-emitting elements are arranged in a triangle shape at positions corresponding to 3 of the 4 vertices of the rectangle, and the contact portion for electrically connecting the cathode terminal and the cathode relay electrode is arranged on the The position corresponding to 1 vertex different from the above 3 vertices.

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