TWI747257B - A method for inspecting a skeleton wafer - Google Patents

Abstract

The present invention relates to a method for inspecting a skeleton wafer (1), comprising the steps of (i) performing template matching of at least one skeleton wafer image and at least one processed wafer image (101); (ii) rescaling said skeleton wafer image to match the processed wafer image’s size (103); and (iii) computing differences between said skeleton wafer image and said processed wafer image (107); Gaussian mask convolution is performed on at least one electronic component of said skeleton wafer image to suppress weight on at least one edge of said skeleton wafer image (105), said step is done after step (ii) and prior to step (iii).

Description

Method for inspecting hollow wafer

The present invention relates to a method for inspecting a skeleton wafer (skeleton wafer), and its purpose is to perform template matching between at least one skeletonized wafer image obtained later and at least one theoretically processed wafer image. ), the ultimate goal is to identify the difference between the two. The method includes the following steps: (i) photographing an image of the hollowed-out wafer; (ii) homogenizing the hollowed-out image obtained by shooting (by performing numerical standardization of the image obtained by shooting row by row and column by column ( (Or normalization) to suppress noise); (iii) use a template that conforms to a wafer map (or wafer map) to correct the angle of the hollow wafer; (iv) by edge The inspection method is further optimized to obtain the edge for cutting more accurately; (v) Re-scale the cut-out wafer image after cutting, and use Gaussian filter to binarize the image (or binarization) ); (vi) Obtain the difference between the hollow wafer obtained later and the theoretically processed wafer. Through the method, the inventor can use only a single image of a complete wafer for comparison, instead of using multiple stitched images that are assembled into a complete wafer for comparison, so the processing time can become Shorter.

As we all know, the traditional hollow wafer inspection method is manually completed by the operator. As a result, the operator superimposes the printed output used to visually present the processed (or processed) wafer (PW) map. On the hollowed-out wafer under the backlight condition, the physical hollowed-out wafer is visually compared with the printed output, and then the defective or defective die that has been erroneously removed from the hollowed-out wafer is manually verified.

Zhang et al. disclosed a wafer surface inspection method based on Gabor features and random dimensionality reduction in Chinese Patent CN 108171688A. According to this method, a CCD camera is used to collect an image of the wafer surface, and then the image is preprocessed. Design 40 Gabor filters to obtain the texture features of the wafer surface, and then perform a convolution operation on the 40 Gabor filters and the image to obtain 40 feature maps. For 40 feature maps Perform random dimensionality reduction, in which threshold partitioning is performed on the images obtained after dimensionality reduction, and the objective function of the segmentation threshold is constructed, and the objective function is solved to obtain the final segmentation threshold. The final segmentation threshold is used for the image Divide into foreground and background, determine the division threshold, and finally accurately detect wafer surface defects. However, the above-mentioned invention CN 108171688 A is a method for wafer surface inspection, which is different from the method of the present invention for inspection of hollowed-out wafers. The method of the present invention can inspect hollowed-out wafers by indicating the coordinates of the die. The Gaussian mask convolution has not been applied in CN 108171688 A.

Xu et al. disclosed a novel reticle inspection method and system in the US published patent US 2011299759 A1. The inspection method and system use modeling methods and information obtained from modeled images to identify various defects. The modeled or simulated image is generated directly from the test or reference image. Some examples include presenting an aerial image in which a desired pattern is projected on a substrate by a lithography system and a photoresist image in which a desired photoresist pattern is presented. First, make the test image present a mask pattern with a limited bandwidth. The pattern can contain only lines to speed up the image processing. Then, use this pattern to build a modeled image, and then use this modeled image to build a modeled feature map. The feature map is used as a basis for inspecting the original test image to identify reticle defects, and may contain information that allows distinguishing between various feature types based on the meaning of their lithography and other features. However, the US published patent US 2011299759 A1 does not disclose inspection steps capable of inspecting hollowed-out wafers and defining the coordinates or positions of dies or electronic components.

Therefore, it is advantageous to have a method of inspecting hollowed-out wafers to alleviate this shortcoming, whereby the inspection can identify the existence of good and/or defective dies by taking a single image of the hollowed-out wafer. The crystal grains have definite coordinates or positions.

Therefore, the main purpose of the present invention is to provide a method for inspecting hollowed-out wafers, which aims to provide high-precision and time-saving inspection procedures.

Another object of the present invention is to provide a method for inspecting hollowed-out wafers, wherein during or after picking and placing, the method can identify and locate under-picked or over-picked dies, and indicate according to the coordinates on the wafer The crystal grains.

Another object of the present invention is to provide a method for inspecting hollowed wafers, wherein the method aims to improve the sensitivity of the system.

By understanding the following detailed description of the present invention or the application of the present invention in practice, other objects of the present invention will become apparent.

According to a preferred embodiment of the present invention, the following content is provided: a method for inspecting hollowed-out wafers, including the following steps: (i) performing a template comparison between at least one hollowed-out wafer image and at least one processed wafer image Yes; (ii) rescaling the hollowed-out wafer image to fit the size of the processed wafer image; and (iii) calculating the difference between the hollowed-out wafer image and the processed wafer image Difference; characterized by: Performing a Gaussian mask convolution operation on at least one electronic component of the hollowed-out wafer image to suppress the weight on at least one edge of the hollowed-out wafer image. This step is performed after step (ii) and in step (iii). ) Before proceeding.

After studying the detailed description in conjunction with the following drawings, other aspects and advantages of the present invention will be discovered: Figure 1 presents an exemplary method flow of the present invention; Figure 2 presents another exemplary method flow of the present invention; An exemplary method flow for scaling a hollowed-out wafer image; and FIG. 4 presents an exemplary method flow for edge optimization of a hollowed-out wafer image.

In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, those of ordinary skill in the art will understand that the present invention can be practiced without these specific details. In other cases, well-known methods, procedures and/or elements have not been described in detail so as not to obscure the present invention.

The present invention will be understood more clearly from the following description of the embodiments of the present invention, which is made by way of example only with reference to the accompanying drawings, which are not drawn to scale.

As used in the present disclosure and the appended claims herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates or otherwise indicates.

Throughout the disclosure of this specification and the claims, the word "including" and its variants, such as "including" and "including", means "including but not limited to" and is not used to exclude other elements, integers, or step. "Exemplary" means "an example" and is not intended to convey an indication of a preferred or ideal embodiment, "such as" is not restrictive, but is used for illustrative purposes.

Referring to the exemplary process of the hollowed-out wafer inspection method (1) presented with reference to FIG. 1, the method (1) includes the following steps: (i) compare at least one hollowed-out wafer image and at least one processed wafer image Image template comparison (101), where the step (i) includes angle correction of the hollowed-out wafer image; (ii) rescaling the hollowed-out wafer image to fit the size of the processed wafer image (103); (iii) Calculate the difference between the hollowed-out wafer image and the processed wafer image (107); perform a Gaussian mask convolution operation on at least one electronic component of the hollowed-out wafer image In order to suppress the weight (105) on at least one edge of the hollowed-out wafer image, this step (105) is completed after step (ii) and before step (iii). After completing the above-mentioned steps (i), (ii) and (iii), the present invention can identify electronic components that are less or more selected. For example, the present invention can identify multiple selected electronic components from good products, and the latter is not expected to belong to the hollow wafer to be inspected. In addition, the present invention can detect unselected electronic components from defective electronic components, unprocessed dies, dummy dies or mirror dies, and the latter is expected to exist on the hollow wafer to be inspected. Finally, the error selection rate can be displayed or expressed based on the difference between the inspected hollow wafer and the wafer map.

At the same time, the invention can use only a single image of a complete wafer, instead of using multiple stitched images assembled into a complete wafer for suitable comparison, to perform hollow wafer inspection on missing or redundant electronic components.

Referring to another exemplary process of the method (1) for inspecting a hollowed-out wafer shown in FIG. 2, the method (1) further includes a step (201) of taking an image of the hollowed-out wafer. A single image is processed on the hollowed-out wafer to calculate the missing or redundant electronic components (such as dies); then the hollowed-out wafer image is homogenized (202). The homogenization of the hollowed-out wafer image is achieved by normalizing the hollowed-out wafer image with at least two one-dimensional vector components, one at a time. It is obtained by projecting on the axis, so this step is completed before step (i).

The step of rescaling the hollowed-out wafer image (103) may be performed after the step of homogenizing the hollowed-out wafer image (202), so that the homogenization can serve as an enhancement method for improving inspection performance. Alternatively, the step of rescaling the hollowed-out wafer image (103) may be performed when the hollowed-out wafer image is not homogenized (202). In addition, before step (ii) and after step (i), the edge optimization (205) of the hollowed-out wafer image is performed.

Refer to the exemplary method flow of rescaling the hollowed-out wafer image (203) shown in FIG. 3. In this case, this step includes the sub-step (301) of measuring the spacing value between the electronic components of the hollowed-out wafer; and then determining the scaling factor (303) of the template for the hollowed-out wafer image and the Template comparison of processed wafer images; finally build a template image with a wafer map, where each electronic component of the template image has a resolution of at least 3×3 pixels (305), preferably It is in the range of 3×3 pixels to 10×10 pixels.

Referring to the exemplary method flow of the edge optimization (205) of the hollowed-out wafer image shown in FIG. 4, the step is performed by the following sub-steps: identifying the edge of at least one side of the hollowed-out wafer image Use the position as a reference (401); verify the position of the edge with the maximum gradient of the pixel grayscale value (403); and use the measured position to update the edge of the wafer selection area (405).

Claims (7)

A method (1) for inspecting hollowed-out wafers, including the following steps: (i) performing template comparison (101) between at least one hollowed-out wafer image and at least one processed wafer image; (ii) rescaling the Hollowing out the wafer image to match the size of the processed wafer image (103); and (iii) calculating the difference between the hollowed-out wafer image and the processed wafer image (107); The method is characterized in that the step of performing a Gaussian mask convolution operation on at least one electronic component of the hollowed-out wafer image to suppress the weight (105) on at least one edge of the hollowed-out wafer image is performed in the step (ii) ) And before this step (iii). The method (1) for inspecting a hollowed-out wafer according to claim 1, wherein the method (1) further includes homogenizing the hollowed-out wafer image by normalizing the hollowed-out wafer image with at least two one-dimensional vector components The step of wafer image (202), in which the one-dimensional vector component is obtained by projection on rows and columns, so that this step is completed before step (i). The method (1) for inspecting a hollowed-out wafer according to claim 1 or 2, wherein the method (1) further includes the following step: performing edge optimization on the hollowed-out wafer image (205), wherein the step is Execute before step (ii) and after step (i). The method (1) for inspecting a hollowed-out wafer according to claim 1, wherein the step of rescaling the hollowed-out wafer image (103) includes the following sub-steps: (a) measuring the gap between the electronic components of the hollowed-out wafer (301); (b) Determine the template scaling factor (303) used for the template comparison of the hollowed-out wafer image and the processed wafer image; and (c) Constructing a template image (305) using a wafer map, wherein each electronic component of the template image has a resolution of at least 3×3 pixels. The method (1) for inspecting a hollowed-out wafer according to claim 1, wherein the step (i) of comparing at least one hollowed-out wafer image with at least one processed wafer image includes comparing the Angle adjustment and angle correction of the hollow wafer image. The method (1) for inspecting a hollowed-out wafer according to claim 3, wherein the step (205) of performing edge optimization on the hollowed-out wafer image includes the following sub-steps: (a) identifying the hollowed-out wafer image (401); (b) Use the maximum gradient of the pixel gray scale value to verify the position of the edge; and (c) Use the measured position to update the edge of the wafer selection area (405). The method (1) for inspecting a hollowed-out wafer according to claim 1 or 2 or 4 or 5, wherein the hollowed-out wafer image is taken by using at least one imaging unit to take an image of the hollowed-out wafer (201) And obtained.

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