TWI746854B - High electron mobility transistor and method for forming the same - Google Patents

Abstract

A method for forming a high electron mobility transistor includes forming a buffer layer on a transparent substrate. A barrier layer is formed on the buffer layer. A channel layer is disposed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. A dielectric layer is formed on the barrier layer. Source/drain electrodes are formed through the dielectric layer and the barrier layer and disposed on the buffer layer. A shielding layer is formed conformally covering the dielectric layer and the source/drain electrodes. A thermal process is performed on the source/drain electrodes.

Description

High electron mobility transistor and its forming method

The embodiment of the present invention relates to a semiconductor technology, in particular to a high electron mobility transistor.

High Electron Mobility Transistor (HEMT) is widely used in high power semiconductor devices due to its advantages of high breakdown voltage and high output voltage.

Traditionally, high electron mobility transistors are formed by stacking three or five group semiconductors. However, the heterojunction formed between the source/drain electrode and the third and fifth group semiconductor has a very high resistance value. A high-temperature thermal process is required to diffuse the metal to form an ohmic contact to reduce the contact resistance ( contact resistance, Rc) resistance value. However, when the third and fifth group semiconductors and the substrate are both light-transmitting materials, it is easy to make the temperature sensor detect abnormalities, and the ohmic contact formation fails, which makes it impossible to effectively reduce the resistance.

Although the existing high electron mobility transistors generally meet the requirements, they are not satisfactory in all aspects. In particular, the formation of good ohmic contacts for high electron mobility transistors still needs further improvement.

According to one embodiment, the present invention provides a method for forming a high electron mobility transistor, including: forming a buffer layer on a light-transmitting substrate; forming a barrier layer on the buffer layer, and the channel region is located in the buffer layer, adjacent to the buffer layer and The interface of the barrier layer; the formation of a dielectric layer on the barrier layer; the formation of source/drain electrodes, which pass through the dielectric layer and the barrier layer, and are placed on the buffer layer; the formation of a light-shielding layer that conforms to the dielectric Layer and source/drain electrodes; and thermally process the source/drain electrodes.

According to another embodiment, the present invention provides a high electron mobility transistor including: a buffer layer located on a light-transmitting substrate; a barrier layer located on the buffer layer, wherein the channel region is located in the buffer layer and is adjacent to the buffer layer and the barrier layer. The interface of the layer; the dielectric layer is located on the barrier layer; the source/drain electrode passes through the dielectric layer and the barrier layer and is located on the buffer layer; the light shielding layer covers the source/drain electrode.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, several embodiments are cited below in conjunction with the accompanying drawings, which are described in detail as follows.

10‧‧‧wafer

12‧‧‧Temperature sensor

16‧‧‧Light source

100, 200, 300, 400‧‧‧High electron mobility transistor

102‧‧‧Substrate

104‧‧‧Buffer layer

106‧‧‧Barrier layer

108‧‧‧Passage Area

110‧‧‧Dielectric layer

112‧‧‧Source/Drain electrode

112i‧‧‧Interface

114, 114a, 114b‧‧‧shading layer

116‧‧‧Heat process

118‧‧‧Etching process

120‧‧‧Gate electrode

224‧‧‧Etching stop layer

318‧‧‧Etching process

426‧‧‧Energy Band Adjustment Layer

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale and are only used for illustration and illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention.

Figures 1 to 6, 7A, 7B, 8, and 9 are schematic cross-sectional diagrams illustrating different stages of forming a high electron mobility transistor according to some embodiments.

10 to 12 are schematic cross-sectional diagrams illustrating different stages of forming a high electron mobility transistor according to other embodiments.

13 to 14 are schematic cross-sectional diagrams illustrating different stages of forming a high electron mobility transistor according to still other embodiments.

15 to 16 are schematic cross-sectional diagrams of high electron mobility transistors drawn according to still other embodiments.

FIG. 17 is a graph showing the temperature rise curve for forming a high electron mobility transistor according to some embodiments.

Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes specific elements and their arrangement embodiments to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and should not be used to limit the scope of the embodiments of the present invention. For example, in the specification, it is mentioned that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and it also includes the embodiments between the first feature and the second feature. The embodiment of the feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or labels may be used in different embodiments, and these repetitions are only used to briefly and clearly describe the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and/or structures discussed.

In addition, terms that are relative to space may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spaces are relatively used In order to facilitate the description of the relationship between one element(s) or feature and another element(s) or feature in the illustration, the relative terms in space include the different orientations of the device in use or operation, as well as in the drawings. The orientation described. When the device is turned to different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, if there is no specific description of "about", "approximately" or "approximately", "about", "approximately", and "approximately" can still be implied. The meaning of "probably".

Although the steps in some of the described embodiments are performed in a specific order, these steps can also be performed in other logical orders. In different embodiments, some of the steps described may be replaced or omitted, and some other operations may be performed before, during, and/or after the steps described in the embodiments of the present invention. Other features can be added to the high electron mobility transistor in the embodiment of the present invention. In different embodiments, some features may be replaced or omitted.

The embodiment of the present invention provides a method for forming a high electron mobility transistor (HEMT). When the ohmic contact between the source/drain electrode and the channel layer is formed by a high temperature thermal process, the device is The light-shielding layer is formed to prevent high-temperature light from passing through the light-transmitting Group III or 5 semiconductors and the light-transmitting substrate, and the temperature sensor under the substrate detects abnormality, so that a good ohmic contact cannot be formed, and the resistance cannot be reduced.

FIGS. 1-9 are schematic cross-sectional diagrams illustrating different stages of forming the high electron mobility transistor 100 according to some embodiments. As shown in FIG. 1, a substrate 102 is provided. In some embodiments, the substrate 102 may be an Al ₂ O ₃ (sapphire) substrate. In addition, the aforementioned semiconductor substrate can also be an element semiconductor, including silicon or germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide, and gallium arsenide. , Gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors, including silicon germanium alloy (SiGe), phosphorous gallium arsenide alloy (GaAsP), AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or the above materials的组合。 The combination. In some embodiments, the substrate 102 may be a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination of the above. In addition, the substrate 102 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a bottom plate, a buried oxide layer disposed on the bottom plate, or a semiconductor layer disposed on the buried oxide layer. . In some embodiments, the substrate 102 is a light-transmitting substrate. In this context, the light-transmitting substrate 102 refers to the substrate 102 having a transmittance of more than 10% under a light source with a wavelength of 300 nm to 2500 nm, for example, a transmittance of 10% to 99%.

Next, as shown in FIG. 2, a buffer layer 104 is formed on the substrate 102. In some embodiments, the buffer layer 104 includes a III-V semiconductor, such as GaN. The buffer layer 104 may also include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V semiconductor materials, or a combination thereof. In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), and hydride vapor phase epitaxy (MBE) may be used. HVPE), other appropriate methods, or a combination of the above to form the buffer layer 104 on the substrate 102.

Next, as shown in FIG. 3, a barrier layer 106 is formed on the buffer layer 104. In some embodiments, the barrier layer 106 includes a material different from the buffer layer 104. The barrier layer 106 may include a III-V semiconductor, such as Al _x Ga _1-x N, where 0<x<1. The barrier layer 106 may also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other appropriate III-V materials, or a combination of the foregoing. In some embodiments, the barrier layer 106 can be formed on the buffer layer 104 using molecular beam epitaxy, metal organic vapor deposition, hydride vapor epitaxy, other appropriate methods, or a combination of the above.

Since the materials of the buffer layer 104 and the barrier layer 106 are different, and their band gaps are different, a heterojunction is formed at the interface between the buffer layer 104 and the barrier layer 106. The energy band at the heterojunction is bent, and the conduction band (conduction band) is bent deep to form a quantum well, which confines the electrons generated by the piezoelectric effect (Piezoelectricity) in the quantum well. Therefore, the buffer layer 104 and the barrier A two-dimensional electron gas (2DEG) is formed at the interface of the layer 106 to form a conduction current. As shown in FIG. 3, a channel region 108 is formed at the interface between the buffer layer 104 and the barrier layer 106, and the channel region 108 is where the two-dimensional electron gas forms a conduction current.

Next, as shown in FIG. 4, a dielectric layer 110 is formed on the barrier layer 106. In some embodiments, the dielectric layer 110 is an oxide. In some embodiments, the dielectric layer 110 includes SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , MgO, Sc ₂ O ₃ , HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO ₂ , ZnO ₂ , ZrO ₂ , AlSiN ₃ , SiC, or Ta ₂ O ₅ , other suitable dielectric materials, or a combination of the above. In some embodiments, chemical vapor deposition (chemical vapor deposition, CVD) (such as plasma enhanced chemical vapor deposition (plasma enhanced CVD, PECVD), high density plasma chemical vapor deposition (high density plasma CVD) , HDPCVD), atomic layer deposition (ALD), and/or other suitable techniques to deposit dielectric materials to form the dielectric layer 110. In some embodiments, a thermal oxidation process may be used to thermally grow the dielectric layer 110 in an oxygen-containing or nitrogen-containing environment (for example, containing NO or N _{2 O).} The dielectric layer 110 can reduce the leakage current in the subsequent gate formation, increase the voltage range that the gate can withstand, and further reduce the channel resistance.

Next, as shown in FIG. 5, a source/drain electrode 112 is formed, which passes through the dielectric layer 110 and the barrier layer 106, and is disposed on the buffer layer 104. In some embodiments, each of the source/drain electrodes 112 may include Ti, Al, W, Au, Pd, other suitable metal materials, alloys thereof, or combinations thereof. In some embodiments, a lithography process and an etching process may be performed to form source/drain electrode openings in the dielectric layer 110 and the barrier layer 106, and then chemical vapor deposition, physical vapor deposition (such as Evaporation or sputtering), electroplating, atomic layer deposition, other appropriate methods, or a combination of the above to deposit a conductive material on the dielectric layer 110 and fill it into the source/drain electrode opening, and then remove it by an etching process The conductive material outside the source/drain electrode openings forms the source/drain electrode 112.

In some embodiments, after forming the source/drain electrode openings, before filling conductive materials to form the source/drain electrodes 112, a passivation layer is conformably formed to line the source/drain electrodes 112 and the dielectric. Between the electrical layer 110 and the barrier layer 106 (not shown). The passivation layer may include SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), Other insulating materials, or a combination of the above. In some embodiments, the passivation layer may be formed using metal organic vapor deposition, chemical vapor deposition, other appropriate methods, or a combination of the above. The passivation layer can protect the underlying film and provide physical isolation and structural support.

Next, as shown in FIG. 6, a light shielding layer 114 is formed to conformably cover the dielectric layer 110 and the source/drain electrodes 112. In some embodiments, the light shielding layer 114 includes TiN. The light-shielding layer 114 may also include Al, Ag, Cu, AlCu, Pt, W, Ru, Ni, TaN, TiAlN, TiW, TiO, TiO ₂ , other light-blocking materials, or a combination thereof. In some embodiments, the light-shielding layer 114 may be deposited using a physical vapor deposition process (such as evaporation or sputtering), atomic layer deposition, electroplating, other suitable processes, or a combination of the foregoing. The light-shielding layer 114 can be selected from materials with a transmittance of less than 10%, for example, 0% to 10%, for a light source with a wavelength of 300 nm to 2500 nm. The thickness of the light-shielding layer 114 may be 100 Å to 2000 Å, and the thickness will vary depending on the light transmission characteristics of the selected material. If the thickness of the light-shielding layer 114 is too thick, the film may be easily broken or peeled due to overhang. If the thickness of the light-shielding layer 114 is too thin, the light-shielding effect may be insufficient.

Then, as shown in FIG. 7A, a thermal process 116 is performed on the source electrode/drain electrode 112. Due to the high temperature of the thermal process 116, the metal in the source electrode/drain electrode 112 will diffuse to the channel region 108, thus forming an ohmic contact at the interface 112i between the source electrode/drain electrode 112 and the channel region 108, which can reduce The resistance value of the interface 112i between the source electrode/drain electrode 112 and the channel region 108. In some embodiments, the thermal process 116 uses an infrared light source with a wavelength between 700 nm and 2500 nm. The temperature of the thermal process 116 is between 500° C. and 1000° C., and the duration is between 10 seconds and 120 seconds. If the temperature of the thermal process 116 is too high or the time is too long, the device characteristics may be deteriorated due to high temperature or long-time reaction by-products and form a high-resistance interface. If the temperature is too low or the time is too short, it will not be able to The interface 112i between the electrode/drain electrode 112 and the channel region 108 forms a good ohmic contact.

FIG. 7B is a schematic cross-sectional view of the device during the thermal process 116 according to some embodiments. In some embodiments, the high electron mobility transistor 100 is formed on the wafer 10, including the substrate 102 and the structure above it, and the temperature sensor 12 is located under the wafer 10. During the thermal process 116, the light source 16 irradiates the wafer 10, and the temperature sensor 12 at the bottom detects the temperature of the wafer 10 to determine the length of time the light source 16 irradiates. However, when the substrate 102 is a light-transmitting substrate, the light source 16 may penetrate the substrate 102 and directly illuminate the temperature sensor 12, resulting in an increase in the detected temperature. However, at this time, the wafer 10 may not have absorbed enough heat energy. Therefore, the interface 112i between the source electrode/drain electrode 112 and the channel region 108 cannot form an ohmic contact, so that the resistance cannot be effectively reduced.

As shown in FIGS. 7A and 7B, since the light shielding layer 114 is formed on the dielectric layer 110 and the source electrode/drain electrode 112 before the thermal process 116, the light source 16 used for heating in the thermal process 116 is not easily penetrated The structure of the substrate 102 and its upper part, therefore, the temperature sensor at the bottom of the wafer 10 is less prone to abnormal temperature detection. Therefore, the thermal process 116 can be performed between the source electrode/drain electrode 112 and the channel region 108 The interface 112i forms a good ohmic contact, further reducing the resistance.

It is worth noting that the number, shape, and configuration of the temperature sensors 12 at the bottom of the wafer 10 shown in FIG. 7B are only an example, and the embodiment of the present invention is not limited thereto. In the embodiment of the present invention, the temperature sensors 12 at the bottom of the wafer 10 can be of any number, shape, and configuration, depending on the process requirements.

Then, as shown in FIG. 8, the light-shielding layer 114 is removed by an etching process 118. In some embodiments, the etching process 118 may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. For example, the dry etching process can include oxygen-containing gas, fluorine-containing gas (such as CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ , and/or C ₂ F ₆ ), and chlorine-containing gas (such as Cl ₂ , CHCl ₃₎ , CCl ₄ , and/or BCl ₃ ), bromine-containing gas (such as HBr and/or CHBR ₃ ), iodine-containing gas, other suitable gas and/or plasma, and/or a combination of the foregoing. For example, the wet etching process may include dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia (ammonia), hydrofluoric acid (HF) solution, Etching in nitric acid (HNO ₃ ), and/or acetic acid (CH ₃ COOH), or other suitable wet etchant. In some embodiments, the etching process 118 completely removes the light shielding layer 114. The light shielding layer 114 remaining between the source electrode/drain electrode 112 and contacting different source electrode/drain electrode 112 may cause an unwanted short circuit.

Next, as shown in FIG. 9, a gate electrode 120 is formed on the barrier layer 106. In some embodiments, the gate electrode 120 may include polysilicon, metal (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or a combination thereof), metal alloy, metal nitride (e.g., nitrogen Tungsten silicide, molybdenum nitride, titanium nitride, tantalum nitride, the like, or a combination of the above), metal silicide (e.g. tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, and similar Or a combination of the above), a metal oxide (ruthenium oxide, indium tin oxide, the like, or a combination of the above), other suitable conductive materials, or a combination of the above. In some embodiments, a lithography process and an etching process may be performed to form gate openings in the dielectric layer 110, and then a chemical vapor deposition process (such as a low pressure vapor deposition process or a plasma-assisted chemical vapor deposition process) ), physical vapor deposition process (such as resistance heating evaporation method, electron beam evaporation method, or sputtering method), electroplating method, atomic layer deposition process, other suitable processes, or a combination of the above on the dielectric layer 110 The conductive material is deposited and filled into the gate opening, and then the conductive material outside the gate opening is removed by etching to form the gate electrode 120.

As mentioned above, before the thermal process, the high electron mobility transistor is covered with a light shielding layer to prevent the heating light of the thermal process from penetrating the high electron mobility transistor, which may cause abnormal temperature detection. The normal heating of the thermal process can form a good ohmic contact at the interface between the source electrode/drain electrode and the channel area, reducing the contact resistance.

FIGS. 10 to 12 show schematic cross-sectional views showing different stages of forming the high electron mobility transistor 200 according to other embodiments of the present invention. The same or similar manufacturing processes or components as in the foregoing embodiment will use the same component symbols, and the detailed content will not be repeated. The difference from the foregoing embodiment is that, as shown in FIG. 10, before the light shielding layer 114 is formed, an etch stop layer 224 is formed to conformably cover the dielectric layer 110 and the source/drain electrodes 112.

In some embodiments, the etch stop layer 224 is an oxide. In some embodiments, the etch stop layer 224 includes SiO ₂ , Si ₃ N ₄ , SiON, Al ₂ O ₃ , MgO, Sc ₂ O ₃ , HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO ₂ , ZnO ₂ , ZrO ₂ , or Ta ₂ O ₅ , similar materials, or a combination of the above. In some embodiments, chemical vapor deposition methods (such as plasma enhanced chemical vapor deposition, high-density plasma chemical vapor deposition), atomic layer deposition processes, and/or other suitable techniques may be used to deposit dielectric materials to An etch stop layer 224 is formed. In some embodiments, the thickness of the etch stop layer 224 may be 100 Å to 2000 Å. If the thickness of the etch stop layer 224 is too thick, holes may be caused by overhangs or the film may be broken due to excessive stress. If the thickness of the etch stop layer 224 is too thin, it may not be enough to stop the subsequent etching process on this layer. Above.

Next, as shown in FIG. 11, a thermal process 116 is performed on the source electrode/drain electrode 112. Due to the high temperature of the thermal process 116, the metal in the source electrode/drain electrode 112 will diffuse to the channel region 108, thus forming an ohmic contact at the interface 112i between the source electrode/drain electrode 112 and the channel region 108. Since the light shielding layer 114 is formed on the dielectric layer 110 and the source/drain electrode 112 before the thermal process 116, the light used for heating in the thermal process 116 is less likely to penetrate the high electron mobility transistor 100, so It is less likely to cause abnormal temperature detection. Therefore, the thermal process 116 can form a good ohmic contact at the interface 112i between the source electrode/drain electrode 112 and the channel region 108 to further reduce the resistance.

Then, as shown in FIG. 12, the light-shielding layer 114 is removed by an etching process 118. In some embodiments, after the etching process 118 removes the light shielding layer 114, the remaining etching stop layer 224 covers the source electrode/drain electrode 112. Therefore, the thickness of the source electrode/drain electrode 112 may not be changed by the etching process 118, so that after the etching process 118, the thickness of the source electrode/drain electrode 112 is uniform. In some embodiments, the dielectric layer 110 and the etch stop layer 224 are both oxides. In some embodiments, the etching rate of the etching stop layer 224 and the dielectric layer 110 during the etching process 118 is much lower than that of the light shielding layer 114, for example, the etching rate ratio is 1:3 to avoid excessive etching of the source electrode during the etching process 118. Drain electrode 112. In some embodiments, the etching rate of the etch stop layer 224 and the dielectric layer 110 during the etching process 118 is different to avoid over-etching the dielectric layer 110 during the etching process 118.

In some embodiments, after the etching process 118, a deposition process or a thermal oxidation process may be further used to compliantly cover the oxide layer on the etch stop layer 224 (not shown). However, even when the etch stop layer 224 is an oxide, since the etch stop layer 224 is subjected to the thermal process 116, and the oxide layer is not subjected to the thermal process 116, the etch stop layer 224 and the oxide layer are not subject to the subsequent etching process. The etching rate is also different, which can prevent the etching stop layer 224 from being over-etched in the subsequent etching process.

In the embodiment shown in Figures 10 to 12, before the thermal process, the high electron mobility transistor is covered with an etching stop layer and a light shielding layer to prevent heating light from penetrating the high electron mobility transistor, causing The abnormal temperature detection phenomenon, the normal heating of the thermal process can form a good ohmic contact at the interface between the source electrode/drain electrode and the channel area, further reducing the contact resistance. The etching stop layer can also avoid excessive etching of the source electrode/drain electrode and the dielectric layer underneath when the light shielding layer is removed, so that the thickness of the source electrode/drain electrode is uniform.

FIGS. 13 to 14 show schematic cross-sectional views showing different stages of forming the high electron mobility transistor 300 according to other embodiments of the present invention. The same or similar manufacturing processes or components as in the foregoing embodiment will use the same component symbols, and the detailed content will not be repeated. The difference from the foregoing embodiment is that, as shown in FIG. 13, after the thermal process 116 is performed, the light-shielding layer 114 is selectively removed by the etching process 318. In some embodiments, the light shielding layer 114 is selectively removed by a patterning process. The patterning process can include photoresist coating (e.g. spin coating), soft baking, mask alignment, pattern exposure, post-exposure baking, photoresist development, cleaning and drying (e.g. hard baking) )), other suitable technologies, or a combination of the above. The etching process may include a dry etching process (for example, reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination of the foregoing. After removing the light-shielding layer 114, the remaining light-shielding layers 114 respectively include a light-shielding layer 114a covering both sidewalls of the source electrode/drain electrode 112 and a light-shielding layer 114b covering only the dielectric layer 110.

Next, as shown in FIG. 14, a gate electrode 120 is formed on the barrier layer 106. In some embodiments, the remaining light shielding layers 114a and 114b do not contact the gate electrode 120. If the remaining light shielding layers 114a and 114b remain between the source/drain electrode 112 and the gate electrode 120 and contact different source/drain electrodes 112 and the gate electrode 120, it may cause unwanted Short circuit. In addition to the light shielding layer 114 as shielding light during the thermal process 116, the remaining light shielding layer 114b can also be used for other winding purposes later.

In the embodiment shown in Figures 13 to 14, before the thermal process, the high electron mobility transistor is covered with a light-shielding layer to prevent heating light from penetrating the high electron mobility transistor, causing abnormal temperature detection The phenomenon of normal heating in the thermal process can form a good ohmic contact at the interface between the source electrode/drain electrode and the channel area, reducing the contact resistance. Then, the light-shielding layer is selectively removed, and the remaining part of the light-shielding layer can be used for other winding purposes later, saving process cost and time.

FIGS. 15 to 16 are schematic cross-sectional diagrams illustrating the formation of a high electron mobility transistor 400 according to still other embodiments of the present invention. The same or similar manufacturing processes or components as in the foregoing embodiment will use the same component symbols, and the detailed content will not be repeated. The difference from the previous embodiment is that the aforementioned high electron mobility transistor does not require an external gate voltage, and the high electron mobility transistor is in the conducting state, which is a depletion mode (D-mode) high electron mobility. Rate transistors. However, as shown in FIG. 15, before forming the dielectric layer 110, an energy band adjustment layer 426 is formed on the barrier layer 106 and is located below the predetermined area of the gate electrode 120 to be formed later. The band adjustment layer 426 is a P-type doped Group III or V semiconductor, including P-type doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs, and its P-type doping concentration is between 1e17/cm ³ To 1e20/cm ³ . In some embodiments, molecular beam epitaxy, organometal vapor deposition, chemical vapor deposition, hydride vapor epitaxy can be used to deposit P-type doped Group III and V semiconductors, and then through, for example, a photolithography process And an etching process, it is patterned to form an energy band adjustment layer 426.

Next, as shown in FIG. 15, the light shielding layer 114 is covered on the high electron mobility transistor 400, and then a thermal process 116 is performed. Due to the high temperature of the thermal process 116, the metal in the source electrode/drain electrode 112 will diffuse to the channel region 108, thus forming an ohmic contact at the interface 112i between the source electrode/drain electrode 112 and the channel region 108. Since the light shielding layer 114 is formed on the dielectric layer 110 and the source/drain electrode 112 before the thermal process 116, the light used in the thermal process 116 for heating is less likely to penetrate the high electron mobility transistor 400, so It is less likely to cause abnormal temperature detection. Therefore, the thermal process 116 can form a good ohmic contact at the interface 112i between the source electrode/drain electrode 112 and the channel region 108 to further reduce the resistance.

Next, as shown in FIG. 16, after removing the light shielding layer 114, a gate electrode 120 is formed on the energy band adjustment layer 426 to electrically connect the two. Since the energy band adjustment layer 426 is a P-type doped Group III-V semiconductor, the P-type doping can increase the energy band. Therefore, the quantum well energy at the interface between the buffer layer 104 and the barrier layer 106 can be higher than the Fermi level, resulting in a channel There may be no two-dimensional electron gas generated in the layer 108, so there may be no conduction current. In the above embodiment, since the energy band adjustment layer 426 can raise the energy band, when the gate voltage is not applied, the high electron mobility transistor 400 can be in the off state, that is, the high electron mobility transistor 400 can be an enhancement type. mode, E-mode) high electron mobility transistor. Compared with the depletion type (D-mode) high electron mobility transistor, the enhanced (E-mode) high electron mobility transistor is safer, has lower standby power dissipation, and does not require Supplying a negative bias voltage can also reduce circuit complexity and manufacturing costs.

In the embodiment shown in Figures 15 to 16, before the thermal process, the high electron mobility transistor is covered with a light-shielding layer to prevent the heating light source from penetrating the high electron mobility transistor, causing abnormal temperature detection The normal heating of the thermal process can make the interface between the source electrode/drain electrode and the channel area form a good ohmic contact, further reducing the contact resistance. By forming an energy band adjustment layer under the gate electrode to adjust the energy band, an enhanced high electron mobility transistor is formed that is in an off state when no gate voltage is applied.

It is worth noting that the aforementioned embodiments of high electron mobility transistors 100, 200, and 300 can also be applied to the embodiments shown in Figures 15 to 16. An energy band adjustment layer is formed under the gate electrode to adjust the energy band to form an enhanced Type high electron mobility transistor.

FIG. 17 is a graph showing the temperature rise curve for forming a high electron mobility transistor according to some embodiments. The solid line data indicates the heating curve of the light shielding layer 114 when the thermal process 116 is not used. The dotted line data represents the temperature rise curve of the light shielding layer 114 when the thermal process 116 is performed.

As shown in FIG. 17, if the light-shielding layer 114 is not used during the thermal process 116, it is easy to cause abnormal detection of the temperature sensor, and the measured temperature will fluctuate and be unstable, causing the formation of ohmic contact to fail and the resistance cannot be reduced. In contrast, when the light-shielding layer 114 is used, the temperature rises steadily. Therefore, the thermal process can be heated normally, and a good ohmic contact can be formed at the interface between the source electrode/drain electrode and the channel region, further reducing the contact resistance .

Although the advantages related to certain embodiments of the present technology have been described in the embodiments, other embodiments may also have such advantages. Not all embodiments must have the above advantages to be within the scope of the present invention.

In summary, the embodiment of the present invention provides a method for forming a high electron mobility transistor. Before the thermal process is performed to form the ohmic contact at the interface between the source electrode/drain electrode and the channel region, the source electrode /A light-shielding layer is formed on the drain electrode and the dielectric layer to prevent the heated high temperature light from penetrating the high electron mobility transistor, causing abnormal temperature detection. In this way, the thermal process can be heated normally, and a good ohmic contact is formed at the interface between the source electrode/drain electrode and the channel region, which further reduces the contact resistance. In addition, an etching stop layer can be formed before the light shielding layer is formed to make the thickness of the source electrode/drain electrode uniform. In addition, if the light-shielding layer is selectively removed, the remaining light-shielding layer will be used for subsequent winding purposes. This method can be applied to form depletion high electron mobility transistors and enhanced high electron mobility transistors.

The above content summarizes the features of many embodiments, so anyone with ordinary knowledge in the technical field can better understand the aspects of the embodiments of the present invention. Anyone with ordinary knowledge in the technical field may design or modify other manufacturing processes and structures based on the embodiment of the present invention without difficulty to achieve the same purpose and/or obtain the same advantages as the embodiment of the present invention. Any person with ordinary knowledge in the technical field should also understand that various changes, substitutions and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such equivalent creations do not exceed the spirit and scope of the embodiments of the present invention.

100‧‧‧High Electron Mobility Transistor

102‧‧‧Substrate

104‧‧‧Buffer layer

106‧‧‧Barrier layer

108‧‧‧Passage Area

110‧‧‧Dielectric layer

112‧‧‧Source/Drain electrode

112i‧‧‧Interface

114‧‧‧Shading layer

116‧‧‧Heat process

Claims (16)

A method for forming a high electron mobility transistor (HEMT) includes: forming a buffer layer on a transparent substrate; forming a barrier layer on the buffer layer, wherein a channel region is located in the buffer layer Layer, adjacent to an interface between the buffer layer and the barrier layer; forming a dielectric layer on the barrier layer; forming a source/drain electrode passing through the dielectric layer and the barrier layer, and On the buffer layer; forming a light-shielding layer to conformally cover the dielectric layer and the two sidewalls and upper surface of the source/drain electrode; and after forming the light-shielding layer, the source electrode /Drain electrode undergoes a thermal process. The method for forming a transistor with a high electron mobility as described in item 1 of the scope of the patent application further includes: after performing the thermal process, completely removing the light-shielding layer. The method for forming a high electron mobility transistor as described in item 1 of the scope of the patent application further includes: after performing the thermal process, selectively removing a portion of the light-shielding layer on the dielectric layer, wherein the remaining light-shielding layer The layer covers both sidewalls of the source/drain electrode. The method for forming a high electron mobility transistor as described in item 2 or 3 of the scope of the patent application further includes: before forming the light shielding layer, forming an etch stop layer to conformally cover the dielectric layer and On the source/drain electrode. According to the method for forming a high electron mobility transistor described in item 4 of the scope of patent application, the etching stop layer and the dielectric layer are both oxides, and when the light shielding layer is removed, the etching stop layer and the dielectric layer The etching rate of the electrical layer is different. The method for forming a high-electron mobility transistor as described in item 1 of the scope of the patent application further includes: forming a gate electrode on the barrier layer and located between the source/drain electrodes. The method for forming a high electron mobility transistor as described in item 6 of the scope of the patent application further includes: forming a band adjustment layer on the barrier layer before forming the gate electrode, and It is located under a predetermined area of the gate electrode; wherein the energy band adjustment layer is a P-type doped Group III-V semiconductor. According to the method for forming a high electron mobility transistor described in claim 1, wherein the thermal process reduces the resistance of an interface between the source/drain electrode and the channel region. According to the method for forming a high electron mobility transistor described in claim 1, wherein the temperature of the thermal process is between 500° C. and 1000° C., and the duration of the thermal process is between 10 seconds and 120 seconds. The method for forming a high electron mobility transistor as described in the scope of the patent application, wherein the light-shielding layer includes TiN, Al, Ag, Cu, AlCu, Pt, W, Ru, Ni, TaN, TiAlN, TiW, TiO , TiO ₂ , or a combination of the above. A high electron mobility transistor includes: a buffer layer on a light-transmitting substrate; a barrier layer on the buffer layer, wherein a channel region is located in the buffer layer, adjacent to the buffer layer and the barrier layer An interface of the layer; a dielectric layer located on the barrier layer; a source/drain electrode passing through the dielectric layer and the barrier layer and disposed on the buffer layer; a light-shielding layer covering On both sidewalls and upper surface of the source/drain electrode; and a gate electrode located on the barrier layer and between the source/drain electrodes, wherein the light-shielding layer does not contact the gate electrode . In the high electron mobility transistor described in item 11 of the scope of patent application, the light-shielding layer is more discontinuously disposed on the dielectric layer. The high electron mobility transistor described in item 11 of the scope of patent application further includes: an etch stop layer, which conformally covers the dielectric layer and the source/drain electrode, and is located on the Under the shading layer. The high electron mobility transistor as described in item 13 of the scope of patent application, wherein the etch stop layer and the dielectric layer are both oxides, and the etch stop layer and the dielectric layer have different etching rates for the same etchant . The high electron mobility transistor described in item 11 of the scope of patent application further includes: a band adjustment layer (band adjustment layer) located on the barrier layer and under the gate electrode; wherein the energy The band adjustment layer is a P-type doped Group III or V semiconductor. The high electron mobility transistor described in item 11 of the scope of patent application, wherein the light-shielding layer includes TiN, Al, Ag, Cu, AlCu, Pt, W, Ru, Ni, TaN, TiAlN, TiW, TiO, TiO ₂ , Or a combination of the above.

Images