TWI741227B - Input detection circuit of receiver and operating method thereof - Google Patents

Abstract

An input detection circuit of a receiver includes a control unit, a first resistor, a second resistor and a first transistor ~ a fourth transistor. The first transistor and second transistor are coupled between an operating voltage and ground. The third transistor and fourth transistor are coupled between the operating voltage and ground. The first resistor is coupled to a first input terminal of an equalizer and also coupled between the first transistor and second transistor. The second resistor is coupled to a second input terminal of equalizer and also coupled between the third transistor and fourth transistor. The control unit is coupled to an output terminal of equalizer and gates of the second transistor and third transistor. Resistances of the first resistor and second resistor are appropriately designed to make a voltage difference between first input terminal and second input terminal larger than noise but smaller than normal signal.

Description

Input detection circuit of receiver and its operation method

The present invention relates to receivers, and more particularly to an input detection circuit of a receiver and its operation method.

As shown in Figure 1, the traditional iSP (integrated-Stream Protocol) signal transmission interface system 1 is composed of a transmitter (Transmitter) TX and a receiver (Receiver) RX, and the receiver RX includes an equalizer. EQ clock and data recovery (Clock and data recovery) circuit CDR.

When the signal transmission interface system 1 is activated, most of the transmitters TX will keep the differential signals IN and IP output through the first channel CH1 and the second channel CH2 at a fixed voltage level before transmitting normal signals. VCM gives the receiver RX. However, since the receiver RX cannot know whether the transmitter TX has started to transmit normal signals at this time, in this case, if there is noise, the receiver RX cannot distinguish between the noise and the normal signal, causing the receiver RX to fail. The equalizer EQ will receive and amplify the noise, as shown in Figure 2.

As for the clock and data recovery circuit CDR of the subsequent stage, it will operate according to the positive and negative edge changes of the differential output signal (EOP-EON) output by the equalizer EQ. Therefore, once the noise is amplified by the equalizer EQ and input to the clock and data recovery circuit In the case of CDR, the clock and data recovery circuit CDR will malfunction according to the noise, such as locking to the wrong frequency, etc. This phenomenon needs to be improved urgently.

In view of this, the present invention provides an input detection circuit of a receiver and an operation method thereof to effectively solve the above-mentioned problems encountered in the prior art.

A specific embodiment according to the present invention is an input detection circuit of a receiver. In this embodiment, the input detection circuit includes a control unit, a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor and the second transistor are connected in series between the working voltage and the ground terminal. The third transistor and the fourth transistor are connected in series between the working voltage and the ground terminal. One end of the first resistor is coupled to the first input end of the equalizer and the other end is coupled between the first transistor and the second transistor. One end of the second resistor is coupled to the second input end of the equalizer and the other end is coupled between the third transistor and the fourth transistor. The control unit is coupled to the output terminal of the equalizer, the gates of the second transistor and the third transistor. The resistance values of the first resistor and the second resistor are appropriately designed so that the voltage difference between the first input terminal and the second input terminal of the equalizer is larger than the noise but smaller than the normal signal.

In one embodiment, the control unit respectively outputs the first control signal and the second control signal to the gate of the second transistor and the gate of the third transistor to change the equalizer through the second transistor and the first resistance The potential of the first input terminal changes the potential of the second input terminal of the equalizer through the third transistor and the second resistor, causing a voltage difference between the first input terminal and the second input terminal of the equalizer.

In one embodiment, the first control signal has a high level and the second control signal The control signal has a low level, causing the second transistor and the first resistor to lower the potential of the first input terminal of the equalizer, and the third transistor and the second resistor raise the potential of the second input terminal of the equalizer, the voltage difference It is the potential of the second input terminal minus the potential of the first input terminal.

In one embodiment, the control unit receives the differential output signal output from the output terminal of the equalizer and generates the first control signal and the second control signal according to the differential output signal.

In one embodiment, in the presence of noise, the voltage difference between the first input terminal and the second input terminal of the equalizer is greater than the noise but smaller than the normal signal, so that the output of the equalizer is The differential output signals are all positive values, and there is no differential output signal with alternating positive and negative values.

In one embodiment, when the control unit detects that the number of positive edge triggers of the differential output signal output by the output terminal of the equalizer reaches a preset number of times, the control unit sets the first control signal to have a low level and the second control The signal has a high level, so that there is no longer a voltage difference between the first input terminal and the second input terminal of the equalizer, and the receiver returns to the normal operating mode.

In one embodiment, the receiver further includes a clock and data recovery circuit, coupled to the output terminal of the equalizer, for receiving the differential output signal output from the output terminal of the equalizer.

In one embodiment, the receiver further includes an input resistor and a first static electricity protection resistor and a second static electricity protection resistor. One end of the first electrostatic protection resistor is coupled to the first resistor and the first input terminal and the other end thereof is coupled to one end of the input resistor. One end of the second electrostatic protection resistor is coupled to the second resistor and the second input terminal and the other end thereof is coupled Input The other end of the resistance.

Another embodiment according to the present invention is an input detection circuit operation method for operating the input detection circuit in the receiver. The receiver contains an equalizer. The input detection circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, and a control unit. The first transistor and the second transistor are connected in series between the working voltage and the ground terminal. The third transistor and the fourth transistor are connected in series between the working voltage and the ground terminal. One end of the first resistor is coupled to the first input end of the equalizer and the other end is coupled between the first transistor and the second transistor. One end of the second resistor is coupled to the second input end of the equalizer and the other end is coupled between the third transistor and the fourth transistor. The control unit is respectively coupled to the output end of the equalizer and the second transistor. The gate of the crystal and the gate of the third transistor.

The operation method of the input detection circuit includes the following steps: (a) the control unit outputs the first control signal and the second control signal to the gate of the second transistor and the gate of the third transistor respectively; (b) through the second transistor The crystal and the first resistor change the potential of the first input terminal and change the potential of the second input terminal through the third transistor and the second resistor, causing a voltage difference between the first input terminal and the second input terminal; and (c) After appropriately designing the resistance of the first resistor and the second resistor, the voltage difference between the first input terminal and the second input terminal can be larger than the noise but smaller than the normal signal.

Compared with the prior art, the input detection circuit of the receiver and its operation method of the present invention can generate more than the value between the first input terminal and the second input terminal of the equalizer when there is noise input to the receiver. Noise but less than the voltage difference of one of the normal signals, causing the equalizer to output to the clock and the differential output signal of the data recovery circuit It is a positive value and does not output a differential output signal with alternating positive and negative values. Once the control unit detects that the number of positive edge triggers of the differential output signal output by the equalizer reaches the preset number of times, the control unit will stop generating a voltage difference between the first input terminal and the second input terminal of the equalizer , To return to the normal operating mode of the receiver. Therefore, the input detection circuit and operation method of the receiver of the present invention can effectively prevent the clock and data recovery circuit in the prior art from malfunctioning due to noise.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

1‧‧‧Signal Transmission Interface System

TX‧‧‧Transmitter

RX‧‧‧Receiver

CH1‧‧‧The first channel

CH2‧‧‧Second channel

IN, IP‧‧‧Differential signal

RT‧‧‧Input resistance

RE1‧‧‧The first electrostatic protection resistor

RE2‧‧‧Second ESD protection resistor

INE‧‧‧First input signal

IPE‧‧‧Second input signal

EQ‧‧‧Equalizer

EON‧‧‧First output signal

EOP‧‧‧Second output signal

(EOP-EON)‧‧‧Differential output signal

CDR‧‧‧Clock and data recovery circuit

PW‧‧‧Power on signal

VCM‧‧‧Fixed voltage level

T1~T3‧‧‧Time interval

Vod‧‧‧Voltage difference

3‧‧‧Input detection circuit

30‧‧‧Control Unit

RDN‧‧‧First resistor

RPU‧‧‧Second resistor

MP1‧‧‧First Transistor

MN1‧‧‧Second Transistor

MP2‧‧‧Third Transistor

MN2‧‧‧Fourth Transistor

VDD‧‧‧Working voltage

GND‧‧‧Ground terminal

DN‧‧‧First control signal

PU‧‧‧Second control signal

HV‧‧‧High level

LV‧‧‧Low level

S10~S14‧‧‧Step

Figure 1 shows a schematic diagram of a conventional signal transmission interface system.

FIG. 2 is a schematic diagram showing that the differential output signal output by the conventional equalizer before receiving the normal signal will have alternate positive and negative values, causing the clock and data recovery circuit to malfunction.

FIG. 3 is a schematic diagram illustrating the application of the input detection circuit in a receiver according to a preferred embodiment of the present invention.

4 is a schematic diagram showing the correspondence between the voltage difference between the first input terminal and the second input terminal of the equalizer and the fixed voltage level.

FIG. 5A shows that in the presence of noise, the first input signal received by the first input terminal of the equalizer is maintained at a fixed voltage level and the second input signal received by the second input terminal is maintained at a fixed voltage level Schematic above the standard.

FIG. 5B is a schematic diagram showing that the differential output signals output by the equalizer are all positive values.

FIG. 6 shows the timing diagrams of the power-on signal, the first input signal and the second input signal, the differential output signal, the first control signal and the second control signal, respectively.

FIG. 7 is a flowchart of the operation method of the input detection circuit according to another preferred embodiment of the present invention.

A specific embodiment according to the present invention is an input detection circuit of a receiver. In this embodiment, the signal transmission interface system includes a transmitter and a receiver. After the signal transmission interface system is turned on, the transmitter has not yet begun to transmit normal signals to the receiver. The input detection circuit generates more noise but greater noise between the first input terminal and the second input terminal of the equalizer in the receiver. Less than a voltage difference of the normal signal, causing the differential output signal of the equalizer output to the clock and data recovery circuit to be positive, until the input detection circuit detects the positive edge of the differential output signal output by the equalizer When the number of triggers reaches the preset number of times, the voltage difference between the first input terminal and the second input terminal of the equalizer will stop and the receiver will return to the normal operating mode, which can effectively avoid the time in the prior art. The pulse and data recovery circuit generates malfunctions based on noise.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of the input detection circuit 3 applied to the receiver RX in this embodiment.

As shown in FIG. 3, the receiver RX includes an equalizer EQ, a clock and data recovery circuit CDR, an input resistor RT, a first electrostatic protection resistor RE1, and a second electrostatic protection resistor RE2. The input detection circuit 3 includes a control unit 30, a first resistor RDN, and a Two resistors RPU, first transistor MP1, second transistor MN1, third transistor MP2, and fourth transistor MN2. Among them, the first transistor MP1 and the third transistor MP2 are P-type transistors, and the second transistor MN1 and the fourth transistor MN2 are N-type transistors, but not limited to this.

The first transistor MP1 and the second transistor MN1 are connected in series between the working voltage VDD and the ground terminal GND. The third transistor MP2 and the fourth transistor MN2 are connected in series between the working voltage VDD and the ground terminal GND. One end of the first resistor RDN is coupled to the first input end of the equalizer EQ and the other end is coupled between the first transistor MP1 and the second transistor MN1. One end of the second resistor RPU is coupled to the second input end of the equalizer EQ and the other end is coupled between the third transistor MP2 and the fourth transistor MN2. The control unit 30 is coupled to the output terminal of the equalizer EQ, the gate of the second transistor MN1 and the gate of the third transistor MP2, for receiving the first output signal EON and the second output signal output by the equalizer EQ The EOP then provides the first control signal DN and the second control signal PU to the gate of the second transistor MN1 and the gate of the third transistor MP2 respectively.

The clock and data recovery circuit CDR is coupled to the output terminal of the equalizer EQ for receiving the first output signal EON and the second output signal EOP output by the output terminal of the equalizer EQ. One end of the first electrostatic protection resistor RE1 is coupled to the first input terminal of the first resistor RDN and the equalizer EQ, and the other end of the first electrostatic protection resistor RE1 is coupled to one end of the input resistor RT. One end of the second electrostatic protection resistor RE2 is coupled to the second input terminal of the second resistor RPU and the equalizer EQ, and the other end of the second electrostatic protection resistor RE2 is coupled to the other end of the input resistor RT.

When the signal transmission interface system is turned on, the transmitter has not yet started to transmit Normal signal to the receiver RX, the transmitter will output the differential signal IN and IP stay at a fixed voltage level VCM to the receiver RX.

In order to prevent the equalizer EQ of the receiver RX from amplifying the received noise and outputting it to the clock and data recovery circuit CDR, the control unit 30 respectively outputs the first control signal DN and the second control signal PU to the second transistor MN1 The gate of the second transistor MN1 and the third transistor MP2 are controlled to turn on or off respectively, and the equalizer EQ can be changed through the second transistor MN1 and the first resistor RDN The potential of the first input signal INE received by the first input terminal of the equalizer is changed through the third transistor MP2 and the second resistor RPU to change the potential of the second input signal IPE received by the second input terminal of the equalizer EQ, causing the equalizer A voltage difference Vod is generated between the first input terminal and the second input terminal of the EQ.

It should be noted that, in one embodiment, the first control signal DN output by the control unit 30 to the gate of the second transistor MN1 has a high level and the control unit 30 outputs to the second gate of the third transistor MP2. The control signal PU has a low level, causing the second transistor MN1 and the first resistor RDN to pull down the potential of the first input signal INE received by the first input terminal of the equalizer EQ, and the third transistor MP2 and the second resistor RPU pull down The potential of the second input signal IPE received by the second input terminal of the higher levelizer EQ, and the potential of the second input signal IPE received by the second input terminal of the equalizer EQ minus the first input terminal of the equalizer EQ received The potential of the first input signal INE is the voltage difference Vod between the first input terminal and the second input terminal of the equalizer EQ.

After appropriately designing the resistance of the first resistor RDN and the second resistor RPU, the voltage difference between the first input terminal and the second input terminal of the equalizer EQ can be made Vod is larger than the noise but smaller than the normal signal. In the presence of noise, since the voltage difference Vod between the first input terminal and the second input terminal of the equalizer EQ is greater than the noise but smaller than the normal signal, the differential output signal (EOP -EON) are all positive values, and will not generate a differential output signal with alternating positive and negative values like the prior art equalizer EQ.

Then, when the transmitter starts to transmit the normal signal to the receiver RX, the control unit 30 will detect the positive edge trigger times of the differential output signal (EOP-EON) output by the equalizer EQ and determine whether it reaches the preset times (For example, 3 times, but not limited to this), to confirm that the equalizer EQ has received the normal signal.

When the control unit 30 determines that the number of positive edge triggers of the differential output signal (EOP-EON) output by the equalizer EQ has reached the preset number of times, the control unit 30 will set the first control signal DN output by it to have a low level and The output second control signal PU has a high level, so that the voltage difference Vod is no longer generated between the first input terminal and the second input terminal of the equalizer EQ, and returns to the normal operation mode of the receiver RX.

When the control unit 30 determines that the number of positive edge triggers of the differential output signal (EOP-EON) output by the equalizer EQ has not reached the preset number, it still maintains that the first control signal DN output has a high level and its output The second control signal PU has a low level.

Please refer to FIG. 4, which is a schematic diagram showing the correspondence between the voltage difference Vod between the first input terminal and the second input terminal of the equalizer EQ and the fixed voltage level VCM.

As shown in Figure 4, the second input received by the second input of the equalizer EQ The potential of the signal IPE is higher than the fixed voltage level VCM and the potential of the first input signal INE received by the first input terminal of the equalizer EQ is lower than the fixed voltage level VCM. As for the voltage difference Vod between the first input terminal and the second input terminal of the equalizer EQ, the voltage difference Vod can be obtained by the following formula: Vod=VDD*(RT+RE1+RE2)/(RT+RE1+RE2+RDN+RPU )

Next, as shown in Figure 5A, since the voltage difference Vod between the first input terminal and the second input terminal of the equalizer EQ is greater than the noise, even in the presence of noise, the first The first input signal INE received by the input terminal is maintained below the fixed voltage level VCM and the second input signal IPE received by the second input terminal is maintained above the fixed voltage level VCM, resulting in a differential output of the equalizer EQ output The signals (EOP-EON) are all positive values, as shown in Figure 5B, instead of the differential output signal (EOP-EON) produced by the prior art equalizer EQ, which has alternate positive and negative values and is difficult to distinguish from the normal signal. .

Next, please refer to Figure 6. Figure 6 shows the power-on signal PW, the first input signal INE and the second input signal IPE, the differential output signal (EOP-EON), the first control signal DN and the second control signal, respectively. Timing diagram of UP.

As shown in FIG. 6, when the system is started, the power-on signal PW changes from a low level LV to a high level HV. In the time interval T1, the transmitter has not sent the normal signal to the receiver RX, so the equalizer EQ has not received the normal signal.

At this time, the first control signal DN output by the control unit 30 to the gate of the second transistor MN1 has a high level HV and the second control signal PU output by the control unit 30 to the gate of the third transistor MP2 has a low level LV , Causing the second transistor MN1 and the first resistor RDN lower the potential of the first input signal INE received by the first input terminal of the equalizer EQ, and the third transistor MP2 and the second resistor RPU raise the first input signal INE received by the second input terminal of the equalizer EQ. 2. The potential of the input signal IPE. By properly designing the resistance of the first resistor RDN and the second resistor RPU, the voltage difference Vod between the first input terminal and the second input terminal of the equalizer EQ can be greater than the noise but less than the normal signal, resulting in equalization The differential output signals (EOP-EON) of the EQ output of the converter are all positive values.

In the time interval T2, the transmitter starts to transmit the normal signal to the receiver RX, so the equalizer EQ starts to receive the normal signal. At this time, the control unit 30 detects the positive edge trigger times of the differential output signal (EOP-EON) output by the equalizer EQ and determines whether it reaches the preset times. In this embodiment, the preset number of times is 3, but it is not limited to this.

When the control unit 30 determines that the number of positive edge triggers of the differential output signal (EOP-EON) output by the equalizer EQ has reached the preset number of times (for example, 3 times), the control unit 30 sets the first control signal output by it The DN changes from the original high level to the low level and the second control signal PU that sets its output changes from the original low level to the high level, resulting in the first input and second input of the equalizer EQ in the time interval T3 The voltage difference Vod is no longer generated between the terminals, and the normal operation mode of the receiver RX is restored.

In this way, when the system has just started and the transmitter has not yet sent a normal signal to the receiver RX, the input detection circuit 3 of the present invention can effectively avoid the clock and data recovery circuit CDR based on the amplified noise output by the equalizer EQ. Misoperation occurs, until the input detection circuit 3 of the present invention confirms that the equalizer EQ of the receiver RX has received a normal signal, it will return to the normal operation mode of the receiver RX, and the equalizer EQ will output The amplified normal signal is sent to the clock and data recovery circuit CDR.

Another embodiment according to the present invention is an operation method of an input detection circuit. In this embodiment, the input detection circuit operation method is used to operate the input detection circuit in the receiver. The receiver contains an equalizer. The input detection circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, and a control unit. The first transistor and the second transistor are connected in series between the working voltage and the ground terminal. The third transistor and the fourth transistor are connected in series between the working voltage and the ground terminal. One end of the first resistor is coupled to the first input end of the equalizer and the other end is coupled between the first transistor and the second transistor. One end of the second resistor is coupled to the second input end of the equalizer and the other end is coupled between the third transistor and the fourth transistor. The control unit is respectively coupled to the output end of the equalizer and the second transistor. The gate of the crystal and the gate of the third transistor.

Please refer to FIG. 7. FIG. 7 shows a flowchart of the operation method of the input detection circuit in this embodiment. As shown in FIG. 7, the operation method of the input detection circuit includes the following steps: Step S10: When the system is turned on, the control unit respectively outputs a first control signal and a second control signal to the gate of the second transistor and the third transistor Step S12: Change the potential of the first input terminal through the second transistor and the first resistor, and change the potential of the second input terminal through the third transistor and the second resistor, so that the first input terminal and the second input A voltage difference is generated between the terminals; and Step S14: After appropriately designing the resistance of the first resistor and the second resistor The voltage difference between the first input terminal and the second input terminal can be made larger than the noise but smaller than the normal signal.

Compared with the prior art, the input detection circuit of the receiver and its operation method of the present invention can generate more than the noise between the first input terminal and the second input terminal of the equalizer when there is noise input to the receiver. The noise is smaller than the voltage difference of one of the normal signals, so that the differential output signals from the equalizer to the clock and data recovery circuit are all positive values, and the differential output signals with alternating positive and negative values will not be output. Once the control unit detects that the number of positive edge triggers of the differential output signal output by the equalizer reaches the preset number of times, the control unit will stop the voltage difference between the first input terminal and the second input terminal of the equalizer. To return to the normal operating mode of the receiver. Therefore, the input detection circuit and operation method of the receiver of the present invention can effectively prevent the clock and data recovery circuit in the prior art from malfunctioning due to noise.

From the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the purpose is to cover various changes and equivalent arrangements within the scope of the patent for which the present invention is intended. Based on the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the purpose is to cover various changes and equivalent arrangements within the scope of the patent for which the present invention is intended.

RX‧‧‧Receiver

IN, IP‧‧‧Differential signal

RT‧‧‧Input resistance

RE1‧‧‧The first electrostatic protection resistor

RE2‧‧‧Second ESD protection resistor

INE‧‧‧First input signal

IPE‧‧‧Second input signal

EQ‧‧‧Equalizer

EON‧‧‧First output signal

EOP‧‧‧Second output signal

CDR‧‧‧Clock and data recovery circuit

Vod‧‧‧Voltage difference

3‧‧‧Input detection circuit

30‧‧‧Control Unit

RDN‧‧‧First resistor

RPU‧‧‧Second resistor

MP1‧‧‧First Transistor

MN1‧‧‧Second Transistor

MP2‧‧‧Third Transistor

MN2‧‧‧Fourth Transistor

VDD‧‧‧Working voltage

GND‧‧‧Ground terminal

DN‧‧‧First control signal

PU‧‧‧Second control signal

Claims (12)

An input detection circuit (3), applied to a receiver (RX), the receiver (RX) includes an equalizer (EQ), and the input detection circuit (3) includes: a first transistor ( MP1) and a second transistor (MN1) are connected in series between a working voltage (VDD) and a ground (GND), and the second transistor (MN1) is located between the first transistor (MP1) and the Between the ground terminal (GND); a third transistor (MP2) and a fourth transistor (MN2) are connected in series between the working voltage (VDD) and the ground terminal (GND) and the third transistor (MP2) is located between the working voltage (VDD) and the fourth transistor (MN2); a first resistor (RDN), one end of which is coupled to a first input terminal of the equalizer (EQ) and its The other end is coupled between the first transistor (MP1) and the second transistor (MN1); a second resistor (RPU), one end of which is coupled to a second input of the equalizer (EQ) Terminal and the other terminal is coupled between the third transistor (MP2) and the fourth transistor (MN2); and a control unit (30) respectively coupled to the output terminal of the equalizer (EQ), The gate of the second transistor (MN1) and the gate of the third transistor (MP2); wherein the resistance of the first resistor (RDN) and the second resistor (RPU) can be properly designed so that the A voltage difference (Vod) between the first input terminal and the second input terminal of the equalizer (EQ) is larger than the noise but smaller than the normal signal; the control unit (30) respectively outputs a first control signal (DN ) And a second control signal (PU) to the gate of the second transistor (MN1) and the gate of the third transistor (MP2) to pass through the second transistor (MN1) and the first resistor (RDN) Change the potential of the first input terminal of the equalizer (EQ) and change the second input of the equalizer (EQ) through the third transistor (MP2) and the second resistor (RPU) The potential of the equalizer (EQ) between the first input terminal and the second input terminal to generate the Voltage difference (Vod); the control unit (30) receives a differential output signal (EOP-EON) output from the output terminal of the equalizer (EQ) and generates the differential output signal (EOP-EON) The first control signal (DN) and the second control signal (PU). For the input detection circuit described in item 1 of the scope of patent application, the receiver (RX) also includes a clock and data recovery circuit (CDR) coupled to the output terminal of the equalizer (EQ) for Receive the differential output signal (EOP-EON) output from the output terminal of the equalizer (EQ). For the input detection circuit described in item 1 of the scope of patent application, the first control signal (DN) has a high level and the second control signal (PU) has a low level, causing the second transistor and the first The resistor pulls down the potential of the first input terminal of the equalizer (EQ) and the third transistor and the second resistor pull up the potential of the second input terminal of the equalizer (EQ), the voltage difference (Vod) is the potential of the second input terminal minus the potential of the first input terminal. The input detection circuit described in item 1 of the scope of patent application, wherein the receiver (RX) further includes an input resistor (RT), a first electrostatic protection resistor (RE1) and a second electrostatic protection resistor (RE2) , One end of the first electrostatic protection resistor (RE1) is coupled to the first resistor (RDN) and the first input terminal and the other end is coupled to one end of the input resistor (RT), the second electrostatic protection resistor (RE2) One end of) is coupled to the second resistor (RPU) and the second input end, and the other end is coupled to the other end of the input resistor (RT). Such as the input detection circuit described in item 1 of the scope of patent application, in which the voltage difference between the first input terminal and the second input terminal of the equalizer (EQ) ( Vod) is greater than the noise but less than the normal signal, so that the differential output signal (EOP-EON) output by the output terminal of the equalizer (EQ) is all positive Value without generating a differential output signal with alternating positive and negative values. The input detection circuit described in item 3 of the scope of patent application, wherein when the control unit (30) detects the differential output signal (EOP-EON) output from the output terminal of the equalizer (EQ) When the number of positive edge triggers reaches a preset number, the control unit (30) sets the first control signal (DN) to have a low level and the second control signal (PU) to have a high level, causing the equalizer (EQ) The voltage difference (Vod) is no longer generated between the first input terminal and the second input terminal, but returns to the normal operation mode of the receiver (RX). An input detection circuit operation method for operating an input detection circuit in a receiver. The receiver includes an equalizer. The input detection circuit includes a first transistor, a second transistor, and a The third transistor, a fourth transistor, a first resistor, a second resistor, and a control unit, the first transistor and the second transistor are connected in series between a working voltage and a ground terminal, and the The second transistor is located between the first transistor and the ground terminal, the third transistor and the fourth transistor are connected in series between the operating voltage and the ground terminal, and the third transistor is located at the operating voltage And the fourth transistor, one end of the first resistor is coupled to a first input end of the equalizer and the other end is coupled between the first transistor and the second transistor, the One end of the second resistor is coupled to a second input end of the equalizer and the other end is coupled between the third transistor and the fourth transistor. The control unit is respectively coupled to the equalizer The output terminal, the gate of the second transistor and the gate of the third transistor, the input detection circuit operation method includes the following steps: (a) The control unit outputs a first control signal and a second control respectively Signal to the gate of the second transistor and the gate of the third transistor; (b) changing the potential of the first input terminal through the second transistor and the first resistor, and through the third transistor and The second resistance changes the second input terminal The potential of, causes a voltage difference between the first input terminal and the second input terminal; and (c) after properly designing the resistance of the first resistor and the second resistor, the first input terminal and The voltage difference between the second input terminals is larger than the noise but smaller than the normal signal; wherein, the control unit receives a differential output signal output from the output terminal of the equalizer and generates the first output signal according to the differential output signal A control signal and the second control signal. For the input detection circuit operation method described in item 7 of the scope of patent application, wherein the first control signal has a high level and the second control signal has a low level, causing the second transistor and the first resistor to pull down the The potential of the first input terminal and the third transistor and the second resistor raise the potential of the second input terminal. The voltage difference is the potential of the second input terminal minus the potential of the first input terminal. The operation method of the input detection circuit as described in item 7 of the scope of patent application, wherein when there is noise, the voltage difference between the first input terminal and the second input terminal is larger than the noise but smaller than the normal signal , Resulting in the differential output signal output from the output terminal of the equalizer is all positive, and the differential output signal with alternating positive and negative values will not be generated. The operation method of the input detection circuit as described in item 8 of the scope of patent application, wherein when the control unit detects that the positive edge of the differential output signal output by the output terminal of the equalizer reaches a preset number of times At this time, the control unit sets the first control signal to have a low level and the second control signal to have a high level, so that the voltage difference between the first input terminal and the second input terminal is no longer generated, and returns to the receiving The normal operating mode of the device. The input detection circuit operation method as described in item 7 of the scope of patent application, wherein the The receiver also includes a clock and data recovery circuit coupled to the output end of the equalizer for receiving the differential output signal from the output end of the equalizer. According to the operation method of the input detection circuit described in item 7 of the scope of patent application, the receiver further includes an input resistor, a first electrostatic protection resistor and a second electrostatic protection resistor, one end of the first electrostatic protection resistor is coupled The first resistor and the first input terminal are connected and the other end is coupled to one end of the input resistor, one end of the second electrostatic protection resistor is coupled to the second resistor and the second input terminal, and the other end is coupled to the Input the other end of the resistance.

Images