CN106534011B - receiver and related control method - Google Patents
receiver and related control method Download PDFInfo
- Publication number
- CN106534011B CN106534011B CN201510569956.8A CN201510569956A CN106534011B CN 106534011 B CN106534011 B CN 106534011B CN 201510569956 A CN201510569956 A CN 201510569956A CN 106534011 B CN106534011 B CN 106534011B
- Authority
- CN
- China
- Prior art keywords
- signal
- feedback equalization
- decision feedback
- data
- equalization coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/01—Equalisers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Dc Digital Transmission (AREA)
Abstract
A receiver and a related control method. The receiver includes: a continuous time linear equalizer for receiving a received signal and processing the received signal according to a pole and a boost level to generate a first equalized signal; a slicing circuit, coupled to the continuous time linear equalizer, for generating a data signal according to the first equalization signal and a feedback equalization signal; and a decision feedback equalization circuit, coupled to the slicing circuit, for processing the data signal according to a decision feedback equalization coefficient set and generating the feedback equalization signal; the boost level is adjusted according to a first decision feedback equalization coefficient in the decision feedback equalization coefficient set, and the pole position is adjusted according to a second decision feedback equalization coefficient.
Description
Technical field
The present invention relates to a kind of receiver (receiver) and corresponding control methods, and it is in particular to a kind of can be according to decision
The parameter of feedback equalizer (decision feedback equalizer) adjusts continuous time linear equalizer
The receiver of lift level (the boost level) and pole (pole) of (continuous time linear equalizer)
With corresponding control methods.
Background technique
Electronic circuit (such as chip, crystal grain, integrated circuit) is the most important hardware foundation of advanced information society；Different
Electronic circuit available channel (channel) is connected to interconnection system, with via Channel Exchange signal (such as information, data, message,
Order and/or grouping etc.), allow different electronic circuit can mutually coordinated running, play the comprehensive function of addition.But, lead to
The characteristic in road itself also will affect the quality of signal contact transmission.In general, channel is low-pass nature, therefore suppression signal can be subtracted
In high frequency section, lead to distorted signals (distortion)；For example, when one as transmitter (transmitter,
Abbreviation Tx) electronic circuit when the signal of one square-wave waveform being transmitted to the electronic circuit of a receiver via channel, receive
The signal waveform that device receives can be a slow waveform for rising slow drop, be unable to maintain that the liter edge and drop edge of square-wave waveform.It is connecing
It receives in the signal waveform that device (receiver, abbreviation Rx) is received, vernier (pre-cursor) before slow ascending part point can be considered one,
Its slow peak value risen can be considered a main cursor, and vernier (post-cursor) after then can be considered one by the part of the slow drop of peak value.Letter
Number distortion, which can further result in, interferes (ISI, inter-symbol interference) between symbol, influences the matter of signal transmission
Amount, such as say it is to improve bit error rate.
In order to compensate the influence caused by passage, filtering mechanism and equalizer set can be respectively set in the transmitter and in the receiver
System.For example, the filtering mechanism of transmitter may include pre- strengthen filter (a pre-emphasis filter) to strengthen
The high frequency section of launcher signal；The equilibrating mechanism of receiver then may include a continuous time linear equalizer (continuous
Time linear equalizer, abbreviation CTLE) and a decision feedback equalization circuit (decision feedback
Equalizer, abbreviation DFE).When a signal to be passed is sent to receiver by transmitter, transmitter filter can be according to more
A filter factor drives to be filtered for signal to be passed, then by filtered signal to channel；Receiver receiving channel transmits
After signal, equilibrium treatment can be carried out to the signal that receives according to multiple equalizing coefficients, then by taken in signal after equalization also its take
The content and/or other information (such as clock) of load.
Fig. 1 is please referred to, depicted is known array device/solution sequence device (Serdes) schematic diagram.In the electricity of transmitter Tx
In sub-circuit, strengthens filter (pre-emphasis filter) 102 in advance and receive data-signal (data signal) S and generate
The data-signal Sw of filtering.Wherein, strengthen the size (increase for the high frequency section that filter 102 improves in data-signal S in advance
The magnitude of higher frequencies) and become the data-signal Sw filtered.
Later, the data-signal Sw of filtering is sent to the other end via one end of channel (channel) 104 and becomes and receive
The electronic circuit of signal Sx and input sink 110 is to rebuild data-signal S.
Receiver 110 includes: data sampler (data sampler) 113, edge sampler (edge sampler)
115,117, decision feedback equalizer clock data recovery circuit (clock data recovering circuit)
(decision feedback equalizer) 119 and summer (adder) 111.
Substantially, the reception signal Sx on the other end in channel 104 can input sink 110.Summer 111 is by decision
Feedback equalizer 119 generate feedback equalization signal (feedback equalizing signal) Sf and receive signal Sx into
Superposition signal (superposed signal) Sz is generated after row aggregation.
Data sampler 113 samples superposition signal Sz according to data clock dCLK and generates data sampling signal
(sampled data signal)Sd.Furthermore edge sampler 115 samples superposition signal Sz according to edge clock eCLK simultaneously
Generate edge sampled signal (sampled edged signal) Sedg.
In addition, clock data recovery circuit 117 receives sampled data signal Sd and edge sampled signal Sedg and generates
Data clock dCLK and edge clock eCLK.Decision feedback equalization circuit 119 receives sampled data signal Sd and generates feedback
Equalizing signal Sf.
Substantially, the receiver 110 of Fig. 1 is to carry out data and its data to superposition signal Sz to adopt along (data edge)
Sample, and data clock dCLK and edge clock eCLK is generated using clock data recovery circuit 117.Such receiver
110, clock data recovery circuit 117 needs to generate the data clock dCLK and edge clock eCLK of double data rate,
Excessively to sample (over sampling) superposition signal Sz.Furthermore data clock dCLK and edge clock eCLK each other it
Between phase difference be 180 degree.
As an example it is assumed that clock data recovery circuit 117 needs to produce when the data rate of data-signal S is 16Gbps
The raw data clock dCLK and edge clock eCLK for being up to 8GHz rate is marched toward when could obtain as different information, and then is rebuild
Data-signal S.
Furthermore it needs to utilize spring spring phase detectors (bang-bang phase in clock data recovery circuit 117
Detector), for receiving data sampling signal Sd and edge sampled signal Sedg, and phase more new information is generated accordingly
The phase of (phase update information) to adjust data clock dCLK and edge clock eCLK.
Summary of the invention
The present invention provides a kind of receiver, comprising: a continuous time linear equalizer receives signal and according to one
Pole handles the reception signal with a lift level and generates one first equalizing signal；It is continuous to be coupled to this for one clipper circuit
Linearly balanced device, to generate a data-signal according to first equalizing signal and a feedback equalization signal；And one
Decision feedback equalization circuit is coupled to the clipper circuit, to handle data letter according to a decision feedback equalization coefficient sets
Number, and generate the feedback equalization signal；Wherein, the lift level is according to one first decision in the decision feedback equalization coefficient sets
Feedback equalization coefficient is adjusted.
According to above receiver, the present invention more proposes corresponding control method, including the following steps: (a) adjusts the company
Continuous linearly balanced device has the maximum lift level and a smallest pole；(b) it is equal persistently to receive the decision feedback
Weigh coefficient sets；(c) when the first decision feedback equalization coefficient in the decision feedback equalization coefficient sets is less than a first threshold,
The lift level is reduced until the first decision feedback equalization coefficient is not less than the first threshold；And (d) when the decision feedback
When one second decision feedback equalization coefficient in equalizing coefficient group is less than a second threshold, a pole is improved until second decision
Feedback equalization coefficient is not less than the second threshold.
More preferably understand to have to above-mentioned and other aspect of the invention, preferred embodiment is cited below particularly, and cooperates attached
Figure, is described in detail below.
Detailed description of the invention
Fig. 1 depicted is known array device/solution sequence device (Serdes) schematic diagram.
Fig. 2 is the influence that citing schematic channel transmits signal.
Fig. 3 is interference (ISI) between citing signal symbol.
Fig. 4 is the schematic diagram of 1 symbol of Xiang Yingyi logic.
The depicted receiver schematic diagram for first embodiment of the invention of Fig. 5.
It is continuous time linear equalizer circuit diagram and its frequency response schematic diagram of the present invention depicted in Fig. 6 A to Fig. 6 C.
Fig. 7 A show in continuous time linear equalizer different dominant pole ωp1Two impulse response h1 (t) and h2 (t)
Schematic diagram.
Fig. 7 B is channel impulse response (channel impulse response) v (t) and continuous time linear equalizer
Convolution integration (convolution) schematic diagram of middle larger pole (2.5GHz) the impulse response h1 (t) of tool.
Fig. 7 C is to have (0.5GHz) pulse of lower pole in channel impulse response v (t) and continuous time linear equalizer to ring
Answer the convolution integration schematic diagram of h2 (t).
The depicted control method for continuous time linear equalizer of the present invention of Fig. 8.
The depicted receiver schematic diagram for second embodiment of the invention of Fig. 9.
[symbol description]
102: strengthening filter in advance
104,204: channel
110: receiver
111: summer
113: data sampler
115: edge sampler
117: clock data recovery circuit
119: decision feedback equalizer
500,800: receiver
510: continuous time linear equalizer
520,820: summer
530,830: clipper circuit
532,832: data slicer
534,834: error cutter
536,836: edge cutter
550,850: clock data recovery circuit
560,860: adaptive filter
570,870: decision feedback equalizer
Specific embodiment
The influence that schematic channel transmits signal referring to FIG. 2, it is illustrated.In Fig. 2, a transmitter Tx is through a channel
204 and be connected to a receiver Rx, when transmitter Tx will send the data-signal Sw of a filtering to receiver, the data of filtering
Signal Sw can be formed via the propagation in channel 204 receives signal Sx, is received by receiver Rx.In the example in figure 2, filtering
Data-signal Sw carries 1 symbol of logic in time point t0 with the square wave for continuing a period UI.As caused by channel 204
A slow waveform for rising slow drop can be presented in wave distortion, the square wave in the data-signal Sw of filtering in receiving signal Sx.It is received
Sampling of the device Rx to signal Sx is received, 1 symbol of logic can be corresponded to the peak value sampling Sx [k0] of time point t [k0], form main cursor.
Relative to main cursor, receiving part of the signal Sx before time point t [k0] is preceding vernier, such as the sampling Sx of time point t [k0-1]
[k0-1]；Part of the signal Sy after time point t [k0] is rear vernier, such as the sampling Sx [k0+1] of time point t [k0+1].Time point
Interval between t [k0-1], t [k0] and t [k0+1] can be equal to period UI.
Ideally, the intensity of preceding vernier and rear vernier should be zero, leave behind main cursor.But, because it is logical
Non-ideal effects caused by road characteristic receive the preceding vernier and rear vernier that can leave suitable intensity in signal Sx, and cause symbol
Between interfere (ISI).
Continue Fig. 2, with continued reference to FIG. 3, interfering (ISI) between its citing signal symbol.In the example in figure 3, filtering
Data-signal Sw, to three symbols are carried between t3, is sequentially logic 1,0 and 1 in time point t0.Via the transmitting in channel 204, time point
T0 can form waveform Wa in receiver Rx to 1 square wave of logic between t1, and time point t2 to 1 square wave of logic between t3 is then in receiver Rx
Waveform Wb is formed, and the reception signal Sx of receiver Rx is to be synthesized by waveform Wa with Wb, patrolling in the data-signal Sw of filtering
It collects 1,0 and 1 and respectively corresponds sampling Sx [k0], the Sx [k0+1] and Sx [k0+2] received in signal Sx.
As seen from Figure 3, because the rear vernier (part after time point t [k0]) of waveform Wa and waveform Wb preceding vernier (when
Part before point t [k0+2]) can be in time point t [k0+1] addition, therefore the intensity for sampling Sx [k0+1] will not drop to zero, make originally
Should represent logical zero sampling Sx [k0+1] can because between symbol interfere (ISI) due to be mistaken for logic 1.By begging for for Fig. 2 and Fig. 3
By it is found that in order to compensate for channel characteristic and subtract and interfere (ISI) between suppression symbol, it should completely to consider preceding vernier and rear vernier
It influences.
Substantially, the decision feedback equalization circuit in receiver is formed by reducing the influence of rear vernier in reception signal Sx
Superposition signal Sz；The effect of this equilibrating mechanism can be illustrated with Fig. 4.As shown in figure 4, response one logic, 1 symbol, receives letter
Number Sx can present one it is slow rise slow drop waveform, reflect logic 1 in the sampling Sz [k] of superposition signal Sz, but vernier part still has thereafter
Comparable signal strength.But, after via decision feedback equalization circuit, the rear vernier part received in signal Sx can be fed back
Equalizing signal reduces, and makes the corresponding sampling Sz [k+1] in rear vernier part, Sz [k+2] etc. that can level off to zero, to inhibit between symbol
It interferes (ISI).
Furthermore in order to reduce the rear vernier part received in signal Sx, decision feedback equalization circuit needs anti-according to decision
Present equalizing coefficient group (DFE coefficient set) h1, h2, h3, the variation of h4, h5 generates feedback equalization signal.Such as Fig. 4
Shown, because superposition signal Sz is greater than the intensity of time point t [k+2] in the intensity of time point t [k+1], therefore coefficient h 1 is also greater than coefficient
h2。
Referring to FIG. 5, its depicted receiver schematic diagram for first embodiment of the invention.Receiver 500 includes: continuous
Linearly balanced device 510, clipper circuit 530, clock data recovery circuit 550, adaptive filter (adaptive
Filter) 560, decision feedback equalizer 570 and summer 520.Wherein, clipper circuit 530 further include: data slicer
(data slicer) 532, error cutter (error slicer) 534 and edge cutter (edge slier) 536.Furthermore
Adaptive filter 560 may be based on adaptive filter (the least mean square based of least-mean-square filter
adaptive filter)。
As shown in figure 5, the other end in channel 204 is connected to receiver 500, so that receiving signal Sx input sink
500 continuous time linear equalizer 510 receives the size of the high frequency section in signal Sx and as the first equilibrium to improve
Signal (first equalized signal) Sy.Furthermore the feedback that summer 520 generates decision feedback equalizer 570 is equal
Weighing apparatus signal Sf and the first equalizing signal Sy generates superposition signal Sz after being added up.
In clipper circuit 530, data slicer 532 is cut according to the first killer voltage Ss1 with data clock dCLK
Superposition signal Sz simultaneously generates data-signal (data signal) Sd.Edge cutter 536 is according to the second killer voltage Ss2 and side
Superposition signal Sz is sampled along clock eCLK and generates edge signal (edged signal) Sedg.536 basis of error cutter
To cut superposition signal Sz and error signal (error signal) is generated according to reference voltage Vref and data clock dCLK
Serr.Wherein, the first killer voltage Ss1 and the second killer voltage Ss2 is fixed voltage level, such as 0V.
In addition, clock data recovery circuit 550 receives data-signal Sd and edge signal Sedg and generates data clock
DCLK and edge clock eCLK is to clipper circuit 530.Furthermore adaptive filter 560 receives data-signal Sd and error is believed
Number Serr generates a reference voltage Vref to error cutter 534, and generates a decision feedback equalization coefficient sets (DFE
Coefficient set) to decision feedback equalizer 570 and continuous time linear equalizer 510.Substantially, adaptive filtering
Device 560 dynamically changes the reference voltage Vref and decision feedback equalization system according to data-signal Sd and error signal Serr
Array.It for example, include five decision feedback equalization coefficient hs 1, h2, h3, h4, h5 in decision feedback equalization coefficient sets.When
So, decision feedback equalization coefficient sets of the present invention are not limited to the number of decision feedback equalization coefficient.
Furthermore decision feedback equalizer 570 generates feedback after receiving data-signal Sd and decision feedback equalization coefficient sets
Signal Sf weigh to summer 520, to reduce the rear vernier part in the first equalizing signal Sy.Substantially, superposition signal Sz, anti-
Present the relationship between equalizing signal Sf and the first equalizing signal Sy are as follows:
Furthermore it is linearly equal that continuous time linear equalizer 510 controls continuous time according to decision feedback equalization coefficient sets
The frequency response (frequency response) of weighing apparatus 510.For example, the promotion electricity of control continuous time linear equalizer 510
Flat (boost level) and pole (pole).Substantially, lift level can be the gain of continuous time linear equalizer 510.
Furthermore the receiver 500 of first embodiment is that data and its data are carried out to superposition signal Sz along (data edge)
Cutting, and data clock dCLK and edge clock eCLK is generated using clock data recovery circuit 550.Furthermore clock
Data recovery circuit 550 needs to generate data clock dCLK and edge clock eCLK, excessively to sample (over
Sampling) superposition signal Sz.Furthermore the phase difference between data clock dCLK and edge clock eCLK is 180 degree.
In addition, needing to utilize spring spring phase detectors (bang-bang phase in clock data recovery circuit 550
Detector), for receiving data-signal Sd and edge signal Sedg, and phase more new information (phase is generated accordingly
Update information) to adjust the phase of data clock dCLK and edge clock eCLK.
Fig. 6 A to Fig. 6 C is please referred to, depicted is continuous time linear equalizer circuit diagram of the present invention and its frequency response
Schematic diagram.Continuous time linear equalizer 510 include: load Rl, bias current source (bias current source) Ibias,
Transistor M1, M2, variable resistance Rs, variable capacitance Cs.Wherein, receiving signal Sx and the first equalizing signal Sy is all differential wave
(differential signal)。
Transistor M1 grid is that first input end receives positive reception signal (positive receiving signal) Sx+,
Drain electrode is that the first output end generates minus first equalizing signal (negative first equalized signal) Sy-, source electrode with
Bias current source Ibias is connected between ground terminal GND.Transistor M2 grid is that the second input terminal receives negative reception signal
(negative receiving signal) Sx- drains and generates positive first equalizing signal (positive for second output terminal
First equalized signal) Sy-, bias current source Ibias is connected between source electrode and ground terminal GND.Furthermore first is defeated
Connection load Rl between outlet and voltage source Vcc；Connection load Rl between second output terminal and voltage source Vcc.Furthermore transistor
Variable resistance Rs and variable capacitance Cs is connected between M1 source electrode and transistor M2 source electrode.
According to an embodiment of the invention, the resistance value of variable resistance Rs is determined according to first in decision feedback equalization coefficient sets
Feedback equalizing coefficient h1 is instigated rebellion within enemy camp to determine；Furthermore the capacitance of variable capacitance Cs is according to second in decision feedback equalization coefficient sets
Decision feedback equalization coefficient h 2 is determined with third decision feedback equalization coefficient h 3.
Assuming that excessively balanced (the over-equalizes channel loss) pass loss of continuous time linear equalizer 510
When, the first decision feedback equalization coefficient h 1 can become negative value.At this point, the resistance value of control variable resistance Rs is to control its promotion
Level (boost level), that is, yield value.Furthermore, it is assumed that when pole too small (pole is too small), can be made
Two decision feedback equalization coefficient hs 2 become negative value with third decision feedback equalization coefficient h 3.At this point, the electricity of control variable capacitance Cs
Capacitance is to control pole location (pole position).
As shown in Figure 6B, the relational graph between the resistance value size and lift level of variable resistance Rs.Substantially, may be used
The resistance value that power transformation hinders Rs is bigger, and lift level is higher.When lift level is excessively high, the first decision feedback equalization coefficient can be made
H1 can become negative value.
As shown in Figure 6 C, the relational graph between the capacitance size and pole of variable capacitance Cs.It substantially, can power transformation
The capacitor resistance value for holding Cs is bigger, and pole is smaller.When pole is too small, the second decision feedback equalization coefficient h 2 can be made to determine with third
Instigating rebellion within enemy camp feedback equalizing coefficient h3 becomes negative value
Furthermore has transfer function (transfer function) H (s) of the continuous time linear equalizer 510 of duopole
It may be expressed as:
Assuming that
Then,
Therefore, the impulse response (impulse response) of continuous time linear equalizer 510 may be expressed as:Adc is DC current gain (DC gain), ωp1With ωp2For two poles, ωzFor zero point,
And k1 is negative value.
It as shown in Figure 7 A, is dominant pole ω different in continuous time linear equalizerp1Two impulse response h1 (t) with
H2 (t) schematic diagram.Since k1 is that negative value and impulse response h2 (t) have lesser pole (0.5GHz).So in impulse response h2
(t) it is formed by natural exponential function (exponential function), it can be because of slower decaying (attenuation)
And longer time is caused to rest on negative value.
Fig. 7 B is channel impulse response (channel impulse response) v (t) and continuous time linear equalizer
Convolution integration (convolution) schematic diagram of middle larger pole (2.5GHz) the impulse response h1 (t) of tool.Fig. 7 C is channel pulse
Has the convolution integration of lower pole (0.5GHz) impulse response h2 (t) in response v (t) and continuous time linear equalizer
(convolution) schematic diagram.
By Fig. 7 C it is found that the convolution integration result of channel impulse response v (t) and impulse response h2 (t) is it is found that will generate
The the second decision feedback equalization coefficient h 2 and third decision feedback equalization coefficient h 3 of negative value.And by Fig. 7 B it is found that channel pulse is rung
The convolution integration result of v (t) and impulse response h1 (t) are answered it is found that the second decision feedback equalization coefficient h 2 of positive value will be generated
With third decision feedback equalization coefficient h 3.In other words, by 560 calculated second decision feedback equalization system of adaptive filter
Number h2 and third decision feedback equalization coefficient h 3 are it is estimated that interfere (residual ISI) between the symbol of remnants.
According to the above description, it can be seen that, the embodiment of the present invention is to control using decision feedback equalization coefficient sets continuously
Lift level (boost level) and extreme value (pole) in linearly balanced device 510.For example, if continuous time
When linear equalizer 510 crosses equalization channel loss, the first decision feedback equalization coefficient h 1 can become negative value.If in addition, pole
When too small, the second decision feedback equalization coefficient h 2 can be made to become negative value with third decision feedback equalization coefficient h 3.In other words,
The resistance value of variable resistance Rs is adjusted according to the first decision feedback equalization coefficient h 1 in continuous time linear equalizer 510；
And the capacitance of variable capacitance Cs is according to the second decision feedback equalization coefficient h 2 and third in continuous time linear equalizer 510
Decision feedback equalization coefficient h 3 adjusts.In this way, may make continuous time linear equalizer according to decision feedback equalization coefficient sets
510 reach its target equalization of level (target equalization level).
Fig. 8 is please referred to, depicted is the control method of continuous time linear equalizer of the present invention.Firstly, adjustment is continuous
Variable resistance Rs and variable capacitance Cs in linearly balanced device 510, to provide the lift level and minimum of maximum value
Pole (step S702).Later, decision feedback equalization coefficient sets (step S704) is received.
Judge whether the first decision feedback equalization coefficient h 1 is less than first threshold Threshold1 (step S706), and first
Threshold value Threshold1 may be set to such as 0.
When determining that the first decision feedback equalization coefficient h 1 is less than first threshold Threshold1 (step S706), adjustment can
The resistance value of power transformation resistance is to reduce lift level (step S708).Then, (the step when determining that lift level does not reach minimum value
S710), step S704 is returned to.
Furthermore (the step when determining the first decision feedback equalization coefficient h 1 not less than first threshold Threshold1
S706), or determine when lift level reaches minimum value (step S710), continue judge the second decision feedback equalization coefficient h 2 and
Whether third decision feedback equalization coefficient h 3 is less than second threshold Threshold2 (step S712), and second threshold
Threshold2 may be set to such as 0.
It is not less than second threshold with third decision feedback equalization coefficient h 3 in the second decision feedback equalization coefficient h of confirmation 2
When Threshold2 (step S712), stopping is adjusted (step S718).
It is less than second threshold with third decision feedback equalization coefficient h 3 in the second decision feedback equalization coefficient h of confirmation 2
When Threshold2 (step S712), the capacitance of variodenser is adjusted to improve pole (step S714).Then, it is determining not yet
When reaching maximum pole (step S716), step S704 is returned to；Conversely, stopping being adjusted (step S718).
It can be seen from the above explanation first adjusting the continuous time linear equalizer 510 has most in the control method of Fig. 8
Big lift level and the smallest pole；Then, the decision feedback equalization coefficient sets are persistently received.When the first decision feedback is equal
When the coefficient h 1 that weighs is less than first threshold Threshold1, lift level is reduced until the first decision feedback equalization coefficient h 1 is not less than
First threshold Threshold1；And when the second decision feedback equalization coefficient h 2 and third decision feedback equalization coefficient h 3 are small
When second threshold Threshold2, pole is improved until the second decision feedback equalization coefficient h 2 and third decision feedback equalization system
Number h3 is not less than the second threshold.
In other words, continuous time linear equalizer 510 of the invention is adjusted according to the first decision feedback equalization coefficient h 1
The resistance value of whole variable resistance is and anti-according to the second decision feedback equalization coefficient h 2 and third decision to change lift level
Equalizing coefficient h3 is presented to adjust the capacitance of variable capacitance to change pole.
Furthermore the present invention can also be according only to the second decision feedback equalization coefficient h 2 or third decision feedback equalization coefficient
H3 adjusts the capacitance of variable capacitance.Alternatively, according to the second decision feedback equalization coefficient h 2 and third decision feedback equalization system
The relationship between h3 is counted to adjust the capacitance of variable capacitance, such as the second decision feedback equalization coefficient h 2 and third decision feedback
The aggregation relationship of equalizing coefficient h3.
Referring to FIG. 9, its depicted receiver schematic diagram for second embodiment of the invention.Receiver 800 includes: continuous
Linearly balanced device 510, clipper circuit 830, clock data recovery circuit 850, adaptive filter 860, decision feedback are equal
Weighing apparatus 870 and summer 820.Wherein, clipper circuit 830 further include: data slicer 832, edge cutter 836 are cut with error
Cutter 834.Adaptive filter 860 may be based on the adaptive filter of least-mean-square filter.
The other end in channel 204 is connected to receiver 800, so that receiving the consecutive hours of signal Sx input sink 800
Between linear equalizer 510, to improve receive signal Sx in high frequency section size and become the first equalizing signal Sy.Again
Person, after summer 820 is added up the feedback equalization signal Sf that decision feedback equalizer 870 generates and the first equalizing signal Sy
Generate superposition signal Sz.
In clipper circuit 830, data slicer 832 is cut according to one first killer voltage Ss1 with clock signal clk
Superposition signal Sz simultaneously generates data-signal Sd.Edge cutter 836 according to one second killer voltage Ss2 and clock signal clk come
Cutting superposition signal Sz simultaneously generates edge sampled signal Sedg.Error cutter 834 is according to according to reference voltage Vref and clock
Signal CLK cuts superposition signal Sz and generates error signal (error signal) Serr.
In addition, clock data recovery circuit 850 receives data-signal Sd and edge sampled signal Sedg and generates clock
Signal CLK is to clipper circuit 830.Furthermore adaptive filter 860 receives data-signal Sd and error signal Serr to generate one
Reference voltage Vref generates a decision feedback equalization coefficient sets (DFE coefficient set) to error cutter 834
To decision feedback equalizer 870 and continuous time linear equalizer 510.
Substantially, adaptive filter 860 dynamically changes the reference according to data-signal Sd and error signal Serr
Voltage Vref and decision feedback equalization coefficient sets.It for example, include five decision feedbacks in decision feedback equalization coefficient sets
Equalizing coefficient h1, h2, h3, h4, h5.Certainly, decision feedback equalization coefficient sets of the present invention are not limited to decision feedback equalization system
Several numbers.
Furthermore decision feedback equalizer 870 generates feedback after receiving data-signal Sd and decision feedback equalization coefficient sets
Signal Sf weigh to summer 820, to reduce the rear vernier part in the first equalizing signal Sy.Substantially, superposition signal Sz, anti-
Present the relationship between equalizing signal Sf and the first equalizing signal Sy are as follows:
Furthermore it is linearly equal that continuous time linear equalizer 510 controls continuous time according to decision feedback equalization coefficient sets
The frequency response (frequency response) of weighing apparatus 510.For example, the promotion electricity of control continuous time linear equalizer 510
Flat (boost level) and pole (pole).Substantially, lift level can be the gain of continuous time linear equalizer 510.
Furthermore the receiver 800 of second embodiment is to carry out data to superposition signal Sz using identical clock signal clk
And the sampling of phase error.
It can be seen from the above explanation the present invention proposes receiver and its corresponding control methods.It is equal using the first decision feedback
Weighing apparatus coefficient h 1 adjusts the resistance value of the variable resistance in continuous time linear equalizer 510, to change lift level.Again
Person adjusts the capacitance of variable capacitance using the second decision feedback equalization coefficient h 2 with third decision feedback equalization coefficient h 3,
To change pole.
Although however, it is not to limit the invention in conclusion the present invention is disclosed as above with preferred embodiment.This hair
Bright one of ordinary skill in the art without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Therefore, originally
The protection scope of invention is subject to view the appended claims confining spectrum.
Claims (10)
1. a kind of receiver, comprising:
Continuous time linear equalizer receives signal and handles the reception signal with lift level according to pole and generate
First equalizing signal；
Clipper circuit is coupled to the continuous time linear equalizer, to according to first equalizing signal and feedback equalization signal
To generate data-signal；And
Decision feedback equalization circuit is coupled to the clipper circuit, to handle the data according to decision feedback equalization coefficient sets
Signal, and generate the feedback equalization signal；
Wherein, which is adjusted according to the first decision feedback equalization coefficient in the decision feedback equalization coefficient sets
It is whole.
2. receiver as described in claim 1, wherein the pole is according to the second decision in the decision feedback equalization coefficient sets
Feedback equalization coefficient is adjusted with third decision feedback equalization coefficient.
3. receiver as described in claim 1, wherein it is logical to receive this to be connected to channel for the continuous time linear equalizer
The reception signal of road output.
4. receiver as described in claim 1, wherein the reception signal includes just receiving signal and bearing to receive signal, and be somebody's turn to do
First equalizing signal includes positive first equalizing signal and minus first equalizing signal, and the continuous time linear equalizer includes:
The first transistor, grid be first input end receive the positive reception signal, drain for the first output end generate this minus first
Equalizing signal；
Second transistor, grid be the second input terminal receive this it is negative receive signal, drain for second output terminal generate this positive first
Equalizing signal；
First bias current source, is connected between ground terminal and the source electrode of the first transistor；
Second bias current source, is connected between the ground terminal and the source electrode of the second transistor；
First load, is connected between first output end and voltage source；
Second load, is connected between the second output terminal and the voltage source；
Variable resistance is connected between the source electrode of the first transistor and the source electrode of the second transistor；And variable capacitance connection
Between the source electrode of the first transistor and the source electrode of the second transistor.
5. receiver as claimed in claim 4, wherein in the continuous time linear equalizer, according to the decision feedback equalization
The first decision feedback equalization coefficient in coefficient sets is come the resistance value that adjusts the variable resistance.
6. receiver as claimed in claim 4, wherein in the continuous time linear equalizer, according to the decision feedback equalization
The second decision feedback equalization coefficient in coefficient sets adjusts the capacitance of the variable capacitance with third decision feedback equalization coefficient.
7. receiver as described in claim 1 further includes wherein clock data recovery circuit and adaptive filtering in receiver
Device, and the clipper circuit includes:
Data slicer receives superposition signal and the first killer voltage, and generates the data-signal according to clock signal and extremely should
Clock data recovery circuit and the adaptive filter；
Edge cutter receives the superposition signal and the second killer voltage, and generates edge signal extremely according to the clock signal
The clock data recovery circuit；And
Error cutter receives the superposition signal and reference voltage, and it is suitable to this to generate according to the clock signal error signal
Answering property filter；
Wherein, clock data recovery circuit generates the clock signal according to the data-signal and the edge signal；The adaptability
Filter generates the reference voltage and the feedback equalization coefficient sets according to the data-signal and the error signal；And the superposition signal
For the superposition result of first equalizing signal and the feedback equalization signal.
8. receiver as described in claim 1 further includes wherein clock data recovery circuit and adaptive filtering in receiver
Device, and the clipper circuit includes:
Data slicer receives superposition signal and the first killer voltage, and generates the data-signal according to data clock signal
To the clock data recovery circuit and the adaptive filter；
Edge cutter receives the superposition signal and the second killer voltage, and generates edge signal according to edge clock signal
To the clock data recovery circuit；And
Error cutter receives the superposition signal and reference voltage, and generates error signal extremely according to the data clock signal
The adaptive filter；
Wherein, clock data recovery circuit generates the data clock signal and the side according to the data-signal and the edge signal
Along clock signal；The adaptive filter generates the reference voltage and the feedback equalization according to the data-signal and the error signal
Coefficient sets；And the superposition signal is the superposition result of first equalizing signal and the feedback equalization signal.
9. a kind of control method for applying to receiver described in claim 1, further includes the following steps:
(a) continuous time linear equalizer is adjusted with the maximum lift level and the smallest pole；
(b) the decision feedback equalization coefficient sets are persistently received；
(c) when the first decision feedback equalization coefficient in the decision feedback equalization coefficient sets is less than first threshold, reducing should
Lift level is not less than the first threshold until the first decision feedback equalization coefficient；And
(d) when the second decision feedback equalization coefficient in the decision feedback equalization coefficient sets is less than second threshold, pole is improved
Until the second decision feedback equalization coefficient is not less than the second threshold.
10. control method as claimed in claim 9, further includes: when the third decision in the decision feedback equalization coefficient sets is anti-
When presenting equalizing coefficient less than the second threshold, the pole is improved until the third decision feedback equalization coefficient is not less than second threshold
Value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510569956.8A CN106534011B (en) | 2015-09-09 | 2015-09-09 | receiver and related control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510569956.8A CN106534011B (en) | 2015-09-09 | 2015-09-09 | receiver and related control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106534011A CN106534011A (en) | 2017-03-22 |
| CN106534011B true CN106534011B (en) | 2019-06-14 |
Family
ID=58346841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510569956.8A Active CN106534011B (en) | 2015-09-09 | 2015-09-09 | receiver and related control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106534011B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI741227B (en) * | 2018-11-13 | 2021-10-01 | 瑞鼎科技股份有限公司 | Input detection circuit of receiver and operating method thereof |
| CN111726104B (en) * | 2019-03-22 | 2024-08-27 | 瑞昱半导体股份有限公司 | Decision feedback equalizer |
| CN110493152B (en) * | 2019-08-19 | 2021-09-28 | 哈尔滨工业大学 | Self-adaptive equalization circuit based on frequency spectrum balancing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579618A (en) * | 2013-10-09 | 2015-04-29 | 创意电子股份有限公司 | Method applied to interconnection system and related processing module |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2115929B1 (en) * | 2007-01-09 | 2014-05-21 | Rambus Inc. | Receiver with clock recovery circuit and adaptive sample and equalizer timing |
| US8731040B2 (en) * | 2010-09-28 | 2014-05-20 | Lsi Corporation | Adapting transfer functions of continuous-time equalizers |
| US8588288B2 (en) * | 2010-11-19 | 2013-11-19 | Maxim Integrated Products, Inc. | Method and apparatus for controlling a continuous time linear equalizer |
-
2015
- 2015-09-09 CN CN201510569956.8A patent/CN106534011B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579618A (en) * | 2013-10-09 | 2015-04-29 | 创意电子股份有限公司 | Method applied to interconnection system and related processing module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106534011A (en) | 2017-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11115247B2 (en) | Methods and circuits for asymmetric distribution of channel equalization between devices | |
| US10560291B2 (en) | High-speed signaling systems and methods with adaptable, continuous-time equalization | |
| US9705708B1 (en) | Integrated circuit with continuously adaptive equalization circuitry | |
| US8325793B2 (en) | Precursor ISI cancellation using adaptation of negative gain linear equalizer | |
| US8831142B2 (en) | Adaptive cancellation of voltage offset in a communication system | |
| US8472513B2 (en) | TX back channel adaptation algorithm | |
| US20150381393A1 (en) | Adaptive Cancellation of Voltage Offset in a Communication System | |
| US9438450B1 (en) | Receiver and associated control method | |
| EP1540820A2 (en) | Method and apparatus for channel equalization | |
| TW200917650A (en) | Continuous time-decision feedback equalizer | |
| US10742453B1 (en) | Nonlinear equalizer with nonlinearity compensation | |
| CN110858824B (en) | Pre-compensator based quantization for clock recovery | |
| US9124454B1 (en) | Method and apparatus for adaptively determining settings of a transmit equalizer | |
| US20220302951A1 (en) | Network transceiver with vga channel specific equalization | |
| US9363110B2 (en) | Apparatus and methods for estimating optical Ethernet data sequences | |
| US8208529B2 (en) | Equalization apparatus and method of compensating distorted signal and data receiving apparatus | |
| CN106534011B (en) | receiver and related control method | |
| TWI440337B (en) | Hybrid equalization system | |
| CN102437978B (en) | Method and device for balancing digital microwaves | |
| US8644369B1 (en) | Equalizer adaptation for heavily compressed or clipped communications signals | |
| CN102404259A (en) | Mixing balance system | |
| CN106533646B (en) | Clock Data Recovery System in Sequencer/Deserializer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |