TWI738627B - Smart network interface controller system and method of detecting error - Google Patents

Abstract

A method of detecting method is disclosed in the present invention. In the method, a SoC(System on a Chip) is utilized to detect a parity error, a system error and a multi bit ECC memory error; then a CPLD(Complex Programmable Logic Device) is utilized to save and transmit the above error to a BMC(Baseboard Management Controller); and then a smart network interface controller system is operated to re-boot; finally, the smart network interface controller system starts working when the SoC does not to detect any error. The smart network interface controller system is also disclosed in the present invention.

Description

Intelligent network card system with error detection function and error detection method

The present invention relates to a system and method, in particular to an intelligent network card system with error detection function and an error detection method.

The network card is an indispensable device for connecting to the network for communication, and cooperates with the central processing unit (CPU) on the motherboard to complete the processing of all layers in the entire network protocol. With the development of technology, smart network cards have gradually become popular. Generally speaking, compared with traditional network cards, smart network cards can not only send and receive data, but also have high performance and programmable computing capabilities. However, if the system chip on the smart network card has a parity error (PERR), system error (SERR), or multi-bit ECC memory error, it will cause the system chip to malfunction and lead to smart The network card is not working properly. Therefore, there is room for improvement in the prior art.

In view of the various problems derived from the inability of the smart network card to operate normally due to parity errors, system errors, or memory errors in the prior art. One of the main objectives of the present invention is to provide a smart network card system with error detection function to solve at least one problem in the prior art.

In order to solve the problems of the prior art, the necessary technical means adopted by the present invention are to provide an intelligent network card system with error detection function, which is externally connected to a host system and includes a processing chip and a complex programmable logic device. The processing chip includes a parity check detection module, a system error detection module, a correction memory detection module, and a first communication module. The parity detection module is used for detecting parity error information of one of the processing chips. The system error detection module is used for detecting system error information of one of the processing chips. The correction memory detection module is used to detect one of the processing chips and correct memory error information. The first communication module is electrically connected to the parity detection module, the system error detection module, and the correction memory detection module for detecting parity error information, system error information, and correction memory When detecting at least one of the modules, at least one of the above-mentioned parity error information, system error information, and correction memory detection module is sent.

The complex programmable logic device is electrically connected to the processing chip, and includes a receiving module, an error storage module and a second communication module. The receiving module is electrically connected to the first communication module for receiving at least one of the above-mentioned parity error information, system error information, and correction memory detection module. The error storage module is electrically connected to the receiving module, and includes a parity storage unit, a system error storage unit, and a correction memory storage unit. The parity storage unit is used for storing parity error information. The system error storage unit is used for storing system error information. The modified memory storage unit is used to store and modify memory error information. The second communication module is electrically connected to the error storage module for transmitting at least one of the parity error information, system error information, and correction memory detection module to a baseboard management controller of the host system.

After receiving and storing at least one of the parity error information, system error information, and correction memory detection module, the baseboard management controller sends a clear signal to enable the smart network card system to be operated and restarted separately After that, the error storage module clears at least one of the parity error information, system error information, and correction memory detection module, so that the smart network card system can operate normally.

On the basis of the above-mentioned necessary technical means, an auxiliary technical means derived from the present invention is to make the first communication module in the intelligent network card system with error detection function use a serial general purpose input and output (Serial General Purpose Input and Output). Input/Output; SGPIO) interface is electrically connected to the receiving module.

On the basis of the above-mentioned necessary technical means, an auxiliary technical means derived from the present invention is that the second communication module in the intelligent network card system with error detection function is an I2C module.

On the basis of the above-mentioned necessary technical means, an auxiliary technical means derived from the present invention is to make the second communication module in the intelligent network card system with error detection function use a Power Management Bus (PMBUS). ) It is electrically connected to the baseboard management controller of the host system.

In order to solve the problems of the prior art, the necessary technical means adopted by the present invention is to provide another error detection method, which is implemented by using the smart network card system with error detection function as described above, and includes the following steps: using parity check The detection module, the system error detection module, and the corrected memory detection module detect at least one of the above-mentioned parity error information, system error information, and corrected memory error information; use the first communication module Send out at least one of the aforementioned parity error information, system error information, and corrected memory error information; use the receiving module to receive at least one of the aforementioned parity error information, system error information, and corrected memory error information ; Use the error storage module to store at least one of the above-mentioned parity error information, system error information and corrected memory error information; use the second communication module to store the above-mentioned parity error information, system error information and corrected memory At least one of the error information is sent to the baseboard management controller; the smart network card system is restarted separately; the error storage module is used to receive the clear signal, and clear the above-mentioned parity error information, system error information and correction memory detection mode At least one of the group.

As mentioned above, the smart network card system with error detection function and error detection method provided by the present invention utilize the parity detection module, the system error detection module, and the correction memory detection module to detect separately Test the parity error information, system error information and correction memory error information of the processing chip, and use the parity storage unit, system error storage unit and correction memory storage unit to store parity error information, system error information and corrections respectively Memory error information. Compared with the prior art, the present invention can normally and stably record parity error information, system error information, and correct memory error information that would cause chip failures to work normally. It is sent to the baseboard management controller of the host system, and can be restarted separately from the host system, so that the error storage module clears the above error information until the parity detection module, the system error detection module and the correction memory detection After the test module does not detect the above error information, the smart network card system with error detection function can operate normally.

The specific embodiments of the present invention will be described in more detail below in conjunction with the schematic diagrams. According to the following description and the scope of patent application, the advantages and features of the present invention will be more clear. It should be noted that the drawings all adopt a very simplified form and all use imprecise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

Please refer to the first and second figures. The first figure shows the block diagram of the smart network card system with error detection function provided by the preferred embodiment of the present invention; and the second figure shows the preferred embodiment of the present invention. The flow chart of the error detection method provided by the embodiment. As shown in the figure, an error detection method is implemented using a smart network card system 1 with an error detection function, and includes steps S101 to S108.

The intelligent network card system 1 with error detection function is externally connected to a host system 2 and includes a processing chip 11 and a complex programmable logic device (CPLD) 12.

The processing chip 11 includes a parity detection module 111, a system error detection module 112, a correction memory detection module 113, and a first communication module 114. Among them, the processing chip 11 is a system on a chip (System on a Chip; SoC).

The complex programmable logic device 12 is electrically connected to the processing chip 11 and includes a receiving module 121, an error storage module 122, and a second communication module 123. The error storage module 122 includes a parity storage unit 1221, a system error storage unit 1222, and a correction memory storage unit 1223.

Step S101: Whether the parity detection module, the system error detection module, and the correction memory detection module detect parity error information, system error information or correct memory error information.

The parity detection module 111 is used for detecting a parity error (PERR) information of the processing chip 11. The system error detection module 112 is used for detecting a system error (SERR) information of the processing chip 11. The modified memory detection module 113 is used to detect a Multi Bit ECC Memory Error (Multi Bit ECC Memory Error) information of the processing chip 11. The above parity error information, system error information, and corrected memory error information can be collectively referred to as error information. If the processing chip 11 generates any of the above parity error information, system error information, and corrected memory error information, it will As a result, the processing chip 11 fails to operate normally. In actual operation, the processing chip 11 may also generate at least two of the above-mentioned parity error information, system error information, and correction memory error information.

Therefore, the parity detection module 111, the system error detection module 112, and the correction memory detection module 113 will detect whether the processing chip 11 generates the aforementioned parity error information, system error information, and correct memory errors. Any one of information. When the parity detection module 111, the system error detection module 112, and the corrected memory detection module 113 detect at least one of the above-mentioned parity error information, system error information, and corrected memory error information , It will go to step S102.

Step S102: Use the first communication module to transmit the above-mentioned error information.

The first communication module 114 is electrically connected to the parity detection module 111, the system error detection module 112, and the correction memory detection module 113 for receiving and transmitting the aforementioned parity error information and system errors At least one of information and correction memory error information.

For example, when only the parity detection module 111 detects the parity error information, but the system error detection module 112 and the corrected memory detection module 113 do not detect the system error information and correct the memory In the case of error information, the first communication module 114 only transmits parity error information. When the parity detection module 111 and the system error detection module 112 respectively detect the parity error information and the system error information, and the corrected memory detection module 113 does not detect the corrected memory error information , The first communication module 114 will send out parity error information and system error information.

Step S103: Use the receiving module to receive the above-mentioned error information.

The receiving module 121 of the complex programmable logic device 12 is electrically connected to the first communication module 114 for receiving the above-mentioned error information. As mentioned above, what kind of error information is transmitted by the first communication module 114, and which kind of error information will be received by the receiving module 121. In actual operation, the first communication module 114 may be electrically connected to the receiving module 121 through a serial general purpose input/output (Serial General Purpose Input/Output; SGPIO) interface, but it is not limited to this.

Step S104: Use the error storage module to store the above-mentioned error information.

The error storage module 122 of the complex programmable logic device 12 is electrically connected to the receiving module 121 for storing the above-mentioned error information, and includes a parity storage unit 1221, a system error storage unit 1222, and a correction memory storage Unit 1223. As mentioned above, which kind of error information is received by the receiving module 121, and which kind of error information will be stored by the error storage module 122. The parity storage unit 1221 is used to store parity error information, the system error storage unit 1222 is used to store system error information, and the correction memory storage unit 1223 is used to store correction memory error information.

Step S105: Use the second communication module to transmit the above-mentioned error information to the baseboard management controller.

The second communication module 123 of the complex programmable logic device 12 is electrically connected to the error storage module 122 for transmitting the error information to a baseboard management controller (BMC) 21 of the host system 2. As described above, what kind of error information is stored by the error storage module 122, and what kind of error information will be transmitted by the second communication module 123.

Step S106: Utilize the baseboard management controller to store the above-mentioned error information and send a clear signal.

The baseboard management controller 21 stores the above-mentioned error information and knows that the smart network card system 1 with error detection function is in an abnormal state, so it generates and transmits a clear signal. The storage of the above-mentioned error information by the baseboard management controller 21 also allows a user to observe and learn from the host system 2 the state of the smart network card system 1 with an error detection function and the type of error information that caused the abnormal state.

Step S107: Restart the smart network card system separately.

Because the smart network card system 1 with error detection function is externally connected to the host system 2, the smart network card system 1 with error detection function is operated separately from the host system 2 and restarts. It should be noted that the smart network card system 1 with the error detection function is restarted separately, and the host system 2 will not be affected, so the host system 2 can still operate normally.

Step S108: Use the error storage module to receive the clear signal, and clear the above-mentioned error information.

After the error storage module 122 of the complex programmable logic device 12 receives the clear signal, it clears the above-mentioned error information.

The above step S108 will be followed by step S101. At this time, the parity detection module 111, the system error detection module 112 and the correction memory detection module 113 will be used to detect whether the processing chip 11 generates the above parity. Verify at least one of error information, system error information, and corrected memory error information. If the result is still yes, the above steps S102 to S108 will be performed again.

When the parity detection module 111, the system error detection module 112, and the correction memory detection module 113 do not detect the processing chip 11, the above parity error information, system error information, and correction memory error information are generated. Any of the above means that the smart network card system 1 with error detection function can operate normally, and the error detection method provided by the preferred embodiment of the present invention will end.

In summary, the intelligent network card system with error detection function and error detection method provided by the present invention utilize the parity detection module, the system error detection module, and the correction memory detection module to detect separately Test the parity error information, system error information and correction memory error information of the processing chip, and use the parity storage unit, system error storage unit and correction memory storage unit to store parity error information, system error information and corrections respectively Memory error information. Compared with the prior art, the present invention can normally and stably record parity error information, system error information, and correct memory error information that would cause chip failures to work normally. It is sent to the baseboard management controller of the host system, and can be restarted separately from the host system, so that the error storage module clears the above error information until the parity detection module, system error detection module, and correction memory detection After the test module does not detect the above error information, the smart network card system with error detection function can operate normally.

In addition, if the parity detection module, the system error detection module, and the correction memory detection module continue to detect the above-mentioned error information, the intelligent error detection function provided by the preferred embodiment of the present invention The network card system and error detection method will repeat the above steps of detection, transmission, storage, restarting, etc., until the parity detection module, system error detection module, and correction memory detection module are not detected After the above error information, the intelligent network card system with error detection function can operate normally.

Through the detailed description of the above preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the purpose is to cover various changes and equivalent arrangements within the scope of the patent for which the present invention is intended.

1: Intelligent network card system with error detection function 11: Handling wafers 111: Parity detection module 112: System error detection module 113: Modify the memory detection module 114: The first communication module 12: Complex programmable logic device 121: receiving module 122: Error storage module 1221: Parity storage unit 1222: System error storage unit 1223: Modify the memory storage unit 123: The second communication module 2: Host system 21: baseboard management controller

The first figure is a block diagram showing the smart network card system with error detection function provided by the preferred embodiment of the present invention; and The second figure is a flowchart of the error detection method provided by the preferred embodiment of the present invention.

1: Intelligent network card system with error detection function

11: Handling wafers

111: Parity detection module

112: System error detection module

113: Modify the memory detection module

114: The first communication module

12: Complex programmable logic device

121: receiving module

122: Error storage module

1221: Parity storage unit

1222: System error storage unit

1223: Modify the memory storage unit

123: The second communication module

2: Host system

21: baseboard management controller

Claims (5)

An intelligent network card system with error detection function is externally connected to a host system and includes: A processing wafer, including: A parity detection module for detecting parity error information of one of the processing chips; A system error detection module for detecting system error information of one of the processing chips; A modified memory detection module for detecting one of the processing chips to correct memory error information; and A first communication module is electrically connected to the parity detection module, the system error detection module, and the correction memory detection module for detecting the parity error information, When at least one of the system error information and the modified memory detection module is sent, at least one of the above-mentioned parity error information, the system error information and the modified memory detection module is sent; and A complex programmable logic device, which is electrically connected to the processing chip, includes: A receiving module is electrically connected to the first communication module for receiving at least one of the parity error information, the system error information, and the corrected memory detection module: An error storage module, which is electrically connected to the receiving module, and includes: A parity storage unit for storing the parity error information; A system error storage unit for storing the system error information; and A modified memory storage unit for storing the modified memory error information; and A second communication module is electrically connected to the error storage module for transmitting at least one of the parity error information, the system error information, and the corrected memory detection module to the host One of the system baseboard management controllers; Wherein, after the baseboard management controller receives and stores at least one of the parity error information, the system error information, and the corrected memory detection module, it transmits a clear signal to make the smart network card system receive After the operation is separately restarted, the error storage module clears at least one of the parity error information, the system error information, and the corrected memory detection module, so that the smart network card system operates normally. The smart network card system with error detection function according to claim 1, wherein the first communication module uses a serial general purpose input/output (Serial General Purpose Input/Output; SGPIO) interface to electrically connect the receiver Module. The smart network card system with error detection function according to claim 1, wherein the second communication module is an I2C module. The intelligent network card system with error detection function according to claim 1, wherein the second communication module uses a power management bus (Power Management Bus; PMBUS) to electrically connect the baseboard management control of the host system Device. An error detection method is implemented using the smart network card system with error detection function as described in claim 1, and includes the following steps: (a) Use the parity detection module, the system error detection module, and the corrected memory detection module to detect the above-mentioned parity error information, the system error information, and the corrected memory error At least one of the information; (b) Using the first communication module to transmit at least one of the aforementioned parity error information, the system error information, and the corrected memory error information; (c) Using the receiving module to receive at least one of the parity error information, the system error information, and the corrected memory error information; (d) Use the error storage module to store at least one of the above-mentioned parity error information, the system error information, and the corrected memory error information; (e) Using the second communication module to transmit at least one of the parity error information, the system error information, and the corrected memory error information to the baseboard management controller; (f) Restart the smart network card system separately; (g) Using the error storage module to receive the clear signal, and clear at least one of the above-mentioned parity error information, the system error information, and the correction memory detection module.

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