TW202236274A - Smart network interface controller system and method of detecting error - Google Patents

Abstract

A method of detecting method is disclosed in the present invention. In the method, a SoC(System on a Chip) is utilized to detect a parity error, a system error and a multi bit ECC memory error; then a CPLD(Complex Programmable Logic Device) is utilized to save and transmit the above error to a BMC(Baseboard Management Controller); and then a smart network interface controller system is operated to re-boot; finally, the smart network interface controller system starts working when the SoC does not to detect any error. The smart network interface controller system is also disclosed in the present invention.

Description

Intelligent network card system with error detection function and error detection method

The present invention relates to a system and method, in particular to an intelligent network card system with error detection function and an error detection method.

The network card is an essential device for accessing the network for communication, and cooperates with the Central Processing Unit (CPU) on the motherboard to complete the processing of each layer in the entire network protocol. With the development of science and technology, smart network cards are becoming more and more popular. Generally speaking, compared with traditional network cards, smart network cards not only can send and receive data, but also have high-performance and programmable computing capabilities. However, if the system chip on the smart network card has a parity error (Parity Error; PERR), a system error (System Error; SERR) or a correction memory error (Multi Bit ECC Memory Error), it will cause the system chip to fail, resulting in smart The network card is not functioning properly. Therefore, there is room for improvement in the prior art.

In view of the various problems derived from the inability of the smart network card to operate normally due to parity error, system error or memory error correction in the prior art. One of the main objectives of the present invention is to provide an iNIC system with error detection function to solve at least one problem in the prior art.

In order to solve the problems of the prior art, the necessary technical means adopted by the present invention is to provide an intelligent network card system with error detection function, which is externally connected to a host system and includes a processing chip and a complex programmable logic device. The processing chip includes a parity detection module, a system error detection module, a correction memory detection module and a first communication module. The parity check detection module is used for detecting one parity check error information of the processing chip. The system error detection module is used for detecting system error information of the processing chip. The memory correction detection module is used for detecting memory error information of one of the processing chips. The first communication module is electrically connected to the parity detection module, the system error detection module and the correction memory detection module for detecting parity error information, system error information and correction memory When at least one of the detection modules is used, at least one of the above-mentioned parity error information, system error information and memory correction detection module is sent.

The complex programmable logic device is electrically connected to the processing chip, and includes a receiving module, an error storage module and a second communication module. The receiving module is electrically connected to the first communication module for receiving at least one of the above-mentioned parity error information, system error information and memory correction detection module. The error storage module is electrically connected to the receiving module, and includes a parity storage unit, a system error storage unit and a correction memory storage unit. The parity storage unit is used for storing parity error information. The system error storage unit is used for storing system error information. The correction memory storage unit is used for storing correction memory error information. The second communication module is electrically connected to the error storage module for transmitting at least one of the above-mentioned parity error information, system error information and the correction memory detection module to a baseboard management controller of the host system.

Wherein, after the baseboard management controller receives and stores at least one of the above-mentioned parity error information, system error information, and the correction memory detection module, it sends a clear signal, so that the smart network card system can be independently restarted. Afterwards, the error storage module clears at least one of the above-mentioned parity error information, system error information and memory detection module, so as to make the smart network card system operate normally.

On the basis of the above-mentioned necessary technical means, an auxiliary technical means derived from the present invention is to make the first communication module in the intelligent network card system with error detection function use a series of general-purpose input and output (Serial General Purpose) Input/Output; SGPIO) interface is electrically connected to the receiving module.

On the basis of the above-mentioned necessary technical means, an auxiliary technical means derived from the present invention is to make the second communication module in the intelligent network card system with error detection function be an I2C module.

On the basis of the above-mentioned necessary technical means, an auxiliary technical means derived from the present invention is to make the second communication module in the intelligent network card system with error detection function use a power management bus (Power Management Bus; PMBUS ) is electrically connected to the baseboard management controller of the host system.

In order to solve the problems of the prior art, the necessary technical means adopted by the present invention is to provide an additional error detection method, which is implemented by using the intelligent network card system with error detection function as described above, and includes the following steps: using parity check The detection module, the system error detection module and the correction memory detection module detect at least one of the above-mentioned parity error information, system error information and correction memory error information; using the first communication module Send out at least one of the above-mentioned parity error information, system error information, and corrected memory error information; use the receiving module to receive at least one of the above-mentioned parity error information, system error information, and corrected memory error information ; Use the error storage module to store at least one of the above-mentioned parity error information, system error information and correction memory error information; use the second communication module to store the above-mentioned parity error information, system error information and correction memory At least one of the error information is sent to the baseboard management controller; the smart network card system is restarted independently; the error storage module is used to receive the clear signal, and the above-mentioned parity error information, system error information and correction memory detection module are cleared at least one of the group.

Based on the above, the intelligent network card system and error detection method with error detection function provided by the present invention use the parity detection module, the system error detection module, and the corrected memory detection module to respectively detect The parity check error information, system error information and correction memory error information of the processing chip are measured, and the parity check storage unit, the system error storage unit and the correction memory storage unit are used to respectively store the parity check error information, system error information and correction Memory error information, compared with the prior art, the present invention can normally and stably record the parity check error information, system error information and correct memory error information that will cause the processing chip failure to work normally, and can store the above error information sent to the baseboard management controller of the host system, and can be restarted independently relative to the host system, so that the error storage module clears the above error information until the parity check detection module, system error detection module and correction memory detection module After the test module fails to detect the above error information, the intelligent network card system with error detection function can operate normally.

The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. The advantages and features of the present invention will be more clear from the following description and claims. It should be noted that all the drawings are in very simplified form and use imprecise scales, which are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

Please refer to the first figure and the second figure, wherein, the first figure shows the block diagram of the intelligent network card system with error detection function provided by the preferred embodiment of the present invention; and, the second figure shows the preferred embodiment of the present invention A flow chart of the error detection method provided by the embodiment. As shown in the figure, an error detection method is implemented by using an iNIC system 1 with an error detection function, and includes steps S101 to S108.

The smart network card system 1 with error detection function is externally connected to a host system 2 and includes a processing chip 11 and a complex programmable logic device (Complex Programmable Logic Device, CPLD) 12 .

The processing chip 11 includes a parity detection module 111 , a system error detection module 112 , a modified memory detection module 113 and a first communication module 114 . Wherein, the processing chip 11 is a System on a Chip (SoC).

The CPLD 12 is electrically connected to the processing chip 11 and includes a receiving module 121 , an error storage module 122 and a second communication module 123 . The error storage module 122 includes a parity storage unit 1221 , a system error storage unit 1222 and a correction memory storage unit 1223 .

Step S101 : whether the parity check detection module, the system error detection module and the correction memory detection module detect parity error information, system error information or correction memory error information.

The parity detection module 111 is used for detecting a Parity Error (PERR) information of the processing chip 11 . The system error detection module 112 is used for detecting a system error (System Error; SERR) information of the processing chip 11 . The modified memory detection module 113 is used for detecting a modified memory error (Multi Bit ECC Memory Error) information of the processing chip 11 . The above-mentioned parity error information, system error information and corrected memory error information can be collectively referred to as error information. If any of the above-mentioned parity error information, system error information and corrected memory error information is generated by the processing chip 11, As a result, the processing chip 11 fails to operate normally. In actual operation, the processing chip 11 may also generate at least two of the above-mentioned parity error information, system error information and correct memory error information.

Therefore, the parity detection module 111, the system error detection module 112 and the correction memory detection module 113 will detect whether the processing chip 11 generates the above-mentioned parity error information, system error information and correction memory error any of the information. When the parity detection module 111, the system error detection module 112 and the correction memory detection module 113 detect at least one of the above-mentioned parity error information, system error information and correction memory error information , it will enter step S102.

Step S102: Utilize the first communication module to send the above error information.

The first communication module 114 is electrically connected to the parity detection module 111, the system error detection module 112 and the correction memory detection module 113, and is used to receive and transmit the above-mentioned parity error information and system error information. at least one of information and memory error correction information.

For example, when only the parity check detection module 111 detects the parity check error information, but the system error detection module 112 and the correction memory detection module 113 do not detect the system error information and the correction memory In case of error information, the first communication module 114 will only send out parity error information. When the parity detection module 111 and the system error detection module 112 detect the parity error information and the system error information respectively, but the correction memory detection module 113 does not detect the correction memory error information , the first communication module 114 will send parity error information and system error information.

Step S103: Use the receiving module to receive the above error information.

The receiving module 121 of the CPLD 12 is electrically connected to the first communication module 114 for receiving the above error information. As mentioned above, which kind of error information is transmitted by the first communication module 114, the receiving module 121 will receive that kind of error information. In actual operation, the first communication module 114 can be electrically connected to the receiving module 121 through a serial general purpose input/output (Serial General Purpose Input/Output; SGPIO) interface, but not limited thereto.

Step S104: Use the error storage module to store the above error information.

The error storage module 122 of the complex programmable logic device 12 is electrically connected to the receiving module 121 for storing the above error information, and includes a parity storage unit 1221, a system error storage unit 1222 and a correction memory storage Unit 1223. As mentioned above, the error storage module 122 will store the error information that is received by the receiving module 121 . The parity storage unit 1221 is used to store parity error information, the system error storage unit 1222 is used to store system error information, and the correction memory storage unit 1223 is used to store correction memory error information.

Step S105: Utilize the second communication module to transmit the above error information to the baseboard management controller.

The second communication module 123 of the CPLD 12 is electrically connected to the error storage module 122 for transmitting the above error information to a Baseboard Management Controller (BMC) 21 of the host system 2 . As mentioned above, which kind of error information is stored by the error storage module 122, that kind of error information will be transmitted by the second communication module 123.

Step S106: Utilize the baseboard management controller to store the above error information, and send a clear signal.

The baseboard management controller 21 will store the above error information and know that the iNIC system 1 with error detection function is in an abnormal state, so it will generate and send a clear signal. The storage of the above error information by the BMC 21 can also allow a user to observe from the host system 2 and know the status of the iNIC system 1 with the error detection function and the type of error information causing the abnormal state.

Step S107: Restart the iNIC system independently.

Since the iNIC system 1 with the error detection function is externally connected to the host system 2 , the iNIC system 1 with the error detection function is operable to reboot independently of the host system 2 . It should be noted that the independent restart of the iNIC system 1 with the error detection function will not affect the host system 2, so the host system 2 can still operate normally.

Step S108: Use the error storage module to receive a clear signal, and clear the above error information.

After receiving the clear signal, the error storage module 122 of the CPLD 12 clears the above error information.

The above step S108 will return to step S101. At this time, the parity detection module 111, the system error detection module 112 and the correction memory detection module 113 will be used to detect whether the processing chip 11 generates the above parity. At least one of verification error information, system error information and memory correction error information. If the result is still yes, the above steps S102 to S108 will be performed again.

When the parity detection module 111, the system error detection module 112 and the correction memory detection module 113 have not detected the processing chip 11 to generate the above parity error information, system error information and correction memory error information Any one of them, it means that the intelligent network card system 1 with error detection function can operate normally, and the error detection method provided by the preferred embodiment of the present invention will end.

To sum up, the intelligent network card system and error detection method with error detection function provided by the present invention use the parity check detection module, the system error detection module, and the corrected memory detection module to respectively detect The parity check error information, system error information and correction memory error information of the processing chip are measured, and the parity check storage unit, the system error storage unit and the correction memory storage unit are used to respectively store the parity check error information, system error information and correction Memory error information, compared with the prior art, the present invention can normally and stably record the parity check error information, system error information and correct memory error information that will cause the processing chip failure to work normally, and can store the above error information sent to the baseboard management controller of the host system, and can be restarted independently relative to the host system, so that the error storage module clears the above error information until the parity check detection module, system error detection module and correction memory detection module After the test module fails to detect the above error information, the intelligent network card system with error detection function can operate normally.

In addition, if the parity detection module, the system error detection module and the correction memory detection module continue to detect the above error information, the smart device with error detection function provided by the preferred embodiment of the present invention The network card system and the error detection method will repeat the steps of detection, transmission, storage, and restart until the parity detection module, the system error detection module and the correction memory detection module do not detect After the above error information is received, the iNIC system with error detection function can operate normally.

Through the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the patent application for the present invention.

1: Intelligent network card system with error detection function 11: Process Wafer 111: Parity detection module 112: System error detection module 113:Fix memory detection module 114: The first communication module 12:Complex programmable logic device 121: Receiving module 122: Error storage module 1221: parity storage unit 1222: System error storage unit 1223: Fix memory storage unit 123: Second communication module 2: Host system 21: Baseboard Management Controller

The first figure shows the block diagram of the intelligent network card system with error detection function provided by the preferred embodiment of the present invention; and The second figure is a flowchart showing the error detection method provided by the preferred embodiment of the present invention.

1: Intelligent network card system with error detection function

11: Process Wafer

111: Parity detection module

112: System error detection module

113:Fix memory detection module

114: The first communication module

12:Complex programmable logic device

121: Receiving module

122: Error storage module

1221: parity storage unit

1222: System error storage unit

1223: Fix memory storage unit

123: Second communication module

2: Host system

21: Baseboard Management Controller

Claims (5)

An intelligent network card system with error detection function is externally connected to a host system and includes: A processed wafer, comprising: a parity detection module, which is used to detect a parity error information of the processing chip; A system error detection module is used to detect system error information of the processing chip; a correction memory detection module for detecting error information of a correction memory of the processing chip; and A first communication module is electrically connected to the parity detection module, the system error detection module and the correction memory detection module for detecting the parity error information, When at least one of the system error information and the modified memory detection module is used, at least one of the above-mentioned parity error information, the system error information and the modified memory detection module is sent; and A complex programmable logic device electrically connected to the processing chip, comprising: A receiving module, electrically connected to the first communication module, for receiving at least one of the parity error information, the system error information and the corrected memory detection module: An error storage module is electrically connected to the receiving module and includes: a parity storage unit for storing the parity error information; a system error storage unit for storing the system error information; and a correction memory storage unit for storing the correction memory error information; and A second communication module, electrically connected to the error storage module, for transmitting at least one of the above-mentioned parity error information, the system error information and the corrected memory detection module to the host One of the systems is a baseboard management controller; Wherein, after the baseboard management controller receives and stores at least one of the above-mentioned parity error information, the system error information, and the corrected memory detection module, it sends a clear signal to enable the smart network card system to be protected. After operatively restarting independently, the error storage module clears at least one of the above-mentioned parity error information, the system error information and the corrected memory detection module, so as to make the smart network card system operate normally. The intelligent network card system with error detection function as described in claim 1, wherein the first communication module is electrically connected to the receiver by using a Serial General Purpose Input/Output (SGPIO) interface mod. The intelligent network card system with error detection function as described in claim 1, wherein the second communication module is an I2C module. The smart network card system with error detection function as described in claim 1, wherein the second communication module is electrically connected to the baseboard management control of the host system by using a Power Management Bus (PMBUS) device. An error detection method is implemented by using the intelligent network card system with error detection function as described in claim 1, and includes the following steps: (a) Using the parity detection module, the system error detection module and the correction memory detection module to detect the parity error information, the system error information and the correction memory error at least one of the information; (b) using the first communication module to transmit at least one of the above-mentioned parity error information, the system error information and the corrected memory error information; (c) using the receiving module to receive at least one of the above-mentioned parity error information, the system error information and the corrected memory error information; (d) use the error storage module to store at least one of the above-mentioned parity error information, the system error information and the corrected memory error information; (e) using the second communication module to transmit at least one of the parity error information, the system error information and the corrected memory error information to the baseboard management controller; (f) cause the iNIC system to reboot individually; (g) using the error storage module to receive the clear signal, and clear at least one of the above-mentioned parity error information, the system error information and the correction memory detection module.

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