TWI738434B - 多晶片封裝製程方法 - Google Patents

多晶片封裝製程方法 Download PDF

Info

Publication number
TWI738434B
TWI738434B TW109125166A TW109125166A TWI738434B TW I738434 B TWI738434 B TW I738434B TW 109125166 A TW109125166 A TW 109125166A TW 109125166 A TW109125166 A TW 109125166A TW I738434 B TWI738434 B TW I738434B
Authority
TW
Taiwan
Prior art keywords
chip
layer
pads
production
pad
Prior art date
Application number
TW109125166A
Other languages
English (en)
Other versions
TW202205450A (zh
Inventor
林柏全
Original Assignee
禾瑞亞科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 禾瑞亞科技股份有限公司 filed Critical 禾瑞亞科技股份有限公司
Priority to TW109125166A priority Critical patent/TWI738434B/zh
Priority to CN202010948169.5A priority patent/CN113972176A/zh
Priority to US17/034,221 priority patent/US11587923B2/en
Application granted granted Critical
Publication of TWI738434B publication Critical patent/TWI738434B/zh
Publication of TW202205450A publication Critical patent/TW202205450A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

本發明為有關一種多晶片封裝製程方法，係於封裝載板於固晶區之至少一側邊分別設有外接引腳，並於固晶區處固設有第一晶片、第二晶片，且第一晶片、第二晶片分別包含有內部電路之電晶體層、複數金屬層、複數VIA層及焊墊層等，而第一晶片於製程中可依據第二晶片的不同設計變化，進行至少一層之金屬層、VIA層與複數虛設焊墊的設計修改，並於進行封裝前測試之後再對第一晶片、第二晶片進行晶粒切割及黏晶、打線、封裝及封裝後測試，以成型車用之多晶片，達到第一晶片僅需修改至少一層或一層以上的層面，即可配合第二晶片設計變化進行多晶片封裝製程之目的。

Description

多晶片封裝製程方法
本發明係提供一種多晶片封裝製程方法，尤指行車電腦之晶片設計製作，透過封裝載板上之第一晶片上固設有第二晶片，第一晶片可依據第二晶片的不同設計供進行所需的至少一層或一層以上的層面修改，即可進行車用晶片設計、封裝，而達到節省設計經費、方便加工、製作之目的。
按，一般行車用電腦使用之車用晶片，大都採用四方無引腳狀(QFN)封裝方式的之車用晶片，且此種型式的車用晶片在設計時為了堆疊二顆晶片(請同時參閱第五、六、七圖所示)，而位於上方之上方晶片A的製作為依據下列各步驟實施：
(E01)上方晶片A基功能設計；(E02)電晶體層製作；(E03)第一金屬層製作；(E04)第一VIA層製作；(E05)第二金屬層製作；(E06)第二VIA層製作；(E07)第三金屬層製作；(E08)第三VIA層製作；(E09)第四金屬層製作；(E10)焊墊層製作；(E11)封裝前測試；暫時完成上方晶片A之製作，並進行下方晶片B之製作，係依據下列各步驟實施：
(F01)下方晶片基本功能設計；(F02)電晶體層 製作；(F03)第一金屬層製作；(F04)第一VIA層製作；(F05)第二金屬層製作；(F06)第二VIA層製作；(F07)第三金屬層製作；(F08)第三VIA層製作；(F09)第四金屬層製作；(F10)焊墊層製作；(F11)線路重新佈局〔RDL〕設計；(F12)第一層聚合物製作；(F13)重佈線金屬層製作；(F14)第二層聚合物製作；(F15)球下金屬層製作；(F16)封裝前測試；(E12)上方晶片A固設於上述步驟(E01)~(E11)製作的下方晶片B上；(E13)晶粒切割及黏晶；(E14)打線；(E15)封裝；(E16)封裝後測試〔FT〕；(E17)完成車用晶片之製作。
但上方晶片A與下方晶片B係不同廠商所生產製作，因不同廠商所製造的晶片A、B其線路、焊接墊腳位等設計配置的方式均不同、相鄰間距W1、W2亦有差距，而下方晶片B的焊墊B2必須配合上方晶片A的焊墊A2進行預設線路的佈局、配置及焊墊腳位的調整等，但若欲更換不同廠商製造的上方晶片A時，下方晶片B的線路佈局、配置及焊墊腳位等都必須重新設計、調整，封裝完成後的車用晶片又必須重新進行測試，相當耗時費工、極不符合經濟效益，則如何解決目前車用晶片焊接引線設置，其於進行封裝時容易重疊、接觸而導致短路、失敗之問題與困擾，且欲更換所使用的堆疊晶片時，必須進行線路佈局、焊接引線等重新設計、調整之麻煩與缺失。
再者，該上方晶片A與下方晶片B在堆疊製作時，其位於上方晶片A的焊接引線A1(Bonding Wire)必須注意角度 、不同訊號的焊接引線A1之間不能交錯、位於上方晶片A與下方晶片B的焊接引線A1、B1必須形成高度差、不能產生重疊接觸，否則會有短路的情況，但在進行封裝製程時因封裝壓力、膠體模流等因素，相當容易導致鄰近的焊接引線A1、B1下沉、彎區或偏移等，而形成焊接引線A1、B1發生重疊、接觸的短路現象(如第五、六圖之左上角及右下角位置，以環圈標示處所示)，造成車用晶片封裝失敗、不能使用的問題，亦造成產品不良率提升之缺失，則為了保持二晶片A、B焊接引線A1、B1形成高度差，導致車用晶片封裝後具有較高的厚度，即不易符合電子產品輕、薄、短、小的設計理念訴求，則習知上方晶片A、下方晶片B在設計、製作時必須依據不同線路、焊接墊腳位等而重新設計各金屬層、各VIA層及焊墊層等設計之麻煩與缺失，更換不同廠商製作之上方晶片A時，原有的下方晶片B即形成無法應用的庫存，導致製作成本增加，且重新設計下方晶片B的線路佈局，重新製作不同的下方晶片B以配合不同廠商之上方晶片A，亦必須支付重新設計下方晶片B的費用，更不符合經濟效益，即為從事此行業之相關廠商所亟欲研究改善之方向所在者。
故，發明人有鑑於上述之問題與缺失，乃搜集相關資料，經由多方評估及考量，並以從事於此行業累積之多年經驗，經由不斷研發及修改，始設計出此種可解決車用晶片的設計、製造時的缺失的四方平面封裝形式之車用晶片製程方法之發明專利誕生者。
本發明之主要目的乃在於該四方平面封裝之多晶片，係於封裝載板於固晶區之至少一側邊分別設有外接引腳，並於固晶區處固設具 有內部電路之第一晶片、第二晶片，且第一晶片、第二晶片分別包含內部電路之電晶體層、複數金屬層、複數VIA層及焊墊層等，而第一晶片於製程中可依據第二晶片的不同設計變化，進行至少一層之金屬層、VIA層與第一焊墊層的複數虛設焊墊之設計修改，並於進行封裝前測試之後，再對第一晶片、第二晶片進行晶粒切割及黏晶、打線、封裝及封裝後測試，以成型車用之多晶片，達到第一晶片僅需修改至少一層或一層以上的層面，即可配合第二晶片設計變化進行多晶片封裝製程之目的。
本發明之次要目乃在於該第一晶片之內部電路係包含電晶體層、複數金屬層及複數VIA層，其各金屬層上分別設有呈X軸向或Y軸向之線路，且各VIA層為設置於上、下二相鄰的金屬層之間，並具有用以連接上、下二相鄰金屬層的線路之導通孔，而該第一晶片之第一焊墊層係於內部電路的至少一側邊透過複數線路依序電性連設有複數輸入及輸出單元、複數第一焊墊，並於內部電路的至少一側邊與複數輸入及輸出單元之間設有複數虛設焊墊，該第一晶片之內部電路設有利用複數金屬層的預設線路分別電性連接於內部電路之電晶體層、第一焊墊層之各虛設焊墊、各輸入及輸出單元各、各第一焊墊，再於第一晶片的內部電路之電晶體層上固設第二晶片，以進行後續之晶粒切割及黏晶、打線、封裝與測試等製程之步驟。
本發明之另一目乃在於該第一晶片之內部電路係包含電晶體層、複數金屬層及複數VIA層，其各金屬層上分別設有呈X軸向或Y軸向之線路，且各VIA層為設置於上、下二相鄰的金屬層之間，並具有用以連接上、下二相鄰金屬層的線路之導通孔，則該第一晶片之第一焊墊 層係於內部電路的至少一側邊透過複數線路依序連設有複數輸入及輸出單元、複數第一焊墊，且於複數輸入及輸出單元與第一焊墊之間設有複數虛設焊墊，該第一晶片之內部電路設有利用複數金屬層的預設線路分別電性連接於電晶體層、第一焊墊層之各輸入及輸出單元、各虛設焊墊及各第一焊墊，即可於第一晶片的內部電路之電晶體層上固設第二晶片，以進行後續之晶粒切割及黏晶、打線、封裝與測試等製程步驟。
本發明之再一目的乃在於該第一晶片的內部電路上所固設之第二晶片，若更換為不同廠商製作之第二晶片時，只需針對第一晶片的最上方至少一層之第四金屬層、第四VIA層、第五金屬層及第一焊墊層的複數第一焊墊與複數虛設焊墊層等進行修改，而第一晶片位於第四金屬層以下之其它各層面並不需進行修改，則可降低重新進行線路佈局設計的費用，節省製程時間，而具有省時、省工、可更符合經濟效益等之功效。
1:封裝載板
10:固晶區
11:外接引腳
2:晶片
21:第一晶片
211:內部電路
212:輸入及輸出單元
213:第一焊墊
214:虛設焊墊
215:第一導線
216:線路
217:導通孔
218:隔離封圈結構
22:第二晶片
221:第二焊墊
2211:第二導線
A:晶片
A1:焊接引線
A2:焊墊
B:晶片
B1:焊接引線
B2:焊墊
W1:間距
W2:間距
〔第1圖〕係為本發明多晶片之製作流程圖(一)。
〔第2圖〕係為本發明多晶片之製作流程圖(二)。
〔第3圖〕係為本發明多晶片較佳實施例之晶片俯視圖。
〔第4圖〕係為本發明多晶片另一實施例之晶片俯視圖。
〔第5圖〕係為習知車用晶片之製作流程圖(一)。
〔第6圖〕係為習知車用晶片之製作流程圖(二)。
〔第7圖〕係為習知車用晶片之側視圖。
為達成上述目的與功效，本發明所採用之技術手段及其構造、實施之方法等，茲繪圖就本發明之較佳實施例詳加說明其特徵與功能如下，俾利完全瞭解。
請參閱第一、二、三、四圖所示，係為本發明多晶片之製作流程圖(一)、多晶片之製作流程圖(二)、多晶片較佳實施例之晶片俯視圖、多晶片另一實施例之晶片俯視圖，由各圖中所示可以清楚看出，本發明之堆疊式多晶片，在實施例中，該多晶片結構為四方平面封裝型式，實際實施時不以此為限，該多晶片封裝之製程方法，其中：
該多晶片係包括封裝載板1及至少二個或二個以上之晶片2，該封裝載板1係包括位於中央位置之固晶區10，其四側邊分別設有複數外接引腳11可供電性連接至外部預設電子電路，而該至少二個或二個以上之晶片2係包括第一晶片21及第二晶片22，該第一晶片21設有內部電路211(Core)，且第一晶片21為固設於封裝載板1之固晶區10處，該第一晶片21係包含內部電路211之電晶體層、複數金屬層、分別位於任二相鄰金屬層之間的複數VIA層及具有複數第一焊墊213、複數虛設焊墊214之第一焊墊層等，其各金屬層上分別設有呈X軸向或Y軸向之線路216，且各VIA層為設置於任二上、下相鄰的金屬層之間，各VIA層並具有貫通之導通孔217用以連接任二上、下相鄰金屬層的線路216；則於該第一晶片21之內部電路211的至少一側邊可依序設有複數輸入及輸出單元212、複數第一焊墊213，而該內部電路211的至少一側邊與複數輸入及輸出單元212之間設有複數虛設焊墊(Dummy Pads)214，該第一晶片21之內部 電路211可利用各金屬層的各線路216分別電性連接於電晶體層、第一焊墊層之各輸入及輸出單元各212、各第一焊墊213、各虛設焊墊214等，再於第一晶片21的內部電路之電晶體層上固設第二晶片22，以供執行後續之晶粒切割及黏晶、打線、封裝與測試等製程步驟，而成型為車用之多晶片。
另，該第一晶片21位於頂部之第一焊墊層，亦可於內部電路211的至少一側邊可依序設有複數輸入及輸出單元212及複數第一焊墊213，再於複數輸入及輸出單元212與複數第一焊墊213之間設有複數虛設焊墊(Dummy Pads)214，該第一晶片21之內部電路211(Core)可利用各金屬層的線路216分別電性連接於電晶體層、第一焊墊層之各輸入及輸出單元212、各虛設焊墊214及各第一焊墊213，即可於第一晶片21的電晶體層上固設第二晶片22，以進行後續之晶粒切割及黏晶、打線、封裝與測試等製程之步驟。
該第一晶片21之內部電路211，係可依據下列各步驟實施製作：
(C01)電晶體層製作。
(C02)第一層金屬層製作。
(C03)第一VIA層製作。
(C04)第二層金屬層製作。
(C05)第二VIA層製作。
(C06)第三層金屬層製作。
(C07)第三VIA層製作。
(C08)第四層金屬層製作。
(C09)第四VIA層製作。
(C10)第五層金屬層製作。
(C11)第一焊墊層的複數輸入及輸出單元212、複數第一焊墊213與複數虛設焊墊214之製作，其中該部驟(C08)~(C11)係針對第二晶片22的複數第二焊墊221之配置，進行修改至少一層之金屬層、VIA層與複數虛設焊墊214的設計變更所製作而成；最後再進行：
(C12)封裝前測試(CP)。
上述該第一晶片21之製作步驟(C01)~(C08)，係針對第一晶片21之基本功能設計進行製作而成，且製程之步驟(C08)~(C11)係針對不同第二晶片22的複數第二焊墊221有不同的設計配置時，可針對至少一層金屬層、VIA層與第一焊墊層之複數虛設焊墊214進行設計變更之修改，而不必對步驟(C01)~(C07)的任一層面進行修改。
上述該第一晶片21係於內部電路211之電晶體層固設第二晶片22，而該第二晶片22包括有電晶體層、複數金屬層、分別位於任二相鄰金屬層之間的複數VIA層及具有複數第二焊墊221之第二焊墊層等，且該第二晶片22為可依據下列各步驟實施製作：
(D01)電晶體層製作。
(D02)第一層金屬層製作。
(D03)第一VIA層製作。
(D04)第二層金屬層製作。
(D05)第二VIA層製作。
(D06)第三層金屬層製作。
(D07)第三VIA層製作。
(D08)第四層金屬層製作。
(D09)第二焊墊層之複數第二焊墊221製作。
(D10)封裝前測試。
(D11)將第二晶片22固設於第一晶片21之內部電路211的電晶體層上，並執行以下步驟：
(D111)晶粒切割及黏晶。
(D112)打線。
(D113)封裝。
(D114)封裝後測試(FT)。
(D115)成型為車用晶片。
上述該第二晶片22之製作步驟(D01)~(D10)，係針對第二晶片22之基本功能設計進行製作而成。
再者，上述該第一晶片21之第一焊墊層於內部電路211的至少一側邊所設之複數第一焊墊213與各虛設焊墊(Dummy Pads)214間係可呈相互對位或相互錯位方式、分別設置於複數輸入及輸出單元212的二側邊處，再由複數第一焊墊213處分別利用第一導線215電性連接至封裝載板1上相對應之各外接引腳11處；而該第一晶片21係包括內部電路211之電晶體層、複數金屬層、複數VI A層及第一焊墊層等複數層面，並於第一焊墊層設有複數虛設焊墊214，且各金屬層上分別設有呈X軸向或Y軸向之線路，且各VIA層為分別設置於任二上、下相鄰金屬層之間，各VIA層並具有導通孔217可用以連接任二上、下相鄰金屬層間之線路216，以供任二上、下相鄰金屬層間之線路216可分別透過各VIA層之導通孔217呈電性導通。
另，該第一晶片21之第一焊墊層，係於內部電路211與二相鄰不同排列方向的輸入及輸出單元212之間，可分別設有複數虛設焊墊214，而第一晶片21則可於最上方二層或三層金屬層間分設置內部線路216，以供同一排列方向或二不同排列方向相鄰之複數虛設焊墊214間可分別利用線路216呈電性連接，且位於最上方二層金屬層間之VIA層為可具有複數導通孔217，可用以連接最上方二相鄰金屬層間之線路216，換句話說，各虛設焊墊214係透第一晶片21過最上方二層或三層金屬層以及VIA層所構成之內部線路216電性連接至另一虛設焊墊214，此另一虛設焊墊214係安置在一適當位置，用以藉第二導線2211連接至外接引腳11；藉由經由內部線路216電性連接的二個虛設焊墊214，使第二導線2211不會接近或碰觸到第一導線215；則可供第二晶片22之第二焊墊層的各第二焊墊221有設計上的變化時，只需修改第一晶片21位於最上方至少一層金屬層、VIA層、第一焊墊層的複數虛設焊墊214之設計變更，即可藉由增加或減少虛設焊墊214的數量設置，即可供第一晶片21與第二晶片22之間形成搭配適用，可供進行打線、封裝等製程，而不需變更第一晶片21位於第四金屬層以下各層面之線路216、複數導通孔217等設計，達到 設計、製作具有省時、省工及省成本之目的。
又，位於第一晶片21的第一焊墊層之複數輸入及輸出單元212二側分別設置之複數第一焊墊213及複數虛設焊墊214(或位於輸入及輸出單元212一側相鄰設置之複數第一焊墊213、複數虛設焊墊214)，分別相對應之各第一焊墊213與各虛設焊墊214係可呈相互對位排列、相互錯位(品字型)排列、直線式排列、斜線狀排列、弧線狀排列、前後排交錯狀或多排錯落狀排列等，各種不同的設置方式，僅需具有各第一焊墊213、各虛設焊墊214、各第二焊墊221及各外接引腳11之間，均不會與相鄰的各第一導線215、各第二導線2211發生相互接近、抵觸之功能即可，非因此即侷限本發明之專利範圍，舉凡利用其它修飾及等效結構變化等，均應同理包含於本發明之專利範圍內，合予陳明。
且該第一晶片21於內部電路211與複數第一焊墊213之間設有至少一個以上之隔離封圈結構218(Seal Ring)，而複數輸入及輸出單元212係可位於隔離封圈結構218上，並由內部電路211的至少一側分別利用線路216依序電性連接複數輸入及輸出單元212與複數第一焊墊213等，且該複數輸入及輸出單元212係作為訊號傳輸(輸入或輸出)作用而為習知技術，多設計作為阻抗匹配或靜電保護(ESD)等，為附加之電路，不為必要存在之電路，但在增加該複數輸入及輸出單元212電路時，會對整體觸控積體電路之電路配置產生影響，故予以補充說明；另，該第一晶片21之複數輸入及輸出單元212之細部功能，非為本發明要點，故不再贅述。
且該第二晶片22係可為記憶體晶片(如揮發性記憶體、非揮發性記憶體或快閃記憶體)、應用處理器晶片〔如中央處理器(CPU)〕、圖形處理器、數位訊號處理器、密碼處理器、微處理器或微控制器等各種型式晶片。
上述之封裝載板1、至少二個或二個以上晶片2之第一晶片21、第二晶片22於進行組裝加工時，係於封裝載板1的固晶區10處供堆疊狀之第一晶片21、第二晶片22電性固接，則於第二晶片22表面上至少一組第二焊墊221、可利用同一條第二導線2211分別電性連接至相對應之虛設焊墊214及封裝載板1的相對應之各外接引腳11處；亦可於第二晶片22表面至少一組第二焊墊221分別利用第二導線2211電性連接至相對應之虛設焊墊214，再由相對應之另一虛設焊墊214處分別利用另一條第二導線2211電性連接至封裝載板1的相對應之外接引腳11處，以完成封裝載板1、晶片2之第一晶片21與第二晶片22間的打線接合作業；後續即可再透過四方無引腳(QFN)封裝加工作業，將封裝載板1、第一晶片21、第二晶片22成型為四方無引腳形式之車用多晶片。
在車用之多晶片的製程中，第一晶片21與第二晶片22通常都是由不同廠商所製造，而第一晶片21必須配合第二晶片22的複數第二焊墊221之腳位的變化設計，當設計有需要更換不同廠商之第二晶片22時，第一晶片21只需要修改工程變更命令(ECO，Engineer Change Order)最上方之至少一層之金屬線路(Metal)層或VIA層之光罩設計圖案即可，並可使用原本的晶片( IC)製程，在同一個製程中完成更改，不需要用到重分佈線路製程(RDL)，並將相對應的虛設焊墊214及預設線路間的線路216佈局配置予以改變更換，藉以配合不同第二晶片22的複數第二焊墊221腳位設計變化即可，並不必變化第一晶片21之第四金屬層下方其它各金屬層、各VIA層等各層面之原來設計模式、設計圖案之佈局及配置等，可解決使用不同廠商製造之第二晶片22時，第二晶片22表面至少一組第二焊墊221因腳位變化而與第一晶片21的各虛設焊墊214之間，所產生之打線接合的問題，則能節省第一晶片21重新設計電路佈局之繁索程序，以及有效節省製程時間、降低設計及製造成本，更符合經濟效益。
故本發明主要為針對車用之多晶片之進行設計，當車用之多晶片之第二晶片22更換為不同廠商製作，其複數第二焊墊221之腳位有所變化時，即可透過第一晶片21最上方的至少一層之金屬層、VIA層及第一焊墊層之虛設焊墊214層等之修改、變更，而不需整個第一晶片21的複數金屬層、複數VIA層及焊墊等所有層面均進行變更設計、重新製作，則可使第一晶片21可配合第二晶片22的更換，對第一晶片21進行簡單的線路佈局修改即可為保護重點，惟，以上所述僅為本發明之較佳實施例而已，非因此即侷限本發明之專利範圍，故舉凡運用本發明之說明書及圖式內容等所為簡易修飾及等效結構變化，均應同理包含於本發明之專利範圍內，合予陳明。
綜上所述，本發明上述多晶片封裝製程方法於實際實施應用時，為確實能達到其功效及目的，故本發明為一實用性優異之發明，為符合發明專利之申請要件，爰依法提出申請，盼 審委早日賜准本案，以 保障發明人之辛苦研發創設，倘若 鈞局暨貴審委有任何稽疑，請不吝來函指示，發明人定當竭力配合，實感德便。

Claims (7)

  1. 一種多晶片封裝製程方法，該多晶片係包括封裝載板及至少二個或二個以上呈堆疊之晶片，該封裝載板係包含有固晶區及位於該固晶區之至少一側邊之複數外接引腳，且該固晶區係供固設該至少二個或二個以上呈堆疊之晶片，該至少二個或二個以上呈堆疊之晶片係包括第一晶片及第二晶片，而該第一晶片係包含有內部電路之電晶體層、複數金屬層、複數VIA層以及具有複數第一焊墊與複數虛設焊墊之第一焊墊層；該第二晶片為包含有電晶體層、複數金屬層、複數VIA層以及具有複數第二焊墊之第二焊墊層，並於該第一晶片、該第二晶片進行封裝前測試後，執行晶粒切割及黏晶、打線、封裝、封裝後測試之步驟，以成型為車用晶片，其中該第一晶片之製作為依據下列各步驟實施製作：(C01)電晶體層製作；(C02)第一層金屬層製作；(C03)第一VIA層製作；(C04)第二層金屬層製作；(C05)第二VIA層製作；(C06)第三層金屬層製作；(C07)第三VIA層製作；(C08)第四層金屬層製作；(C09)第四VIA層製作；(C10)第五層金屬層製作； (C11)第一焊墊層的複數第一焊墊與複數虛設焊墊之製作；其中該步驟(C08)~(C11)係針對該第二晶片的複數第二焊墊之配置，進行修改至少一層之金屬層、VIA層與複數虛設焊墊的設計變更製作而成。
  2. 如申請專利範圍第1項所述之多晶片封裝製程方法，其中該第一晶片之製作步驟(C01)~(C08)係針對第一晶片之基本功能設計進行製作而成。
  3. 如申請專利範圍第1項所述之多晶片封裝製程方法，其中該第一晶片係於任二相鄰金屬層之間分別設有VIA層，其各金屬層上分別設有呈X軸向或Y軸向之線路，而該第一晶片之第一焊墊層係於內部電路的至少一側邊透過複數線路依序電性連設有複數輸入及輸出單元與複數第一焊墊，並於內部電路的至少一側邊與複數輸入及輸出單元之間設有複數虛設焊墊。
  4. 如申請專利範圍第3項所述之多晶片封裝製程方法，其中該第一晶片之內部電路利用複數線路分別電性連接於電晶體層、第一焊墊層之各虛設焊墊、各輸入及輸出單元、各第一焊墊，且各VIA層分別設有連接任二相鄰金屬層間的線路之導通孔。
  5. 如申請專利範圍第1項所述之多晶片封裝製程方法，其中該第一晶片係於任二相鄰金屬層之間分別設有VIA層，其各金屬層上分別設有呈X軸向或Y軸向之線路，則該第一晶片之第一焊墊層係於內部電路的至少一側邊透過複數線路依序電性連設有複數輸入及輸出單元與複數第一焊墊，且於複數輸入及輸出單元與複數第一焊墊之間 設有複數虛設焊墊。
  6. 如申請專利範圍第1項所述之多晶片封裝製程方法，其中該第一晶片之內部電路利用複數線路分別電性連接於電晶體層、第一焊電層之各輸入及輸出單元、各虛設焊墊及各第一焊墊，則各VIA層分別設有連接任二相鄰金屬層間的線路之導通孔。
  7. 如申請專利範圍第1項所述之多晶片封裝製程方法，其中該第二晶片為包含有電晶體層、複數金屬層、位於任二相鄰金屬層之間的複數VIA層以及具有複數第二焊墊之第二焊墊層，該第二晶片之製作為依據下列各步驟實施：(D01)電晶體層製作；(D02)第一層金屬層製作；(D03)第一VIA層製作；(D04)第二層金屬層製作；(D05)第二VIA層製作；(D06)第三層金屬層製作；(D07)第三VIA層製作；(D08)第四層金屬層製作；(D09)第二焊墊層之複數第二焊墊製作。
TW109125166A 2020-07-24 2020-07-24 多晶片封裝製程方法 TWI738434B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW109125166A TWI738434B (zh) 2020-07-24 2020-07-24 多晶片封裝製程方法
CN202010948169.5A CN113972176A (zh) 2020-07-24 2020-09-10 多芯片封装制程方法
US17/034,221 US11587923B2 (en) 2020-07-24 2020-09-28 Multichip package manufacturing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109125166A TWI738434B (zh) 2020-07-24 2020-07-24 多晶片封裝製程方法

Publications (2)

Publication Number Publication Date
TWI738434B true TWI738434B (zh) 2021-09-01
TW202205450A TW202205450A (zh) 2022-02-01

Family

ID=78777881

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109125166A TWI738434B (zh) 2020-07-24 2020-07-24 多晶片封裝製程方法

Country Status (3)

Country Link
US (1) US11587923B2 (zh)
CN (1) CN113972176A (zh)
TW (1) TWI738434B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140045326A1 (en) * 2011-10-13 2014-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a semiconductor device having a post-passivation interconnect structure
US9070570B2 (en) * 2012-12-20 2015-06-30 SK Hynix Inc. Stack packages having token ring loops
US9129850B2 (en) * 2011-12-07 2015-09-08 Ps4 Luxco S.A.R.L. Semiconductor device manufacturing method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090043898A (ko) * 2007-10-30 2009-05-07 삼성전자주식회사 스택 패키지 및 그 제조 방법, 및 스택 패키지를 포함하는카드 및 시스템
KR101604605B1 (ko) * 2009-09-24 2016-03-21 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US8390103B2 (en) * 2010-07-12 2013-03-05 Analog Devices, Inc. Apparatus for integrated circuit packaging
KR102247916B1 (ko) * 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
KR102579877B1 (ko) * 2016-11-22 2023-09-18 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10741537B2 (en) * 2017-01-18 2020-08-11 Taiwan Semiconductor Manufacturing Coompany Ltd. Semiconductor structure and manufacturing method thereof
KR102438456B1 (ko) * 2018-02-20 2022-08-31 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR102149387B1 (ko) * 2019-02-13 2020-08-28 삼성전기주식회사 전자 소자 모듈

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140045326A1 (en) * 2011-10-13 2014-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a semiconductor device having a post-passivation interconnect structure
US9129850B2 (en) * 2011-12-07 2015-09-08 Ps4 Luxco S.A.R.L. Semiconductor device manufacturing method
US9070570B2 (en) * 2012-12-20 2015-06-30 SK Hynix Inc. Stack packages having token ring loops

Also Published As

Publication number Publication date
US20220028851A1 (en) 2022-01-27
US11587923B2 (en) 2023-02-21
CN113972176A (zh) 2022-01-25
TW202205450A (zh) 2022-02-01

Similar Documents

Publication Publication Date Title
JP2016535463A (ja) 垂直コラムを有するオーバラップ形スタック化ダイパッケージ
TWI308282B (en) Method for designing chip package by re-using existing mask designs
JPH07111971B2 (ja) 集積回路装置の製造方法
US20220384376A1 (en) Package structure of semiconductor device with improved bonding between the substrates
TWI584425B (zh) 扇出型晶圓級封裝結構
US6657910B2 (en) Semiconductor device having internal power terminals including a positive power terminal and a negative power terminal
TWI738434B (zh) 多晶片封裝製程方法
CN106206557B (zh) 硅中介层
TW201640635A (zh) 封裝結構及其製作方法
US7867829B2 (en) Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device
US7489519B1 (en) Power and ground ring snake pattern to prevent delamination between the gold plated ring and mold resin for wirebond PBGA
US9245857B2 (en) Chip package
TWI673845B (zh) 薄膜覆晶封裝結構
US11705427B2 (en) Mirror-image chips on a common substrate
TW201724432A (zh) 具改良佈線結構之球柵陣列封裝結構及其基板
TWI771718B (zh) 多晶片封裝結構
TW202205551A (zh) 多晶片封裝結構（一）
US20080303177A1 (en) Bonding pad structure
JPH04218918A (ja) 半導体装置及びその製造方法
TWI766532B (zh) 可撓性線路基板
US20080078995A1 (en) Chip structure
US11929340B2 (en) Arrangement of power-grounds in package structures
TWI714865B (zh) 晶圓結構
US9991196B2 (en) Printed circuit board and method of fabricating an element
TW202407900A (zh) 承載結構