TWI738272B - Data arrangement method of flash memory, flash memory storage device and flash memory control circuit unit - Google Patents

Abstract

A data arrangement method of a flash memory, a flash memory storage device and a flash memory control circuit unit are provided. The method can be applied to a flash memory, an embedded memory device or a solid-state disk with a three-dimensional (3D) structure. The method includes: executing a background garbage collection operation in a background mode; receiving at least one write command from a host when the background garbage collection operation is not completed, suspending the background garbage collection operation and exiting the background mode; executing the at least one write command; and entering the background mode and continued executing the background garbage collection operation after completing the at least one write command. Therefore, execution efficiency of the write command in the foreground mode can be optimized.

Description

Flash memory data sorting method, flash memory storage device and flash memory control circuit unit

The present invention relates to a memory management technology, and more particularly to a flash memory data sorting method, a flash memory storage device and a flash memory control circuit unit.

Digital cameras, mobile phones and MP3 players have grown rapidly in the past few years, which has led to a rapid increase in consumer demand for storage media. Because rewritable non-volatile memory modules (for example, flash memory) have the characteristics of non-volatile data, power saving, small size, fast reading and writing speed, and no mechanical structure, Therefore, it is suitable for being built in various portable multimedia devices as exemplified above. Therefore, the flash memory industry has become a very popular part of the electronics industry in recent years.

The memory storage device based on flash memory cannot overwrite the existing storage data, and needs to release the physical erasure unit through garbage collection operation on the storage data. Generally speaking, in the process of performing garbage collection, multiple physical erasing units are selected as the source physical erasing unit, and one physical erasing unit is selected as the target physical erasing unit. Then, the valid data in the source physical erasing unit is moved (or copied) to the target physical erasing unit, and the source physical erasing unit is erased to release the space occupied by the invalid data of the source physical erasing unit. However, before the target entity erase unit is turned off (that is, it is set to no longer be able to write any data), every write command of the host system must be garbage collected. As a result, the period during which garbage collection is performed will affect the operating efficiency of the write command of the host system in the dirty state of the flash memory storage device, which in turn causes the delay of the flash memory storage device. Therefore, how to reduce the delay caused by the garbage collection operation, thereby improving the operating efficiency of the flash memory storage device, is a topic of concern to those skilled in the art.

The present invention provides a flash memory data sorting method, a flash memory storage device and a flash memory control circuit unit, which can dynamically select the source entity erasing unit of the garbage collection operation and dynamic management to perform the garbage collection operation Time to improve the execution efficiency of write instructions.

An exemplary embodiment of the present invention provides a flash memory data organization method, which is used in a memory storage device including a rewritable non-volatile memory module, and the flash memory data organization method includes: The background mode executes a background garbage collection operation; receives at least one write instruction from the host system when the background garbage collection operation is not completed, suspends the background garbage collection operation and exits the background mode; executes the write instruction; and After completing the execution of the at least one write instruction, enter the background mode and continue to perform the background garbage collection operation.

In an embodiment of the present invention, the method further includes: when performing the background garbage collection operation, copying valid data of one or more source entity erasing units to the target entity erasing unit; erasing the One or more source entity erasing units and releasing the one or more source entity erasing units as idle entity erasing units; and when the background garbage collection operation is suspended, the one or more source entities are suspended The effective data of the erasing unit is copied to the target entity erasing unit, and the target entity erasing unit is retained and enters the foreground mode from the background mode to execute the at least one write command.

In an embodiment of the present invention, the step of performing the background garbage collection operation in the background mode includes: selecting one or more of the physical erasing units as valid counts corresponding to a plurality of physical erasing units The one or more source physical erasing units and the effective data of the one or more source physical erasing units are copied to the target physical erasing unit.

In an embodiment of the present invention, the step of executing the at least one write instruction includes: if a foreground garbage collection operation is performed during the execution of the at least one write instruction, corresponding to the physical erasing unit The latest effective count of selects one or more of the physical erasure units as the one or more source physical erasure units, and copies the effective data of the one or more source physical erasure units to The target entity erasing unit.

In an embodiment of the present invention, the background garbage collection operation and the foreground garbage collection operation share the same target entity erasing unit.

In an embodiment of the present invention, the first activation threshold for determining to perform the background garbage collection operation is greater than the second activation threshold for determining to perform the foreground garbage collection operation.

In an embodiment of the present invention, the step of entering the background mode and continuing to perform the background garbage collection operation after completing the execution of the at least one write instruction further includes: after completing the execution of the at least one write instruction, Enter the background mode after a predetermined time; execute the background garbage collection operation according to the latest effective count corresponding to the physical erasing unit, and select one or more of the physical erasing units as the one or more A source physical erasing unit, and copy valid data of the one or more source physical erasing units to the target physical erasing unit.

An exemplary embodiment of the present invention provides a flash memory storage device, including a connection interface unit, a rewritable non-volatile memory module, and a flash memory control circuit unit. The connection interface unit is used for coupling to the host system. The flash memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the flash memory control circuit unit is used to perform background garbage collection in a background mode operate. The flash memory control circuit unit is further configured to receive at least one write instruction from the host system when the background garbage collection operation is not completed, suspend the background garbage collection operation and exit the background mode. The flash memory control circuit unit is further used to execute the at least one write command. Moreover, the flash memory control circuit unit is further configured to enter the background mode after completing the execution of the at least one write instruction and continue to perform the background garbage collection operation.

In an embodiment of the present invention, the flash memory control circuit unit is further used for copying the effective data of one or more source entity erasing units to the target entity erasing when performing the background garbage collection operation unit. The flash memory control circuit unit is further used for erasing the one or more source physical erasing units and releasing the one or more source physical erasing units as idle physical erasing units. Moreover, the flash memory control circuit unit is further configured to suspend the copying of valid data of the one or more source physical erasing units to the target physical erasing unit when the background garbage collection operation is suspended, And reserve the target entity erasing unit and enter the foreground mode from the background mode to execute the at least one write command.

In an embodiment of the present invention, in the operation of performing the background garbage collection operation in the background mode, the flash memory control circuit unit is further configured to select the effective count corresponding to a plurality of physical erasing units. One or more of the physical erasing units are used as the one or more source physical erasing units, and valid data of the one or more source physical erasing units are copied to the target physical erasing unit.

In an embodiment of the present invention, in the operation of executing the at least one write instruction, if a foreground garbage collection operation is performed during the execution of the at least one write instruction, the flash memory control circuit The unit is further used for selecting one or more of the physical erasing units as the one or more source physical erasing units according to the latest effective count corresponding to the physical erasing unit, and combining the one or more The valid data of a plurality of source physical erasing units are copied to the target physical erasing unit.

In an embodiment of the present invention, the background garbage collection operation and the foreground garbage collection operation share the same target entity erasing unit.

In an embodiment of the present invention, the first activation threshold for determining to perform the background garbage collection operation is greater than the second activation threshold for determining to perform the foreground garbage collection operation.

In an embodiment of the present invention, after the execution of the at least one write command is completed, the background mode is entered and the background garbage collection operation is continued. The flash memory control circuit unit is further used for The background mode is entered after a predetermined time has elapsed after the completion of the execution of the at least one write instruction. Moreover, the flash memory control circuit unit is further configured to perform the background garbage collection operation according to the latest effective count corresponding to the physical erasing unit, and select one or more of the physical erasing units as The one or more source physical erasing units and the effective data of the one or more source physical erasing units are copied to the target physical erasing unit.

Example embodiments of the present invention provide a flash memory control circuit unit for controlling a flash memory storage device including a rewritable non-volatile memory module, and the flash memory control circuit unit includes a host Interface, memory interface and memory management circuit. The host interface is used for coupling to a host system. The memory interface is used for coupling to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The flash memory control circuit unit is used to perform a background garbage collection operation in a background mode. The flash memory control circuit unit is further configured to receive at least one write instruction from the host system when the background garbage collection operation is not completed, suspend the background garbage collection operation and exit the background mode. The flash memory control circuit unit is further used to execute the at least one write command. Moreover, the flash memory control circuit unit is further configured to enter the background mode after completing the execution of the at least one write instruction and continue to perform the background garbage collection operation.

In an embodiment of the present invention, the flash memory control circuit unit is further used for copying the effective data of one or more source entity erasing units to the target entity erasing when performing the background garbage collection operation unit. The flash memory control circuit unit is further used for erasing the one or more source physical erasing units and releasing the one or more source physical erasing units as idle physical erasing units. Moreover, the flash memory control circuit unit is further configured to suspend the copying of valid data of the one or more source physical erasing units to the target physical erasing unit when the background garbage collection operation is suspended, And reserve the target entity erasing unit and enter the foreground mode from the background mode to execute the at least one write command.

In an embodiment of the present invention, in the operation of performing the background garbage collection operation in the background mode, the flash memory control circuit unit is further configured to select the effective count corresponding to a plurality of physical erasing units. One or more of the physical erasing units are used as the one or more source physical erasing units, and valid data of the one or more source physical erasing units are copied to the target physical erasing unit.

In an embodiment of the present invention, in the operation of executing the at least one write instruction, if a foreground garbage collection operation is performed during the execution of the at least one write instruction, the flash memory control circuit The unit is further used for selecting one or more of the physical erasing units as the one or more source physical erasing units according to the latest effective count corresponding to the physical erasing unit, and combining the one or more The valid data of a plurality of source physical erasing units are copied to the target physical erasing unit.

In an embodiment of the present invention, the background garbage collection operation and the foreground garbage collection operation share the same target entity erasing unit.

In an embodiment of the present invention, the first activation threshold for determining to perform the background garbage collection operation is greater than the second activation threshold for determining to perform the foreground garbage collection operation.

In an embodiment of the present invention, after the execution of the at least one write command is completed, the background mode is entered and the background garbage collection operation is continued. The flash memory control circuit unit is further used for The background mode is entered after a predetermined time has elapsed after the completion of the execution of the at least one write instruction. Moreover, the flash memory control circuit unit is further configured to perform the background garbage collection operation according to the latest effective count corresponding to the physical erasing unit, and select one or more of the physical erasing units as The one or more source physical erasing units and the effective data of the one or more source physical erasing units are copied to the target physical erasing unit.

Based on the above, in the foreground garbage collection operation and the background garbage collection operation, the effective data of the source entity erasing unit can be moved (or copied) to the same target entity erasing unit. And in the foreground mode, when the number of free physical erasing units of the rewritable non-volatile memory module is not greater than the activation threshold, multiple source physical erasing units are selected based on the effective counts corresponding to multiple physical erasing units To perform garbage collection. And when the number of free physical erase units of the rewritable non-volatile memory module is greater than the activation threshold, the write command is executed. In other words, by dynamically selecting the source entity erasing unit of the garbage collection operation and dynamically managing the time for executing the garbage collection operation, the execution efficiency of the write instruction can be effectively improved.

Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit unit). Generally, the memory storage device is used together with the host system, so that the host system can write data to the memory storage device or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment. And FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another exemplary embodiment.

1 and 2, the host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 are all coupled to a system bus 110.

In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can write data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 is coupled to the I/O device 12 through the system bus 110. For example, the host system 11 can transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In this exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be coupled to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication Storage (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory. A memory storage device based on various wireless communication technologies such as a bulk storage device (for example, iBeacon). In addition, the motherboard 20 can also be coupled to a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. Type I/O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

In an exemplary embodiment, the host system mentioned is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, FIG. 3 is a schematic diagram of the host system and the memory storage device according to another exemplary embodiment. 3, in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for it. Various non-volatile memory storage devices such as SD card 32, CF card 33 or embedded storage device 34 are used. The embedded storage device 34 includes embedded MMC (eMMC) 341 and/or embedded Multi Chip Package (embedded Multi Chip Package, eMCP) storage device 342. The memory module is directly coupled to the host system. Embedded storage device on the substrate.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. 4, the memory storage device 10 (in this embodiment, flash memory storage device) includes a connection interface unit 402, a memory control circuit unit 404 (in this embodiment, flash memory control Circuit unit) and a rewritable non-volatile memory module 406.

The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 402. In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited to this, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 Standard, high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal flash memory (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 and the memory control circuit unit 404 can be packaged in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and perform data processing in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 Operations such as writing, reading, and erasing.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and used to store data written by the host system 11. The rewritable non-volatile memory module 406 may be a single level cell (SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell). Module), Multi Level Cell (MLC) NAND-type flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), and a third-level memory cell ( Triple Level Cell, TLC) NAND type flash memory module (that is, a flash memory module that can store 3 bits in a memory cell), Quad Level Cell (QLC) NAND type flash memory module Flash memory module (that is, a flash memory module that can store 4 bits in a memory cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate of each memory cell and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying the read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 can constitute a plurality of physical programming units, and these physical programming units can constitute a plurality of physical erasing units. Specifically, the memory cells on the same character line can form one or more physical programming units. If each memory cell can store more than two bits, the physical programming unit on the same character line can be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. The reliability of the physical programming unit.

In this exemplary embodiment, the physical programming unit is the smallest programming unit. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical sector (sector). If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors to store user data, and the redundant bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area can also include 8, 16, or more or less physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erasing unit contains one of the smallest number of memory cells to be erased. For example, the physical erasing unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404.

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control commands are burned into the read-only memory. When the memory storage device 10 is operating, these control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control commands of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of code (for example, the memory module is dedicated to storing system data). System area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store it in the rewritable non-volatile memory The control commands in the volume module 406 are loaded into the random access memory of the memory management circuit 502. After that, the microprocessor unit runs these control commands to perform data writing, reading, and erasing operations.

In addition, in another exemplary embodiment, the control commands of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cell or the memory cell group of the rewritable non-volatile memory module 406. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erasing circuit is used to issue an erasing command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit is used for processing data to be written to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding writing and reading. Take and erase operations. In an exemplary embodiment, the memory management circuit 502 can also send other types of command sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

The host interface 504 is coupled to the memory management circuit 502. The memory management circuit 502 can communicate with the host system 11 through the host interface 504. The host interface 504 can be used to receive and identify commands and data sent by the host system 11. For example, the commands and data sent by the host system 11 can be sent to the memory management circuit 502 through the host interface 504. In addition, the memory management circuit 502 can transmit data to the host system 11 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited to this. The host interface 504 can also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, and MS standards. , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406. In other words, the data to be written into the rewritable non-volatile memory module 406 is converted into a format acceptable by the rewritable non-volatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 needs to access the rewritable non-volatile memory module 406, the memory interface 506 will send the corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (for example, changing read Take the voltage level or perform garbage collection operations, etc.) corresponding to the sequence of instructions. These command sequences are generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506, for example. These command sequences can include one or more signals, or data on the bus. These signals or data may include script codes or program codes. For example, in the read command sequence, the read identification code, memory address and other information will be included.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

The error checking and correcting circuit 508 is coupled to the memory management circuit 502 and used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 will generate a corresponding error correcting code (ECC) for the data corresponding to the write command. And/or error detecting code (EDC), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error correction code and/or error check code to the rewritable non-volatile In the memory module 406. After that, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will read the error correction code and/or error check code corresponding to the data at the same time, and the error check and correction circuit 508 Based on this error correction code and/or error check code, error checking and correction operations will be performed on the read data.

The buffer memory 510 is coupled to the memory management circuit 502 and used to temporarily store data and commands from the host system 11 or data from the rewritable non-volatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and used to control the power of the memory storage device 10.

In an exemplary embodiment, the rewritable non-volatile memory module 406 of FIG. 4 is also called a flash memory module, and the memory control circuit unit 404 is also called for controlling the flash memory The flash memory controller of the physical module. In an exemplary embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. 6, the memory management circuit 502 can logically group the physical units 610(0) to 610(B) of the rewritable non-volatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610(0)~610(A) in the storage area 601 are used to store data, and the physical units 610(A+1)~610(B) in the replacement area 602 are used to replace the storage area 601 Damaged physical unit. For example, if the data read from a certain physical unit contains too many errors to be corrected, the physical unit will be regarded as a damaged physical unit. It should be noted that if there is no available physical erasing unit in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 as a write protect state, and no more data can be written. .

In this exemplary embodiment, each physical unit refers to a physical erasing unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical programming unit, or consist of multiple continuous or discontinuous physical addresses. The memory management circuit 502 will configure the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In this exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic unit may also refer to a logic programming unit, a logic erasing unit, or consist of multiple consecutive or discontinuous logic addresses. In addition, each of the logical units 612(0)-612(C) may be mapped to one or more physical units.

The memory management circuit 502 can record the mapping relationship between the logical unit and the physical unit (also referred to as the logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform the processing of the memory storage device 10 according to the logical-physical address mapping table. Data access operations.

It should be noted that the following description of the operation of the memory control circuit unit 404 is equivalent to the description of the operation of the memory management circuit 502.

The flash memory data sorting method provided in this embodiment can be applied to a three-dimensional (3D) structure flash memory, an embedded memory device or a solid state drive, but the invention is not limited to this.

In this embodiment, the memory storage device 10 performs the background garbage collection operation in the background mode. If the memory storage device 10 receives a write command from the host system 11 while performing the background garbage collection operation, the memory storage device 10 suspends the background garbage collection operation and exits the background mode and enters the foreground mode. Then, the memory storage device 10 receives a plurality of write commands from the host system 11, enters the background mode after completing the execution of the write commands, and continues to perform the background garbage collection operation. Specifically, when the memory storage device 10 receives a write command from the host system 11, the memory control circuit unit 404 needs to immediately execute and respond to the host system 11 to avoid timeout. Herein, the mode in response to the program executed by the host system 11 is called the foreground mode. In contrast, the memory control circuit unit 404 can also operate in an idle state (that is, without receiving a command from the host system 11). For example, garbage collection can be performed when idle. Here, the mode not in response to the program executed by the host system 11 is called the background mode. In this embodiment, the memory storage device 10 enters the background mode from the foreground mode during idle time, and performs the garbage collection operation when the garbage collection conditions of the background mode are met.

The garbage collection condition in the background mode can be, for example, the memory control circuit unit 404 determines whether the number of free physical erasing units of the rewritable non-volatile memory module 406 is greater than the start threshold of the background garbage collection operation . Moreover, when the number of idle physical erasing units of the rewritable non-volatile memory module 406 is not greater than the activation threshold, the memory control circuit unit 404 performs the background garbage collection operation. When performing the background garbage collection operation, the memory control circuit unit 404 transfers (or copies) the valid data of multiple source physical erasing units to the target physical erasing unit, erasing the source physical erasing unit and releasing the source physical erasing unit The erasing unit is an idle physical erasing unit. In addition, when the background garbage collection operation is suspended, the memory control circuit unit 404 suspends the transfer (or copy) of the effective data of the source entity erasing unit to the target entity erasing unit, and reserves the target entity erasing unit and enters from the background mode Foreground mode to execute write instructions.

Generally speaking, if the number of free physical erase units is insufficient when the write command is executed in the foreground mode, the memory control circuit unit 404 will perform a garbage collection operation after completing the execution of a write command. However, other write instructions must be stopped when garbage collection is performed, which will cause delays.

Therefore, in the flash memory data sorting method provided in this embodiment, the memory control circuit unit 404 can determine whether the number of free physical erasing units of the rewritable non-volatile memory module 406 after entering the foreground mode Greater than the start threshold of the foreground garbage collection operation. Moreover, when the number of idle physical erasing units of the rewritable non-volatile memory module 406 is not greater than the activation threshold, the memory control circuit unit 404 performs the foreground garbage collection operation. In one embodiment, the start threshold for judging to perform the background garbage collection operation is greater than the start threshold for judging to perform the foreground garbage collection operation.

In one embodiment, when the memory control circuit unit 404 performs the background garbage collection operation in the background mode, it selects a plurality of source physical erasing units to perform the garbage collection operation according to the valid counts corresponding to the plurality of physical erasing units. Specifically, when the number of idle physical erasing units is not greater than the activation threshold, the memory control circuit unit 404 determines the arrangement order of the physical erasing units according to the effective count corresponding to each of the physical erasing units. Then, when performing the background garbage collection operation, the memory control circuit unit 404 selects one or more of the physical erasing units included in the rewritable non-volatile memory module 406 as the source physical erasing unit according to the sort order, and Move (or copy) the valid data of the source entity erasing unit to the target entity erasing unit. If the valid data stored in a certain source physical erase unit has been moved (or copied), the memory control circuit unit 404 erases the source physical erase unit and releases the erased source physical erase unit to be idle Physical erasure unit. The memory control circuit unit 404 can increase the number of free physical erasing units according to the number of free physical erasing units.

In an exemplary embodiment, the arrangement order of each physical erasing unit is related to the amount of valid data in each physical erasing unit (represented by a valid count here). According to the value of the effective count, the physical erasing unit can be determined as the source physical erasing unit when the background garbage collection operation is performed. In this exemplary embodiment, the memory control circuit unit 404 sorts from the physical erasing unit with a small effective count to the physical erasing unit with a large effective count according to the value of the effective count corresponding to each physical erasing unit. unit. In this exemplary embodiment, the memory control circuit unit 404 starts from the physical erasing unit with the smallest effective count, selects the physical erasing unit as the source physical erasing unit according to the arrangement sequence, and erases according to the selected source physical The unit performs garbage collection operations.

In one embodiment, if the memory control circuit unit 404 determines that the number of free physical erasing units of the rewritable non-volatile memory module 406 is not greater than the start threshold of the foreground garbage collection operation when executing the write command, and When the foreground garbage collection operation needs to be performed, the memory control circuit unit 404 updates the arrangement sequence of the physical erasing units according to the numerical value of the effective count corresponding to the physical erasing unit. Moreover, the memory control circuit unit 404 selects one or more of the physical erasing units included in the rewritable non-volatile memory module 406 as the source physical erasing unit according to the updated arrangement order, and erases the source physical The effective data of the unit is moved (or copied) to the target entity to erase the unit.

In one embodiment, the background garbage collection operation and the foreground garbage collection operation share the same target entity erasure unit. Specifically, in this embodiment, when the memory control circuit unit 404 performs the foreground garbage collection operation, it moves (or copies) the valid data of the source entity erasing unit to the same target entity as the background garbage collection operation. Wipe the unit. However, the present invention is not limited to this. In another embodiment, the background garbage collection operation and the foreground garbage collection operation can also wipe out the corresponding target entity units.

In other words, because some write operations have been performed before the foreground garbage collection operation is performed, which changes the effective count of the physical erase unit, therefore, in the flash memory data organization method provided in this embodiment, the memory When the control circuit unit 404 determines whether to perform the garbage collection operation in the foreground mode, it can dynamically select the source entity erasing unit of the garbage collection operation according to the effective count of the current entity erasing unit, instead of performing the physical erasing of the background garbage collection. The effective count of the erasing unit is used to select the source physical erasing unit, and the purpose of releasing the most physical erasing unit can be achieved.

In another embodiment, when the foreground garbage collection operation is performed, the erased source physical erase unit is released as an idle physical erase unit, and the memory control circuit unit 404 can erase the unit based on the released idle physical erase unit Increase the number of free physical erasure units. At this time, the number of free physical erasing units increases, and the memory control circuit unit 404 determines whether the number of free physical erasing units is greater than the activation threshold. If the memory control circuit unit 404 determines that the number of free physical erasing units is not greater than the activation threshold, it means that the number of free physical erasing units in the rewritable non-volatile memory module 406 is still insufficient, so the memory control circuit unit 404 Continue to perform foreground garbage collection operations. In contrast, if the memory control circuit unit 404 determines that the number of free physical erasing units is greater than the start threshold, it stops performing the foreground garbage collection operation and continues to execute the write command.

On the other hand, when the number of free physical erasing units is greater than the activation threshold, the memory control circuit unit 404 executes the write command. At this time, the memory storage device 10 continuously receives a plurality of write commands from the host system 11. When the write command is executed, the memory control circuit unit 404 writes the data corresponding to the write command to the rewritable non-volatile memory module. In the group 406, therefore, the number of free physical erasure units will be reduced. When the write command is executed, the memory control circuit unit 404 can determine whether the number of idle physical erasing units is greater than the activation threshold. If the memory control circuit unit 404 determines that the number of free physical erasing units is not greater than the activation threshold, it re-determines the arrangement order of the source physical erasing units according to the effective count corresponding to the physical erasing unit, and performs garbage collection according to the updated arrangement order operate. The specific method of garbage collection operation is as described above, and will not be repeated here.

In one embodiment, the memory control circuit unit 404 enters the background mode after a predetermined time has passed after completing the execution of the write command. And after entering the background mode, the memory control circuit unit 404 updates the arrangement order of the physical erasing units according to the value of the latest valid count corresponding to the physical erasing unit, and selects the rewritable non-volatile memory module 406 according to the arrangement order One or more of the included physical erasing units are used as the source physical erasing unit, and the effective data of the source physical erasing unit is moved (or copied) to the target physical erasing unit. Here, the memory control circuit unit 404 moves (or copies) the valid data of the source entity erasing unit to the same target entity erasing unit as when the background garbage collection operation is suspended.

FIG. 7 is an example of a flash memory data sorting method according to an exemplary embodiment of the present invention. FIG. 8 is a schematic diagram of a target entity erasing unit according to an exemplary embodiment of the present invention. Referring to FIG. 7, in this exemplary embodiment, the execution time of the memory control circuit unit 404 is divided into an idle time T _IDLE and a foreground operation time T _FG . The memory control circuit unit 404 enters the background mode _{during the idle time T IDLE.} In the background mode, the memory control circuit unit 404 can perform data transfer (or copy) operations. For example, in this exemplary embodiment, the memory control circuit unit 404 performs a garbage collection operation when the garbage collection conditions in the background mode are met. _{Specifically, in the idle time T IDLE} between the time point A and the time point B, the background garbage collection time T _{BG is} entered and the background garbage collection operation is performed. The memory control circuit unit 404 will sort the effective count corresponding to each physical erasing unit included in the rewritable non-volatile memory module 406 from the physical erasing unit with the smaller effective count to the one with the effective count. The physical erasure unit with a large value. The memory control circuit unit 404 starts from the physical erasing unit with the smallest effective count, selects the physical erasing unit as the source physical erasing unit according to the arrangement sequence, and selects a physical erasing unit as the target physical erasing unit (for example, The physical erasure unit 810 in FIG. 8). In this embodiment, the memory control circuit unit 404, for example, selects five physical erasing units from the physical erasing units as the source physical erasing units. Then, the memory control circuit unit 404 performs a garbage collection operation according to the selected source entity erasing unit, and moves (or copies) the valid data of the selected 5 source entity erasing units to the target entity erasing unit 810. The memory control circuit unit 404 erases the source physical erase unit and releases the erased source physical erase unit as an idle physical erase unit, and increases the number of idle physical erase units according to the number of released idle physical erase units. However, the memory control circuit unit 404 may receive a write command from the host system 11 when the background garbage collection operation is not completed. For example, time point B in Figure 7.

At time point B, the host system 11 sends multiple write commands, the memory storage device 10 receives multiple write commands from the host system 11, and enters the foreground operation time T _{FG from the idle time T IDLE} , that is, exits the background mode Enter foreground mode to process write instructions. At this time, the memory control circuit unit 404 suspends the background garbage collection operation and enters the foreground mode from the background mode. In this embodiment, because the background garbage collection operation is suspended, the data in the five source entity erasing units selected during the background garbage collection may not have all been moved (or copied) to the target entity erasing unit. Referring to FIG. 8, the memory control circuit unit 404 only completes the transfer (or copy) of the data of three source physical erasing units to the sub-physical erasing units 810(0)~810(2) of the target physical erasing unit. The memory control circuit unit 404 retains the target entity erasing unit 810 and enters the foreground mode. In the foreground mode, the memory control circuit unit 404 determines whether the number of idle physical erasing units of the rewritable non-volatile memory module 406 is greater than the activation threshold TH _FG . In other words, the memory control circuit unit 404 determines whether the number of idle physical erasing units meets the conditions for performing the garbage collection operation in the foreground mode. In this exemplary embodiment, the number of free physical erasing units at time point B does not meet the conditions for performing the garbage collection operation in the foreground mode (that is, the number of free physical erasing units is greater than the activation threshold TH _FG ), the memory control circuit Unit 404 executes write instructions and does not execute garbage collection operations.

Next, the memory storage device 10 continuously receives multiple write commands from the host system 11 from time B to time C (ie, time interval T1). When the write commands are executed, the memory control circuit unit 404 corresponds to the write commands The data of is written into the rewritable non-volatile memory module 406, so the number of free physical erasing units will be reduced. When the write command is executed, the memory control circuit unit 404 can continuously determine whether the number of idle physical erasing units is greater than the activation threshold TH _FG .

At time point C, the memory control circuit unit 404 determines that the number of free physical erasing units meets the conditions for performing the garbage collection operation in the foreground mode (that is, the number of free physical erasing units is not greater than the activation threshold TH _FG ), and then it is based on the physical erasing The effective count corresponding to the erasing unit reselects one or more of the physical erasing units as the source physical erasing unit to perform the garbage collection operation. Here, the re-selected source entity erasure unit may be different from the source entity erasure unit previously selected (for example, in the background mode). Specifically, at time point C, the memory control circuit unit 404 will sort from the physical erasing unit with a small effective count to the entity with a large effective count according to the value of the effective count corresponding to each physical erasing unit Wipe the unit. The memory control circuit unit 404 starts from the physical erasing unit with the smallest effective count, selects the physical erasing unit as the source physical erasing unit according to the arrangement sequence, and selects a physical erasing unit as the target physical erasing unit at the same time. In this exemplary embodiment, the memory control circuit unit 404 performs the foreground garbage collection operation, and transfers (or copies) the valid data of the source entity erasing unit to the sub-entity erasing unit 810 of the target entity erasing unit 801 (3 )~810(5). The memory control circuit unit 404 erases the source physical erase unit and releases the erased source physical erase unit as an idle physical erase unit, and increases the number of idle physical erase units according to the number of released idle physical erase units. In another embodiment, the memory control circuit unit 404 may select other target entity erasing units, and the present invention is not limited to this.

Then, the memory control circuit unit 404 performs a foreground garbage collection operation from time C to time D (ie, time interval T2), and continuously releases idle physical erasing units, so the number of idle physical erasing units will increase. During the garbage collection operation, the memory control circuit unit 404 can continuously determine whether the number of idle physical erasing units is greater than the activation threshold TH _FG . At time D, the memory control circuit unit 404 determines that the number of free physical erasing units does not meet the conditions for performing the garbage collection operation in the foreground mode (that is, the number of free physical erasing units is greater than the activation threshold TH _FG ), then the memory control The circuit unit 404 executes the write instruction.

The relevant content from time point D to time point E (ie, time interval T3) and time point F to time point G (ie, time interval T5) can refer to the implementation content described above from time point B to time point C, and time For the relevant content from point E to time point F (ie, time interval T4), please refer to the implementation content from time point C to time point D, which will not be repeated here. From time E to time F, the memory control circuit unit 404 reselects the source entity erasing unit to perform the foreground garbage collection operation, and can move (or copy) the effective data of the source entity erasing unit to the target entity erasing The fruit body of the unit 801 is erased from the units 810(6) to 810(9). In another embodiment, the memory control circuit unit 404 may select other target entity erasing units, and the present invention is not limited to this.

Then, at time G, the memory storage device 10 no longer receives a write command from the host system 11, so the memory control circuit unit 404 enters the idle time T _{IDLE from the foreground operation time T FG} , that is, exits the foreground mode and enters Background pattern. For the related content of the background mode, please refer to the implementation content described from time point A to time point B, which will not be repeated here. At time point G, the memory control circuit unit 404 can wait for the preset time T _preset , and enter the background garbage collection time T _BG after the preset time T _preset elapses and perform the background garbage collection operation, and can re-select the source entity to erase The unit transfers (or copies) the effective data of the source physical erasing unit to the sub-physical erasing units 810 (10) to 810 (14) of the target physical erasing unit 801. In another embodiment, the memory control circuit unit 404 may select other target entity erasing units, and the present invention is not limited to this. Finally, the memory control circuit unit 404 turns off the target entity erasing unit to complete the garbage collection operation.

FIG. 9 is a flowchart of a flash memory data sorting method according to an exemplary embodiment of the present invention. In step S902, the background garbage collection operation is performed in the background mode. In step S904, when the background garbage collection operation is not completed, at least one write instruction from the host system is received, the background garbage collection operation is suspended, and the background mode is exited. In step S906, a write command is executed. In step S908, after completing the execution of the write instruction, the background mode is entered and the background garbage collection operation is continued.

FIG. 10 is a flowchart of a flash memory data sorting method according to an exemplary embodiment of the present invention. Referring to FIG. 10, in step S1002, the background garbage collection operation is suspended and the background mode is exited to enter the foreground mode. In step S1004, it is determined whether the number of free physical erasing units of the rewritable non-volatile memory module is greater than the activation threshold. When the number of free physical erasing units of the rewritable non-volatile memory module is not greater than the activation threshold (step S1004, judged as No), select multiple source physical erasing units according to the valid counts corresponding to the multiple physical erasing units Divide the unit to perform the foreground garbage collection operation (step S1006). When the number of free physical erasing units of the rewritable non-volatile memory module is greater than the activation threshold (step S1004, the judgment is YES), the write command is executed (step S1008).

However, each step in FIG. 9 and FIG. 10 has been described in detail as above, and will not be repeated here. It should be noted that each step in FIG. 9 and FIG. 10 can be implemented as multiple program codes or circuits, and the present invention is not limited. In addition, the methods in FIG. 9 and FIG. 10 can be used in conjunction with the above exemplary embodiments, or can be used alone, and the present invention is not limited.

In summary, the flash memory data sorting method, flash memory storage device, and flash memory control circuit unit provided by the present invention can be erased according to the current idle entity in response to a write command from the host system The state of the unit dynamically determines whether the garbage collection operation can wait. When it is found that the current number of free physical erasing units exceeds the start threshold, the flash memory control circuit unit will first pending (pending) the current garbage collection operation and execute the write command. And the garbage collection operation will be executed when the garbage collection conditions of the foreground mode are met next time.

In summary, the present invention can move (or copy) the effective data of the source entity erasing unit to the same target entity erasing unit in the foreground garbage collection operation and the background garbage collection operation. And in the foreground mode, when the number of free physical erasing units of the rewritable non-volatile memory module is not greater than the activation threshold, multiple source physical erasing units are selected based on the effective counts corresponding to multiple physical erasing units To perform garbage collection. And when the number of free physical erase units of the rewritable non-volatile memory module is greater than the activation threshold, the write command is executed. Based on this, the present invention dynamically selects the source entity erasure unit of the garbage collection operation and dynamically manages the time to perform the garbage collection operation, which can reduce the probability of performing the garbage collection operation in the foreground mode, and perform the garbage collection in the background mode as much as possible. operate. In addition, by dynamically selecting the source physical erasing unit of the garbage collection operation, the idle physical erasing unit can be quickly released. Accordingly, the delay caused by the garbage collection operation can be reduced, and the execution efficiency of the write instruction can be effectively improved.

10, 30: memory storage device 11, 31: host system 110: system bus 111: processor 112: random access memory 113: read-only memory 114: data transmission interface 12: input/output (I/O ) Device 20: Motherboard 201: Flash Drive 202: Memory Card 203: Solid State Drive 204: Wireless Memory Storage Device 205: Global Positioning System Module 206: Network Interface Card 207: Wireless Transmission Device 208: Keyboard 209: Screen 210: speaker 32: SD card 33: CF card 34: embedded storage device 341: embedded multimedia card 342: embedded multi-chip package storage device 402: connection interface unit 404: memory control circuit unit 406: rewritable non Volatile memory module 502: memory management circuit 504: host interface 506: memory interface 508: error checking and correction circuit 510: buffer memory 512: power management circuit 601, 801: storage area 602: replacement area 610 ( 0)~610(B): physical unit 612(0)~612(C): logical unit 801: target entity erasing unit 810(0)~810(14): sub-entity erasing unit A~G: point in time T1~T5: Time interval TH _BG , TH _FG : start threshold T _IDLE : idle time T _FG : foreground operation time T _BG : background garbage collection time T _preset : preset time S902: step (execute background garbage collection in background mode Operation) S904: Step (receive at least one write instruction from the host system when the background garbage collection operation is not completed, suspend the background garbage collection operation and exit the background mode) S906: Step (execute the write instruction) S908: Step (complete the execution of the write After entering the command, enter the background mode and continue to perform the background garbage collection operation) S1002: Step (pause the background garbage collection operation and exit the background mode to enter the foreground mode) S1004: Step (determine the idle physical erase of the rewritable non-volatile memory module) Whether the number of erasure units is greater than the start threshold) S1006: Step (Select multiple source entity erasure units based on the effective counts corresponding to multiple entity erasure units to perform foreground garbage collection operations) S1008: Step (execute write instructions)

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another exemplary embodiment. FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. FIG. 7 is an example of a flash memory data sorting method according to an exemplary embodiment of the present invention. FIG. 8 is a schematic diagram of a target entity erasing unit according to an exemplary embodiment of the present invention. FIG. 9 is a flowchart of a flash memory data sorting method according to an exemplary embodiment of the present invention. FIG. 10 is a flowchart of a flash memory data sorting method according to an exemplary embodiment of the present invention.

S902: Step (perform background garbage collection operation in background mode)

S904: Step (receive at least one write instruction from the host system when the background garbage collection operation is not completed, suspend the background garbage collection operation and exit the background mode)

S906: Step (execute write instruction)

S908: Step (Enter the background mode after completing the write instruction and continue to perform the background garbage collection operation)

Claims (21)

A flash memory data organization method is used in a flash memory storage device including a rewritable non-volatile memory module, and the flash memory data organization method includes: executing in a background mode A background garbage collection operation to copy valid data of one or more source entity erasing units to the target entity erasing unit; when the background garbage collection operation is not completed, at least one write command from the host system is received, and the background garbage is suspended Collect operation and retain the target entity erasing unit and exit the background mode; execute the at least one write instruction; and after the completion of the at least one write instruction, enter the background mode and continue to perform the background garbage collection operation, wherein the The step of at least one write instruction includes: if a foreground garbage collection operation is performed during the execution of the at least one write instruction, then when the foreground garbage collection operation is performed, the effective of the one or more source entities is erased. The data is copied to the reserved target entity erasing unit. The flash memory data sorting method according to claim 1, further comprising: when the background garbage collection operation is performed, the effective data of the one or more source entity erasing units is copied to the target entity to erase After the cell step, erase the one or more source physical erase units and release the one or more source physical erase units as idle physical erase units; and When the background garbage collection operation is suspended, the effective data of the one or more source entity erasing units is suspended to the target entity erasing unit, and the target entity erasing unit is retained and entering a foreground mode from the background mode To execute the at least one write instruction. The flash memory data organization method according to claim 1, wherein the background garbage collection operation is executed in the background mode to copy the effective data of the one or more source entity erasing units to the target entity erasing unit The steps include: selecting one or more of the physical erasing units as the one or more source physical erasing units according to the effective counts corresponding to the plurality of physical erasing units, and erasing the one or more source entities The effective data of the erasing unit is copied to the target entity erasing unit. The flash memory data sorting method according to claim 3, wherein the step of performing the foreground garbage collection operation further includes: selecting one of the physical erasing units according to the latest effective count corresponding to the physical erasing units One or more erase units are used as the one or more source entities. The flash memory data sorting method according to claim 4, wherein the background garbage collection operation and the foreground garbage collection operation share the same target entity erasing unit. The flash memory data sorting method according to claim 4, wherein a first activation threshold for determining to perform the background garbage collection operation is greater than a second activation threshold for determining to perform the foreground garbage collection operation. According to claim 3, the flash memory data sorting method, wherein the step of entering the background mode after executing the at least one write command and continuing to perform the background garbage collection operation further includes: after the completion of the at least one write command The background mode is entered after a predetermined time after the instruction is entered; the background garbage collection operation is executed according to the latest effective count corresponding to the physical erasing units, and one or more of the physical erasing units are selected as the one or Multiple source physical erasing units, and copy valid data of the one or more source physical erasing units to the target physical erasing unit. A flash memory storage device includes: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module; and a flash memory control circuit unit coupled to the Connecting the interface unit and the rewritable non-volatile memory module, wherein the flash memory control circuit unit is used to perform a background garbage collection operation in a background mode to erase the effectiveness of one or more source entities The data is copied to the target entity erasing unit, and the flash memory control circuit unit is further used to receive at least one write command from the host system when the background garbage collection operation is not completed, suspend the background garbage collection operation and retain the target entity Erase the unit and exit the background mode, the flash memory control circuit unit is further used to execute the at least one write command, and The flash memory control circuit unit is further configured to enter the background mode after completing the execution of the at least one write command and continue to perform the background garbage collection operation. In the operation of executing the at least one write command, if the at least one write command is executed, A foreground garbage collection operation is executed during a write command, and the flash memory control circuit unit is further used to copy the effective data of the one or more source entity erasing units to the foreground garbage collection operation. The retained erase unit of the target entity. The flash memory storage device according to claim 8, wherein the flash memory control circuit unit is further used for copying valid data of one or more source entity erasing units when performing the background garbage collection operation After the operation of the target physical erase unit, erase the one or more source physical erase units and release the one or more source physical erase units as idle physical erase units, and the flash memory control circuit The unit is further used to suspend the copying of the effective data of the one or more source entity erasing units to the target entity erasing unit when the background garbage collection operation is suspended, and to retain the target entity erasing unit from the background mode Enter a foreground mode to execute the at least one write command. The flash memory storage device according to claim 8, wherein the background garbage collection operation is executed in the background mode to copy the effective data of the one or more source physical erasing units to the target physical erasing unit Wherein, the flash memory control circuit unit is further used for selecting one or more of the physical erasing units as the one or more according to the effective counts corresponding to the plurality of physical erasing units. A source physical erasing unit, and copy valid data of the one or more source physical erasing units to the target physical erasing unit. The flash memory storage device according to claim 10, wherein in the operation of performing the foreground garbage collection operation, the flash memory control circuit unit is further configured to select the latest valid count corresponding to the physical erasing units One or more of the physical erasing units serve as the one or more source physical erasing units. The flash memory storage device according to claim 11, wherein the background garbage collection operation and the foreground garbage collection operation share the same target entity erasing unit. The flash memory storage device according to claim 11, wherein a first activation threshold for determining to perform the background garbage collection operation is greater than a second activation threshold for determining to perform the foreground garbage collection operation. The flash memory storage device according to claim 10, wherein after the execution of the at least one write command is completed, the background mode is entered and the background garbage collection operation is continued, the flash memory control circuit unit is further used In order to enter the background mode after a predetermined time has elapsed after the execution of the at least one write command, and the flash memory control circuit unit is further used to execute the background garbage according to the latest valid count corresponding to the physical erasing units Collect operation, select one or more of the physical erasing units as the one or more source physical erasing units, and copy the valid data of the one or more source physical erasing units to the target physical erasing unit one Yuan. A flash memory control circuit unit for controlling a flash memory storage device including a rewritable non-volatile memory module, and the flash memory control circuit unit includes: a host interface for Coupled to a host system; a memory interface for coupling to the rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface, wherein the The flash memory control circuit unit is used for performing a background garbage collection operation in a background mode to copy valid data of one or more source physical erasing units to the target physical erasing unit, and the flash memory control circuit unit is more Used to receive at least one write instruction from the host system when the background garbage collection operation is not completed, suspend the background garbage collection operation, retain the target entity erasing unit and exit the background mode, the flash memory control circuit unit is more Is used to execute the at least one write instruction, and the flash memory control circuit unit is further used to complete the execution of the at least one write instruction and then enter the background mode and continue to perform the background garbage collection operation, wherein the at least one write is executed In the operation of the input command, if a foreground garbage collection operation is performed during the execution of the at least one write command, the flash memory control circuit unit is further used to perform the one or more foreground garbage collection operations during the execution of the foreground garbage collection operation. Copy the valid data of the source entity erasure unit to the reserved target entity erasure list Yuan. The flash memory control circuit unit according to claim 15, wherein the flash memory control circuit unit is further used to erase valid data of one or more source entities when performing the background garbage collection operation After the operation of copying to the target physical erase unit, erase the one or more source physical erase units and release the one or more source physical erase units as idle physical erase units, and the flash memory control circuit The unit is further used to suspend the copying of the effective data of the one or more source entity erasing units to the target entity erasing unit when the background garbage collection operation is suspended, and to retain the target entity erasing unit from the background mode Enter a foreground mode to execute the at least one write command. The flash memory control circuit unit according to claim 15, wherein the background garbage collection operation is performed in the background mode to copy the effective data of the one or more source entity erasing units to the target entity erasing unit In operation, the flash memory control circuit unit is further used for selecting one or more of the physical erasing units as the one or more source physical erasing units according to the effective counts corresponding to the plurality of physical erasing units. And copy the effective data of the one or more source physical erasing units to the target physical erasing unit. The flash memory control circuit unit according to claim 17, wherein in the operation of performing the foreground garbage collection operation, the flash memory control circuit unit is further used for according to the latest valid count corresponding to the physical erasing units Select one or more of these physical erasure units as the One or more source entity erasure units. The flash memory control circuit unit according to claim 18, wherein the background garbage collection operation and the foreground garbage collection operation share the same target entity erasing unit. The flash memory control circuit unit according to claim 18, wherein a first activation threshold for determining to perform the background garbage collection operation is greater than a second activation threshold for determining to perform the foreground garbage collection operation. The flash memory control circuit unit according to claim 17, wherein after completing the execution of the at least one write command, it enters the background mode and continues to perform the background garbage collection operation, the flash memory control circuit unit is more Used to enter the background mode after a predetermined time has elapsed after the execution of the at least one write command is completed, and the flash memory control circuit unit is further used to execute the background mode according to the latest valid count corresponding to the physical erasing units Garbage collection operation, selecting one or more of the physical erasing units as the one or more source physical erasing units, and copying the valid data of the one or more source physical erasing units to the target physical erasing unit In addition to the unit.

Images