TWI737747B - Semiconductor package and method for manufacturing the same - Google Patents

Abstract

Embodiments of the inventive concepts provide a semiconductor package and a method for manufacturing the same. The method includes providing a package comprising a substrate, a semiconductor chip, and a molding layer, the substrate comprising a ground pattern exposed at one surface of the substrate; and applying a solution including metal particles and a conductive carbon material onto the molding layer to form a shielding layer. The shielding layer comprises: the metal particles; and the conductive carbon material connected to at least one of the metal particles. The shielding layer extends onto the one surface of the substrate and is electrically connected to the ground pattern.

Description

Semiconductor package and method for manufacturing semiconductor package

Example embodiments of the present disclosure relate to semiconductor packages and methods for manufacturing semiconductor packages, and more particularly, to semiconductor packages including mask layers and methods for manufacturing the semiconductor packages.

The semiconductor package containing the integrated circuit chip can be used for the presentation of a suitable form for using the integrated circuit chip in an electronic product. In general semiconductor packaging, the semiconductor chip can be mounted on a printed circuit board (PCB) and can be electrically connected to the PCB through bonding wires or bumps. With the development of the electronics industry, high-performance, high-speed and small electronic components have been developed. Therefore, electromagnetic interference may occur between the semiconductor package and other electronic components.

Example embodiments provide a semiconductor package and a method for manufacturing a semiconductor package.

According to an aspect of example embodiments, a method for manufacturing a semiconductor package may include: providing a package including a ground pattern; and forming a mask layer disposed on a top surface and sidewalls of the package and electrically connected to the ground pattern. The mask layer may include metal particles connected to each other, and a conductive carbon material connected to at least one of the metal particles. The metal particles may include first particles and second particles having an aspect ratio greater than that of the first particles.

According to another aspect of another example embodiment, a method for manufacturing a semiconductor package may include: providing a package including a substrate, a semiconductor wafer, and a mold layer; and applying a solution including metal particles and a conductive carbon material to the mold On the plastic layer to form a mask layer. The substrate may include a ground pattern exposed at one surface of the substrate. The mask layer may include metal particles and a conductive carbon material connected to at least one of the metal particles. The mask layer may extend to a surface of the substrate and be electrically connected to the ground pattern. One surface of the base may be one of the bottom surface and the sidewall of the base.

According to another aspect of another example embodiment, a semiconductor package may include: a substrate including a ground structure, the ground structure being exposed at one surface of the substrate; a semiconductor wafer on the substrate; a molding layer provided on the substrate, and molding The layer covers the semiconductor wafer; and a mask layer is provided on one surface of the mold layer and the substrate. The mask layer can contact the ground structure. The mask layer may include metal particles connected to each other, and a conductive carbon material connected to at least one of the metal particles.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

A semiconductor package and a method of manufacturing a semiconductor package according to some example embodiments will be described hereinafter.

FIG. 1A is a plan view illustrating a semiconductor package according to example embodiments. Fig. 1B is a cross-sectional view taken along the line I-II of Fig. 1A.

1A and 1B, the semiconductor package 1 may include a substrate 100, a semiconductor wafer 200, a molding layer 300, and a mask layer 400. The substrate 100 may be a printed circuit board (PCB), a silicon substrate, a redistribution substrate, or a flexible substrate. The substrate 100 may include an insulating layer 130, ground structures 110, 111, and 112, signal structures 120, 121, and 122, and terminals 131 and 132. The ground structures 110, 111, and 112 may include a ground pattern 110, an upper ground via 111, and a lower ground via 112. The signal structures 120, 121 and 122 may include a signal pattern 120, an upper signal via 121 and a lower signal via 122. The terminals 131 and 132 may be disposed on the bottom surface of the insulating layer 130. The terminals 131 and 132 may include a conductive material and may have a solder ball shape. The terminals 131 and 132 may include a ground terminal 131 and a signal terminal 132. The ground terminal 131 may be insulated from the signal terminal 132.

The insulating layer 130 may include multiple layers. The ground pattern 110 may be provided in the insulating layer 130. The ground pattern 110 may include a conductive material such as metal. When viewed from a plan view, the ground pattern 110 may be disposed in the edge portion of the substrate 100. The ground pattern 110 may be exposed at the sidewall 100c of the substrate 100. The lower ground via 112 may be disposed between the ground pattern 110 and the ground terminal 131 in the insulating layer 130. The ground pattern 110 may be electrically connected to the ground terminal 131 through the lower ground via 112. In this specification, it will be understood that when an element is referred to as being "electrically connected" to another element, it can be directly connected to the other element or an intervening element may be present. The upper ground via 111 may be provided on the ground pattern 110 and may be connected to the ground pattern 110. The upper ground via 111 may not be aligned with the lower ground via 112 in the vertical direction. Here, the vertical direction may be a direction perpendicular to the top surface of the substrate 100. The numbers of the lower ground via 112, the ground pattern 110, and the upper ground via 111 are not limited to those illustrated in FIGS. 1A and 1B.

When viewed from a plan view, the signal pattern 120 may be disposed in the central portion of the substrate 100. The signal pattern 120 may be separated from the sidewall 100c of the substrate 100. The signal pattern 120 may include a conductive material such as metal. The signal pattern 120 may be insulated from the ground pattern 110. The signal pattern 120 can be electrically connected to the signal terminal 132 through the lower signal through hole 122.

The semiconductor wafer 200 may be mounted on the top surface of the substrate 100. The semiconductor wafer 200 may include an integrated circuit layer 250 disposed on the bottom surface thereof. The interposers 210 and 220 may be provided between the substrate 100 and the semiconductor wafer 200. The interposers 210 and 220 may include a conductive material (for example, metal), and may have a solder ball shape, a bump shape, or a pillar shape. The intermediary objects 210 and 220 may include a grounding intermediary object 210 and a signal intermediary object 220. The ground interposer 210 may be connected to the upper ground via 111. The integrated circuit layer 250 of the semiconductor wafer 200 may be grounded through the ground interposer 210, the upper ground via 111, the ground pattern 110, the lower ground via 112, and the ground terminal 131. The signal intermediary 220 may be connected to the upper signal through hole 121. When the semiconductor chip 200 is in operation, the electrical signals generated on the integrated circuit layer 250 can be transmitted to the external system through the signal intermediary 220, the upper signal via 121, the signal pattern 120, the lower signal via 122 and the signal terminal 132. Similarly, external electrical signals can be transmitted to the integrated circuit layer 250 through the signal pattern 120. In some embodiments, the interposers 210 and 220 may include wiring provided on the top surface of the substrate 100 and may be electrically connected to the substrate 100.

The molding layer 300 may be provided on the substrate 100 and may cover the semiconductor wafer 200. The molding layer 300 may extend into the gap between the substrate 100 and the semiconductor wafer 200. Alternatively, the primer layer may fill the gap between the substrate 100 and the semiconductor wafer 200. The molding layer 300 may include an insulating polymer material such as an epoxy molding compound (EMC). In some embodiments, hydrophilic functional groups may be provided on the top surface and sidewalls of the molding layer 300. The recess 350 may be provided on the top surface of the molding layer 300. Unlike FIG. 1B, the recess 350 may be provided on the sidewall of the molding layer 300.

The mask layer 400 may be provided on the top surface of the molding layer 300, the sidewalls of the molding layer 300, and the sidewalls 100c of the substrate 100. The mask layer 400 may surround the molding layer 300. Since the mask layer 400 has conductivity, the mask layer 400 can block electromagnetic interference (EMI). Electromagnetic interference (EMI) means that electromagnetic waves radiated or transmitted from an electronic component will interfere with the signal reception/transmission of another electronic component. According to some embodiments, since the semiconductor package 1 includes the mask layer 400, the semiconductor package 1 may not interfere with the operation of another electronic device (for example, a transmitter or a receiver). The mask layer 400 may absorb electromagnetic waves 600 generated from the integrated circuit layer 250 of the semiconductor wafer 200, the interposers 210 and 220, or the substrate 100. The ground pattern 110 may be exposed at the sidewall 100c of the substrate 100, and thus the mask layer 400 may be electrically connected to the ground pattern 110. The electromagnetic wave 600 absorbed in the mask layer 400 may be transmitted to the outside of the semiconductor package 1 through the ground pattern 110 and the ground terminal 131, as illustrated by the arrow in FIG. 1B. The signal pattern 120 may not be exposed at the sidewall 100c of the substrate 100, and therefore the mask layer 400 may not be electrically connected to the signal pattern 120. Hereinafter, the mask layer 400 will be described in more detail.

FIG. 1C is an enlarged view of area III of FIG. 1B.

1B and 1C, the mask layer 400 may include metal particles 410, a conductive carbon material 420, and a polymer 430. The mask layer 400 may have conductivity by the metal particles 410 and the conductive carbon material 420 contained therein. In some embodiments, the metal particles 410 may include silver (Ag). In some embodiments, the metal particles 410 may include gold (Au), copper (Cu), nickel (Ni), iron (Fe), aluminum (Al), or any combination thereof. When the metal particles 410 are separated from each other, electrons may move slowly between the metal particles 410, or it may be difficult to move between the metal particles 410. According to some embodiments, the metal particles 410 may be agglomerated together so as to be physically connected to each other. Therefore, electrons can quickly move between the metal particles 410. As a result, the resistance of the mask layer 400 can be reduced. Since the resistance of the mask layer 400 is reduced, electromagnetic waves absorbed in the mask layer 400 can be quickly transmitted to the outside of the semiconductor package 1. For easy and convenient explanation and description, the interface surface between the metal particles 410 is illustrated in FIGS. 1B and 1C. However, the embodiment of the inventive concept is not limited thereto. In some embodiments, unlike FIGS. 1B and 1C, the metal particles 410 may be connected to each other, and therefore, the interface surface between the metal particles 410 may not be distinguished or shown. The content of the metal particles 410 in the mask layer 400 may be in the range of 40 wt% to 60 wt%. If the content of the metal particles 410 in the mask layer 400 is less than 40 wt %, the mask layer 400 may not sufficiently prevent electromagnetic interference of the semiconductor package 1. If the content of the metal particles 410 in the mask layer 400 is higher than 60 wt%, the weight or manufacturing cost of the mask layer 400 may increase.

The conductive carbon material 420 may be physically connected to the metal particles 410 and electrically connected to the metal particles. Even if the metal particles 410 are separated from each other, the metal particles 410 can still be electrically connected to each other through the conductive carbon material 420. Since the conductivity of the conductive carbon material 420 is lower than that of the metal particles 410, the resistance of the mask layer 400 can be further reduced by the conductive carbon material 420. The conductive carbon material 420 may be covalently bonded to the metal particles 410. The electrical resistance between the conductive carbon material 420 and the metal particles 410 can be further reduced due to the covalent bond. As a result, the resistance of the mask layer 400 can be further reduced. The content of the conductive carbon material 420 in the mask layer 400 may be 0.5 wt% or more, and more specifically, the content in the mask layer 400 may be in the range of 0.5 wt% to 3 wt%. If the content of the conductive carbon material 420 in the mask layer 400 is less than 0.5 wt%, the resistance of the mask layer 400 may increase. If the content of the conductive carbon material 420 in the mask layer 400 is higher than 3 wt %, the content of the metal particles 410 in the mask layer 400 may decrease.

The strength of the interaction between the conductive carbon material 420 and the metal particles 410 that are covalently bonded to each other may be greater than the strength of the interaction between the conductive carbon material 420 and the metal particles 410 that are in contact with each other but are not covalently bonded. When the strength of the interaction (for example, bonding strength) between the conductive carbon material 420 and the metal particles 410 increases, the affinity between the conductive carbon material 420 and the external material and the affinity between the metal particles 410 and the external material may decrease . For example, the external material may be a hydrophilic material, and the mask layer 400 may have hydrophobic properties. The mask layer 400 may have a contact angle of 80 degrees to 110 degrees. Specifically, the mask layer 400 may have a contact angle of 90 degrees to 110 degrees. Therefore, the mask layer 400 may not be contaminated by external materials.

The conductive carbon material 420 may have high thermal conductivity. The thermal conductivity of the conductive carbon material 420 may be higher than the thermal conductivity of the molding layer 300 and the metal particles 410. For example, the conductive carbon material 420 may have a thermal conductivity of about 3000 W/mK. The metal particles 410 may have a thermal conductivity of about 350 W/mK to about 500 W/mK. The molding layer 300 may have a thermal conductivity of about 0.88 W/mK. Since the mask layer 400 includes the conductive carbon material 420, the heat generated by the semiconductor wafer 200 can be quickly released to the outside of the semiconductor package 1 when the semiconductor package 1 is operated. If the content of the conductive carbon material 420 in the mask layer 400 is less than 0.5 wt %, the heat of the semiconductor wafer 200 may be released to the outside of the semiconductor package 1 more slowly. In this situation, the operational reliability of the semiconductor wafer 200 may be degraded. In some embodiments, the conductive carbon material 420 may include carbon nanotubes (eg, multilayer carbon nanotubes). In some embodiments, the conductive carbon material 420 may include graphite, carbon black, or carbon fiber.

The polymer 430 may include a hydrophilic polymer. For example, the polymer 430 may include at least one of epoxy-based polymer or polyurethane. However, the embodiment is not limited to this. In certain embodiments, the polymer 430 may include at least one of various other hydrophilic polymers. The polymer 430 may be provided in the gap between the conductive carbon material 420 and the metal particles 410. The polymer 430 may act as a binder. For example, the metal particles 410 and the conductive carbon material 420 may be adhered to the molding layer 300 by the polymer 430. The hydrophilic functional group may be provided on the molding layer 300, and thus the bonding strength between the polymer 430 and the molding layer 300 may be further increased. Therefore, the mask layer 400 can be adhered to the molding layer 300 more firmly.

As illustrated in FIG. 1B, the mark 450 may be provided on the semiconductor package 1. The mark 450 may be a part of the mask layer 400 which is provided on the recess 350 of the molding layer 300. Hereinafter, the marking 450 of the semiconductor package 1 will be described in more detail.

FIG. 1D is an enlarged plan view illustrating the top surface of the mask layer according to example embodiments. FIG. 1E is an enlarged cross-sectional view of the area IV of FIG. 1B, and corresponds to the cross-sectional view taken along the line V-VI of FIG. 1D. In the following, for easy and convenient explanation, the description of the same technical features as mentioned above will be omitted or briefly mentioned.

Referring to FIGS. 1B, 1D, and 1E, a recess 350 may be provided on the top surface 300a of the molding layer 300. The recess 350 may have an inclined sidewall 350a. The inclined sidewall 350a may be inclined with respect to the top surface 300a of the molding layer 300. The term "tilt" may be determined depending on the average slope between the two ends of the element. In FIGS. 1D and 1E, the top surface 300a of the molding layer 300 is defined as the top surface of the portion of the molding layer 300 (in which the recess 350 is not formed). The recess 350 may have a V-shaped cross section. For example, the inclined sidewalls 350a of the recess 350 may meet each other. Alternatively, in some embodiments, the recess 350 may have a U-shaped cross-section. The depth D1 of the recess 350 may be 20 μm or more. Specifically, the depth D1 of the recess 350 may be 25 μm or more. In this specification, the depth D1 of the recess 350 may mean the vertical depth from the top surface 300 a of the molding layer 300 to the bottom end of the recess 350. The depth D1 of the recess 350 may be smaller than the distance between the top surface 300a of the molding layer 300 and the semiconductor wafer 200, and therefore the semiconductor wafer 200 may not be exposed.

The mask layer 400 may be provided on the molding layer 300 and may extend into the recess 350. The mask layer 400 may conformally cover the inclined sidewalls 350 a of the recess 350 and the top surface 300 a of the molding layer 300, so that the top surface of the mask layer 400 is recessed where the mask layer 400 covers the recess 350. The mask layer 400 may include a first part 401 and a second part 402. The first part 401 may be provided on the top surface 300 a of the molding layer 300 outside the recess 350. The second part 402 may be provided on the recess 350. The second part 402 may extend from the first part 401. The material of the second part 402 may be the same as the material of the first part 401. The composition ratio of the first part 401 of the mask layer 400 may be substantially the same as the composition ratio of the second part 402 of the mask layer 400. The term "substantially equal" can encompass tolerances that may occur during the process. The first portion 401 and the second portion 402 of the mask layer 400 may have a first top surface 401a and a second top surface 402a, respectively. The second portion 402 of the mask layer 400 may have a cross section corresponding to the cross section of the recess 350. In some embodiments, the second portion 402 of the mask layer 400 may have a V-shaped cross section. Alternatively, in some embodiments, the second portion 402 of the mask layer 400 may have a U-shaped cross-section.

The second top surface 402 a of the mask layer 400 may be inclined with respect to the first top surface 401 a of the mask layer 400. The angle θ1 between the second top surface 402a of the mask layer 400 and the first top surface 401a may be in the range of about 130 degrees to about 160 degrees.

Since the second top surface 402a of the mask layer 400 is inclined with respect to the first top surface 401a of the mask layer 400, when light is incident on the first top surface 401a and the second top surface 402a in the same direction, the The reflection angle of the light reflected by the second portion 402 of the mask layer 400 may be different from the reflection angle of the light reflected from the first portion 401 of the mask layer 400. As a result, the intensity of light reflected from the second portion 402 of the mask layer 400 may be different from the intensity of light reflected from the first portion 401 of the mask layer 400. For example, the intensity of light reflected from the first portion 401 of the mask layer 400 may be weaker than the intensity of light reflected from the second portion 402 of the mask layer 400. Here, the intensity of light may mean the amount of light received per unit area during a unit time, and may be a value measured perpendicular to the traveling direction of light. When the difference in intensity between the reflected light of the first portion 401 and the reflected light of the second portion 402 increases, the difference in brightness between the first portion 401 and the second portion 402 of the mask layer 400 may increase. When the depth D1 of the recess 350 is 20 μm or more (specifically, 25 μm or more) and the angle θ1 between the first top surface 401a and the second top surface 402a is in the range of 130 degrees to 160 degrees, from The intensity of the light reflected from the first part 401 may be completely different from the intensity of the light reflected from the second part 402. Therefore, the brightness of the second portion 402 of the mask layer 400 can be clearly distinguished from the brightness of the first portion 401 of the mask layer 400. In other words, the second part 402 of the mask layer 400 may have visibility through the difference in brightness between the first part 401 and the second part 402. For example, the first portion 401 of the mask layer 400 may have a furnace gray color, and the second portion 402 of the mask layer 400 may have a black color. Therefore, the second portion 402 of the mask layer 400 may serve as the mark 450, and the mark 450 may have visibility. In this specification, visibility may mean the visibility of colors, and colors may include hue or brightness. The planar shape of the mark 450 may not be limited to the shape illustrated in FIG. 1D but may be variously modified. Unlike FIG. 1B, the recess 350 and the mark 450 may be provided on the sidewall of the molding layer 300.

2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to example embodiments. FIG. 2D is an enlarged view of area III' of FIG. 2C. In the following, for easy and convenient explanation, the description of the same technical features as mentioned above will be omitted or briefly mentioned.

Referring to FIG. 2A, the semiconductor wafer 200 may be mounted on the packaging substrate 101. The packaging substrate 101 may be a wafer-level substrate. A plurality of semiconductor chips 200 may be provided on the packaging substrate 101. The molding pattern 301 may be formed on the package substrate 101 to cover the semiconductor wafer 200. The laser may be irradiated onto the molded pattern 301 to form the depression 350. The laser may be an infrared laser. The depth of the recess 350 may be 20 μm or more. A plurality of recesses 350 may be formed in the molding pattern 301. The terminals 131 and 132 may be formed on the bottom surface of the package substrate 101. Thereafter, the molding pattern 301 and the package substrate 101 can be sawed along the alternate long and short dashed lines illustrated in FIG. 2A, thereby forming a plurality of unit packages 10. The packaging substrate 101 may be divided into the substrate 100 through a sawing process, and the molding pattern 301 may be divided into the molding layer 300 through the sawing process. The unit package 10 may include a substrate 100, a semiconductor wafer 200 and a molding layer 300. Hereinafter, the process performed on each of the unit packages 10 will be described in detail.

Referring to FIG. 2B, the top surface and sidewalls of the molding layer 300 may be treated with plasma. The plasma treatment process can be performed using oxygen plasma and/or argon plasma. Therefore, hydrophilic functional groups may be formed on the top surface and sidewalls of the molding layer 300. For example, the hydrophilic functional group may include a hydroxyl group (-OH). The plasma treatment process may be further performed on the sidewall 100c of the substrate 100. In some embodiments, the surface roughness of the top surface and sidewalls of the molding layer 300 may be increased through a plasma treatment process.

2C and 2D, a coating solution may be applied to the top surface of the molding layer 300, the sidewalls of the molding layer 300, and the sidewall 100c of the substrate 100 to form a preliminary mask layer 400P. The preliminary mask layer 400P may be in physical contact with the ground pattern 110 of the substrate 100. The preliminary mask layer 400P may extend to the recess 350. The coating solution may include metal particles 410, conductive carbon material 420, polymer 430, and a solvent. The types of the metal particles 410, the conductive carbon material 420, and the polymer 430 may be the same as the related descriptions with reference to FIGS. 1A and 1B. The metal particles 410 may have an average diameter of about 50 nm. The polymer 430 may be a hydrophilic polymer. The conductive carbon material 420 may have hydrophilic properties. The solvent may include at least one of propylene glycol methyl ether acetate (PGMEA), water, and ethanol. The solvent may have hydrophilic properties. Therefore, the conductive carbon material 420 can be uniformly dispersed in the solvent. The coating solution may be applied to the molding layer 300 by a spraying method.

The preliminary mask layer 400P may include the same material as the coating solution. As illustrated in FIG. 2D, the conductive carbon material 420 may not be bonded to the metal particles 410. The metal particles 410 may not be in physical contact with each other. Since the coating solution has hydrophilic properties, the preliminary mask layer 400P may have hydrophilic properties. The preliminary mask layer 400P may interact with the hydrophilic functional groups formed on the molding layer 300 by the plasma treatment process of FIG. 2B. Therefore, the preliminary mask layer 400P can adhere to the molding layer 300 well.

The preliminary mask layer 400P (for example, the polymer of the preliminary mask layer 400P) may be hardened. The preliminary mask layer 400P can be cured at 90 degrees Celsius to 190 degrees Celsius. The solvent may volatilize during the hardening of the preliminary mask layer 400P.

1B and 1C, the preliminary mask layer 400P may be heat-treated to form the mask layer 400. The heat treatment process of the preliminary mask layer 400P may be performed at about 150 degrees Celsius or more (for example, a temperature of 150 degrees Celsius to 300 degrees Celsius). In some embodiments, the heat treatment process of the preliminary mask layer 400P may be performed by an infrared reflow process using an infrared heater. In some embodiments, plasma or high temperature nitrogen may be used to heat treat the preliminary mask layer 400P. In some embodiments, a halogen light lamp may be used to heat treat the preliminary mask layer 400P under vacuum.

The metal particles 410 may be agglomerated together by the heat treatment process so as to be physically connected to each other. The conductive carbon material 420 may be bonded (for example, covalently bonded) to the metal particles 410. Therefore, the resistance of the mask layer 400 may decrease. If the preliminary mask layer 400P is heat-treated at a temperature lower than 150 degrees Celsius, the metal particles 410 may not be sufficiently connected to each other or the conductive carbon material 420 may not be bonded to the metal particles 410. If the preliminary mask layer 400P is heat-treated at a temperature higher than 300 degrees Celsius, the molding layer 300 may be damaged.

Since the conductive carbon material 420 is covalently bonded to the metal particles 410 in the mask layer 400, the mask layer 400 may have hydrophobic properties compared to the preliminary mask layer 400P of FIG. 2D. The contact angle of water with respect to the mask layer 400 may be greater than the contact angle of water with respect to the preliminary mask layer 400P. For example, the contact angle of water relative to the mask layer 400 may be greater than 90 degrees, and the contact angle of water relative to the preliminary mask layer 400P may be less than 90 degrees.

As described with reference to FIGS. 1D and 1E, the angle θ1 between the first top surface 401a and the second top surface 402a of the mask layer 400 may range from about 130 degrees to about 160 degrees. Therefore, the mark 450 with visibility can be formed on the semiconductor package 1 without an additional painting process.

FIG. 3A is a cross-sectional view corresponding to the line I-II of FIG. 1A for explaining a semiconductor package according to example embodiments. 3B and 3C are enlarged cross-sectional views corresponding to the region IV′ of FIG. 3A for explaining a method for forming a mark of a semiconductor package according to example embodiments. In the following, for easy and convenient explanation, the description of the same technical features as mentioned above will be omitted or briefly mentioned.

3A and 3B, the semiconductor package 2 may include a substrate 100, a semiconductor wafer 200, a mold layer 300, and a mask layer 400. The substrate 100, the semiconductor wafer 200, and the mold layer 300 may be formed by the same method as described with reference to FIG. 2A. However, unlike FIG. 2A, the recess 350 may not be formed on the molding layer 300. The mask layer 400 may be formed on the molding layer 300. The mask layer 400 may be formed by the same method as described with reference to FIGS. 2B to 2D. Here, the coating solution may further include titanium oxide, and thus the mask layer 400 may include metal particles 410, a conductive carbon material 420, a polymer 430, and titanium oxide (TiO2). The mask layer 400 may include a first part 401 and a second part 402. The first top surface 401 a of the first portion 401 of the mask layer 400 may be substantially parallel to the second top surface 402 a of the second portion 402 of the mask layer 400.

Referring to FIGS. 3A and 3C, light may be irradiated on the second portion 402 of the mask layer 400. The first portion 401 of the mask layer 400 may not be exposed to light. For example, the light may have a wavelength in the green region, such as a wavelength of 495 nm to 570 nm. A laser device can be used to illuminate the light. The laser device can have (but not limited to) 4W to 6W output power. Titanium oxide can act as a photocatalyst. When irradiated with light, the titanium oxide may react with the polymer 430 to form a modified polymer 431 recessed in the second part 402. The modified polymer 431 may be formed in the upper part of the second part 402 of the mask layer 400. Therefore, the wavelength of the light reflected from the second portion 402 of the mask layer 400 may be different from the wavelength of the light reflected from the first portion 401 of the mask layer 400, and therefore the hue of the second portion 402 may be different from that of the first portion 401. Hue. At this time, the hue of the second part 402 may be different from the hue of the first part 401 in some way, so that the hue of the second part 402 can be completely different from the hue of the first part 401. For example, the first portion 401 of the mask layer 400 may have a furnace gray color, and the second portion 402 of the mask layer 400 may have a brown color. As a result, the second portion 402 of the mask layer 400 may serve as the mark 450, and the mark 450 may have visibility.

When light is irradiated, the second portion 402 of the mask layer 400 may be recessed. Therefore, the second top surface 402 a of the second portion 402 of the mask layer 400 may be inclined with respect to the first top surface 401 a of the first portion 401 of the mask layer 400. However, the angle θ2 between the first top surface 401a and the second top surface 402a of the mask layer 400 may not be limited to the range of the angle θ1 described with reference to FIGS. 1D and 1E. The angle θ2 between the first top surface 401a and the second top surface 402a of the mask layer 400 may be greater than 0 degrees. Therefore, the brightness of the second portion 402 of the mask layer 400 may be different from the brightness of the first portion 401 of the mask layer 400.

FIG. 3D is an enlarged cross-sectional view corresponding to the region IV' of FIG. 3A for explaining a method for forming a mark of a semiconductor package according to example embodiments. In the following, for easy and convenient explanation, the description of the same technical features as mentioned above will be omitted or briefly mentioned.

Referring to FIGS. 3A and 3D, light may be irradiated on the second portion 402 of the mask layer 400. For example, the irradiation of light may be performed by substantially the same method as described with reference to FIG. 3B. For example, the light may have a wavelength in the green region, such as a wavelength of 495 nm to 570 nm. Therefore, the modified polymer 431 may be formed in the upper part of the second part 402, as described with reference to FIG. 3B. When the light is excessively irradiated, the polymer 430 or the modified polymer 431 may be removed from the second portion 402 of the mask layer 400 to expose the metal particles 410 at the second top surface 402a of the mask layer 400. In this situation, the second portion 402 of the mask layer 400 may show the color of the metal particles 410 (for example, silver).

The first portion 401 of the mask layer 400 may not be exposed to light. The metal particles 410 may not be exposed at the first top surface 401a of the mask layer 400, or the density of the metal particles 410 exposed at the first top surface 401a may be less than the density of the metal particles 410 exposed at the second top surface 402a. Therefore, the color of the second part 402 may be different from the color of the first part 401. The first portion 401 of the mask layer 400 may have a furnace gray color. As a result, the second portion 402 of the mask layer 400 may serve as the mark 450, and the mark 450 may have visibility.

4A is a cross-sectional view corresponding to the line I-II of FIG. 1A for explaining a semiconductor package according to some embodiments of the inventive concept. FIG. 4B is an enlarged view of the region III" of FIG. 4A. In the following, for easy and convenient explanation, the description of the same elements as mentioned above will be omitted or simply mentioned.

4A and 4B, the semiconductor package 3 may include a substrate 100, a semiconductor wafer 200, a molding layer 300, and a mask layer 400'. The substrate 100, the semiconductor wafer 200, and the mold layer 300 may be substantially the same as described with reference to FIGS. 1A and 1B.

The mask layer 400 ′ may include metal particles 410 ′, a conductive carbon material 420 and a polymer 430. The metal particles 410', the conductive carbon material 420, and the polymer 430 may include the same materials as the metal particles 410, the conductive carbon material 420, and the polymer 430 described in the embodiment of FIGS. 1A to 1C or 3A, respectively. The metal particles 410 ′ may include first particles 411 and second particles 412. The first particles 411 may have, but are not limited to, a spherical or elliptical shape. The first particles 411 may be connected to each other. In some embodiments, at least two of the first particles 411 may contact each other. In some embodiments, at least two of the first particles 411 may be aggregated. The content of the first particles 411 in the mask layer 400' may be in the range of 2 wt% to 20 wt%. If the content of the first particles 411 in the mask layer 400' is less than 2 wt% or greater than 20 wt%, the resistance of the mask layer 400' may increase.

The aspect ratio of the second particles 412 may be greater than the aspect ratio of the first particles 411. For example, the aspect ratio of the second particles 412 may be in the range of about 5 times to about 20 times the aspect ratio of the first particles 411. Here, the aspect ratio of the particle may mean the ratio of the maximum diameter of the particle to the minimum diameter of the particle. The second particle 412 may have high conductivity due to its large aspect ratio. If the aspect ratio of the second particles 412 is less than 5 times the aspect ratio of the first particles 411, the mask layer 400' may have low electrical conductivity. If the aspect ratio of the second particle 412 is greater than 20 times the aspect ratio of the first particle 411, the size of the mask layer 400' may be excessively increased. The second particles 412 may have, but are not limited to, a flat plate or flake shape. Some of the second particles 412 may be directly connected to each other. The first particles 411 may be provided between the second particles 412. The second particle 412 may be connected to the first particle 411. One of the second particles 412 can be connected to the other second particle 412 through the first particle 411. In other words, even if the second particles 412 are separated from each other, the second particles 412 can still be electrically connected to each other through the first particles 411. The second particle 412 may include the same metal as the first particle 411 or a different metal. The content of the second particles 412 in the mask layer 400' may be in the range of 70 wt% to 90 wt%. If the content of the second particles 412 in the mask layer 400' is less than 70 wt%, the resistance of the mask layer 400' may increase. If the content of the second particles 412 in the mask layer 400' is greater than 90 wt%, the bonding strength between the mask layer 400' and the molding layer 300 may decrease.

In some embodiments, the second particles 412 may be stacked on the molding layer 300. In the case where the second particles 412 are provided on the top surface of the molding layer 300, the long axis of the second particles 412 may be substantially parallel to the top surface of the molding layer 300. In the case where the second particles 412 are provided on the side walls of the molding layer 300, the long axis of the second particles 412 may be substantially parallel to the side walls of the molding layer 300. However, the arrangement of the long axis of the second particle 412 is not limited to this.

The conductive carbon material 420 may be physically and electrically connected to at least one of the metal particles 410'. The content of the conductive carbon material 420 in the mask layer 400' may be in the range of 0.05 wt% to 5 wt%. If the content of the conductive carbon material 420 in the mask layer 400' is less than 0.05 wt%, the conductive carbon material 420 may not be able to sufficiently electrically connect the second particles 412 to each other. If the content of the conductive carbon material 420 in the mask layer 400' is greater than 5 wt%, the content of the second particles 412 may decrease and the resistance of the mask layer 400' may increase.

The polymer 430 may be substantially the same as the polymer 430 described with reference to FIGS. 1A and 1B. For example, the polymer 430 may be provided in the gaps between the first particles 411, the second particles 412 and the conductive carbon material 420. The first particles 411, the second particles 412 and the conductive carbon material 420 may be bonded to the molding layer 300 by the polymer 430. The content of the polymer 430 in the mask layer 400' may be in the range of 7 wt% to 12 wt%. If the content of the polymer 430 in the mask layer 400' is less than 7 wt%, the bonding strength between the mask layer 400' and the molding layer 300 may decrease. If the content of the polymer 430 in the mask layer 400' is greater than 12 wt%, the resistance of the mask layer 400' may increase.

The mark 450 may be provided on the semiconductor package 3. The mark 450 may be the same as the mark 450 of FIGS. 1B, 1D, and 1E. Alternatively, the mark 450 may be the same as the mark 450 of FIG. 3A, and may be formed by the same method as described in the embodiments of FIGS. 3B to 3D.

The semiconductor package 3 can be manufactured by the same method as described with reference to FIGS. 2A to 2D. However, the coating solution may include metal particles 410', conductive carbon material 420, polymer 430, and a solvent. During the heat treatment process of FIGS. 1B and 2C, the conductive carbon material 420 may be chemically bonded (for example, covalently bonded) to one of the first particles 411 and the second particles 412. In some embodiments, the conductive carbon material 420 may not be chemically bonded to the metal particles 410', but may contact the metal particles 410'.

FIG. 5 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Hereinafter, for easy and convenient explanation, the description of the same elements as mentioned above will be omitted or briefly mentioned.

5, the semiconductor package 4 may include a substrate 100, a semiconductor wafer 200, a molding layer 300, a first mask layer 400A, and a second mask layer 400B. The substrate 100, the semiconductor wafer 200, and the mold layer 300 may be substantially the same as described with reference to FIGS. 1A and 1B. The first mask layer 400A may be substantially the same as the mask layer 400 described with reference to FIGS. 1A and 1B. The first mask layer 400A may be formed by substantially the same method as the method of forming the mask layer 400 of FIGS. 2B to 2D. For example, the first mask layer 400A may include the first metal particles 410A, the first conductive carbon material 420A, and the first polymer 430A. The first metal particles 410A may be physically connected to each other through a heat treatment process. The first conductive carbon material 420A may be bonded to the first metal particles 410A. The first mask layer 400A may be electrically connected to the ground pattern 110 of the substrate 100.

The second mask layer 400B may be formed on the first mask layer 400A. The second mask layer 400B may be formed by substantially the same method as the method of forming the mask layer 400 of FIGS. 2B to 2D after the heat treatment process of the first mask layer 400A is completed. For example, the coating solution may be coated on the first mask layer 400A to form the second preliminary mask layer, and the second preliminary mask layer may be heat-treated to form the second mask layer 400B. The second mask layer 400B may include second metal particles 410B, a second conductive carbon material 420B, and a second polymer 430B. The second metal particles 410B may be physically connected to each other through a heat treatment process. The second conductive carbon material 420B may be bonded to the second metal particles 410B. The second mask layer 400B may be electrically connected to the first mask layer 400A. For example, the second metal particle 410B may be connected to the first metal particle 410A or the first conductive carbon material 420A, or the second conductive carbon material 420B may be connected to the first metal particle 410A or the first conductive carbon material 420A. The semiconductor package 4 may include a plurality of mask layers 400A and 400B, and therefore, the electromagnetic interference of the semiconductor package 4 may be blocked more fully. The third mask layer may be provided on the second mask layer 400B. The number of mask layers 400A and 400B can be variously modified. The total thickness of the mask layers 400A and 400B can be adjusted by adjusting the number of the mask layers 400A and 400B.

FIG. 6 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Hereinafter, for easy and convenient explanation, the description of the same elements as mentioned above will be omitted or briefly mentioned.

Referring to FIG. 6, the semiconductor package 5 may include a substrate semiconductor wafer 200, a molding layer 300, a first mask layer 400A' and a second mask layer 400B'. The first mask layer 400A' may include metal particles 410A', a conductive carbon material 420A, and a polymer 430A. The metal particles 410A' include first particles 411A and second particles 412A. The second mask layer 400B' may include metal particles 410B', a conductive carbon material 420B, and a polymer 430B. The metal particles 410B' include first particles 411B and second particles 412B. The metal particles 410A' and 410B', the conductive carbon materials 420A and 420B, and the polymers 430A and 430B may be substantially the same as the metal particles 410', the conductive carbon material 420, and the polymer 430 as described with reference to FIGS. 4A and 4B, respectively.

FIG. 7 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Hereinafter, for easy and convenient explanation, the description of the same elements as mentioned above will be omitted or briefly mentioned.

Referring to FIG. 7, the semiconductor package 6 may include a substrate 100, a semiconductor wafer 200, a molding layer 300 and a mask layer 400. The substrate 100 may have a top surface 100a and a bottom surface 100b opposite to each other. The semiconductor wafer 200 and the molding layer 300 may be substantially the same as described with reference to FIGS. 1A and 1B. The ground structures 110, 111, and 112 may include a ground pattern 110, an upper ground via 111, and a lower ground via 112A and 112B. A plurality of lower ground vias 112A and 112B may be provided. The lower ground vias 112A and 112B may include a first lower ground via 112A and a second lower ground via 112B. The first lower ground via 112A and the second lower ground via 112B may be electrically connected to the ground pattern 110. The ground terminal 131 may be provided on the bottom surface of the second lower ground via 112B. The ground pattern 110 may be spaced apart from the sidewall 100c of the substrate 100. Alternatively, in some embodiments, the ground pattern 110 may extend to the sidewall 100 c of the substrate 100 so as to be electrically connected to the mask layer 400. The signal pattern 120 may be electrically isolated from the ground pattern 110 and the mask layer 400.

The mask layer 400 may further extend onto the bottom surface 100b of the substrate 100 and may be connected to the first lower ground via 112A. The mask layer 400 may be grounded through the first lower ground via 112A, the ground pattern 110, the second lower ground via 112B, and the ground terminal 131. The mask layer 400 may have holes 115 exposing the terminals 131 and 132. The mask layer 400 may be separated from the terminals 131 and 132.

FIG. 8 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Hereinafter, for easy and convenient explanation, the description of the same elements as mentioned above will be omitted or briefly mentioned.

Referring to FIG. 8, the semiconductor package 7 may include a substrate 100, a semiconductor wafer 200, a molding layer 300, and a mask layer 400'. The semiconductor wafer 200 and the molding layer 300 may be substantially the same as described with reference to FIGS. 1A and 1B. The substrate 100 may be substantially the same as described with reference to FIG. 7.

The mask layer 400' may include a conductive carbon material 420, a polymer 430, and metal particles 410' including first particles 411 and second particles 412, as described in FIGS. 4A and 4B. The mask layer 400' may be provided on the molding layer 300. The mask layer 400' may extend onto the bottom surface 100b of the substrate 100 to be connected to the first lower ground via 112A. The mask layer 400' may be grounded through the first lower ground via 112A, the ground pattern 110, the second lower ground via 112B, and the ground terminal 131. The mask layer 400' may have holes 115 exposing the terminals 131 and 132. The mask layer 400' may be separated from the terminals 131 and 132.

FIG. 9 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Hereinafter, for easy and convenient explanation, the description of the same elements as mentioned above will be omitted or briefly mentioned.

Referring to FIG. 9, the semiconductor package 8 may include a substrate 100, a semiconductor wafer 200, a molding layer 300 and a mask layer 400. The semiconductor wafer 200 may be substantially the same as described with reference to FIGS. 1A and 1B.

The ground structures 110, 111A, 111B, and 112 may include a ground pattern 110, upper ground vias 111A and 111B, and a lower ground via 112. The upper ground vias 111A and 111B may include a first upper ground via 111A and a second upper ground via 111B. The first upper ground via 111A may be substantially the same as the upper ground via 111 as described with reference to FIGS. 1A and 1B. For example, the first upper ground via 111A may be connected to the ground interposer 210. When viewed from a plan view, the second upper ground via 111B may be disposed in the edge portion of the substrate 100. When viewed from a plan view, the second upper ground via 111B may be spaced apart from the molding layer 300. The ground pattern 110 may include a plurality of ground patterns, and the first and second upper ground vias 111A and 111B may be connected to ground patterns 110 different from each other. Unlike FIG. 9, one ground pattern 110 may be connected to the first upper ground via 111A and the second upper ground via 111B.

The molding layer 300 may be disposed on the top surface 100 a of the substrate 100. The width of the molding layer 300 may be smaller than the width of the substrate 100. That is, the molding layer 300 may expose a portion (for example, an edge portion) of the substrate 100. The molding layer 300 may expose at least a part (for example, the second upper ground via 111B) of the ground structures 110, 111A, 111B, and 112.

The mask layer 400 may be disposed on the molding layer 300. The mask layer 400 may extend onto the top surface 100a of the substrate 100 exposed by the molding layer 300, and may be connected to the second upper ground via 111B. The mask layer 400 may be grounded through the second upper ground via 111B, the ground pattern 110, the lower ground via 112, and the ground terminal 131. In some embodiments, the mask layer 400 may further extend to the sidewall 100c of the substrate 100. But the inventive concept is not limited to this.

FIG. 10 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Hereinafter, for easy and convenient explanation, the description of the same elements as mentioned above will be omitted or briefly mentioned.

10, the semiconductor package 9 may include a substrate 100, a semiconductor wafer 200, a mold layer 300, and a mask layer 400'. The semiconductor wafer 200 may be substantially the same as described with reference to FIGS. 1A and 1B. The substrate 100, the ground structures 110, 111A, 111B, and 112, and the molding layer 300 may be substantially the same as described with reference to FIG. 9.

The mask layer 400' may include a conductive carbon material 420, a polymer 430, and metal particles 410' including first particles 411 and second particles 412, as described in FIGS. 4A and 4B. The mask layer 400' may extend to the top surface 100a of the substrate 100 exposed by the molding layer 300, and may be connected to the second upper ground via 111B. The mask layer 400' may be grounded through the second upper ground via 111B, the ground pattern 110, the lower ground via 112, and the ground terminal 131. In some embodiments, the mask layer 400' may further extend to the sidewall 100c of the substrate 100. But the inventive concept is not limited to this.

According to some example embodiments, the mask layer may prevent electromagnetic interference (EMI) of the semiconductor package. The metal particles can be physically connected to each other. The conductive carbon material may be physically connected to the metal particles and electrically connected to the metal particles. Therefore, the resistance of the mask layer may decrease. Since the resistance of the mask layer is reduced, it is possible to improve the EMI shielding characteristics of the mask layer.

According to some example embodiments, a mark having visibility may be formed on the semiconductor package.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

1, 2, 3, 4, 5, 6, 7, 8, 9. 101‧‧‧Packaging substrate 110‧‧‧Ground pattern 111‧‧‧Upper ground via 111A‧‧‧First upper ground via 111B‧‧‧Second upper ground via 112‧‧‧Lower ground via 112A‧ ‧‧First lower ground through hole 112B‧‧‧Second lower ground through hole 115‧‧‧Hole 120‧‧‧Signal pattern 121‧‧‧Upper signal through hole 122‧‧‧Lower signal through hole 130‧‧‧ Insulation layer 131. ‧‧‧Top surface 301‧‧‧Molded pattern 350‧‧‧Concavity 350a‧‧‧Slanted sidewall 400, 400'‧‧‧Mask layer 400A, 400A'‧‧‧First mask layer 400B, 400B'‧ ‧‧Second mask layer 400P‧‧‧Preliminary mask layer 401‧‧‧First part 401a‧‧‧First top surface 402‧‧‧Second part 402a‧‧‧Second top surface 410, 410'‧‧ ‧Metal particles 410A, 410A'‧‧‧First metal particles 410B, 410B'‧‧‧Second metal particles 411, 411A‧‧‧First particles 412, 412B‧‧‧Second particles 420‧‧‧Conductive carbon materials 420A‧‧‧First conductive carbon material 420B‧‧‧Second conductive carbon material 430‧‧‧Polymer 430A‧‧‧First polymer 430B‧‧‧Second polymer 431‧‧‧Modified polymer 450 ‧‧‧Mark 600‧‧‧Electromagnetic wave D1‧‧‧Depth θ1, θ2‧‧‧Angle.

The above and/or other aspects will become clearer by describing certain example embodiments with reference to the accompanying drawings, in which: FIG. 1A is a plan view illustrating a semiconductor package according to an example embodiment. Fig. 1B is a cross-sectional view taken along the line I-II of Fig. 1A. FIG. 1C is an enlarged view of area III of FIG. 1B. FIG. 1D is an enlarged plan view illustrating the top surface of the mask layer according to example embodiments. FIG. 1E is an enlarged view of area IV of FIG. 1B. 2A, 2B, and 2C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to example embodiments. FIG. 2D is an enlarged view of area III' of FIG. 2C. FIG. 3A is a cross-sectional view illustrating a semiconductor package according to example embodiments. 3B and 3C are enlarged cross-sectional views illustrating a method for forming a mark of a semiconductor package according to example embodiments. 3D is an enlarged cross-sectional view illustrating a method for forming a mark of a semiconductor package according to example embodiments. 4A is a cross-sectional view illustrating a semiconductor package according to example embodiments. 4B is an enlarged view of region III" of FIG. 4A. FIG. 5 is a cross-sectional view illustrating a semiconductor package according to an example embodiment. FIG. 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment. FIG. 7 is an illustration according to an embodiment Cross-sectional view of a semiconductor package. Fig. 8 is a cross-sectional view illustrating a semiconductor package according to an embodiment. Fig. 9 is a cross-sectional view illustrating a semiconductor package according to an embodiment. Fig. 10 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

9‧‧‧Semiconductor packaging

100‧‧‧Base

100a‧‧‧Top surface

100b‧‧‧Bottom surface

100c‧‧‧ side wall

110‧‧‧Ground pattern

111A‧‧‧First upper ground through hole

111B‧‧‧Second upper ground through hole

112‧‧‧Bottom ground through hole

120‧‧‧Signal pattern

121‧‧‧Upper signal through hole

122‧‧‧Lower signal through hole

130‧‧‧Insulation layer

131‧‧‧Ground terminal

132‧‧‧Signal terminal

200‧‧‧Semiconductor chip

210‧‧‧Grounding Intermediary

220‧‧‧Signal Intermediary

250‧‧‧Integrated circuit layer

300‧‧‧Molding layer

350‧‧‧Sag

400'‧‧‧Mask layer

410'‧‧‧Metal particles

411‧‧‧The first particle

412‧‧‧Second Particle

420‧‧‧Conductive carbon material

430‧‧‧Polymer

450‧‧‧Mark

Claims (25)

A method for manufacturing a semiconductor package, the method comprising: providing a package including a ground pattern; and forming a mask layer disposed on the top surface and sidewalls of the package and electrically connected to the The ground pattern, wherein the mask layer includes: metal particles connected to each other, the metal particles including: first particles; and second particles, which have an aspect ratio greater than that of the first particles; and a conductive carbon material , Which is connected to at least one of the metal particles. The method for manufacturing a semiconductor package as described in the first item of the scope of patent application further includes: before the formation of the mask layer, forming a recess on the top surface of the package, wherein the mask A first portion of the layer is provided on the top surface of the package outside the recess, wherein the second portion of the mask layer is provided on the recess, and wherein the first portion has a first top surface , And the second part has a second top surface extending in an oblique direction with respect to the first top surface. The method for manufacturing a semiconductor package as described in the scope of the patent application, wherein the intensity of the light reflected from the second part of the mask layer is different from the intensity of the light reflected from the first part of the mask layer The intensity of light, wherein the depth of the recess is at least 20 μm, and wherein the angle between the first top surface and the second top surface is in the range of 130 degrees to 160 degrees. The method for manufacturing a semiconductor package as described in claim 3, wherein each of the first part of the mask layer and the second part of the mask layer includes the metal particles and The conductive carbon material, and wherein the composition ratio of the first part is the same as the composition ratio of the second part. The method for manufacturing a semiconductor package as described in claim 1, wherein the mask layer includes a first part and a second part, and wherein the method further includes irradiating light to the first part of the mask layer On the second part without exposing the first part of the mask layer to the light, wherein the light has a wavelength of 495nm to 570nm, wherein the mask layer further includes titanium oxide, and wherein the mask The first portion of the layer reflects light having a first wavelength, and wherein the second portion of the mask layer reflects light having a second wavelength different from the first wavelength. The method for manufacturing a semiconductor package as described in claim 1, wherein the aspect ratio of the second particle is 5 to 20 times the aspect ratio of the first particle Scope. The method for manufacturing a semiconductor package as described in the first item of the scope of the patent application, wherein the mask layer further includes a hydrophilic polymer, and wherein the mask layer has a hydrophobic property. The method for manufacturing a semiconductor package as described in item 1 of the scope of patent application, wherein the conductive carbon material is covalently bonded to the metal particles. A method for manufacturing a semiconductor package, the method comprising: providing a package including a substrate, a semiconductor wafer, and a molding layer, the substrate including a ground pattern exposed at one surface of the substrate; and A solution containing metal particles and a conductive carbon material is coated on the molding layer to form a mask layer, wherein the mask layer includes: the metal particles, in which at least some of the metal particles are directly connected to each other; and connected to The conductive carbon material of at least one of the metal particles, and wherein the mask layer extends to the one surface of the substrate and is electrically connected to the ground pattern. The method for manufacturing a semiconductor package as described in item 9 of the scope of patent application, which further includes forming a depression on the surface of the molding layer before the coating of the solution, and wherein the method is provided in the The intensity of light reflected by the mask layer on the recess is weaker than the intensity of light reflected from the mask layer provided outside the recess. As described in item 9 of the scope of patent application, the method for manufacturing a semiconductor package further includes: heat-treating the mask layer at a temperature of 150 degrees Celsius to 300 degrees Celsius. As described in item 9 of the scope of patent application, the method for manufacturing a semiconductor package further includes forming a hydrophilic functional group on the molding layer, wherein the solution has hydrophilic properties. The method for manufacturing a semiconductor package as described in claim 12, wherein the formation of the hydrophilic functional group includes performing a plasma treatment process on the molding layer, wherein the mask layer further includes hydrophilic And wherein the hydrophilic polymer is provided in the gap between the molded layer and the conductive carbon material and in the gap between the molded layer and the metal particles. The method for manufacturing a semiconductor package as described in item 9 of the scope of patent application, wherein the substrate further includes a signal pattern electrically insulated from the mask layer, and wherein the signal pattern is not located on the one of the substrates. The surface is exposed. According to the method for manufacturing a semiconductor package according to claim 9, wherein the metal particles include: first metal particles; and second metal particles having an aspect ratio greater than that of the first metal particles, wherein The second metal particles are in contact with the first metal particles. As described in item 9 of the scope of patent application, the method for manufacturing a semiconductor package further includes: heat-treating the mask layer to bond the conductive carbon material to the metal particles, wherein at least some of the metal particles They are directly connected to each other during the heat treatment of the mask layer. A semiconductor package includes: a substrate including a ground structure exposed at one surface of the substrate; a semiconductor wafer on the substrate; a molding layer provided on the substrate, the mold A plastic layer covering the semiconductor wafer; and a mask layer provided on the one surface of the mold layer and the substrate, the mask layer being in contact with the ground pattern, wherein the mask layer includes : Metal particles, which are directly connected to each other; and The conductive carbon material is connected to at least one of the metal particles. The semiconductor package according to claim 17, wherein the surface of the molding layer has a recess with a depth of at least 20 μm, wherein the first part of the mask layer is provided outside the recess, wherein the mask The second portion of the layer is provided on the recess, and the angle between the top surface of the first portion of the first mask layer and the top surface of the second portion of the first mask layer It ranges from 130 degrees to 160 degrees. The semiconductor package described in claim 18, wherein the second portion of the mask layer provided on the recess has a wavelength different from that of the light reflected from the mask provided outside the recess The wavelength of the light reflected by the first part of the mask layer, and wherein the mask layer further includes titanium oxide. The semiconductor package according to claim 17, wherein the metal particles include: a first particle; and a second particle having an aspect ratio greater than that of the first particle, wherein the second particle contacts the The first particle. The semiconductor package according to claim 17, wherein the conductive carbon material is covalently bonded to at least one metal particle among the metal particles, and wherein at least two of the metal particles aggregate with each other. According to the semiconductor package described in claim 17, wherein the substrate further includes: a signal pattern disposed therein, wherein the signal pattern is electrically insulated from the mask layer. The semiconductor package according to claim 17, wherein the one surface of the substrate includes a sidewall of the substrate, and wherein the semiconductor wafer and the mold layer are disposed on the top surface of the substrate . The semiconductor package according to claim 17, wherein the one surface of the substrate includes the bottom surface of the substrate, and wherein the semiconductor wafer and the mold layer are disposed on the top surface of the substrate superior. The semiconductor package according to claim 17, wherein the molding layer is disposed on the one surface of the substrate and exposes at least a part of the ground structure.

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