TWI732141B - Enhancement-mode high electron mobility transistors and manufacturing methods thereof - Google Patents

Abstract

A High Electron Mobility Transistor (HEMT) includes a channel layer, a first barrier layer, a depletion layer, a source electrode, a drain electrode and a gate electrode. The first barrier layer is formed on the channel layer and includes a surface and a recess extended from the surface, wherein, along an upward direction from channel layer, the first barrier layer includes a first barrier sublayer, a second barrier sublayer and a third barrier sublayer sequentially stacked on the channel layer. The depletion layer is formed on the first barrier layer, covers the recess in the barrier layer, and extends to cover a portion of the surface of the barrier layer. The source electrode and the drain electrode are respectively formed on the barrier layer, and the gate electrode is formed on the depletion layer and between the source electrode and the drain electrode. The first barrier sublayer, the second barrier sublayer and the third barrier sublayer respectively include a material selected from one of AlGaN, AlInN and AlGaInN, and respectively include a first Al content, a second Al content and a third Al content. The third Al content is less than the first Al content and the second Al content, which are mutually different.

Description

Enhanced high electron mobility transistor and related manufacturing method

This manual is about a high electron mobility transistor (High Electron Mobility Transistor, HEMT) and its manufacturing method; especially about an enhanced high electron mobility transistor (enhancement-mode HEMT, E-mode HEMT) and its manufacturing method .

The structure of the HEMT generally has a channel layer, a barrier layer formed on the channel layer, a source electrode, a drain electrode, and a gate electrode formed on the barrier layer, respectively. By applying a bias to the gate electrode, the two-dimensional electron gas (2DEG) concentration of the channel layer under the gate electrode can be adjusted to achieve the effect of switching HEMT. The structure of the HEMT generally has a channel layer, a barrier layer formed on the channel layer, a source electrode, a drain electrode, and a gate electrode formed on the barrier layer, respectively. By applying a bias to the gate electrode, the two-dimensional electron gas (2DEG) concentration of the channel layer under the gate electrode can be adjusted to achieve the effect of switching HEMT.

The main feature of HEMT is to use a heterojunction formed by contacting materials with different lattice constants to produce 2DEG adjacent to the heterojunction. For example, aluminum gallium nitride (AlGaN) and gallium nitride (GaN) are two materials used to form heterojunctions. material. The phenomenon of spontaneous polarization and piezoelectric polarization caused by the stack of AlGaN and GaN materials causes the energy band at the heterojunction formed between the two to be bent, and the GaN layer 2DEG is generated near the junction, where 2DEG can provide high electron mobility and low impedance. Therefore, HEMT with 2DEG is very suitable for high-speed and high-power circuit applications.

The HEMT can be classified into a depletion-mode HEMT (D-mode HEMT) or an enhanced HEMT (E-mode HEMT) depending on whether a negative bias is required to deplete the 2DEG. The enhanced HEMT depletes the 2DEG in the channel layer under the gate electrode through the process, so that there is no electrical connection between the source electrode and the drain electrode of the HEMT without applying a positive bias. At this time, the enhanced HEMT is in A normally-off state, so the enhanced HEMT can also be referred to as a normally-off HEMT (normally-off HEMT). The conventional method of manufacturing an enhanced HEMT is to insert a P-type depletion layer between the gate electrode and the barrier layer. Due to the reverse polarization effect of the P-type depletion layer, the 2DEG in the channel layer under the gate electrode is depleted, and the 2DEG that electrically connects the source electrode and the drain electrode is interrupted under the gate electrode. Therefore, to manufacture this type of enhanced HEMT, the barrier layer cannot be too thick. However, such a thin barrier layer will cause the 2DEG concentration under the non-gate electrode (that is, between the source electrode or drain electrode and the gate electrode) to be low, so that when the enhanced HEMT is turned on by applying a positive bias, it will be The low concentration of 2DEG in the channel layer causes the problem of too high component impedance.

A high-electron mobility transistor includes a channel layer; a first barrier layer is formed on the channel layer. The first barrier layer includes a surface and a recessed area extending from the surface to the channel layer. In the upward direction of the channel layer, the first barrier layer includes a first barrier sublayer on the channel layer, A second barrier sublayer is on the first barrier sublayer, and a third barrier sublayer is on the second barrier sublayer; a depletion layer is formed on the barrier layer, wherein the depletion layer covers the first barrier layer The recessed area, and extends to cover a part of the surface of the first barrier layer; a source electrode and a drain electrode are respectively formed on the barrier layer; and a gate electrode is formed on the depletion layer and is located on the source electrode And the drain electrode; wherein the materials of the first barrier sublayer, the second barrier sublayer, and the third barrier sublayer respectively include one selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride Material, and the first barrier sub-layer, the second barrier sub-layer, and the third barrier sub-layer respectively have a first aluminum content, a second aluminum content, and a third aluminum content. The third aluminum content is lower than the first aluminum content and the second aluminum content, and the first aluminum content is different from the second aluminum content.

12: Base

14: Buffer layer

16: channel layer

18, 18a, 18b: barrier layer

18-1: Surface

19: Semiconductor layer

20: Depleted layer

21: Gate electrode

22: Source electrode

24: Drain electrode

26: Heterojunction

28: 2DEG

100, 200, 300, 400: HEMT

181: The first barrier sublayer

182: The second barrier sublayer

183: The third barrier sublayer

186: The second barrier layer

184: The first etch stop layer

185: second etch stop layer

L1: width

L2: width

LD: distance

LTP: width

PR1, PR2: patterned etching protection layer

REC: recessed area

REC1: The first recessed area

REC2: The second recessed area

REC3: The third recessed area

TP: overlapping area

FIG. 1 shows a schematic cross-sectional view of a HEMT 100 according to an embodiment of the disclosure.

2A to 2I are schematic cross-sectional views of the HEMT 100 at various stages of the manufacturing process.

3 to 5 respectively show schematic cross-sectional views of HEMTs according to other embodiments of the present disclosure.

Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings, so that those skilled in the art can fully understand the spirit of the present disclosure. The present disclosure is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some same symbols, which indicate components with the same or similar structure, function, and principle, and those with general knowledge and ability in the industry can follow Inferred according to the teaching of this manual. For the sake of simplicity in the description, the elements with the same symbols will not be repeated. Furthermore, when it is mentioned that a first material layer is located on or on a second material layer, it includes the case where the first material layer is in direct contact with the second material layer. Or, there may be one or more other material layers spaced apart. In this case, the first material layer and the second material layer may not be in direct contact. Here, the terms "about" and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, which means that the meaning of "about" and "approximately" can still be implied in the absence of specific instructions. In addition, the terms "layer" and "layer type" usually mean a material with a specific thickness in a region, which can be composed of a single layer or a plurality of sub-layers, as long as the composition provides the same function.

FIG. 1 shows a schematic cross-sectional view of a HEMT 100 according to an embodiment of the disclosure. The HEMT 100 includes a substrate 12, which may include a semiconductor material or a non-semiconductor material. The semiconductor material includes silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs); The material contains sapphire (Al2O3). In one embodiment, the silicon material is selected as the base material of the high-power device because it has high heat conduction and better heat dissipation characteristics. Moreover, when the substrate 12 is a silicon substrate, the HEMT 100 can also be integrated with silicon-based semiconductor devices, such as N-type and P-type metal oxide semiconductor devices or complementary metal oxide semiconductor devices (CMOS).

Then, a buffer layer 14, a channel layer 16, and a barrier layer 18 are epitaxially formed on the substrate 12. In this embodiment, the thickness of the buffer layer 14 is about 0.1 μm-10 μm. Since the semiconductor material of the channel layer 16 to be formed subsequently has a different lattice constant and thermal expansion coefficient from the material used as the substrate 12, the buffer layer 14 is provided to reduce the difference in thermal expansion coefficient. Strain, and reduce the lattice defects that may be caused by the mismatch of lattice constants. The buffer layer 14 may be a single layer or a laminated structure composed of multiple sub-layers. Suspend When the punch layer 14 is a single layer, its material may be a single material. When the buffer layer 14 is a laminated layer composed of a plurality of sub-layers, the material of each sub-layer may be different. In one embodiment, the material of the buffer layer 14 is selected from the group consisting of gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInN). AlInGaN) is a group of materials. For example, the buffer layer 14 may be a stack formed by alternately stacking aluminum gallium nitride (AlGaN) layers and gallium nitride (GaN) layers. In addition, the buffer layer 14 can be doped with other elements such as carbon, wherein the concentration of carbon doping can be gradually or fixed according to the growth direction. The buffer layer 14 near the substrate 12 may further include a nucleation layer (not shown). For example, the nucleation layer may be composed of a single material, such as AlN, with a thickness of about 50nm~500nm, or it may be a low temperature The AlN sub-layer (thickness about 40nm) grown by epitaxial growth and a high-temperature epitaxially grown AlN sublayer (about 150nm thick) are alternately stacked to form a laminated structure.

As shown in FIG. 1, the channel layer 16 is located on the buffer layer 14. The channel layer 16 is composed of a compound formed from elements of groups III-V on the periodic table, which has a first lattice constant and has a thickness ranging from about 50 nm to about 10 μm. In this embodiment, the material of the channel layer 16 includes indium gallium nitride (In _x Ga _1-x N, 0≦x<1). The barrier layer 18 is formed on the channel layer 16. The barrier layer 18 is composed of a compound formed from elements of group III-V on the periodic table, and has a second lattice constant smaller than the first lattice constant, In this embodiment, the material of the barrier layer 18 includes a ternary material of aluminum gallium nitride (AlGaN) or aluminum indium nitride (AlInN), or a quaternary material of aluminum indium gallium nitride (AlInGaN). The barrier layer 18 may be a single layer composed of a single material, or a stack composed of multiple sub-layers of different materials. In one embodiment, the barrier layer 18 is a stack composed of multiple sub-layers, and the barrier layer 18 includes a first barrier sub-layer 181, a second barrier sub-layer 182, and a third barrier sub-layer 183 . The materials of the first barrier sub-layer 181, the second barrier sub-layer 182, and the third barrier sub-layer 183 respectively include one selected from AlGaN, AlInN or AlInGaN, wherein the first barrier sub-layer 181 and the second barrier sub-layer 182 , And the third barrier sub-layer 183 respectively have a first aluminum content, a second aluminum content, and a third aluminum content. For example, the first barrier sublayer 181 includes Al _x Ga _1-x N (0.15≦x≦0.5) material, the second barrier layer 182 includes Al _y Ga _1-y N (0≦y≦0.3) material, and the third barrier layer 182 includes Al y Ga 1-y N (0≦y≦0.3) material. The barrier sublayer 183 includes Al _z Ga _1-z N (≦z≦0.15) material. In order to make the surface of the barrier layer 18 of the HEMT 100 have fewer surface traps and lower dynamic RON, the third aluminum content of the third barrier sublayer 183 needs to be lower than that of the first barrier layer. The first aluminum content of the barrier layer 181 and the second aluminum content of the second barrier layer 182. In addition, the first aluminum content of the first barrier sublayer 181 and the second aluminum content of the second barrier sublayer 182 may be the same or different. In one embodiment, the thickness of the first barrier sub-layer 181 may be between 1 nm and 20 nm, the thickness of the second barrier sub-layer 182 may be between 20 nm and 100 nm, and the thickness of the third barrier sub-layer 183 may be between 20 nm Between and 200nm. The barrier layer 18 and the channel layer 16 are caused by the spontaneous polarization and piezoelectric polarization between each other to cause the band bending and discontinuity at the heterojunction 26, so that the channel layer 16 forms two near the junction. Dimensional electronic gas 28.

Referring to FIG. 1, the barrier layer 18 has a recessed area REC, which extends recessed from the surface 18-1 of the barrier layer 18 toward the channel layer 16, and exposes a part of the first barrier sublayer 181. According to the depth, the recessed area REC can be roughly divided into a first recessed area REC1 and a second recessed area REC2. The depth of the second recessed area REC2 is greater than the depth of the first recessed area REC1, and is in the first recessed area REC1 and the second recessed area. A stepped structure is formed between the REC2, and the thickness of the stepped structure is about the thickness of the second barrier sublayer 182. In addition, the depth of the first recessed area REC1 is approximately the thickness of the third barrier sublayer 183, and the depth of the second recessed area REC2 is approximately the sum of the thicknesses of the third barrier sublayer 183 and the second barrier sublayer 182. At the bottom of the first recessed region REC1, a part of the second barrier sublayer 182 is exposed, and at the bottom of the second recessed region REC2, a part of the first barrier sublayer 181 is exposed.

A depletion layer 20 is formed on the barrier layer 18 and covers the recessed area REC of the barrier layer 18 and also covers the overlap area TP adjacent to the recessed area REC, as shown in FIG. 1. The depletion layer 20 has a reverse polarization effect on the first barrier layer 181, and therefore can reduce or deplete the electron concentration of the two-dimensional electron gas 28 in the channel layer 16 directly below it. In this way, the later formed HEMT 100 will be in a non-conducting state when no bias is applied, that is, the HEMT 100 is a normally-off HEMT. The material of the depletion layer 20 includes p-type III-V semiconductor materials, such as magnesium (Mg) doped gallium nitride (GaN), magnesium, beryllium (Be), zinc (Zn), or cadmium (Cd) doped hexagonal crystals Based on boron nitride (hexagonal-BN, hBN), or containing p-type II-VI group semiconductor materials, for example, hexagonal zinc oxide (ZnO) doped with nitrogen (N) or phosphorus (P). In this embodiment, the depletion layer 20 is a magnesium-doped gallium nitride layer with a thickness between 50 nm and 300 nm, wherein the doping concentration of magnesium is between 1 ^{×10 19} atoms/cm ³ and 1 ^{×10 21} atoms/cm Between ^3.

The source electrode 22 and the drain electrode 24 are formed on the barrier layer 18 on both sides of the depletion layer 20. Through an annealing process, the source electrode 24 and the drain electrode 24 can form a low-resistance electrical contact with the barrier layer 18 below it, for example Ohmic contact. The material of the drain electrode 24 and the source electrode 22 includes one or more conductive materials, such as metals or metals selected from the group consisting of titanium (Ti), aluminum (Al), nickel (Ni), or gold (Au) An alloy formed from the above-mentioned metals.

The gate electrode 21 is formed on the depletion layer 20 and is located between the source electrode 22 and the drain electrode 24. The material of the gate electrode 21 includes one or more layers of conductive materials, such as metal materials such as aluminum, tantalum (Ta), tungsten (W), nickel (Ni), gold (Au), or platinum (Pt), or formed of the above-mentioned metal materials. Alloy, or compound materials such as tantalum nitride (TaN), titanium nitride (TiN) and tungsten silicide (WSi _{2 ).}

Referring to Figure 1, on the surface 18-1 of the barrier layer 18, the overlap area TP where the depletion layer 20 overlaps the barrier layer 18, because the thickness of the barrier layer 18 includes the first barrier layer 181 and the second barrier layer The thickness of the layer 182 and the third barrier sublayer 183 is compared with the recessed area REC, the depletion layer 20 is farther away from the heterojunction 26 in the overlap area TP, so that the 2DEG 28 of the channel layer 16 is affected by the reverse polarization of the depletion layer 20 very Micro, to maintain a certain concentration. At the same time, in the second recessed region REC2, because the depletion layer 20 has a reverse polarization effect for the first barrier layer 181, the 2DEG 28 in the channel layer 16 directly below it can be depleted. In addition, in the first recessed region REC1, because the depletion layer 20 and the channel layer 16 are separated by the first barrier sublayer 181 and the second barrier sublayer 182, compared with the second recessed region REC2, the first recessed region REC1 The concentration of 2DEG 28 is less affected by the depletion layer 20 and will not be depleted. Therefore, the concentration of the 2DEG 28 in the channel layer 16 adjacent to the heterojunction 26 will show a gradient change in the range from the second recessed region REC2 through the first recessed region REC1 to the overlap region TP, that is, from nothing to light. Then it becomes richer, as shown in Figure 1. In this way, the depletion layer 20 at the mesa of the step structure of the first recessed area REC1 and the depletion layer 20 in the overlapping area TP can be regarded as the function of a field plate, which is used to reshape the gate of the HEMT 100 The electric field between the electrode 21 and the drain electrode 24 reduces the peak value of the electric field at the edge of the gate electrode 21 close to the drain electrode 24 to increase the breakdown voltage and reduce the electron trapping effect.

Referring to Figure 1, the width L2 of the second recessed area REC2 is between 0.2 μm and 5 μm; the width L1 of the first recessed area REC1 is between 0.5 μm and 3 μm; The width LTP is between 0.5 μm and 5 μm; and the distance LD between the drain electrode 24 and the depletion layer 20 is between 3 μm and 30 μm. In this embodiment, the width L2 of the second recessed area REC2 is 1.5 μm; the width L1 of the first recessed area REC1 is 1 μm; the width LTP of the overlapping area TP close to the drain electrode 24 is 2 μm; and the drain electrode 24 reaches the depletion layer The distance LD between 20 is 15 μm.

In the conventional HEMT during the repeated switching process, it is easy to reduce the concentration of part of the 2DEG due to the trapping of electrons on the surface of the barrier layer, so that the current value between the source electrode and the drain electrode will be lower than the initial current value. It is low, causing the so-called current collapse (current collapse), that is, the dynamic on-resistance of the HEMT increases accordingly. In Figure 1, the aluminum content of the third barrier sublayer 183 is in the barrier The sub-layers 181, 182, and 183 are the lowest, so the third barrier sub-layer 183 has better epitaxial quality and lower trap density. In addition, the third barrier sub-layer 183 and the channel layer 16 The first barrier sub-layer 181 and the second barrier sub-layer 182 are separated away from the 2DEG 28. Therefore, the third barrier sub-layer 183 has a limited influence on the concentration of the 2DEG 28 due to the electrons trapped on the surface of the third barrier sub-layer 183. In this way, the HEMT 100 Has lower dynamic on-resistance or less current collapse effect.

2A to 2I are schematic cross-sectional views of the HEMT 100 in FIG. 1 at various stages of the manufacturing process.

Figure 2A shows that the buffer layer 14, the channel layer 16, the first barrier sub-layer 181, the second barrier sub-layer 182, and the third barrier sub-layer 183 are epitaxially grown on the substrate 12. The first barrier sub-layer 181, the second barrier sub-layer 183 The second barrier sublayer 182 and the third barrier sublayer 183 constitute the barrier layer 18. The first barrier sublayer 181 includes Al _x Ga _1-x N material, where the aluminum content x can be between 15% and 50%, and the thickness can be between 1 nm and 20 nm. The second barrier sublayer 182 includes Al _y Ga _1-y N material, where the aluminum content y can be between 0% and 30%, and the thickness can be between 20 nm and 100 nm. The third barrier sublayer 183 includes Al _z Ga _1-z N material, where the aluminum content z can be between 0% and 15%, and the thickness can be between 20 nm and 200 nm.

FIG. 2B is a continuation of FIG. 2A and shows that a patterned etching protection layer PR1 is formed on the barrier layer 18. For example, a photoresist is coated on the barrier layer 18, and then a patterned etching protection layer PR1 is generated after a photolithography process and exposure and development. In another embodiment, the patterned etching protection layer PR1 may be a hard mask layer. For example, the patterned etching protection layer PR1 is a silicon nitride patterned through a lithography and etching process. Floor.

Figure 2C is a continuation of Figure 2B, showing that the patterned etching protection layer PR1 is not protected A schematic cross-sectional view of the third barrier sublayer 183 at the position after being removed. For example, inductively coupled plasma (ICP), reactive-ion etching (RIE), or atomic layer etching (ALE) machines can be used to etch the patterned protective layer The third barrier sublayer 183 in the unprotected area of PR1 is etched to form a recessed area REC and expose part of the second barrier sublayer 182. The result is as shown in FIG. 2C.

Figure 2D is a continuation of Figure 2C, showing that a patterned etching protection layer PR2 is formed on the barrier layer 18 and the etching protection layer PR1 to protect the etching protection layer PR1, the sidewalls of the third barrier sublayer 183 in the recessed area REC and the first A part of the second barrier sub-layer 182, in other words, will expose another part of the second barrier sub-layer 182. The patterned etching protection layer PR2 can be a photoresist layer or a hard mask layer. The material of the patterned etching protection layer PR2 may be the same as or different from the material of the patterned etching protection layer PR1.

FIG. 2E is a continuation of FIG. 2D, showing that the second barrier sublayer 182 at the unprotected portion of the patterned etching protection layer PR2 is removed to form a second recessed area REC2 and expose a portion of the first barrier sublayer 181. As mentioned above, the method of removing the second barrier sublayer 182 where the patterned etching protection layer PR2 is not protected can be ICP, RIE, ALE, or the like. FIG. 2F is a continuation of FIG. 2E, showing a schematic cross-sectional view after removing the patterned protective layer PR1 and the patterned protective layer PR2. For example, the patterned protective layer PR1 and the patterned protective layer PR2 can be removed by wet etching or dry etching, but it is not limited thereto. It can be seen from Figure 2F that the recessed area REC substantially includes the first recessed area REC1 and the second recessed area REC2, wherein the bottom of the first recessed area REC1 exposes a part of the second barrier sublayer 182, and the second recessed area A portion of the first barrier sublayer 181 is exposed at the bottom of REC2, and a step structure is formed between the first recessed area REC1 and the second recessed area REC2.

Figure 2G is a continuation of Figure 2F, showing that the barrier layer 18 is epitaxially grown again (epitaxial regrowth) method to form a semiconductor layer 19 with a thickness between 50 nm and 300 nm. The material of the semiconductor layer 19 includes a p-type III-V group semiconductor material, for example, magnesium-doped gallium nitride, a hexagonal boron nitride doped with magnesium, beryllium, zinc, or cadmium, or a p-type II-VI group semiconductor material Materials such as hexagonal zinc oxide doped with nitrogen or phosphorus. FIG. 2H is a continuation of FIG. 2G, showing a cross-sectional view of the depletion layer 20 formed on the barrier layer 18 after the semiconductor layer 19 is patterned. For example, a photolithography and etching process is used to remove the semiconductor layer 19 away from the recessed area REC, while leaving the semiconductor layer 19 at the recessed area REC and its adjacent area to form the depletion layer 20. As shown in Figure 2H, the depletion layer 20 covers the barrier layer 18 in the recessed area REC, that is, the first barrier layer 181 and the second barrier layer 182, and extends to cover a portion of the surface 18-1 of the barrier layer 18 , That is, on a part of the third barrier sublayer 183 to form an overlapping area TP.

Fig. 2I is a continuation of Fig. 2H, showing that the source electrode 22 and the drain electrode 24 are formed on the surface 18-1 of the barrier layer 18 on both sides of the depletion layer 20. Through the annealing process, the source electrode 24 and the drain electrode 24 form a low-resistance electrical contact, such as an ohmic contact, with the barrier layer 18 thereunder. Following Figure 2I, a gate electrode 21 is formed on the depletion layer 20, and the HEMT 100 in Figure 1 is completed. The material selection of the source electrode 22, the drain electrode 24, and the gate electrode 21 has been described in detail above, and will not be repeated.

FIG. 3 shows a schematic cross-sectional view of a HEMT 200 according to another embodiment of the present disclosure. The same or similarities between FIG. 3 and FIG. 1 can be learned by referring to the teaching of FIG. 1 and will not be repeated. In the previous embodiment, in the etching process for forming the first recessed region REC1, the third barrier sublayer 183 may not be completely removed, or part of the second barrier sublayer 182 may be overetched; Similarly, in the etching process for forming the second recessed region REC2, the second barrier sublayer 182 may not be completely removed, or part of the first barrier sublayer 181 may be overetched. Referring to FIG. 3, one or more etching stop layers are added to the barrier layer 18a, thereby effectively controlling the etching depth in the first recessed region REC1 and the first recessed region REC2. In Figure 3, from bottom to top, the barrier layer 18a sequentially includes the first barrier sublayer 181. The first etch stop layer 184, the second barrier sublayer 182, the second etch stop layer 185, and the third barrier sublayer 183, but not limited to this, in other words, the barrier layer 18a does not necessarily include the first etch stop at the same time Layer 184 and second etch stop layer 185. The material of the first etch stop layer 184 and/or the second etch stop layer 185 includes aluminum nitride (AlN), and the thickness thereof may be between 0.5 nm and 2 nm. In this embodiment, the thickness of the first etch stop layer 184 and the second etch stop layer 185 is 1 nm. In the process of etching the third barrier sub-layer 183 or the second barrier sub-layer 182, the end-point detection (EPD) method can be used to detect the signal of a specific element or the generation of a specific reactant gas to determine Whether it has been etched to the first etch stop layer 184 or the second etch stop layer 185. For example, optical emission spectroscopy (OES) can be used to detect the relative relationship between the signal intensity of Ga and Al. When the signal intensity of Ga decreases significantly or the signal intensity of Al gradually decreases and then increases again, that is It can be clearly known that the third barrier sublayer 183 on the second etch stop layer 185 or the second barrier sublayer 182 on the first etch stop layer 184 has been etched clean, or has reached the etch stop layer to precisely control the etching depth.

FIG. 4 shows a schematic cross-sectional view of a HEMT 300 according to another embodiment of the present disclosure. The same or similarities between Fig. 4 and Figs. 1 and 3 can be learned by referring to the teaching of Figs. 1 and 3, and will not be repeated here. In Figure 4, from bottom to top, the barrier layer 18b sequentially includes a first barrier layer 181, a first etch stop layer 184, a second barrier layer 182, a second etch stop layer 185, and a third barrier layer. Layer 183, and second barrier layer 186. Referring to the process descriptions described in FIG. 3 and FIGS. 2D and 2E, the process of HEMT 300 further includes removing the first barrier sublayer 181 exposed by the second recessed region REC2 to form a third recessed region REC3. The recessed area REC substantially includes a first recessed area REC1, a second recessed area REC2, and a second recessed area REC3. Then, a second barrier layer 186 is formed in the recessed area REC and on the third barrier sublayer 183 by epitaxial re-growth. After that, a depletion layer 20 is formed on the second barrier layer 186 to cover the recessed area REC and a part of the third barrier sublayer 183 correspondingly. As shown in Figure 4. The second barrier layer 186 includes an aluminum gallium nitride material, wherein the content of aluminum is between 0.5% and 20% (that is, Al _w Ga _1-w N, 0.05≦w≦0.2), and the second barrier The thickness of layer 186 may be between 5 nm and 20 nm. In an embodiment, the aluminum content in the second barrier layer 186 is greater than the aluminum content in the third barrier sublayer 183.

Referring to Figure 4, the recessed area REC substantially includes a first recessed area REC1, a second recessed area REC2, and a third recessed area REC3. The depth of the third recessed area REC3 is greater than the depth of the second recessed area REC2, and the second recessed area The depth of REC2 is greater than the depth of the first recessed region REC1. A step structure is formed between the first recessed region REC1 and the second recessed region REC2, and between the second recessed region REC2 and the third recessed region REC3. The depth of the first recessed area REC1 is approximately the thickness of the third barrier sublayer 183, the depth of the second recessed area REC2 is approximately the sum of the thicknesses of the third barrier sublayer 183 and the second barrier sublayer 182, and the third recessed area The depth of REC3 is approximately the sum of the thicknesses of the third barrier sublayer 183, the second barrier sublayer 182, and the first barrier sublayer 181. The bottom of the first recessed region REC1 exposes a part of the second barrier sublayer 182, the bottom of the second recessed region REC2 exposes a part of the first barrier sublayer 181, and the bottom of the third recessed region REC3 exposes a part of the channel layer 16. Next, a source electrode 22, a drain electrode 24 and a gate electrode 21 are formed on the third barrier sublayer 183 and the depletion layer 20, respectively, to complete the HEMT 300. The material selection of the source electrode 22, the drain electrode 24, and the gate electrode 21 has been described in detail above, and will not be repeated.

Compared with the HEMT 100 and the HEMT 200 in FIG. 1 and FIG. 3, the threshold voltage (Vth) of the HEMT 300 in FIG. 4 is relatively stable. The threshold voltage of the HEMT 100 or 200 is affected by the thickness of the first barrier sublayer 181 in the second recessed region REC2. The thickness of the first barrier sublayer 181 in the second recessed region REC2 is determined by the epitaxial thickness of the first barrier sublayer 181 and the subsequent etching process. In contrast, after removing the first barrier sublayer 181, the HEMT 300 epitaxially grows the second barrier layer 186. The threshold voltage of the HEMT 300 is roughly determined by the recessed region The epitaxial thickness of the second barrier layer 186 in REC3 is determined, and is not affected by the subsequent etching process. Compared with the threshold voltage of HEMT 100 and 200 which is determined by the results of the epitaxial process and the etching process, the threshold voltage of HEMT 300 is only determined by the result of the epitaxial process, so it will be more stable.

In the HEMT 100, 200, 300 shown in FIGS. 1, 3, and 4, the barrier layer 18, 18a, or 18b in the recessed area REC near the drain electrode 24 has a stepped structure. Thereby, the depletion layer 20 formed subsequently will form the function of a field plate at the step structure, so that the concentration of the 2DEG28 in the channel layer 16 will correspondingly form a gradient change to reshape the gate electrodes of the HEMT 100, 200, and 300 The electric field between 21 and the drain electrode 24 reduces the peak value of the electric field at the edge of the gate electrode 21 on the side of the drain electrode 24 to increase the breakdown voltage and reduce the electron trapping effect. However, this disclosure is not limited to this. FIG. 5 shows a cross-sectional view of a HEMT 400 according to another embodiment of the present disclosure. In Figure 5, a step structure is formed between both sides of the second recessed region REC2 and the first recessed region REC1. Therefore, the barrier layer 18 is located on both sides of the drain electrode 24 and the source electrode 22 in the recessed region REC. All have a stepped structure.

The foregoing descriptions are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present disclosure should fall within the scope of the present disclosure.

12: Base

14: Buffer layer

16: channel layer

18: barrier layer

18-1: Surface

20: Depleted layer

21: Gate electrode

22: Source electrode

24: Drain electrode

26: Heterojunction

28: 2DEG

100: HEMT

181: The first barrier sublayer

182: The second barrier sublayer

183: The third barrier sublayer

L1: width

L2: width

LD: distance

LTP: width

REC: recessed area

REC1: The first recessed area

REC2: The second recessed area

TP: overlapping area

Claims (10)

A high electron mobility transistor, comprising: a channel layer; a first barrier layer formed on the channel layer, the first barrier layer comprising a surface and a recessed area extending from the surface to the channel layer , Wherein, along a direction upward from the channel layer, the first barrier layer includes a first barrier sublayer on the channel layer, a second barrier sublayer on the first barrier sublayer, and a The third barrier sublayer is on the second barrier sublayer; a depletion layer is formed on the first barrier layer, wherein the depletion layer covers the recessed area of the first barrier layer and extends to cover the second barrier layer A part of the surface of a barrier layer; a source electrode and a drain electrode are respectively formed on the first barrier layer; and a gate electrode is formed on the depletion layer and is located on the source electrode and the drain electrode Between the electrodes; wherein, the material of the first barrier sublayer, the second barrier sublayer, and the third barrier sublayer includes one selected from aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride The material; wherein the first barrier sub-layer, the second barrier sub-layer, and the third barrier sub-layer have a first aluminum content, a second aluminum content, and a third aluminum content, the third The aluminum content is lower than the first aluminum content and the second aluminum content, and the first aluminum content is different from the second aluminum content. For example, the high electron mobility transistor of item 1 of the scope of patent application further includes a first etch stop layer formed between the first barrier sublayer and the second barrier sublayer, or formed on the first barrier sublayer Between the second barrier sublayer and the third barrier sublayer. For example, the high electron mobility transistor of item 1 of the scope of patent application, in which, the The recessed area includes a first recessed area and a second recessed area. The first recessed area and the second recessed area extend downward from the surface and respectively have a first depth and a second depth, and the second depth Greater than the first depth. For example, in the high electron mobility transistor of the first item of the patent application, the depletion layer includes a p-type doped layer. For example, the high electron mobility transistor in the scope of the patent application further includes a second barrier layer, wherein the recessed region exposes a part of the channel layer, and the second barrier layer is formed in the recess Within the region and in contact with the exposed part of the channel layer. For example, the high electron mobility transistor of the fifth item of the scope of patent application, wherein the material of the second barrier layer includes Al _w Ga _1-w N, where w is between 0.05 and 0.2. For example, in the high electron mobility transistor of item 5 of the scope of patent application, the second barrier layer includes a fourth aluminum content that is greater than the third aluminum content of the third barrier sublayer. For example, the high electron mobility transistor of the third item of the scope of patent application, wherein, from a cross-sectional view, a stepped structure is formed at the adjacent portion of the first recessed area and the second recessed area. For example, the high electron mobility transistor of the 8th patent application, wherein the step structure is close to the drain electrode. For example, the high electron mobility transistor of the second patent application, wherein the material of the first etch stop layer includes aluminum nitride.

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