TWI730534B - Power supply circuit and digital input buffer, control chip and information processing device using it - Google Patents
Power supply circuit and digital input buffer, control chip and information processing device using it Download PDFInfo
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Abstract
本發明主要揭示一種供電電路,用於將工作電壓調整為一低壓差工作電壓,從而提供該低壓差工作電壓至一施密特電路單元,使得該施密特電路單元之一邏輯高電平(Logic-high)輸出信號的最小值可以達到1.2 V、1.1V、或1.05V,且同時令該施密特電路單元之一邏輯低電平(Logic-low)輸出信號的最大值可以達到0.6 V。並且,將工作電壓調整為所述低壓差工作電壓時,係同時兼容補償N-MOSFET元件和P-MOSFET元件之工藝角變化,讓最差狀況工藝角SNFP和FNSP改變成SS與FF工藝角,藉此方式調控施密特電路單元之輸入翻轉點電壓,使其在全工藝角範圍內之變化能夠受到有效控制而不會有明顯的變動。 The present invention mainly discloses a power supply circuit for adjusting the working voltage to a low-dropout working voltage, thereby providing the low-dropout working voltage to a Schmitt circuit unit, so that one of the Schmitt circuit units is logic high. -high) The minimum value of the output signal can reach 1.2V, 1.1V, or 1.05V, and at the same time, the maximum value of the logic-low output signal of one of the Schmitt circuit units can reach 0.6V. In addition, when the operating voltage is adjusted to the low dropout operating voltage, it is compatible with compensating the process angle changes of N-MOSFET and P-MOSFET elements at the same time, so that the worst-case process angles SNFP and FNSP are changed to SS and FF process angles. In this way, the input switching point voltage of the Schmitt circuit unit is regulated, so that the change in the full process angle range can be effectively controlled without significant changes.
Description
本發明係關於數位輸入緩衝器之技術領域,尤指應用於提供一低壓差工作電壓至一施密特電路單元的一種供電電路。The present invention relates to the technical field of digital input buffers, and particularly refers to a power supply circuit applied to provide a low dropout operating voltage to a Schmitt circuit unit.
傳統的施密特電路主要是由運算放大器和複數個電阻所組成的一個包含正回饋的比較器電路。就實務應用而言,運算放大器具有體積較大和功耗高的缺點,因此其並不利於應用在集成電路的芯片製造。有鑑於此,一種CMOS施密特電路於是被提出。圖1顯示習知的一種CMOS施密特電路的電路拓樸圖,且圖2為習知的CMOS施密特電路的等效電路符號。如圖1所示,習知的CMOS施密特電路2包括:一第一P型MOSFET元件2M1、一第二P型MOSFET元件2M2、一第一N型MOSFET元件2M3、一第二N型MOSFET元件2M4、一反相器20、一第三P型MOSFET元件2M5、以及一第三N型MOSFET元件2M6。The traditional Schmitt circuit is mainly composed of an operational amplifier and a plurality of resistors, a comparator circuit containing positive feedback. In terms of practical applications, operational amplifiers have the disadvantages of large size and high power consumption, so they are not conducive to application in integrated circuit chip manufacturing. In view of this, a CMOS Schmitt circuit is proposed. FIG. 1 shows the circuit topology of a conventional CMOS Schmitt circuit, and FIG. 2 is the equivalent circuit symbol of the conventional CMOS Schmitt circuit. As shown in FIG. 1, the conventional CMOS Schmitt
更詳細地說明,計算該CMOS施密特電路2之一輸入翻轉點電壓V
INV時,可令該第一P型MOSFET元件2M1和該第二P型MOSFET元件2M2為一相同的P型MOSFET元件,且同時令該第一N型MOSFET元件2M3和該第二N型MOSFET元件2M4為一相同的N型MOSFET元件。如此,在忽略該第三P型MOSFET元件2M5與該第三N型MOSFET元件2M6的元件參數的情況下,可以推導出如下所示之輸入翻轉點電壓V
INV的數學運算式:
。
In more detail, when calculating the input inversion point voltage V INV of the
於前述數學運算式之中,V DD為由一低壓供電電路所提供的工作電壓,V TN和V TP分別N型MOSFET元件與P型MOSFET元件的閥值電壓,且γ=β P/β N,其中β P為P型MOSFET元件的增益因子,其為μ PC OX(W P/L P),而β N為N型MOSFET元件的增益因子,其為μ NC OX(W N/L N)。其中,μ P為反轉層的電洞遷移率,μ N為反轉層的電子遷移率,Cox為閘極氧化層的厚度,W P(W N)為閘極寬度,且L P(L nN)為閘極長度。因此,由前述數學運算式可知,該低壓供電電路所提供的工作電壓V DD、P型MOSFET元件和N型MOSFET元件的元件尺寸、及/或P型MOSFET元件和N型MOSFET元件的閥值電壓皆會影響所述輸入翻轉點電壓V INV的最終數值。 In the foregoing mathematical expressions, V DD is the operating voltage provided by a low-voltage power supply circuit, V TN and V TP are the threshold voltages of N-type MOSFET and P-type MOSFET respectively, and γ=β P /β N , Where β P is the gain factor of the P-type MOSFET element, which is μ P C OX (W P /L P ), and β N is the gain factor of the N-type MOSFET element, which is μ N C OX (W N /L N ). Among them, μ P is the hole mobility of the inversion layer, μ N is the electron mobility of the inversion layer, Cox is the thickness of the gate oxide layer, W P (W N ) is the gate width, and L P (L nN ) is the gate length. Therefore, it can be known from the foregoing mathematical expression that the operating voltage V DD provided by the low-voltage power supply circuit, the element size of the P-type MOSFET element and the N-type MOSFET element, and/or the threshold voltage of the P-type MOSFET element and the N-type MOSFET element Both will affect the final value of the input inversion point voltage V INV.
如圖1所示之CMOS施密特電路2經常被應用為一數位輸入緩衝器,其利用該第三P型MOSFET元件2M5以及該第三N型MOSFET元件2M6令邏輯高電平(Logic-high)輸出信號V
OUT與邏輯低電平(Logic-low)輸出信號V
OUT之間具有一定的遲滯,從而防止反復的高/低電平切換導致輸出信號VOUT在輸入翻轉點附近產生毛刺(glitch)。值得說明的是,由該低壓供電電路所提供的工作電壓V
DD通常被要求在2.5V至5.5V之間,這個工作電壓V
DD的範圍可以讓圖1所示之CMOS施密特電路2所輸出的邏輯低電平(Logic-low)輸出信號V
OUT的最大值為0.6V,且令所輸出的邏輯高電平(Logic-high)輸出信號V
OUT的最小值為2.0V。
The CMOS Schmitt
然而,由該低壓供電電路所提供的範圍為2.5V~5.5V的工作電壓V
DD無法使得邏輯低電平(Logic-low)輸出信號V
OUT的最大值為0.6V以及邏輯高電平(Logic-high)輸出信號V
OUT的最小值為1.5V。有鑑於此,圖3即顯示習知的一種包含低壓差穩壓器的施密特電路。如圖3所示,一低壓差穩壓器(Low-dropout regulator, LDO)3被應用於提供一個低壓差工作電壓V
LDO至所述CMOS施密特電路2,從而使得邏輯低電平(Logic-low)輸出信號V
OUT的最大值為0.6V,且同時令邏輯高電平(Logic-high)輸出信號V
OUT的最小值為1.5V。
However, the working voltage V DD in the range of 2.5V~5.5V provided by the low-voltage power supply circuit cannot make the maximum value of the logic -low output signal V OUT be 0.6V and the logic high level (Logic-low). -high) The minimum value of the output signal V OUT is 1.5V. In view of this, Figure 3 shows a conventional Schmitt circuit including a low dropout voltage regulator. As shown in FIG. 3, a low-dropout regulator (LDO) 3 is applied to provide a low-dropout operating voltage V LDO to the
可惜的是,圖3所示包含低壓差穩壓器的施密特電路並無法同時滿足邏輯低電平(Logic-low)輸出信號V OUT的最大值為0.6V及邏輯高電平(Logic-high)輸出信號V OUT的最小值為1.2V、1.1V或1.05V的要求。因此,應進一步考慮的是,如何選用5V電子元件設計出新式的低壓供電電路,使得包含此新式低壓供電電路的(CMOS)施密特電路能夠同時滿足邏輯低電平(Logic-low)輸出信號V OUT的最大值為0.6V及邏輯高電平(Logic-high)輸出信號V OUT的最小值為1.2V、1.1V或1.05V的要求。 Unfortunately, the Schmitt circuit including the low dropout regulator shown in Figure 3 cannot simultaneously satisfy the logic-low output signal V OUT with a maximum value of 0.6V and a logic high level (Logic-low). high) The minimum value of the output signal V OUT is the requirement of 1.2V, 1.1V or 1.05V. Therefore, further consideration should be given to how to select 5V electronic components to design a new low-voltage power supply circuit so that the (CMOS) Schmitt circuit containing this new low-voltage power supply circuit can simultaneously meet the logic-low output signal The maximum value of V OUT is 0.6V and the minimum value of the logic-high output signal V OUT is 1.2V, 1.1V or 1.05V.
因此,本領域亟需用於數位輸入緩衝器之中的一種新式供電電路。 Therefore, there is an urgent need in the art for a new type of power supply circuit used in digital input buffers.
本發明之主要目的在於提供一種供電電路,其用以將一工作電壓調整成一低壓差工作電壓,並提供該低壓差工作電壓至一施密特電路單元,使得該施密特電路單元之一邏輯高電平(Logic-high)輸出信號的最小值可以達到1.2V、1.1V、或1.05V,且同時令該施密特電路單元之一邏輯低電平(Logic-low)輸出信號的最大值可以達到0.6V。 The main purpose of the present invention is to provide a power supply circuit for adjusting a working voltage to a low-dropout working voltage, and providing the low-dropout working voltage to a Schmitt circuit unit, so that one of the Schmitt circuit units has a logic high The minimum value of the Logic-high output signal can reach 1.2V, 1.1V, or 1.05V, and at the same time, the maximum value of the logic-low output signal of one of the Schmitt circuit units can reach 0.6V.
本發明之另一目的在於提供一種供電電路,其用以將一工作電壓調整為一低壓差工作電壓,調整過程同時兼容補償N型MOSFET元件和P型MOSFET元件之工藝角變化,讓最差狀況工藝角之N型MOSFET元件及P型MOSFET元件從SNFP或FNSP工藝角改變成SS或FF工藝角,藉此方式調控施密特電路單元之輸入翻轉點電壓,使其在全工藝角範圍內之變化能夠受到有效控制而不會有明顯的變動。 Another object of the present invention is to provide a power supply circuit, which is used to adjust a working voltage to a low dropout working voltage. The adjustment process is compatible with compensating for the process angle changes of the N-type MOSFET element and the P-type MOSFET element, so that the worst case The N-type MOSFET element and P-type MOSFET element in the process corner are changed from the SNFP or FNSP process angle to the SS or FF process angle, thereby adjusting the input switching point voltage of the Schmitt circuit unit to make it within the range of the full process angle Changes can be effectively controlled without significant changes.
為達成上述目的,本發明提出所述供電電路之一第一實施例,用於提供一低壓差工作電壓至一施密特電路單元,且其包括:一第一MOSFET元件,以其一汲極端和一源極端分別耦接一工作電壓和一接地端電壓;一電流源,耦接於該第一MOSFET元件的一閘極端和該工作電壓之間;一第二MOSFET元件,以其一源極端同時耦接該電流源與該第一MOSFET元件的該閘極端,且其一汲極端和一閘極端係相互耦接;以及一第一電阻,以其一端同時耦接該第二MOSFET元件的該汲極端和該閘極端,且其另一端耦接該接地端電壓;其中,該第一MOSFET元件的該源極端為所述供電電路的一輸出端,用以提供所述低壓差工作電壓至該施密特電路單元。 In order to achieve the above objective, the present invention proposes a first embodiment of the power supply circuit, which is used to provide a low dropout operating voltage to a Schmitt circuit unit, and it includes: a first MOSFET element with a drain terminal And a source terminal are respectively coupled to a working voltage and a ground terminal voltage; a current source is coupled between a gate terminal of the first MOSFET element and the working voltage; a second MOSFET element with a source terminal thereof Simultaneously coupled to the current source and the gate terminal of the first MOSFET element, and a drain terminal and a gate terminal thereof are coupled to each other; and a first resistor whose one end is simultaneously coupled to the second MOSFET element The drain terminal and the gate terminal, and the other terminal thereof is coupled to the ground terminal voltage; wherein, the source terminal of the first MOSFET element is an output terminal of the power supply circuit for providing the low dropout operating voltage to the application Mitter circuit unit.
在第一實施例中,所述供電電路更包括: 一第二電阻,耦接於該第一電阻和該接地端電壓之間;一第三電阻,耦接於該第一MOSFET元件的該源極端和該接地端電壓之間;一第四電阻,耦接於該第一MOSFET元件的該汲極端和該工作電壓之間;以及一電容,耦接於該第一MOSFET元件的該閘極端和該接地端電壓之間;其中,該電流源包含一電阻以及跨於該電阻的一帶隙參考電壓。 In the first embodiment, the power supply circuit further includes: A second resistor, coupled between the first resistor and the ground terminal voltage; a third resistor, coupled between the source terminal of the first MOSFET element and the ground terminal voltage; a fourth resistor, Coupled between the drain terminal of the first MOSFET element and the operating voltage; and a capacitor, coupled between the gate terminal of the first MOSFET element and the ground terminal voltage; wherein, the current source includes a Resistance and a band gap reference voltage across the resistance.
為達成上述目的,本發明進一步提出所述供電電路之一第二實施例,用於提供一低壓差工作電壓至一施密特電路單元,且其包括:一第一MOSFET元件,以其一汲極端和一源極端分別耦接一工作電壓和一接地端電壓;一電流源,耦接於該第一MOSFET元件的一閘極端和該工作電壓之間;以及一第二MOSFET元件,以其一源極端同時耦接該電流源與該第一MOSFET元件的該閘極端,以其一汲極端耦接該接地端電壓,且以其一閘極端耦接一箝制參考電壓;其中,該第一MOSFET元件的該源極端為所述供電電路的一輸出端,用以提供所述低壓差工作電壓至該施密特電路單元。 In order to achieve the above objective, the present invention further provides a second embodiment of the power supply circuit, which is used to provide a low dropout operating voltage to a Schmitt circuit unit, and it includes: a first MOSFET element with one drain A terminal and a source terminal are respectively coupled to a working voltage and a ground terminal voltage; a current source is coupled between a gate terminal of the first MOSFET element and the working voltage; and a second MOSFET element with one of The source terminal is simultaneously coupled to the current source and the gate terminal of the first MOSFET element, a drain terminal thereof is coupled to the ground terminal voltage, and a gate terminal thereof is coupled to a clamp reference voltage; wherein, the first MOSFET The source terminal of the element is an output terminal of the power supply circuit for providing the low dropout operating voltage to the Schmitt circuit unit.
在第二實施例中,所述供電電路更包括:一第一電阻,耦接該第二MOSFET元件的該汲極端和該接地端電壓之間;一第二電阻,耦接於該第一MOSFET元件的該源極端和該接地端電壓之間;一第三電阻,耦接於該第一MOSFET元件的該汲極端和該工作電壓之間;以及一電容,耦接於該第一MOSFET元件的該閘極端和該接地端電壓之間。In the second embodiment, the power supply circuit further includes: a first resistor coupled between the drain terminal of the second MOSFET element and the ground terminal voltage; and a second resistor coupled to the first MOSFET Between the source terminal and the ground terminal voltage of the element; a third resistor coupled between the drain terminal of the first MOSFET element and the operating voltage; and a capacitor coupled to the first MOSFET element Between the gate terminal and the ground terminal voltage.
為達成上述目的,本發明進一步提出所述供電電路之一第三實施例,用於提供一低壓差工作電壓至一施密特電路單元,且其包括:To achieve the above objective, the present invention further provides a third embodiment of the power supply circuit, which is used to provide a low dropout operating voltage to a Schmitt circuit unit, and it includes:
一運算放大器,具有耦接一參考電壓的一正輸入端、一負輸入端和一輸出端;An operational amplifier having a positive input terminal, a negative input terminal and an output terminal coupled to a reference voltage;
一第一MOSFET元件,以其一源極端耦接該運算放大器的該輸出端,且其一汲極端和一閘極端係相互耦接;A first MOSFET element, a source terminal of which is coupled to the output terminal of the operational amplifier, and a drain terminal and a gate terminal of which are coupled to each other;
一第一電阻,其一端同時耦接第一MOSFET元件的該汲極端及該閘極端,且其另一端耦接該運算放大器的該負輸入端;以及A first resistor, one end of which is simultaneously coupled to the drain terminal and the gate terminal of the first MOSFET element, and the other end of which is coupled to the negative input terminal of the operational amplifier; and
一第二電阻,耦接於該第一電阻和一接地端電壓之間;A second resistor, coupled between the first resistor and a ground terminal voltage;
其中,該第一MOSFET元件的該源極端與該運算放大器的該輸出端之間的一共接點為所述供電電路的一輸出端,用以提供所述低壓差工作電壓至該施密特電路單元。Wherein, a common contact between the source terminal of the first MOSFET element and the output terminal of the operational amplifier is an output terminal of the power supply circuit for providing the low dropout operating voltage to the Schmitt circuit unit .
在第三實施例中,所述供電電路更包括一第三電阻,其耦接於該第二電阻和該接地端電壓之間。In the third embodiment, the power supply circuit further includes a third resistor coupled between the second resistor and the ground terminal voltage.
為達成上述目的,本發明進一步提出所述供電電路之一第四實施例,用於提供一低壓差工作電壓至一施密特電路單元,且其包括:To achieve the above objective, the present invention further provides a fourth embodiment of the power supply circuit, which is used to provide a low dropout operating voltage to a Schmitt circuit unit, and includes:
一穩定電壓提供單元,包括:A stable voltage supply unit, including:
一第一運算放大器,具有耦接一參考電壓的一正輸入端、一負輸入端和一輸出端;A first operational amplifier having a positive input terminal, a negative input terminal and an output terminal coupled to a reference voltage;
一第一電阻,耦接於該第一運算放大器的該輸出端和該負輸入端之間;及A first resistor coupled between the output terminal and the negative input terminal of the first operational amplifier; and
一第二電阻,以其一端耦接一地端,且其另一端同時耦接該第一電阻和該第一運算放大器的該輸出端;以及A second resistor, one end of which is coupled to a ground terminal, and the other end of which is simultaneously coupled to the first resistor and the output terminal of the first operational amplifier; and
一電壓電流轉換單元,耦接於該第一運算放大器的該負輸入端和該第二電阻之間的一共接點、一工作電壓、和一接地端電壓之間,用以提供一電流至該共接點;A voltage-current conversion unit, coupled to a common contact between the negative input terminal of the first operational amplifier and the second resistor, a working voltage, and a ground terminal voltage, for providing a current to the Common contact
其中,所述供電電路係以該第一運算放大器的該輸出端提供所述低壓差工作電壓至該施密特電路單元。Wherein, the power supply circuit uses the output terminal of the first operational amplifier to provide the low dropout operating voltage to the Schmitt circuit unit.
在第三實施例中,該電壓電流轉換單元包括:In the third embodiment, the voltage-current conversion unit includes:
一第二運算放大器,具有一正輸入端、一負輸入端和一輸出端;A second operational amplifier having a positive input terminal, a negative input terminal and an output terminal;
一第一MOSFET元件,以其一閘極端和一汲極端分別耦接該第二運算放大器的該輸出端和該負輸入端;A first MOSFET element, a gate terminal and a drain terminal of which are respectively coupled to the output terminal and the negative input terminal of the second operational amplifier;
一第三電阻,其一端耦接一工作電壓,且其另一端同時耦接該第二運算放大器的該負輸入端和該第一MOSFET元件的一源極端;A third resistor, one end of which is coupled to a working voltage, and the other end of which is simultaneously coupled to the negative input terminal of the second operational amplifier and a source terminal of the first MOSFET element;
一電流鏡,同時耦接該第一MOSFET元件的該汲極端、一接地端電壓、以及該第一運算放大器的該負輸入端、該第一電阻和該第二電阻之間的一共接點;A current mirror coupled to the drain terminal of the first MOSFET element, a ground terminal voltage, and a common connection point between the negative input terminal of the first operational amplifier, the first resistor and the second resistor at the same time;
一第二MOSFET元件,其一閘極端耦接該第二運算放大器的該正輸入端,其一源極端耦接該工作電壓,且其一汲極端同時耦接該第二運算放大器的該正輸入端和該接地端電壓;及A second MOSFET element, a gate terminal of which is coupled to the positive input terminal of the second operational amplifier, a source terminal of which is coupled to the operating voltage, and a drain terminal of which is simultaneously coupled to the positive input of the second operational amplifier Terminal and the ground terminal voltage; and
一電流源,其一端耦接該接地端電壓,且其另一端同時耦接該第二MOSFET元件的該汲極端和該第二運算放大器的該正輸入端。A current source, one end of which is coupled to the ground terminal voltage, and the other end of which is simultaneously coupled to the drain terminal of the second MOSFET element and the positive input terminal of the second operational amplifier.
本發明同時提供一種數位輸入緩衝器,其包含如前所述之供電電路。The present invention also provides a digital input buffer, which includes the power supply circuit as described above.
在可行的實施例中,所述數位輸入緩衝器係應用在選自於數位類比轉換電路、上電復位電路、超聲波傳感器電路、光電傳感器電路、電容式指紋傳感器電路、光學式指紋傳感器電路、電子開關電路、信號切換控制電路、IGBT驅動控制電路、電流閾值檢測電路、和電壓閾值檢測電路所組成的群組之中的一種電子電路裝置。In a feasible embodiment, the digital input buffer is applied to a digital analog conversion circuit, a power-on reset circuit, an ultrasonic sensor circuit, a photoelectric sensor circuit, a capacitive fingerprint sensor circuit, an optical fingerprint sensor circuit, and electronics. An electronic circuit device in the group consisting of a switching circuit, a signal switching control circuit, an IGBT drive control circuit, a current threshold detection circuit, and a voltage threshold detection circuit.
為達成上述目的,本發明進一步提出一種控制晶片,其具有一控制電路及如前述之供電電路,其中該控制電路係由該供電電路供電。To achieve the above objective, the present invention further provides a control chip, which has a control circuit and the aforementioned power supply circuit, wherein the control circuit is powered by the power supply circuit.
為達成上述目的,本發明進一步提出一種資訊處理裝置,其具有如前述之控制晶片。To achieve the above objective, the present invention further provides an information processing device, which has the aforementioned control chip.
為使 貴審查委員能進一步瞭解本發明之結構、特徵、目的、與其優點,茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable your reviewer to further understand the structure, features, purpose, and advantages of the present invention, the drawings and detailed descriptions of preferred specific embodiments are attached as follows.
圖4顯示本發明之一種供電電路的第一實施例之電路拓樸圖。於第一實施例中,本發明之供電電路100用以提供一低壓差工作電壓V
LDO至一施密特電路單元2,且其包括:一第一MOSFET元件101、一電流源102、一第二MOSFET元件103、一第一電阻104、一第二電阻105、一第三電阻106、一第四電阻107、以及一電容108。如圖4所示,該第一MOSFET元件101為一N型MOSFET元件,其一汲極端和一源極端分別耦接一工作電壓V
DD和一接地端電壓V
SS。並且,該電流源102耦接於該第一MOSFET元件101的一閘極端和該工作電壓V
DD之間。特別說明的是,所述電流源102包含一電阻以及跨於該電阻的一帶隙參考電壓V
BG。簡單地說,該電流源102的輸出電流值為V
BG/R,其中R為前述電阻之電阻值。
FIG. 4 shows a circuit topology diagram of the first embodiment of a power supply circuit of the present invention. In the first embodiment, the
另一方面,該第二MOSFET元件103為一P型MOSFET元件。如圖4所示,該第二MOSFET元件103的一源極端同時耦接該電流源102與該第一MOSFET元件101的該閘極端,且其一汲極端和一閘極端係相互耦接。更詳細地說明,該第一電阻104的一端同時耦接該第二MOSFET元件103的該汲極端和該閘極端,且其另一端耦接該接地端電壓VSS。並且,該第二電阻105耦接於該第一電阻104和該接地端電壓VSS之間,該第三電阻106耦接於該第一MOSFET元件101的該源極端和該接地端電壓VSS之間,該第四電阻107耦接於該第一MOSFET元件101的該汲極端和該工作電壓VDD之間,且該電容108耦接於該第一MOSFET元件101的該閘極端和該接地端電壓VSS之間。
On the other hand, the
該第一MOSFET元件101(亦即,N型MOSFET元件)的該源極端為所述供電電路100的一輸出端,用以提供所述低壓差工作電壓VLDO至該施密特電路單元2。依據本發明之設計,電流源102所輸出的定電流之值為VBG/R,且由圖4可知所述定電流係依序流過第二MOSFET元件103(亦即,P型MOSFET元件)、第一電阻104和第二電阻105,因此可推算低壓差工作電壓VLDO=Ibxu*(R1+R2)+Vgsp-Vgsn。於前述運算式中,Ibxu為電流源102所輸出的定電流,R1為第一電阻104的電阻值,R2為第二電阻105的電阻值,Vgsp=VTP+Vov,且Vgsn=VTN+Vov。更詳細地說明,VTP和VTN分別為P型MOSFET元件和N型MOSFET元件的閥值電壓,而Vov則為MOSFET元件之過驅動電壓。並且,前述運算式可以進一步地被推導成如下之數學運算式:VLDO=VBG*(R1+R2)/R+VTP-VTN……………(1)。
The source terminal of the first MOSFET element 101 (ie, the N-type MOSFET element) is an output terminal of the
施密特電路單元2的示範性電路拓樸係繪示於圖1之中,且已知施密特電路單元2的輸入翻轉點電壓VINV可利用如下之數學運算式計算而得:
本發明之供電電路100提供低壓差工作電壓VLDO至施密特電路單元2,因此可將上式(1)代入式(2)之中,進而獲得如下之數學運算式:
於前述式(3)中,γ=β
P/β
N。並且,β
P為P型MOSFET元件的增益因子,其為μ
PC
OX(W
P/L
P)。另一方面,β
N為N型MOSFET元件的增益因子,其為μ
NC
OX(W
N/L
N)。必須加以說明的是,在工作電壓V
DD不變的情况下,工藝角(Process corner)的其一最差狀況(worst case)為SNFP,亦即NMOS慢且PMOS快。此最差狀況工藝角決定了施密特電路單元2之邏輯高電平(Logic-high)輸出信號V
OUT的最小值是否可以達到1.2 V、1.1V、或1.05V。另一方面,在工作電壓V
DD不變的情况下,工藝角的另一最差狀況(worst case)為FNSP,亦即NMOS快且PMOS曼。此最差狀況工藝角決定了施密特電路單元2之邏輯低電平(Logic-low)輸出信號V
OUT的最大值是否可以達到0.6V。
In the aforementioned formula (3), γ=β P /β N. Also, β P is the gain factor of the P-type MOSFET element, which is μ P C OX (W P /L P ). On the other hand, β N is the gain factor of the N-type MOSFET element, which is μ N C OX (W N /L N ). It must be noted that when the working voltage V DD remains unchanged, one of the worst cases of the process corner is SNFP, that is, the NMOS is slow and the PMOS is fast. The worst-case process angle determines whether the minimum value of the logic-high output signal V OUT of the
因此,由前述式(3)可知,本發明之供電電路100用以將所述工作電壓V
DD調整為一低壓差工作電壓V
LDO,調整過程同時兼容補償N型MOSFET元件和P型MOSFET元件之工藝角變化。如此設計,即使N型MOSFET元件的閥值電壓及/或P型MOSFET元件因為製程誤差而成為最差狀況(worst case)工藝角,本發明之供電電路100可以通過調降或者調升所述低壓差工作電壓V
LDO的方式,讓最差狀況工藝角之N型MOSFET元件及P型MOSFET元件從SNFP或FNSP工藝角改變成SS或FF工藝角,藉此方式調控該施密特電路單元2之輸入翻轉點電壓V
INV,使其在全工藝角範圍內之變化能夠受到有效控制而不會有明顯的變動。舉例而言,在一最差狀況(worst case)工藝角SNFP的情況下,通過本發明之供電電路100可以適當地調降所述低壓差工作電壓V
LDO。並且,在另一最差狀況工藝角FNSP的情況下,本發明之供電電路100可以適當地調升所述低壓差工作電壓V
LDO。
Therefore, it can be seen from the aforementioned formula (3) that the
圖5顯示本發明之一種供電電路的第二實施例之電路拓樸圖。於第二實施例中,本發明之供電電路200用以提供一低壓差工作電壓V
LDO至一施密特電路單元2,且其包括:一第一MOSFET元件201、一電流源202、一第二MOSFET元件203、一第一電阻204、一第二電阻206、一第三電阻207、以及一電容208。如圖5所示,該第一MOSFET元件201為一N型MOSFET元件,且其一汲極端和一源極端分別耦接一工作電壓V
DD和一接地端電壓V
SS。並且,該電流源202耦接於該第一MOSFET元件201的一閘極端和該工作電壓V
DD之間。另一方面,該第二MOSFET元件203為一P型MOSFET元件,且其一源極端同時耦接該電流源202與該第一MOSFET元件201的該閘極端。並且,該第二MOSFET元件203之一汲極端和一閘極端分別耦接該接地端電壓VSS和一箝制參考電壓VREF_CLAMP。
FIG. 5 shows a circuit topology diagram of a second embodiment of a power supply circuit of the present invention. In the second embodiment, the
更詳細地說明,該第一電阻204耦接該第二MOSFET元件203的該汲極端和該接地端電壓VSS之間,該第二電阻206耦接於該第一MOSFET元件201的該源極端和該接地端電壓VSS之間,該第三電阻207耦接於該第一MOSFET元件201的該汲極端和該工作電壓VDD之間,且該電容208耦接於該第一MOSFET元件201的該閘極端和該接地端電壓VSS之間。
In more detail, the
於第二實施例中,該第一MOSFET元件201的該源極端為所述供電電路200的一輸出端,用以提供所述低壓差工作電壓VLDO至該施密特電路單元2。由圖5的電路拓樸可知所述低壓差工作電壓VLDO=VREF_CLAMP+Vgsp-Vgsn。其中,VREF_CLAMP為用以控制第二MOSFET元件203之導通/關閉的一箝制參考電壓,Vgsp為第二MOSFET元件203的閘極-源極電壓差,且Vgsn為第一MOSFET元件201的閘極-源極電壓差。並且,前述運算式可以進一步地被推導成如下之數學運算式:VLDO=VREF_CLAMP+VTP-VTN……………(4)。
In the second embodiment, the source terminal of the
本發明之供電電路200提供低壓差工作電壓VLDO至施密特電路單元2,因此可將上式(4)代入前面說明所述之式(2)中,進而獲得如下之數學運算式:
由前述式(5)可知,本發明之供電電路200用以將所述工作電壓VDD調整為一低壓差工作電壓VLDO,調整過程同時兼容補償N型MOSFET元件和P型MOSFET元件之工藝角變化。舉例而言,在一最差狀況(worst case)工藝角SNFP的情況下,通過本發明之供電電路100可以適當地調降所述低壓差工作電壓VLDO。並且,在另一最差狀況工藝角FNSP的情況下,本發明之供電電路100可以適當地調升所述低壓差工作電壓VLDO。如此設計,讓最差狀況工藝角之N型MOSFET元件及P型MOSFET元件從SNFP或FNSP工藝角改變成SS或FF工藝角,便能夠調控該施密特電路單元2之輸入翻轉點電壓V
INV,使其在全工藝角範圍內之變化能夠受到有效控制而不會有明顯的變動。
It can be seen from the aforementioned formula (5) that the
圖6顯示本發明之一種供電電路的第三實施例之電路拓樸圖。於第三實施例中,本發明之供電電路300用以提供一低壓差工作電壓V
LDO至一施密特電路單元2,且其包括:一運算放大器301、一第一MOSFET元件302、一第一電阻303、一第二電阻304、以及一第三電阻305。其中,該運算放大器301具有耦接一參考電壓V
REF的一正輸入端、一負輸入端和一輸出端。該第一MOSFET元件302為一P型MOSFET元件,且其一源極端耦接該運算放大器301的該輸出端,而其一汲極端和一閘極端係相互耦接。另一方面,該第一電阻303之一端同時耦接第一MOSFET元件302的該汲極端及該閘極端,且其另一端耦接該運算放大器301的該負輸入端。圖6還繪示該第二電阻304耦接於該第一電阻303和一接地端電壓V
SS之間,且該第三電阻305耦接於該第二電阻304和該接地端電壓V
SS之間。
FIG. 6 shows a circuit topology diagram of a third embodiment of a power supply circuit of the present invention. In the third embodiment, the
於第三實施例中,該第一MOSFET元件302的該源極端與該運算放大器301的該輸出端之間的一共接點為所述供電電路300的一輸出端,用以提供所述低壓差工作電壓V
LDO至該施密特電路單元2。由圖6的電路拓樸可知,本發明在所述運算放大器301的反饋迴路上串接該第一MOSFET元件302。由於該第一MOSFET元件302為一二極體連接形式(Diode-connected)之P型MOSFET元件,因此所述低壓差工作電壓V
LDO會隨著P型MOSFET元件的工藝角進行變化。所述低壓差工作電壓V
LDO為:V
REF*(R3+R2+R1)/(R1+R2)+V
gsp。其中,R3為第一電阻303的電阻值,R2為第二電阻304的電阻值,R1為第三電阻301的電阻值,且V
gsp=V
TP+Vov。V
TP為P型MOSFET元件的閥值電壓,而Vov則為MOSFET元件之過驅動電壓。並且,前述運算式可以進一步地被推導成如下之數學運算式:
V
LDO=V
REF*(R3+R2+R1)/(R1+R2)+V
TP+Vov……(6)。
In the third embodiment, a common contact between the source terminal of the
本發明之供電電路300提供低壓差工作電壓V
LDO至施密特電路單元2,因此可將上式(5)代入前面說明所述之式(2)中,進而獲得如下之數學運算式:
…………………………(7)。
The
由前述式(7)可知,本發明之供電電路300用以將所述工作電壓V
DD調整為一低壓差工作電壓V
LDO,調整過程同時兼容補償N型MOSFET元件和P型MOSFET元件之工藝角變化,具體效果是可以令最差狀況工藝角之N型MOSFET元件及P型MOSFET元件從SNFP或FNSP工藝角改變成SS或FF工藝角,從而能夠調控該施密特電路單元2之輸入翻轉點電壓V
INV,使其在全工藝角範圍內之變化能夠受到有效控制而不會有明顯的變動。
It can be seen from the aforementioned formula (7) that the
圖7顯示本發明之一種供電電路的第四實施例之電路拓樸圖。於第四實施例中,本發明之供電電路400用以提供一低壓差工作電壓V
LDO至一施密特電路單元2,其主要由一穩定電壓提供單元410和一電壓電流轉換單元420組成。如圖7所示,該穩定電壓提供單元410包括:一第一運算放大器411、一第一電阻412以及一第二電阻413。其中,該第一運算放大器411具有耦接一參考電壓V
REF的一正輸入端、一負輸入端和一輸出端,且該第一電阻412耦接於該第一運算放大器411的該輸出端和該負輸入端之間。並且,該第二電阻413之一端耦接一地端,且其另一端同時耦接該第一電阻412和該第一運算放大器411的該輸出端。依據本發明之設計,該電壓電流轉換單元420耦接於該第一運算放大器411的該負輸入端和該第二電阻413之間的一共接點、一工作電壓V
DD、和一接地端電壓V
SS之間,用以提供一電流至該共接點。並且,所述供電電路100係以該第一運算放大器411的該輸出端提供所述低壓差工作電壓V
LDO至該施密特電路單元2。
FIG. 7 shows a circuit topology diagram of a fourth embodiment of a power supply circuit of the present invention. In the fourth embodiment, the
更詳細地說明,該電壓電流轉換單元420包括:一第二運算放大器421、一第一MOSFET元件422、一第三電阻423、一第二MOSFET元件424、一電流源425、以及一電流鏡(包含一第三MOSFET元件426和一第四MOSFET元件427)。其中,該第二運算放大器421具有一正輸入端、一負輸入端和一輸出端,且該第一MOSFET元件422以其一閘極端和一汲極端分別耦接該第二運算放大器421的該輸出端和該負輸入端。另一方面,該第三電阻423之一端耦接一工作電壓V
DD,且其另一端同時耦接該第二運算放大器421的該負輸入端和該第一MOSFET元件422的一源極端。如圖7所示,該第二MOSFET元件424之一閘極端耦接該第二運算放大器421的該正輸入端,且一源極端耦接該工作電壓V
DD,而其一汲極端則同時耦接該第二運算放大器421的該正輸入端和該接地端電壓V
SS。
In more detail, the voltage-
承上述說明,該電流源425之一端耦接該接地端電壓V
SS,且其另一端同時耦接該第二MOSFET元件424的該汲極端和該第二運算放大器421的該正輸入端。圖7還繪示該電流鏡為一NMOS電流鏡,由該第三MOSFET元件426和該第四MOSFET元件427組成。其中,第三MOSFET元件426的源極端和汲極端分別耦接該接地端電壓V
SS和該第一MOSFET元件422的該汲極端,且其閘極端耦接其汲極端。並且,第四MOSFET元件427的源極端和汲極端分別耦接該接地端電壓V
SS和該第一運算放大器411的該負輸入端、該第一電阻412和該第二電阻413之間的共接點,且其閘極端耦接該第一MOSFET元件422的閘極端。
Following the above description, one terminal of the
於第四實施例中,該電壓電流轉換單元420把第二MOSFET元件424的Vgsp電壓轉換成電流,且所述電流為Vgsp/R0;其中,Vgsp=V
TP+Vov,且R0為第三電阻423的電阻值。透過該電流鏡之第四MOSFET元件427將所述電流傳送至該第一運算放大器411的該負輸入端與該第一電阻412及該第二電阻413之間的共接點,可推算出所述低壓差工作電壓V
LDO=V
REF*(R2+R1)/R1+V
gsp*R2/R0。由此可知,調整R2/R0的比例可以改變低壓差工作電壓V
LDO的最終值。在令R2/R0=1的情況下,,前述運算式可以進一步地被推導成如下之數學運算式:
V
REF*(R2+R1)/R1+V
gsp……(8)。
In the fourth embodiment, the voltage-
本發明之供電電路400提供低壓差工作電壓V
LDO至施密特電路單元2,因此可將上式(8)代入前面說明所述之式(2)中,進而獲得如下之數學運算式:
…………………………(9)。
The
由前述式(9)可知,本發明之供電電路400用以將所述工作電壓V
DD調整為一低壓差工作電壓V
LDO,調整過程同時兼容補償N型MOSFET元件和P型MOSFET元件之工藝角變化,具體效果是可以令最差狀況工藝角之N型MOSFET元件及P型MOSFET元件從SNFP或FNSP工藝角改變成SS或FF工藝角,從而能夠調控該施密特電路單元2之輸入翻轉點電壓V
INV,使其在全工藝角範圍內之變化能夠受到有效控制而不會有明顯的變動。
It can be seen from the aforementioned formula (9) that the
依上述的說明,本發明可進一步提出一種數位輸入緩衝器,其包含一施密特電路單元2以及如前所述本發明之供電電路(100, 200, 300, 400)的任一實施例。在可行的實施例中,該數位輸入緩衝器係應用在一電子電路裝置之中,且該電子電路裝置可為下列任一者:數位類比轉換電路、上電復位電路、超聲波傳感器電路、光電傳感器電路、電容式指紋傳感器電路、光學式指紋傳感器電路、電子開關電路、信號切換控制電路、IGBT驅動控制電路、電流閾值檢測電路、和電壓閾值檢測電路。According to the above description, the present invention can further provide a digital input buffer, which includes a
依上述的說明,本發明可進一步提出一種控制晶片,其具有前述的供電電路及一控制電路,其中該控制電路係由該供電電路供電以提供穩定、可靠的工作性能。Based on the above description, the present invention can further provide a control chip having the aforementioned power supply circuit and a control circuit, wherein the control circuit is powered by the power supply circuit to provide stable and reliable working performance.
依上述的說明,本發明可進一步提出一種資訊處理裝置,其具有前述的控制晶片以提供穩定、可靠的工作性能。Based on the above description, the present invention can further provide an information processing device with the aforementioned control chip to provide stable and reliable working performance.
如此,上述已完整且清楚地說明本發明之一種供電電路;並且,經由上述可得知本發明具有下列優點:In this way, the above has completely and clearly described a power supply circuit of the present invention; and from the above, it can be seen that the present invention has the following advantages:
(1)本發明之供電電路可將一工作電壓調V
DD整成一低壓差工作電壓V
LDO,並提供該低壓差工作電壓V
LDO至一施密特電路單元2,使得該施密特電路單元2之一邏輯高電平(Logic-high)輸出信號的最小值可以達到1.2 V、1.1V、或1.05V,且同時令該施密特電路單元2之一邏輯低電平(Logic-low)輸出信號的最大值可以達到0.6 V。
(1) The power supply circuit of the present invention can adjust a working voltage V DD into a low-dropout working voltage V LDO , and provide the low-dropout working voltage V LDO to a
(2)本發明提供所述供電電路的四個示範性實施例,皆可用以將一工作電壓V
DD調整為一低壓差工作電壓V
LDO,調整過程同時兼容補償N型MOSFET元件和P型MOSFET元件之工藝角變化,讓最差狀況工藝角之N型MOSFET元件及P型MOSFET元件從SNFP或FNSP工藝角改變成SS或FF工藝角,藉此方式調控施密特電路單元2之輸入翻轉點電壓V
INV,使其在全工藝角範圍內之變化能夠受到有效控制而不會有明顯的變動。
(2) The present invention provides four exemplary embodiments of the power supply circuit, all of which can be used to adjust an operating voltage V DD to a low dropout operating voltage V LDO , and the adjustment process is compatible with compensating N-type MOSFET components and P-type MOSFETs. The process angle of the device changes, so that the N-type MOSFET element and P-type MOSFET element of the worst-case process angle are changed from the SNFP or FNSP process angle to the SS or FF process angle, thereby adjusting the input flip point of the
必須加以強調的是,前述本案所揭示者乃為較佳實施例,舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者,俱不脫本案之專利權範疇。It must be emphasized that the foregoing disclosures in this case are preferred embodiments, and any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those who are familiar with the art will not deviate from the patent of this case. Right category.
綜上所陳,本案無論目的、手段與功效,皆顯示其迥異於習知技術,且其首先發明合於實用,確實符合發明之專利要件,懇請 貴審查委員明察,並早日賜予專利俾嘉惠社會,是為至禱。In summary, regardless of the purpose, means, and effects of this case, it is shown that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. Please check it out and grant the patent as soon as possible. Society is for the best prayer.
<本發明><The present invention>
2:施密特電路單元2: Schmidt circuit unit
100:供電電路100: power supply circuit
101:第一MOSFET元件101: The first MOSFET element
102:電流源102: current source
103:第二MOSFET元件103: The second MOSFET element
104:第一電阻104: first resistance
105:第二電阻105: second resistor
106:第三電阻106: third resistor
107:第四電阻107: Fourth resistor
108:電容108: Capacitor
200:供電電路200: power supply circuit
201:第一MOSFET元件201: The first MOSFET element
202:電流源202: current source
203:第二MOSFET元件203: The second MOSFET element
204:第一電阻204: first resistance
206:第二電阻206: second resistor
207:第三電阻207: third resistor
208:電容208: Capacitor
300:供電電路300: power supply circuit
301:運算放大器301: Operational amplifier
302:第一MOSFET元件302: The first MOSFET element
303:第一電阻303: first resistance
304:第二電阻304: second resistor
305:第三電阻305: third resistor
400:供電電路400: power supply circuit
410:穩定電壓提供單元410: Stable voltage supply unit
411:第一運算放大器411: The first operational amplifier
412:第一電阻412: first resistance
413:第 二電阻413: second resistor
420:電壓電流轉換單元420: voltage-current conversion unit
421:第二運算放大器421: second operational amplifier
422:第一MOSFET元件422: The first MOSFET element
423:第三電阻423: third resistor
424:第二MOSFET元件424: second MOSFET element
425:電流源425: current source
426:第三MOSFET元件426: third MOSFET element
427:第四MOSFET元件427: Fourth MOSFET element
<習知><Acquaintances>
2:CMOS施密特電路2: CMOS Schmitt circuit
2020
2M1:第一P型MOSFET元件2M1: The first P-type MOSFET element
2M2:第二P型MOSFET元件2M2: Second P-type MOSFET element
2M3:第一N型MOSFET元件2M3: The first N-type MOSFET element
2M4:第二N型MOSFET元件2M4: Second N-type MOSFET element
2M5:第三P型MOSFET元件2M5: The third P-type MOSFET element
2M6:第三N型MOSFET元件2M6: The third N-type MOSFET element
3:低壓差穩壓器3: Low dropout regulator
圖1為習知的一種CMOS施密特電路的電路拓樸圖; 圖2為習知的CMOS施密特電路的等效電路符號; 圖3為習知的一種包含低壓差穩壓器的施密特電路; 圖4為本發明之一種供電電路的第一實施例之電路拓樸圖; 圖5為本發明之一種供電電路的第二實施例之電路拓樸圖; 圖6為本發明之一種供電電路的第三實施例之電路拓樸圖;以及 圖7為本發明之一種供電電路的第四實施例之電路拓樸圖。 Figure 1 is a circuit topology diagram of a conventional CMOS Schmitt circuit; Figure 2 is the equivalent circuit symbol of the conventional CMOS Schmitt circuit; Figure 3 is a conventional Schmitt circuit including a low dropout regulator; 4 is a circuit topology diagram of the first embodiment of a power supply circuit of the present invention; Fig. 5 is a circuit topology diagram of a second embodiment of a power supply circuit of the present invention; Fig. 6 is a circuit topology diagram of a third embodiment of a power supply circuit of the present invention; and FIG. 7 is a circuit topology diagram of a fourth embodiment of a power supply circuit of the present invention.
2:施密特電路單元 2: Schmidt circuit unit
100:供電電路 100: power supply circuit
101:第一MOSFET元件 101: The first MOSFET element
102:電流源 102: current source
103:第二MOSFET元件 103: The second MOSFET element
104:第一電阻 104: first resistance
105:第二電阻 105: second resistor
106:第三電阻 106: third resistor
107:第四電阻 107: Fourth resistor
108:電容 108: Capacitor
Claims (9)
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TW108144993A TWI730534B (en) | 2019-12-09 | 2019-12-09 | Power supply circuit and digital input buffer, control chip and information processing device using it |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI329967B (en) * | 2007-05-01 | 2010-09-01 | Sitronix Technology Corp | |
EP2551743B1 (en) * | 2011-07-27 | 2014-07-16 | ams AG | Low-dropout regulator and method for voltage regulation |
US20150310324A1 (en) * | 2013-01-09 | 2015-10-29 | Excelio Technology (Shenzhen) Co., Ltd. | Radio frequency identification tag and low dropout regulator (ldo) circuit consuming ultra-low power |
US9715245B2 (en) * | 2015-01-20 | 2017-07-25 | Taiwan Semiconductor Manufacturing Company Limited | Circuit for generating an output voltage and method for setting an output voltage of a low dropout regulator |
CN110456854A (en) * | 2019-08-22 | 2019-11-15 | 上海华力微电子有限公司 | Low pressure difference linear voltage regulator |
-
2019
- 2019-12-09 TW TW108144993A patent/TWI730534B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI329967B (en) * | 2007-05-01 | 2010-09-01 | Sitronix Technology Corp | |
EP2551743B1 (en) * | 2011-07-27 | 2014-07-16 | ams AG | Low-dropout regulator and method for voltage regulation |
US20150310324A1 (en) * | 2013-01-09 | 2015-10-29 | Excelio Technology (Shenzhen) Co., Ltd. | Radio frequency identification tag and low dropout regulator (ldo) circuit consuming ultra-low power |
US9715245B2 (en) * | 2015-01-20 | 2017-07-25 | Taiwan Semiconductor Manufacturing Company Limited | Circuit for generating an output voltage and method for setting an output voltage of a low dropout regulator |
CN110456854A (en) * | 2019-08-22 | 2019-11-15 | 上海华力微电子有限公司 | Low pressure difference linear voltage regulator |
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