TWI727860B - Wafer transverse impact test device and wafer strength test method - Google Patents

Abstract

A wafer transverse impact test device and a wafer strength test method are provided. The wafer transverse impact test device includes a carrier and an impactor. The wafer strength test method includes a first preparation step and a first impact step. The first preparation step provides a test wafer disposed and lying flat on the carrier and a pre-impacted edge zone of the test wafer corresponds to an impact opening of the carrier. The first impact step provides the impactor passing through the impact opening and impacting the pre-impacted edge zone of the test wafer along a predetermined plane that is perpendicular to a normal vector of the test wafer. Accordingly, the test wafer breaks into two half-wafers along a crystal direction of the test wafer. Each of the half-wafers includes a fractured edge that is parallel to the crystal direction, and the two half-wafers are respectively defined as a first half-wafer and a second half-wafer.

Description

Wafer lateral impact test device and wafer strength test method

The invention relates to a wafer testing device and a wafer testing method, in particular to a wafer lateral impact testing device and a wafer strength testing method.

As shown in Figure 1, when the conventional wafer strength test device and wafer strength test method test the mechanical strength of a single wafer, the bending resistance test is often performed in the direction perpendicular to the wafer surface (please refer to the Chinese patent No. CN105181462A and Figure 1), but this kind of test has gradually been unable to meet the current wafer strength test requirements. Therefore, how to overcome the above-mentioned defects through the improvement of the structural design of the wafer impact test device or the design or improvement of the wafer strength test method has become one of the important issues to be solved by this business.

In view of the shortcomings of the prior art, the present invention provides a wafer transverse impact test device, which includes: a bearing seat with an impact opening positioned on a predetermined plane; wherein the bearing seat is used for a wafer to be tested flat Lying and falling on the predetermined plane, and the wafer to be tested is defined with a crystal orientation passing through its center; and a striker, which is arranged corresponding to the striker, and the striker can move along the Operating on the predetermined plane; wherein the impact direction of the striker is parallel to the crystal direction; wherein, when the wafer to be tested is laid flat on the carrier, the impact The striker can pass through the impact opening along the predetermined plane, and strike a pre-strike edge area of the wafer to be tested along the crystal direction, so that the wafer to be tested moves along the crystal direction. Fragmented into two half wafers; wherein, the pre-strike edge area is the edge portion of the wafer to be tested located at the impact port.

In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a wafer strength testing method, which includes: a first preparation step: laying a wafer to be tested on a carrier, And make a pre-strike edge area of the wafer to be tested correspond to an impact port of the carrier; wherein the wafer to be tested includes a first crystal orientation and is sandwiched with the first crystal orientation Forming a second non-parallel crystal orientation; and a first impact step: using an impactor to pass through the impact opening along a predetermined plane perpendicular to the normal vector of a wafer surface of the wafer to be tested, and along The first crystal orientation hits the pre-strike edge area of the wafer to be tested, so that the wafer to be tested is broken into two half wafers along the first crystal orientation; The impact direction of the striker is parallel to the first crystal orientation; wherein each half-wafer includes a fragmentation edge parallel to the first crystal orientation, and the two half-wafers are respectively defined It is a first half-wafer and a second half-wafer; wherein the pre-strike edge area is the edge portion of the wafer to be tested located at the impact port.

One of the beneficial effects of the present invention is that the wafer lateral impact test device and the wafer strength test method can impact the pre-strike along the predetermined plane where the wafer to be tested is located. The edge area is used to test the test strength required for the wafer to be tested to break along the crystal direction.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the provided drawings are only for reference and description, and are not used to limit the present invention.

100: Wafer lateral impact test device

1: bearing seat

11: Wafer stage

111: impact port

112: Bottom

113: Sidewall

114: Carrying bump

115: installation block

12: Impactor carrier

121: Depressed part

1211: Insert board

1212: Support

122: Bearing Department

1221: Impactor carrying rail

12211: recess

13: Scheduled plane

2: Impactor

21: Impact head

22: Impact bar

3: Force controller

31: Tension spring

32: Force scale indicator

33: hook

4: Crystal orientation sensor

5: Support frame

51: lock firmware

52: Support arm

53: top bar

200: wafer to be tested

201: The first crystal orientation

202: second crystal orientation

203: The Third Crystal Orientation

204: first half wafer

205: second half wafer

S1: The first preparation step

S2: First impact step

S3: Second preparation step

S4: Second impact step

S5: The third preparatory step

S6: Third impact step

FIG. 1 is a schematic diagram of the operation of a conventional wafer strength testing device.

FIG. 2 is a three-dimensional schematic diagram of the wafer lateral impact test device according to the first embodiment of the present invention.

3 is an exploded schematic diagram of the wafer lateral impact test device according to the first embodiment of the present invention.

FIG. 4 is a three-dimensional schematic diagram of the wafer carrier according to the first embodiment of the present invention.

5A is a schematic plan view of the wafer to be tested according to the first embodiment of the present invention.

5B is a schematic plan view of another wafer to be tested according to the first embodiment of the present invention.

FIG. 6 is a three-dimensional schematic diagram of the impactor carrier according to the first embodiment of the present invention.

FIG. 7 is a three-dimensional schematic diagram of the impactor hitting the wafer to be tested according to the first embodiment of the present invention.

Fig. 8 is a schematic diagram of the striker of the first embodiment of the present invention.

Fig. 9 is an enlarged schematic diagram of part VIII of Fig. 6.

FIG. 10 is a schematic diagram of the change of the impact force of the impactor against the wafer to be tested according to the first embodiment of the present invention.

FIG. 11 is a flowchart of a wafer strength testing method according to a second embodiment of the present invention.

FIG. 12 is a schematic diagram of a support frame against a half-wafer according to a second embodiment of the present invention.

FIG. 13A is a schematic diagram of the striker hitting the first half wafer according to the second embodiment of the present invention.

FIG. 13B is a schematic diagram of the striker hitting the second half-wafer according to the second embodiment of the present invention.

The following is a specific embodiment to illustrate the implementation of the "wafer lateral impact test device and wafer strength test method" disclosed in the present invention. Those skilled in the art can The advantages and effects of the present invention can be understood from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual size, and are stated in advance. The following embodiments will further describe the related technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as "first", "second", and "third" may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another, or one signal from another signal. In addition, the term "or" used in this document may include any one or a combination of more of the associated listed items depending on the actual situation.

[First Embodiment]

Please refer to Figures 2 to 10, which are the first embodiment of the present invention. It should be noted that the relevant quantities and appearances mentioned in the corresponding drawings of this embodiment are only used to specifically illustrate the present invention. In order to understand the content of the present invention, it is not used to limit the protection scope of the present invention.

2 and 3, this embodiment discloses a wafer lateral impact test device 100, which includes: a bearing seat 1, a striker 2 corresponding to the bearing seat 1, connected to the striker 2 A force controller 3, a crystal orientation sensor 4 installed on the carrier 1, and a support frame 5 movably installed on the carrier 1.

As shown in FIGS. 2 and 7, the carrier 1 has a wafer carrier 11 and an impactor carrier 12 connected to the wafer carrier 11. Wherein, the wafer carrier 11 is formed with an impact opening 111 located on a predetermined plane 13, and the carrier 1 (the wafer carrier 11) is used for a wafer 200 to be tested lying down. It falls on the predetermined plane 13. Wherein, the wafer 200 to be tested has a pre-strike edge area for the striker 2 to perform a wafer lateral impact test. It should be noted, The pre-strike edge area is an edge portion of the wafer to be tested located at the impact port.

As shown in FIG. 5A, the wafer 200 to be tested includes two crystal orientations passing through its center. In this embodiment, one of the crystal orientations is defined as a first crystal orientation 201, and the other crystal orientation is defined as a first crystal orientation 201. The orientation is defined as a second crystal orientation 202, and the first crystal orientation 201 and the second crystal orientation 202 are sandwiched non-parallel. Furthermore, the first crystal orientation 201 and the second crystal orientation 202 are preferably sandwiched by 90 degrees, but the present invention is not limited to this. For example, as shown in FIG. 5B, the waiting The test wafer 200 may include the first crystal orientation 201 passing through its center, and the second crystal orientation 202 and a third crystal orientation 201 that are sandwiched by the first crystal orientation 201 and formed by no more than 90 degrees. To 203. Wherein, the first crystal orientation 201, the second crystal orientation 202, and the third crystal orientation 203 intersect at the center of the wafer 200 to be tested.

It should be noted that, in this embodiment, the angle between the first crystal orientation 201 and the second crystal orientation 202 is 60 degrees, and the first crystal orientation 201 is opposite to the third crystal orientation 203. The clamping angle is 60 degrees, and the angle between the second crystal orientation 202 and the third crystal orientation 203 is 120 degrees.

It should be noted that the wafer 200 to be tested is preferably an epitaxial wafer in this embodiment. Wherein, the size of the wafer 200 to be tested is preferably 6 inches (inch), but this embodiment is not limited to this. For example, the wafer 200 to be tested can also be a polished wafer or other types of silicon wafers, and the size of the wafer 200 to be tested can also be 8 inches or Other sizes such as 12 inches.

As shown in FIGS. 3 and 4, the wafer carrier 11 has a circular bottom surface 112, a side wall 113 surrounding the edge of the bottom surface 112, and is disposed on the edge of the bottom surface 112 and abuts against the bottom surface 112. A plurality of carrying protrusions 114 of the side wall 113 and a mounting block 115 disposed on a side of the side wall 113 relatively far away from the plurality of carrying protrusions 114. Wherein, the predetermined plane 13 is located above the plurality of bearing bumps 114, and the impact opening 111 is formed on the side wall 113. A plurality of the bearing bumps 114 are located between the bottom surface 112 and the predetermined plane 13, and the bottom surface 112 and the predetermined plane 13 Parallel to each other. The mounting block 115 is used to lock the support frame 5 into and fixed, but the present invention is not limited to the above.

It should be noted that, in this embodiment, the bottom surface 112 has a thickness and a plurality of locking holes, which are used for locking and fixing the striker carrier 12 with each other. Wherein, an edge of the bottom surface 112 adjacent to the impact opening 111 is linear, and the number of the locking holes is preferably four, but the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the edge of the impact opening 111 may also be arc-shaped, and the number of the locking holes may also be three or more.

As shown in FIGS. 3 and 6, the striker 2 is fixed to the striker carrier 12. The impactor carrier 12 has a recessed portion 121 and a supporting portion 122. In more detail, one end of the recessed portion 121 is engaged with the wafer stage 11 (inserted into the impact opening 111 of the wafer stage 11 and engaged with the bottom surface 112), and the recessed portion The other end of 121 is connected to the carrying portion 122. It should be noted that the striker carrier 12 is integrally formed in this embodiment. In other words, there is no gap between the recessed portion 121 and the carrying portion 122, but the present invention is not limited to this. For example, the striker carrier 12 may not be integrally formed, so the recessed portion 121 and the carrying portion 122 may be connected to each other in a combined manner.

In more detail, the recessed portion 121 has an insertion plate 1211 and a supporting portion 1212 connected to the carrying portion 122. Wherein, the insertion plate 1211 has a plurality of locking holes and is suspended on the ground relative to the supporting portion 1212, and the supporting portion 1212 and the carrying portion 122 are in a stepped shape. Furthermore, the distance that the supporting portion 1212 is suspended above the ground is substantially equal to the thickness of the bottom surface 112 of the wafer stage 11.

When the recessed portion 121 is inserted into the impact opening 111, the insertion plate 1211 is located on the bottom surface 112 of the wafer stage 11, and the straight edge of the bottom surface 112 and the support portion The 1212 snaps to each other. The plurality of locking holes and the plurality of locking holes of the bottom surface 112 correspond to each other and can be fixed to each other by a plurality of screws. The number of the locking holes is preferably 4, but the present invention Not limited to this. For example, in other embodiments not shown in the present invention, the number of the locking holes may also be three or more.

As shown in FIGS. 6 and 7, the carrying portion 122 is a rectangular parallelepiped and has an impactor carrying rail 1221. The impactor bearing rail 1221 is recessed from both ends of the bearing portion 122 in the longitudinal direction to form a long recessed rail. Wherein, the striker carrying rail 1221 can preferably accommodate half the volume of the striker 2 in this embodiment, and the striker carrying rail 1221 has a recess 12211 for engaging the striker 2 Fixed, but the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the impactor carrying rail 1221 can also accommodate more than half of the volume of the impactor 2.

As shown in FIGS. 3 and 10, the striker 2 is provided on the striker carrier 12 corresponding to the striker opening 111, and the striker 2 can operate along the predetermined plane 13 (such as: The striker 2 strikes the wafer to be tested 200 arranged on the predetermined plane 13). In more detail, when the wafer 200 to be tested is laid flat on the carrier 1, the striker 2 can pass through the striker 111 along the predetermined plane 13 and along the first A crystal orientation 201 impacts the pre-strike edge area of the wafer 200 to be tested (that is, the impact direction of the striker 2 is parallel to the first crystal orientation 201), so that the to-be-tested wafer 200 The test wafer 200 is broken into two half wafers 204 and 205 along the first crystal direction 201.

As shown in FIGS. 7 and 8, the striker 2 includes an striker 21 facing the striker 111 and an striker 22 integrally formed with the striker 21. Wherein, the impact rod 22 is combined with the force controller 3. When the striker 2 is set on the striker carrier 12, the striker 21 and the striker rod 22 are suspended.

The impact rod 22 is used to be pushed by the force controller 3 to cause the impact head 21 to impact the pre-strike edge area of the wafer 200 to be tested. Wherein, one end of the impact rod 22 is connected to the impact head 21, and the other end of the impact rod 22 is combined with the force controller 3. The impact The impact path of the rod 22 is in line with the first crystal orientation 201.

As shown in FIGS. 7 and 9, the outer surface of the impact head 21 is spherical, so that the impact head 21 can keep hitting the wafer 200 to be tested in a point contact manner at the moment when the impact head 21 hits the wafer to be tested. The pre-strike edge area (that is, the point of impact) of the wafer 200 is measured. Wherein, the center of the impact point and the impact head 21 are located on a straight line extending from the two ends of the impact rod 22. It should be noted that the radius of the impact head 21 is greater than the thickness of the wafer 200 to be tested.

As shown in Figs. 8 and 10, the force controller 3 can be used to control the force released by the striker 2 when it operates. In more detail, the striker 2 can use the force controller 3 to successively control the force of striking the wafer 200 to be tested, so as to accurately measure the strength of the wafer 200 to be tested. In this embodiment, the force controller 3 can measure the intensity value of the wafer 200 to be tested by successively increasing the impact force of 50 grams (g). As shown in FIG. 10, the force controller 3 controls the impactor 2 to impact the wafer 200 to be tested with an impact force of 600 grams (g) for the first time, and then gradually increases the impact force of 50 grams (g) until The force controller 3 controls the striker 2 to strike the wafer 200 to be tested with an impact force of 700 grams (g) and break the wafer 200 to be tested, and at the same time, the wafer to be tested is also measured 200 intensity. However, the present invention is not limited to this. The force controller 3 can adjust the impact force each time according to the requirements of the operator, and is not limited to adjusting the impact force of 50 grams (g) each time.

As shown in FIG. 8, the force controller 3 has a tension spring 31, a force scale indicator 32, and a hook 33. Wherein, one end of the tension spring 31 is connected to the impact rod 22, the other end of the tension spring 31 is connected to the hook 33, and the force scale indicator 32 is disposed on the hook 33. In this embodiment, the operator can use the hook 33 to extend the tension spring 31 so that its length corresponds to a specific scale on the force scale indicator 32 to control the force of the tension spring 31 when it is released. However, the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the force controller 3 may also be a gear electronic control device that can control the impact force. The gear electronic control device further includes a secondary collision preventing device, which can prevent the secondary collision of the striker 2 from affecting the test result.

As shown in FIGS. 4 and 5, the crystal orientation sensor 4 is an infrared sensor in this embodiment and the number is three, but the invention is not limited to this. For example, in other embodiments not shown in the present invention, the number of the crystal orientation sensors 4 may also be three or more. The crystal orientation sensor 4 is disposed on (or buried in) the side wall 113 of the wafer stage 11 and corresponds to the impact opening 111. Furthermore, the crystal orientation sensor 4 and the impact opening 111 are respectively located on the side wall 113 of the wafer stage 11 of the carrier 1. Wherein, when the wafer 200 to be tested is laid flat on the carrier 1, the crystal orientation sensor 4 can measure the first part of the wafer 200 to be tested along the predetermined plane 13. One crystal orientation 201, the second crystal orientation 202, and the third crystal orientation 203.

As shown in FIGS. 7 and 12, the supporting frame 5 has two locking members 51, a supporting arm 52 locked by the two locking members 51, and a supporting arm 52 arranged on the supporting arm 52. Rod 53. Wherein, the abutment rod 53 can be used to abut and position a broken edge of any one of the half wafers 204, 205 (for the convenience of description, the abutment rod 53 is used to position the semi-crystal in FIG. The fragmented edge of circle 204). It should be noted that, in this embodiment, the abutting rod 53 abuts and positions the half-wafer 204, and the support frame 5 is locked and fixed to the wafer stage through any fastener 51 On the mounting block 115 of 11, another locking member 51 and the abutting rod 53 are locked and fixed to an end of the support arm 52 relatively far away from the mounting block 115, but the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the other locking member 51 and the abutting rod 53 can also be mounted on the supporting arm 52 according to the size of the half wafer 204 Move up and then fix.

[Second Embodiment]

Refer to FIGS. 11 to 13B, which are the second embodiment of the present invention. It should be noted that this embodiment is similar to the above-mentioned first embodiment, so the similarities between the two embodiments will not be repeated; Furthermore, the relevant quantities and appearances mentioned in the corresponding drawings in this embodiment are only used to specifically The embodiments of the present invention are described to facilitate understanding of the content of the present invention, rather than to limit the protection scope of the present invention.

This embodiment discloses a wafer strength test method, which can perform at least three wafer strength tests on the same wafer 200 to be tested. As shown in FIG. 11, the wafer strength test method includes the following steps in sequence: a first preparation step S1, a first impact step S2, a second preparation step S3, a second impact step S4, a The third preparation step S5, a third impact step S6. Wherein, the first wafer strength test performs the first preparation step S1 and the first impact step S2, and the second wafer strength test performs the second preparation step S3 and the second impact step S4, For the third wafer strength test, the third preparation step S5 and the third impact step S6 are performed.

It should be noted that the wafer strength test method in this embodiment is implemented by the wafer lateral impact test device 100 in the first embodiment above, so in this embodiment, it is related to the wafer Please also refer to the first embodiment and FIGS. 2 to 10 for the description of the lateral impact test device 100, but the wafer strength test method of the present invention is not limited to be implemented by the wafer lateral impact test device 100.

The first preparation step S1: lay the wafer 200 to be tested on the carrier 1 (the wafer stage 11), and make the wafer 200 to be tested The striking edge area corresponds to the striking opening 111 of the bearing seat 1 for the striker 2 to strike. Wherein, the wafer 200 to be tested has the first crystal orientation 201, and each of the second crystal orientations 202 and the third crystal orientation 201 that are sandwiched by the first crystal orientation 201 is not greater than 90 degrees. Direction 203, but the present invention is not limited to this. For example, as shown in FIG. 5B, the wafer 200 to be tested may also only include the first crystal direction 201 and the same as the first crystal direction 201. The clamp forms the second crystal orientation 202 that is non-parallel.

The first impact step S2: use the impactor 2 to pass through the impact opening 111 along the predetermined plane 13 perpendicular to the normal vector of a wafer surface of the wafer 200 to be tested, and along the first A crystal orientation 201 hits the pre-strike edge area of the wafer 200 to be tested, and the first crystal orientation 201 Located in the pre-strike edge area, so that the wafer 200 to be tested is broken into two half wafers 204 and 205 along the first crystal direction 201. Wherein, the impact direction of the striker 2 is parallel to the first crystal orientation 201. The two half wafers 204 and 205 formed by the fragmentation of the wafer 200 to be tested are arranged in mirror symmetry with each other. Each of the half wafers 204, 205 includes a chipping edge parallel to the first crystal orientation 201, and the two half wafers 204, 205 are defined as a first half wafer 204 and a second half wafer 204, respectively. Two-half wafer 205.

As shown in FIGS. 12 and 13A, the second preparation step S3: lay the first half-wafer 204 on the carrier 1 (the wafer carrier 11), and install it The support frame 5 of the carrier 1 presses against and positions the cracked edge of the first half-wafer 204, so that a pre-strike edge area of the first half-wafer 204 corresponds to the cracked edge of the first half-wafer 204. The impact opening 111 of the bearing seat 1. Wherein, part of the pre-strike edge area abuts against the side wall 113 of the wafer carrier 11.

The second impact step S4: use the impactor 2 to pass through the impact opening 111 along the predetermined plane 13 and impact on all the first half wafer 204 along the second crystal direction 202 The pre-strike edge region, and the second crystal orientation 202 is located in the pre-strike edge region, so that the first half-wafer 204 is broken along the second crystal direction 202. Wherein, the impact path of the impactor 2 is in a straight line with the second crystal orientation 202, and the impact force of the impactor 2 in the second impact step S4 and the impact force of the impactor 2 in the first The impact force in the impact step S2 is different.

As shown in FIG. 12 and FIG. 13B, the third preparation step S5: lay the second half wafer 205 flat on the carrier 1 (the wafer carrier 11), and use the The support frame 5 presses against and positions the cracked edge of the second half-wafer 205 so that a pre-strike edge area of the second half-wafer 205 corresponds to the impact opening of the carrier 1 111. Wherein, part of the pre-strike edge area abuts against the side wall 113 of the wafer carrier 11.

The third impact step S6: use the impactor 2 to pass through the impact opening 111 along the predetermined plane 13 and impact on the second half-wafer 205 along the third crystal orientation 203 Narrate Pre-strike the edge region, and the third crystal orientation 203 is located in the pre-strike edge region, so that the second half-wafer 205 is broken along the third crystal orientation 203. Wherein, the impact path of the impactor 2 is in a straight line with the third crystal orientation 203, and the impact force of the impactor 2 in the third impact step S6 is the same as that of the impactor 2 in the The impact force in the first impact step S2 is different from the impact force in the second impact step S4.

[Beneficial effects of the embodiment]

One of the beneficial effects of the present invention is that the wafer lateral impact test device and the wafer strength test method can impact the pre-strike along the predetermined plane where the wafer to be tested is located. The edge area is used to test the test strength required for the wafer to be tested to break along the crystal direction.

Furthermore, the wafer lateral impact test device and wafer strength test method provided by the present invention can pass "the bearing seat with the impact port located on the predetermined plane and corresponding to the impact port" The impactor provided", "in the first preparation step, the wafer to be tested is laid flat on the carrier, and the pre-strike edge area of the wafer to be tested corresponds to In the impact opening of the carrier," and "in the first impact step, the impactor passes through the predetermined plane perpendicular to the normal vector of a wafer surface of the wafer to be tested. The impingement port and hitting the pre-strike edge area of the wafer to be tested, so that the wafer to be tested is broken into two half-wafers along the first crystal orientation", In order to increase the test times of the wafer lateral impact test device, the time and cost of the wafer strength test method are greatly saved.

The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the description and schematic content of the present invention are included in the application of the present invention. Within the scope of the patent.

100: Wafer lateral impact test device

1: bearing seat

11: Wafer stage

111: impact port

113: Sidewall

115: installation block

12: Impactor carrier

13: Scheduled plane

2: Impactor

22: Impact bar

3: Force controller

32: Force scale indicator

33: hook

4: Crystal orientation sensor

5: Support frame

51: lock firmware

52: Support arm

53: top bar

Claims (10)

A wafer lateral impact test device, comprising: a bearing seat with an impact opening located on a predetermined plane; wherein, the bearing seat is used for a wafer to be tested lying down on the predetermined plane. On a plane, and the wafer to be tested is defined with a crystal orientation passing through its center; and a striker, which is arranged corresponding to the striker, and the striker can operate along the predetermined plane; wherein , The impact direction of the striker is parallel to the crystal orientation; wherein, when the wafer to be tested is laid flat on the carrier, the striker can pass through the predetermined plane The impingement port and hit a pre-strike edge area of the wafer to be tested along the crystal direction, so that the wafer to be tested is broken into two half wafers along the crystal direction; The pre-strike edge area is an edge portion of the wafer to be tested located at the impact port. The wafer lateral impact test device according to claim 1, wherein the wafer lateral impact test device further includes a support frame movably installed on the carrier, and the support frame can be used to top A chipped edge of any one of the half wafers is pressed and positioned. The wafer lateral impact test device according to claim 1, wherein the wafer lateral impact test device further includes a crystal orientation sensor installed on the carrier, and the crystal orientation sensor is connected to The impact openings are respectively located on the sidewalls of the supporting base; wherein, when the wafer to be tested is laid flat on the supporting base, the crystal orientation sensor can measure the The crystal orientation of the wafer to be tested. The wafer lateral impact test device according to claim 1, wherein the impact The device includes an impact head facing the impact port, and the outer surface of the impact head is spherical, so that the impact head can be used to keep hitting the pre-strike edge area in a point contact manner. The wafer lateral impact test device according to claim 4, wherein the radius of the impact head is greater than the thickness of the wafer to be tested. The wafer lateral impact test device according to claim 4, wherein the carrier includes a wafer stage on which the impact port is formed and an impactor stage connected to the wafer stage, and the The striker is fixed on the striker carrier, and the striker is suspended. The wafer lateral impact test device according to claim 1, wherein the wafer lateral impact test device further includes a force controller connected to the striker, and the force controller can be used to control all State the force released by the impactor during operation. A method for testing the strength of a wafer, comprising: a first preparation step: lay a wafer to be tested on a carrier, and make a pre-strike edge area of the wafer to be tested correspond to the An impact port of the carrier; wherein the wafer to be tested includes a first crystal orientation and a second crystal orientation that is non-parallel to the first crystal orientation; and a first impact step: An impactor passes through the impact opening along a predetermined plane perpendicular to the normal vector of a wafer surface of the wafer to be tested, and strikes the pre-test of the wafer to be tested along the first crystal direction. Hitting the edge area, so that the wafer to be tested is broken into two half-wafers along the first crystal orientation; wherein the impact direction of the striker is parallel to the first crystal orientation; Wherein, each of the half-wafers includes a chipping edge parallel to the first crystal orientation, and the two half-wafers are defined as a first half-wafer and a second half-wafer respectively; wherein The pre-strike edge area is an edge portion of the wafer to be tested located at the impact port. The wafer strength testing method according to claim 8, wherein the wafer strength testing method further comprises: a second preparation step: laying the first half wafer flat on the carrier, And a support frame installed on the carrier is used to abut and position the chipping edge of the first half-wafer so that a pre-strike edge area of the first half-wafer corresponds to the carrier The impact opening of the seat; wherein the second crystal orientation is located in the pre-strike edge region; and a second impact step: use the impactor to pass through the impact opening along the predetermined plane and along the The second crystal direction impinges on the pre-strike edge area of the first half-wafer, so that the first half-wafer is broken along the second crystal direction. The wafer strength testing method according to claim 9, wherein the wafer to be tested further includes a third crystal orientation, and the third crystal orientation is respectively related to the first crystal orientation and the second crystal orientation. The wafer strength test method further includes: a third preparation step: lay the second half-wafer on the carrier and place it on top of the support frame. Abutting and positioning the chipping edge of the second half-wafer so that a pre-strike edge area of the second half-wafer corresponds to the impact opening of the carrier; and a third impact step : Use the striker to pass through the striker along the predetermined plane and strike the second half-wafer along the third crystal direction Pre-strike the edge area to make the second half-wafer fragment along the third crystal direction.

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