TWI727860B - Wafer transverse impact test device and wafer strength test method - Google Patents

Wafer transverse impact test device and wafer strength test method Download PDF

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TWI727860B
TWI727860B TW109124718A TW109124718A TWI727860B TW I727860 B TWI727860 B TW I727860B TW 109124718 A TW109124718 A TW 109124718A TW 109124718 A TW109124718 A TW 109124718A TW I727860 B TWI727860 B TW I727860B
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wafer
impact
tested
crystal orientation
carrier
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TW109124718A
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Chinese (zh)
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謝偉傑
陳瑞斌
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環球晶圓股份有限公司
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Abstract

A wafer transverse impact test device and a wafer strength test method are provided. The wafer transverse impact test device includes a carrier and an impactor. The wafer strength test method includes a first preparation step and a first impact step. The first preparation step provides a test wafer disposed and lying flat on the carrier and a pre-impacted edge zone of the test wafer corresponds to an impact opening of the carrier. The first impact step provides the impactor passing through the impact opening and impacting the pre-impacted edge zone of the test wafer along a predetermined plane that is perpendicular to a normal vector of the test wafer. Accordingly, the test wafer breaks into two half-wafers along a crystal direction of the test wafer. Each of the half-wafers includes a fractured edge that is parallel to the crystal direction, and the two half-wafers are respectively defined as a first half-wafer and a second half-wafer.

Description

晶圓橫向撞擊測試裝置及晶圓強度測試方法 Wafer lateral impact test device and wafer strength test method
本發明涉及一種晶圓測試裝置及一種晶圓測試方法,特別是涉及一種晶圓橫向撞擊測試裝置及晶圓強度測試方法。 The invention relates to a wafer testing device and a wafer testing method, in particular to a wafer lateral impact testing device and a wafer strength testing method.
如圖1所示,習知的晶圓強度測試裝置及晶圓強度測試方法在測試單片晶圓的機械強度時,往往是以垂直晶圓表面的方向進行抗折測試(請參酌中國公告專利號CN105181462A以及圖1),但此種測試已逐漸無法滿足現今的晶圓強度測試需求。故,如何通過晶圓撞擊測試裝置的結構設計的改良或是晶圓強度測試方法的設計或改良,來克服上述的缺陷,已成為該項事業所欲解決的重要課題之一。 As shown in Figure 1, when the conventional wafer strength test device and wafer strength test method test the mechanical strength of a single wafer, the bending resistance test is often performed in the direction perpendicular to the wafer surface (please refer to the Chinese patent No. CN105181462A and Figure 1), but this kind of test has gradually been unable to meet the current wafer strength test requirements. Therefore, how to overcome the above-mentioned defects through the improvement of the structural design of the wafer impact test device or the design or improvement of the wafer strength test method has become one of the important issues to be solved by this business.
本發明針對現有技術的不足提供一種晶圓橫向撞擊測試裝置,其包括:一承載座,具有位在一預定平面上的一撞擊口;其中,所述承載座用以供一待測晶圓平躺設置而落在所述預定平面上,並且所述待測晶圓定義有穿過其中心的一晶向;以及一撞擊器,其對應於所述撞擊口設置,並且所述撞擊器能沿著所述預定平面運作;其中,所述撞擊器的撞擊方向與所述晶向呈平行;其中,當所述待測晶圓平躺地設置於所述承載座時,所述撞 擊器能沿所述預定平面穿過所述撞擊口、並沿所述晶向撞擊在所述待測晶圓的一預擊邊緣區,以使所述待測晶圓沿所述晶向而碎裂成兩個半晶圓;其中,所述預擊邊緣區為位於所述撞擊口的所述待測晶圓的邊緣部分。 In view of the shortcomings of the prior art, the present invention provides a wafer transverse impact test device, which includes: a bearing seat with an impact opening positioned on a predetermined plane; wherein the bearing seat is used for a wafer to be tested flat Lying and falling on the predetermined plane, and the wafer to be tested is defined with a crystal orientation passing through its center; and a striker, which is arranged corresponding to the striker, and the striker can move along the Operating on the predetermined plane; wherein the impact direction of the striker is parallel to the crystal direction; wherein, when the wafer to be tested is laid flat on the carrier, the impact The striker can pass through the impact opening along the predetermined plane, and strike a pre-strike edge area of the wafer to be tested along the crystal direction, so that the wafer to be tested moves along the crystal direction. Fragmented into two half wafers; wherein, the pre-strike edge area is the edge portion of the wafer to be tested located at the impact port.
為了解決上述的技術問題,本發明所採用的其中一技術方案是提供一種晶圓強度測試方法,其包括:一第一準備步驟:將一待測晶圓平躺地設置於一承載座上,並使所述待測晶圓的一預擊邊緣區對應於所述承載座的一撞擊口;其中,所述待測晶圓包含一第一晶向、及與所述第一晶向相夾形成非平行的一第二晶向;以及一第一撞擊步驟:以一撞擊器沿著垂直所述待測晶圓的一晶圓面法向量的一預定平面穿過所述撞擊口、並沿所述第一晶向撞擊在所述待測晶圓的所述預擊邊緣區,以使所述待測晶圓沿所述第一晶向而碎裂成兩個半晶圓;其中,所述撞擊器的撞擊方向與所述第一晶向呈平行;其中,每個所述半晶圓包含有平行所述第一晶向的一碎裂邊緣,並且兩個所述半晶圓分別定義為一第一半晶圓與一第二半晶圓;其中,所述預擊邊緣區為位於所述撞擊口的所述待測晶圓的邊緣部分。 In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a wafer strength testing method, which includes: a first preparation step: laying a wafer to be tested on a carrier, And make a pre-strike edge area of the wafer to be tested correspond to an impact port of the carrier; wherein the wafer to be tested includes a first crystal orientation and is sandwiched with the first crystal orientation Forming a second non-parallel crystal orientation; and a first impact step: using an impactor to pass through the impact opening along a predetermined plane perpendicular to the normal vector of a wafer surface of the wafer to be tested, and along The first crystal orientation hits the pre-strike edge area of the wafer to be tested, so that the wafer to be tested is broken into two half wafers along the first crystal orientation; The impact direction of the striker is parallel to the first crystal orientation; wherein each half-wafer includes a fragmentation edge parallel to the first crystal orientation, and the two half-wafers are respectively defined It is a first half-wafer and a second half-wafer; wherein the pre-strike edge area is the edge portion of the wafer to be tested located at the impact port.
本發明的其中一有益效果在於,所述晶圓橫向撞擊測試裝置及晶圓強度測試方法能將以撞擊器沿著所述待測晶圓所處的所述預定平面而撞擊在所述預擊邊緣區,據以測試所述待測晶圓沿所述晶向而碎裂所需的測試強度。 One of the beneficial effects of the present invention is that the wafer lateral impact test device and the wafer strength test method can impact the pre-strike along the predetermined plane where the wafer to be tested is located. The edge area is used to test the test strength required for the wafer to be tested to break along the crystal direction.
為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與圖式,然而所提供的圖式僅用於提供參考與說明,並非用來對本發明加以限制。 In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the provided drawings are only for reference and description, and are not used to limit the present invention.
100:晶圓橫向撞擊測試裝置 100: Wafer lateral impact test device
1:承載座 1: bearing seat
11:晶圓載台 11: Wafer stage
111:撞擊口 111: impact port
112:底面 112: Bottom
113:側壁 113: Sidewall
114:承載凸塊 114: Carrying bump
115:安裝塊 115: installation block
12:撞擊器載台 12: Impactor carrier
121:凹陷部 121: Depressed part
1211:插入板 1211: Insert board
1212:支撐部 1212: Support
122:承載部 122: Bearing Department
1221:撞擊器承載軌道 1221: Impactor carrying rail
12211:凹部 12211: recess
13:預定平面 13: Scheduled plane
2:撞擊器 2: Impactor
21:撞擊頭 21: Impact head
22:撞擊桿 22: Impact bar
3:力道控制器 3: Force controller
31:拉力彈簧 31: Tension spring
32:力道刻度標示計 32: Force scale indicator
33:掛勾 33: hook
4:晶向感測器 4: Crystal orientation sensor
5:支撐架 5: Support frame
51:鎖固件 51: lock firmware
52:支撐臂 52: Support arm
53:頂抵桿 53: top bar
200:待測晶圓 200: wafer to be tested
201:第一晶向 201: The first crystal orientation
202:第二晶向 202: second crystal orientation
203:第三晶向 203: The Third Crystal Orientation
204:第一半晶圓 204: first half wafer
205:第二半晶圓 205: second half wafer
S1:第一準備步驟 S1: The first preparation step
S2:第一撞擊步驟 S2: First impact step
S3:第二準備步驟 S3: Second preparation step
S4:第二撞擊步驟 S4: Second impact step
S5:第三準備步驟 S5: The third preparatory step
S6:第三撞擊步驟 S6: Third impact step
圖1為習知的晶圓強度測試裝置的動作示意圖。 FIG. 1 is a schematic diagram of the operation of a conventional wafer strength testing device.
圖2為本發明第一實施例的晶圓橫向撞擊測試裝置的立體示意圖。 FIG. 2 is a three-dimensional schematic diagram of the wafer lateral impact test device according to the first embodiment of the present invention.
圖3為本發明第一實施例的晶圓橫向撞擊測試裝置的分解示意圖。 3 is an exploded schematic diagram of the wafer lateral impact test device according to the first embodiment of the present invention.
圖4為本發明第一實施例的晶圓載台的立體示意圖。 FIG. 4 is a three-dimensional schematic diagram of the wafer carrier according to the first embodiment of the present invention.
圖5A為本發明第一實施例的待測晶圓的平面示意圖。 5A is a schematic plan view of the wafer to be tested according to the first embodiment of the present invention.
圖5B為本發明第一實施例的另一待測晶圓的平面示意圖。 5B is a schematic plan view of another wafer to be tested according to the first embodiment of the present invention.
圖6為本發明第一實施例的撞擊器載台的立體示意圖。 FIG. 6 is a three-dimensional schematic diagram of the impactor carrier according to the first embodiment of the present invention.
圖7為本發明第一實施例的撞擊器撞擊待測晶圓的立體示意圖。 FIG. 7 is a three-dimensional schematic diagram of the impactor hitting the wafer to be tested according to the first embodiment of the present invention.
圖8為本發明第一實施例的撞擊器的示意圖。 Fig. 8 is a schematic diagram of the striker of the first embodiment of the present invention.
圖9為圖6的VIII部分的放大示意圖。 Fig. 9 is an enlarged schematic diagram of part VIII of Fig. 6.
圖10為本發明第一實施例的撞擊器撞擊待測晶圓的撞擊力道變化示意圖。 FIG. 10 is a schematic diagram of the change of the impact force of the impactor against the wafer to be tested according to the first embodiment of the present invention.
圖11為本發明第二實施例的晶圓強度測試方法的流程圖。 FIG. 11 is a flowchart of a wafer strength testing method according to a second embodiment of the present invention.
圖12為本發明第二實施例的支撐架抵頂半晶圓的示意圖。 FIG. 12 is a schematic diagram of a support frame against a half-wafer according to a second embodiment of the present invention.
圖13A為本發明第二實施例的撞擊器撞擊第一半晶圓的示意圖。 FIG. 13A is a schematic diagram of the striker hitting the first half wafer according to the second embodiment of the present invention.
圖13B為本發明第二實施例的撞擊器撞擊第二半晶圓的示意圖。 FIG. 13B is a schematic diagram of the striker hitting the second half-wafer according to the second embodiment of the present invention.
以下是通過特定的具體實施例來說明本發明所公開有關“晶圓橫向撞擊測試裝置及晶圓強度測試方法”的實施方式,本領域技術人員可 由本說明書所公開的內容瞭解本發明的優點與效果。本發明可通過其他不同的具體實施例加以施行或應用,本說明書中的各項細節也可基於不同觀點與應用,在不背離本發明的構思下進行各種修改與變更。另外,本發明的附圖僅為簡單示意說明,並非依實際尺寸的描繪,事先聲明。以下的實施方式將進一步詳細說明本發明的相關技術內容,但所公開的內容並非用以限制本發明的保護範圍。 The following is a specific embodiment to illustrate the implementation of the "wafer lateral impact test device and wafer strength test method" disclosed in the present invention. Those skilled in the art can The advantages and effects of the present invention can be understood from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual size, and are stated in advance. The following embodiments will further describe the related technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention.
應當可以理解的是,雖然本文中可能會使用到“第一”、“第二”、“第三”等術語來描述各種元件或者信號,但這些元件或者信號不應受這些術語的限制。這些術語主要是用以區分一元件與另一元件,或者一信號與另一信號。另外,本文中所使用的術語“或”,應視實際情況可能包括相關聯的列出項目中的任一個或者多個的組合。 It should be understood that although terms such as "first", "second", and "third" may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another, or one signal from another signal. In addition, the term "or" used in this document may include any one or a combination of more of the associated listed items depending on the actual situation.
[第一實施例] [First Embodiment]
請參閱圖2至圖10所示,其為本發明的第一實施例,需先說明的是,本實施例對應附圖所提及的相關數量與外型,僅用來具體地說明本發明的實施方式,以便於了解本發明的內容,而非用來侷限本發明的保護範圍。 Please refer to Figures 2 to 10, which are the first embodiment of the present invention. It should be noted that the relevant quantities and appearances mentioned in the corresponding drawings of this embodiment are only used to specifically illustrate the present invention. In order to understand the content of the present invention, it is not used to limit the protection scope of the present invention.
參閱圖2及圖3所示,本實施例公開一種晶圓橫向撞擊測試裝置100,其包括:一承載座1、對應所述承載座1設置的一撞擊器2、連接於所述撞擊器2的一力道控制器3、安裝於所述承載座1的一晶向感測器4、及可活動地安裝於所述承載座1的一支撐架5。 2 and 3, this embodiment discloses a wafer lateral impact test device 100, which includes: a bearing seat 1, a striker 2 corresponding to the bearing seat 1, connected to the striker 2 A force controller 3, a crystal orientation sensor 4 installed on the carrier 1, and a support frame 5 movably installed on the carrier 1.
如圖2及圖7所示,所述承載座1具有一晶圓載台11以及連接所述晶圓載台11的一撞擊器載台12。其中,所述晶圓載台11形成有位在一預定平面13上的一撞擊口111,並且所述承載座1(的所述晶圓載台11)用以供一待測晶圓200平躺設置而落在所述預定平面13上。其中,所述待測晶圓200具有一預擊邊緣區用以供所述撞擊器2進行晶圓橫向撞擊測試。需要說明的是, 所述預擊邊緣區為位於所述撞擊口的所述待測晶圓的邊緣部分。 As shown in FIGS. 2 and 7, the carrier 1 has a wafer carrier 11 and an impactor carrier 12 connected to the wafer carrier 11. Wherein, the wafer carrier 11 is formed with an impact opening 111 located on a predetermined plane 13, and the carrier 1 (the wafer carrier 11) is used for a wafer 200 to be tested lying down. It falls on the predetermined plane 13. Wherein, the wafer 200 to be tested has a pre-strike edge area for the striker 2 to perform a wafer lateral impact test. It should be noted, The pre-strike edge area is an edge portion of the wafer to be tested located at the impact port.
如圖5A所示,所述待測晶圓200包含穿過其中心的兩個晶向,於本實施例中,其中一個所述晶向定義為一第一晶向201,另一個所述晶向定義為一第二晶向202,並且所述第一晶向201與所述第二晶向202相夾呈非平行。進一步地說,所述第一晶向201與所述第二晶向202相夾較佳呈90度,但本發明並不限於此,舉例來說,所述如圖5B所示,所述待測晶圓200可以包含穿過其中心的所述第一晶向201、及各與所述第一晶向201相夾形成有不大於90度的所述第二晶向202與一第三晶向203。其中,所述第一晶向201、所述第二晶向202、以及所述第三晶向203相交於所述待測晶圓200的圓心。 As shown in FIG. 5A, the wafer 200 to be tested includes two crystal orientations passing through its center. In this embodiment, one of the crystal orientations is defined as a first crystal orientation 201, and the other crystal orientation is defined as a first crystal orientation 201. The orientation is defined as a second crystal orientation 202, and the first crystal orientation 201 and the second crystal orientation 202 are sandwiched non-parallel. Furthermore, the first crystal orientation 201 and the second crystal orientation 202 are preferably sandwiched by 90 degrees, but the present invention is not limited to this. For example, as shown in FIG. 5B, the waiting The test wafer 200 may include the first crystal orientation 201 passing through its center, and the second crystal orientation 202 and a third crystal orientation 201 that are sandwiched by the first crystal orientation 201 and formed by no more than 90 degrees. To 203. Wherein, the first crystal orientation 201, the second crystal orientation 202, and the third crystal orientation 203 intersect at the center of the wafer 200 to be tested.
需要說明的是,於本實施例中,所述第一晶向201與所述第二晶向202相夾的角度呈60度,所述第一晶向201與所述第三晶向203相夾的角度呈60度,所述第二晶向202與所述第三晶向203相夾的角度呈120度。 It should be noted that, in this embodiment, the angle between the first crystal orientation 201 and the second crystal orientation 202 is 60 degrees, and the first crystal orientation 201 is opposite to the third crystal orientation 203. The clamping angle is 60 degrees, and the angle between the second crystal orientation 202 and the third crystal orientation 203 is 120 degrees.
需要說明的是,所述待測晶圓200於本實施例中較佳是一磊晶晶圓片(Epitaxial Wafer)。其中,所述待測晶圓200的尺寸較佳是6吋(inch),但本實施例並不限於此。舉例來說,所述待測晶圓200也可以是一拋光矽晶圓片(Polished Wafer)或是其他種類的矽晶圓片,而所述待測晶圓200的尺寸也可以是8吋或12吋等其他尺寸。 It should be noted that the wafer 200 to be tested is preferably an epitaxial wafer in this embodiment. Wherein, the size of the wafer 200 to be tested is preferably 6 inches (inch), but this embodiment is not limited to this. For example, the wafer 200 to be tested can also be a polished wafer or other types of silicon wafers, and the size of the wafer 200 to be tested can also be 8 inches or Other sizes such as 12 inches.
如圖3及圖4所示,所述晶圓載台11具有呈圓形的一底面112、環繞設置於所述底面112邊緣的一側壁113、設置於所述底面112的邊緣且貼靠所述側壁113的多個承載凸塊114、以及設置於所述側壁113相對遠離多個所述承載凸塊114一側的一安裝塊115。其中,所述預定平面13位於多個所述承載凸塊114的上方,所述撞擊口111形成於所述側壁113。多個所述承載凸塊114位於所述底面112與所述預定平面13之間,且所述底面112與所述預定平面13 彼此相互平行。所述安裝塊115用以供所述支撐架5鎖入固定,但本發明不以上述為限。 As shown in FIGS. 3 and 4, the wafer carrier 11 has a circular bottom surface 112, a side wall 113 surrounding the edge of the bottom surface 112, and is disposed on the edge of the bottom surface 112 and abuts against the bottom surface 112. A plurality of carrying protrusions 114 of the side wall 113 and a mounting block 115 disposed on a side of the side wall 113 relatively far away from the plurality of carrying protrusions 114. Wherein, the predetermined plane 13 is located above the plurality of bearing bumps 114, and the impact opening 111 is formed on the side wall 113. A plurality of the bearing bumps 114 are located between the bottom surface 112 and the predetermined plane 13, and the bottom surface 112 and the predetermined plane 13 Parallel to each other. The mounting block 115 is used to lock the support frame 5 into and fixed, but the present invention is not limited to the above.
需要說明的是,所述底面112於本實施例中具有一厚度以及多個鎖入孔,其用以與所述撞擊器載台12相互鎖入固定。其中,所述底面112鄰近所述撞擊口111的一邊緣呈直線狀,且所述鎖入孔的數量較佳是4個,但本發明並不以此為限。舉例來說,在本發明未繪示的其他實施例中,所述撞擊口111的所述邊緣也可以呈圓弧狀,且所述鎖入孔的數量也可以是3個以上。 It should be noted that, in this embodiment, the bottom surface 112 has a thickness and a plurality of locking holes, which are used for locking and fixing the striker carrier 12 with each other. Wherein, an edge of the bottom surface 112 adjacent to the impact opening 111 is linear, and the number of the locking holes is preferably four, but the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the edge of the impact opening 111 may also be arc-shaped, and the number of the locking holes may also be three or more.
如圖3及圖6所示,所述撞擊器載台12固定有所述撞擊器2。所述撞擊器載台12具有一凹陷部121以及一承載部122。更詳細地說,所述凹陷部121的一端與所述晶圓載台11卡合連接(插入所述晶圓載台11的所述撞擊口111並卡合於所述底面112),所述凹陷部121的另一端與所述承載部122連接。需要說明的是,所述撞擊器載台12於本實施例中是一體成形。也就是說,所述凹陷部121與所述承載部122的連接處沒有間隙,但本發明並不以此為限。舉例來說,所述撞擊器載台12也可以不是一體成形,因此所述凹陷部121與所述承載部122可以以組合的方式相互連接。 As shown in FIGS. 3 and 6, the striker 2 is fixed to the striker carrier 12. The impactor carrier 12 has a recessed portion 121 and a supporting portion 122. In more detail, one end of the recessed portion 121 is engaged with the wafer stage 11 (inserted into the impact opening 111 of the wafer stage 11 and engaged with the bottom surface 112), and the recessed portion The other end of 121 is connected to the carrying portion 122. It should be noted that the striker carrier 12 is integrally formed in this embodiment. In other words, there is no gap between the recessed portion 121 and the carrying portion 122, but the present invention is not limited to this. For example, the striker carrier 12 may not be integrally formed, so the recessed portion 121 and the carrying portion 122 may be connected to each other in a combined manner.
更詳細地說,所述凹陷部121具有一插入板1211以及與所述承載部122連接的一支撐部1212。其中,所述插入板1211具有多個鎖固孔且相對於所述支撐部1212懸空於地面,所述支撐部1212與所述承載部122之間呈階梯狀。進一步地說,所述支撐部1212懸空於地面的距離大致等於所述晶圓載台11的所述底面112的所述厚度。 In more detail, the recessed portion 121 has an insertion plate 1211 and a supporting portion 1212 connected to the carrying portion 122. Wherein, the insertion plate 1211 has a plurality of locking holes and is suspended on the ground relative to the supporting portion 1212, and the supporting portion 1212 and the carrying portion 122 are in a stepped shape. Furthermore, the distance that the supporting portion 1212 is suspended above the ground is substantially equal to the thickness of the bottom surface 112 of the wafer stage 11.
當所述凹陷部121插入所述撞擊口111時,所述插入板1211位於所述晶圓載台11的所述底面112上,且所述底面112中呈直線的所述邊緣與所述支撐部1212相互卡合。多個所述鎖固孔與所述底面112的多個所述鎖入孔相互對應且可經由多個螺絲相互固定。所述鎖固孔的數量較佳是4個,但本發明 並不以此為限。舉例來說,在本發明未繪示的其他實施例中,所述鎖固孔的數量也可以是3個以上。 When the recessed portion 121 is inserted into the impact opening 111, the insertion plate 1211 is located on the bottom surface 112 of the wafer stage 11, and the straight edge of the bottom surface 112 and the support portion The 1212 snaps to each other. The plurality of locking holes and the plurality of locking holes of the bottom surface 112 correspond to each other and can be fixed to each other by a plurality of screws. The number of the locking holes is preferably 4, but the present invention Not limited to this. For example, in other embodiments not shown in the present invention, the number of the locking holes may also be three or more.
如圖6及圖7所示,所述承載部122是一長方體且具有一撞擊器承載軌道1221。所述撞擊器承載軌道1221自所述承載部122的長度方向的兩端凹陷並形成長條凹陷狀的一軌道。其中,所述撞擊器承載軌道1221於本實施例中較佳可容納所述撞擊器2的一半體積,而且所述撞擊器承載軌道1221具有一凹部12211,用以供所述撞擊器2卡合固定,但本發明並不以此為限。舉例來說,在本發明未繪示的其他實施例中,所述撞擊器承載軌道1221也可以容納所述撞擊器2一半以上的體積。 As shown in FIGS. 6 and 7, the carrying portion 122 is a rectangular parallelepiped and has an impactor carrying rail 1221. The impactor bearing rail 1221 is recessed from both ends of the bearing portion 122 in the longitudinal direction to form a long recessed rail. Wherein, the striker carrying rail 1221 can preferably accommodate half the volume of the striker 2 in this embodiment, and the striker carrying rail 1221 has a recess 12211 for engaging the striker 2 Fixed, but the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the impactor carrying rail 1221 can also accommodate more than half of the volume of the impactor 2.
如圖3及圖10所示,所述撞擊器2對應於所述撞擊口111設置於所述撞擊器載台12上,並且所述撞擊器2能沿著所述預定平面13運作(如:所述撞擊器2撞擊設置於所述預定平面13上的所述待測晶圓200)。更詳細地說,當所述待測晶圓200平躺地設置於所述承載座1時,所述撞擊器2能沿所述預定平面13穿過所述撞擊口111、並沿所述第一晶向201撞擊在所述待測晶圓200的所述預擊邊緣區(也就是說,所述撞擊器2的撞擊方向與所述第一晶向201呈平行),以使所述待測晶圓200沿所述第一晶向201而碎裂成兩個半晶圓204、205。 As shown in FIGS. 3 and 10, the striker 2 is provided on the striker carrier 12 corresponding to the striker opening 111, and the striker 2 can operate along the predetermined plane 13 (such as: The striker 2 strikes the wafer to be tested 200 arranged on the predetermined plane 13). In more detail, when the wafer 200 to be tested is laid flat on the carrier 1, the striker 2 can pass through the striker 111 along the predetermined plane 13 and along the first A crystal orientation 201 impacts the pre-strike edge area of the wafer 200 to be tested (that is, the impact direction of the striker 2 is parallel to the first crystal orientation 201), so that the to-be-tested wafer 200 The test wafer 200 is broken into two half wafers 204 and 205 along the first crystal direction 201.
如圖7及圖8所示,所述撞擊器2包含有面向所述撞擊口111的一撞擊頭21、以及與所述撞擊頭21一體成形的一撞擊桿22。其中,所述撞擊桿22與所述力道控制器3組合。當所述撞擊器2設置於所述撞擊器載台12上時,所述撞擊頭21與所述撞擊桿22呈懸空狀。 As shown in FIGS. 7 and 8, the striker 2 includes an striker 21 facing the striker 111 and an striker 22 integrally formed with the striker 21. Wherein, the impact rod 22 is combined with the force controller 3. When the striker 2 is set on the striker carrier 12, the striker 21 and the striker rod 22 are suspended.
所述撞擊桿22用來被所述力道控制器3推動,進而使所述撞擊頭21撞擊所述待測晶圓200的所述預擊邊緣區。其中,所述撞擊桿22的一端連接所述撞擊頭21,所述撞擊桿22的另一端與所述力道控制器3組合。所述撞擊 桿22的撞擊路徑與所述第一晶向201呈一直線。 The impact rod 22 is used to be pushed by the force controller 3 to cause the impact head 21 to impact the pre-strike edge area of the wafer 200 to be tested. Wherein, one end of the impact rod 22 is connected to the impact head 21, and the other end of the impact rod 22 is combined with the force controller 3. The impact The impact path of the rod 22 is in line with the first crystal orientation 201.
如圖7及圖9所示,所述撞擊頭21的外表面呈球面狀,以使所述撞擊頭21在撞擊所述待測晶圓200的瞬間能保持以點接觸的方式撞擊所述待測晶圓200的所述預擊邊緣區(也就是,撞擊點)。其中,所述撞擊點與所述撞擊頭21的圓心位在所述撞擊桿22的兩端相連所延伸的一直線上。需要說明的是,所述撞擊頭21的半徑大於所述待測晶圓200的厚度。 As shown in FIGS. 7 and 9, the outer surface of the impact head 21 is spherical, so that the impact head 21 can keep hitting the wafer 200 to be tested in a point contact manner at the moment when the impact head 21 hits the wafer to be tested. The pre-strike edge area (that is, the point of impact) of the wafer 200 is measured. Wherein, the center of the impact point and the impact head 21 are located on a straight line extending from the two ends of the impact rod 22. It should be noted that the radius of the impact head 21 is greater than the thickness of the wafer 200 to be tested.
如圖8及圖10所示,所述力道控制器3能用來控制所述撞擊器2運作時所釋放的力量。更詳細的說,所述撞擊器2可藉由所述力道控制器3逐次控制撞擊所述待測晶圓200的力道,以精準地測量所述待測晶圓200的強度。於本實施例中,所述力道控制器3可經由逐次增加50公克(g)的撞擊力道以測量相應的所述待測晶圓200的強度數值。如圖10所示,所述力道控制器3首次控制所述撞擊器2以600公克(g)的撞擊力道撞擊所述待測晶圓200,而後逐次增加50公克(g)的撞擊力道,直到所述力道控制器3控制所述撞擊器2以700公克(g)的撞擊力道撞擊所述待測晶圓200並使所述待測晶圓200破裂,同時也測得所述待測晶圓200的強度。但本發明並不限於此,所述力道控制器3可依操作人員需求調整每次的撞擊力道,並不限於每次調整50公克(g)的撞擊力道。 As shown in Figs. 8 and 10, the force controller 3 can be used to control the force released by the striker 2 when it operates. In more detail, the striker 2 can use the force controller 3 to successively control the force of striking the wafer 200 to be tested, so as to accurately measure the strength of the wafer 200 to be tested. In this embodiment, the force controller 3 can measure the intensity value of the wafer 200 to be tested by successively increasing the impact force of 50 grams (g). As shown in FIG. 10, the force controller 3 controls the impactor 2 to impact the wafer 200 to be tested with an impact force of 600 grams (g) for the first time, and then gradually increases the impact force of 50 grams (g) until The force controller 3 controls the striker 2 to strike the wafer 200 to be tested with an impact force of 700 grams (g) and break the wafer 200 to be tested, and at the same time, the wafer to be tested is also measured 200 intensity. However, the present invention is not limited to this. The force controller 3 can adjust the impact force each time according to the requirements of the operator, and is not limited to adjusting the impact force of 50 grams (g) each time.
如圖8所示,所述力道控制器3具有一拉力彈簧31、一力道刻度標示計32、以及一掛勾33。其中,所述拉力彈簧31的一端與所述撞擊桿22連接,所述拉力彈簧31的另一端與所述掛勾33相連接,所述力道刻度標示計32設置於所述掛勾33上。於本實施例中,操作人員可藉由所述掛勾33拉長所述拉力彈簧31使其長度對應所述力道刻度標示計32上的特定刻度以控制所述拉力彈簧31釋放時的力量,但本發明並不限於此。舉例來說,在本發明未繪示的其他實施例中,所述力道控制器3也可以是可控制撞擊力道的一齒輪電控裝 置,且所述齒輪電控裝置還進一步包含一防止二次碰撞裝置,其可避免所述撞擊器2在撞擊時的二次碰撞影響測試結果。 As shown in FIG. 8, the force controller 3 has a tension spring 31, a force scale indicator 32, and a hook 33. Wherein, one end of the tension spring 31 is connected to the impact rod 22, the other end of the tension spring 31 is connected to the hook 33, and the force scale indicator 32 is disposed on the hook 33. In this embodiment, the operator can use the hook 33 to extend the tension spring 31 so that its length corresponds to a specific scale on the force scale indicator 32 to control the force of the tension spring 31 when it is released. However, the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the force controller 3 may also be a gear electronic control device that can control the impact force. The gear electronic control device further includes a secondary collision preventing device, which can prevent the secondary collision of the striker 2 from affecting the test result.
如圖4及圖5所示,所述晶向感測器4於本實施例中是一紅外線感測器且其數量為3個,但本發明並不以此為限。舉例來說,在本發明未繪示的其他實施例中,所述晶向感測器4的數量也可以是3個以上。所述晶向感測器4設置於(或埋置於)所述晶圓載台11的所述側壁113並對應於撞擊口111。進一步地說,所述晶向感測器4與所述撞擊口111分別位於所述承載座1的所述晶圓載台11的所述側壁113。其中,當所述待測晶圓200平躺地設置於所述承載座1時,所述晶向感測器4能沿所述預定平面13測得所述待測晶圓200的所述第一晶向201、所述第二晶向202、以及所述第三晶向203。 As shown in FIGS. 4 and 5, the crystal orientation sensor 4 is an infrared sensor in this embodiment and the number is three, but the invention is not limited to this. For example, in other embodiments not shown in the present invention, the number of the crystal orientation sensors 4 may also be three or more. The crystal orientation sensor 4 is disposed on (or buried in) the side wall 113 of the wafer stage 11 and corresponds to the impact opening 111. Furthermore, the crystal orientation sensor 4 and the impact opening 111 are respectively located on the side wall 113 of the wafer stage 11 of the carrier 1. Wherein, when the wafer 200 to be tested is laid flat on the carrier 1, the crystal orientation sensor 4 can measure the first part of the wafer 200 to be tested along the predetermined plane 13. One crystal orientation 201, the second crystal orientation 202, and the third crystal orientation 203.
如圖7及圖12所示,所述支撐架5具有兩個鎖固件51、被兩個所述鎖固件51鎖合的一支撐臂52、以及設置於所述支撐臂52上的一頂抵桿53。其中,所述頂抵桿53能用來頂抵與定位任一個所述半晶圓204、205的一碎裂邊緣(為方便說明,所述頂抵桿53於圖12中定位所述半晶圓204的所述碎裂邊緣)。需要說明的是,於本實施例中,所述頂抵桿53是頂抵與定位所述半晶圓204,並且所述支撐架5透過任一個鎖固件51鎖合固定於所述晶圓載台11的所述安裝塊115上,另一個所述鎖固件51與所述頂抵桿53鎖合固定於所述支撐臂52相對遠離所述安裝塊115的一端,但本發明並不限於此。舉例來說,在本發明未繪示的其他實施例中,所述另一個所述鎖固件51與所述頂抵桿53也可以依所述半晶圓204的大小而在所述支撐臂52上移動而後固定。 As shown in FIGS. 7 and 12, the supporting frame 5 has two locking members 51, a supporting arm 52 locked by the two locking members 51, and a supporting arm 52 arranged on the supporting arm 52. Rod 53. Wherein, the abutment rod 53 can be used to abut and position a broken edge of any one of the half wafers 204, 205 (for the convenience of description, the abutment rod 53 is used to position the semi-crystal in FIG. The fragmented edge of circle 204). It should be noted that, in this embodiment, the abutting rod 53 abuts and positions the half-wafer 204, and the support frame 5 is locked and fixed to the wafer stage through any fastener 51 On the mounting block 115 of 11, another locking member 51 and the abutting rod 53 are locked and fixed to an end of the support arm 52 relatively far away from the mounting block 115, but the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the other locking member 51 and the abutting rod 53 can also be mounted on the supporting arm 52 according to the size of the half wafer 204 Move up and then fix.
[第二實施例] [Second Embodiment]
參閱圖11至圖13B所示,其為本發明的第二實施例,需先說明的是,本實施例類似於上述第一實施例,所以兩個實施例的相同處則不再加以贅述;再者,本實施例對應附圖所提及的相關數量與外型,僅用來具體地 說明本發明的實施方式,以便於了解本發明的內容,而非用來侷限本發明的保護範圍。 Refer to FIGS. 11 to 13B, which are the second embodiment of the present invention. It should be noted that this embodiment is similar to the above-mentioned first embodiment, so the similarities between the two embodiments will not be repeated; Furthermore, the relevant quantities and appearances mentioned in the corresponding drawings in this embodiment are only used to specifically The embodiments of the present invention are described to facilitate understanding of the content of the present invention, rather than to limit the protection scope of the present invention.
本實施例公開一種晶圓強度測試方法,其至少可對同一片所述待測晶圓200進行三次晶圓強度測試。如圖11所示,所述晶圓強度測試方法依序包括下列幾個步驟:一第一準備步驟S1、一第一撞擊步驟S2、一第二準備步驟S3、一第二撞擊步驟S4、一第三準備步驟S5、一第三撞擊步驟S6。其中,第一次晶圓強度測試進行所述第一準備步驟S1以及所述第一撞擊步驟S2,第二次晶圓強度測試進行所述第二準備步驟S3以及所述第二撞擊步驟S4,第三次晶圓強度測試進行所述第三準備步驟S5以及所述第三撞擊步驟S6。 This embodiment discloses a wafer strength test method, which can perform at least three wafer strength tests on the same wafer 200 to be tested. As shown in FIG. 11, the wafer strength test method includes the following steps in sequence: a first preparation step S1, a first impact step S2, a second preparation step S3, a second impact step S4, a The third preparation step S5, a third impact step S6. Wherein, the first wafer strength test performs the first preparation step S1 and the first impact step S2, and the second wafer strength test performs the second preparation step S3 and the second impact step S4, For the third wafer strength test, the third preparation step S5 and the third impact step S6 are performed.
需要說明的是,所述晶圓強度測試方法於本實施例中是通過上述第一實施例中的所述晶圓橫向撞擊測試裝置100來實施,所以在本實施例中有關於所述晶圓橫向撞擊測試裝置100的描述還請一併參考第一實施例及其圖2至圖10,但本發明的晶圓強度測試方法並不侷限以所述晶圓橫向撞擊測試裝置100來實現。 It should be noted that the wafer strength test method in this embodiment is implemented by the wafer lateral impact test device 100 in the first embodiment above, so in this embodiment, it is related to the wafer Please also refer to the first embodiment and FIGS. 2 to 10 for the description of the lateral impact test device 100, but the wafer strength test method of the present invention is not limited to be implemented by the wafer lateral impact test device 100.
所述第一準備步驟S1:將所述待測晶圓200平躺地設置於所述承載座1(的所述晶圓載台11)上,並使所述待測晶圓200的所述預擊邊緣區對應於所述承載座1的所述撞擊口111以供所述撞擊器2撞擊。其中,所述待測晶圓200具有所述第一晶向201、及各與所述第一晶向201相夾形成有不大於90度的所述第二晶向202與所述第三晶向203,但本發明並不限於此,舉例來說,如圖5B所示,所述待測晶圓200也可以僅包含所述第一晶向201、及與所述第一晶向201相夾形成非平行的所述第二晶向202。 The first preparation step S1: lay the wafer 200 to be tested on the carrier 1 (the wafer stage 11), and make the wafer 200 to be tested The striking edge area corresponds to the striking opening 111 of the bearing seat 1 for the striker 2 to strike. Wherein, the wafer 200 to be tested has the first crystal orientation 201, and each of the second crystal orientations 202 and the third crystal orientation 201 that are sandwiched by the first crystal orientation 201 is not greater than 90 degrees. Direction 203, but the present invention is not limited to this. For example, as shown in FIG. 5B, the wafer 200 to be tested may also only include the first crystal direction 201 and the same as the first crystal direction 201. The clamp forms the second crystal orientation 202 that is non-parallel.
所述第一撞擊步驟S2:以所述撞擊器2沿著垂直所述待測晶圓200的一晶圓面法向量的所述預定平面13穿過所述撞擊口111、並沿所述第一晶向201撞擊在所述待測晶圓200的所述預擊邊緣區,並且所述第一晶向201 位於所述預擊邊緣區,以使所述待測晶圓200沿所述第一晶向201而碎裂成兩個半晶圓204、205。其中,所述撞擊器2的撞擊方向與所述第一晶向201呈平行。其中,所述待測晶圓200所碎裂形成的兩個所述半晶圓204、205呈彼此鏡像對稱設置。每個所述半晶圓204、205包含有平行所述第一晶向201的一碎裂邊緣,並且兩個所述半晶圓204、205分別定義為一第一半晶圓204與一第二半晶圓205。 The first impact step S2: use the impactor 2 to pass through the impact opening 111 along the predetermined plane 13 perpendicular to the normal vector of a wafer surface of the wafer 200 to be tested, and along the first A crystal orientation 201 hits the pre-strike edge area of the wafer 200 to be tested, and the first crystal orientation 201 Located in the pre-strike edge area, so that the wafer 200 to be tested is broken into two half wafers 204 and 205 along the first crystal direction 201. Wherein, the impact direction of the striker 2 is parallel to the first crystal orientation 201. The two half wafers 204 and 205 formed by the fragmentation of the wafer 200 to be tested are arranged in mirror symmetry with each other. Each of the half wafers 204, 205 includes a chipping edge parallel to the first crystal orientation 201, and the two half wafers 204, 205 are defined as a first half wafer 204 and a second half wafer 204, respectively. Two-half wafer 205.
如圖12及圖13A所示,所述第二準備步驟S3:將所述第一半晶圓204平躺地設置於所述承載座1(的所述晶圓載台11)上,並以安裝於所述承載座1的所述支撐架5頂抵與定位所述第一半晶圓204的所述碎裂邊緣,以使所述第一半晶圓204的一預擊邊緣區對應於所述承載座1的所述撞擊口111。其中,部分所述預擊邊緣區抵頂於所述晶圓載台11的所述側壁113。 As shown in FIGS. 12 and 13A, the second preparation step S3: lay the first half-wafer 204 on the carrier 1 (the wafer carrier 11), and install it The support frame 5 of the carrier 1 presses against and positions the cracked edge of the first half-wafer 204, so that a pre-strike edge area of the first half-wafer 204 corresponds to the cracked edge of the first half-wafer 204. The impact opening 111 of the bearing seat 1. Wherein, part of the pre-strike edge area abuts against the side wall 113 of the wafer carrier 11.
所述第二撞擊步驟S4:以所述撞擊器2沿著所述預定平面13穿過所述撞擊口111、並沿所述第二晶向202撞擊在所述第一半晶圓204的所述預擊邊緣區,並且所述第二晶向202位於所述預擊邊緣區,以使所述第一半晶圓204沿所述第二晶向202而碎裂。其中,所述撞擊器2的撞擊路徑與所述第二晶向202呈一直線,且所述撞擊器2於所述第二撞擊步驟S4中的撞擊力道與所述撞擊器2於所述第一撞擊步驟S2中的撞擊力道不同。 The second impact step S4: use the impactor 2 to pass through the impact opening 111 along the predetermined plane 13 and impact on all the first half wafer 204 along the second crystal direction 202 The pre-strike edge region, and the second crystal orientation 202 is located in the pre-strike edge region, so that the first half-wafer 204 is broken along the second crystal direction 202. Wherein, the impact path of the impactor 2 is in a straight line with the second crystal orientation 202, and the impact force of the impactor 2 in the second impact step S4 and the impact force of the impactor 2 in the first The impact force in the impact step S2 is different.
如圖12及圖13B所示,所述第三準備步驟S5:將所述第二半晶圓205平躺地設置於所述承載座1(所述晶圓載台11)上,並以所述支撐架5抵頂與定位所述第二半晶圓205的所述碎裂邊緣,以使所述第二半晶圓205的一預擊邊緣區對應於所述承載座1的所述撞擊口111。其中,部分所述預擊邊緣區抵頂於所述晶圓載台11的所述側壁113。 As shown in FIG. 12 and FIG. 13B, the third preparation step S5: lay the second half wafer 205 flat on the carrier 1 (the wafer carrier 11), and use the The support frame 5 presses against and positions the cracked edge of the second half-wafer 205 so that a pre-strike edge area of the second half-wafer 205 corresponds to the impact opening of the carrier 1 111. Wherein, part of the pre-strike edge area abuts against the side wall 113 of the wafer carrier 11.
所述第三撞擊步驟S6:以所述撞擊器2沿著所述預定平面13穿過所述撞擊口111、並沿所述第三晶向203撞擊在所述第二半晶圓205的所述 預擊邊緣區,並且所述第三晶向203位於所述預擊邊緣區,以使所述第二半晶圓205沿所述第三晶向203而碎裂。其中,所述撞擊器2的所述撞擊路徑與所述第三晶向203呈一直線,且所述撞擊器2於所述第三撞擊步驟S6中的撞擊力道與所述撞擊器2於所述第一撞擊步驟S2與所述第二撞擊步驟S4中的撞擊力道不同。 The third impact step S6: use the impactor 2 to pass through the impact opening 111 along the predetermined plane 13 and impact on the second half-wafer 205 along the third crystal orientation 203 Narrate Pre-strike the edge region, and the third crystal orientation 203 is located in the pre-strike edge region, so that the second half-wafer 205 is broken along the third crystal orientation 203. Wherein, the impact path of the impactor 2 is in a straight line with the third crystal orientation 203, and the impact force of the impactor 2 in the third impact step S6 is the same as that of the impactor 2 in the The impact force in the first impact step S2 is different from the impact force in the second impact step S4.
[實施例的有益效果] [Beneficial effects of the embodiment]
本發明的其中一有益效果在於,所述晶圓橫向撞擊測試裝置及晶圓強度測試方法能將以撞擊器沿著所述待測晶圓所處的所述預定平面而撞擊在所述預擊邊緣區,據以測試所述待測晶圓沿所述晶向而碎裂所需的測試強度。 One of the beneficial effects of the present invention is that the wafer lateral impact test device and the wafer strength test method can impact the pre-strike along the predetermined plane where the wafer to be tested is located. The edge area is used to test the test strength required for the wafer to be tested to break along the crystal direction.
再者,本發明所提供的晶圓橫向撞擊測試裝置及晶圓強度測試方法,其能通過“具有位在所述預定平面上的所述撞擊口的所述承載座與對應於所述撞擊口設置的所述撞擊器”、“所述第一準備步驟中將所述待測晶圓平躺地設置於所述承載座上,並使所述待測晶圓的所述預擊邊緣區對應於所述承載座的所述撞擊口”、以及“所述第一撞擊步驟中以所述撞擊器沿著垂直所述待測晶圓的一晶圓面法向量的所述預定平面穿過所述撞擊口、並撞擊在所述待測晶圓的所述預擊邊緣區,以使所述待測晶圓沿所述第一晶向而碎裂成兩個半晶圓”的技術方案,以提升所述晶圓橫向撞擊測試裝置的測試次數,並大量節省所述晶圓強度測試方法所需花費的時間與費用。 Furthermore, the wafer lateral impact test device and wafer strength test method provided by the present invention can pass "the bearing seat with the impact port located on the predetermined plane and corresponding to the impact port" The impactor provided", "in the first preparation step, the wafer to be tested is laid flat on the carrier, and the pre-strike edge area of the wafer to be tested corresponds to In the impact opening of the carrier," and "in the first impact step, the impactor passes through the predetermined plane perpendicular to the normal vector of a wafer surface of the wafer to be tested. The impingement port and hitting the pre-strike edge area of the wafer to be tested, so that the wafer to be tested is broken into two half-wafers along the first crystal orientation", In order to increase the test times of the wafer lateral impact test device, the time and cost of the wafer strength test method are greatly saved.
以上所公開的內容僅為本發明的優選可行實施例,並非因此侷限本發明的申請專利範圍,所以凡是運用本發明說明書及圖式內容所做的等效技術變化,均包含於本發明的申請專利範圍內。 The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the description and schematic content of the present invention are included in the application of the present invention. Within the scope of the patent.
100:晶圓橫向撞擊測試裝置 100: Wafer lateral impact test device
1:承載座 1: bearing seat
11:晶圓載台 11: Wafer stage
111:撞擊口 111: impact port
113:側壁 113: Sidewall
115:安裝塊 115: installation block
12:撞擊器載台 12: Impactor carrier
13:預定平面 13: Scheduled plane
2:撞擊器 2: Impactor
22:撞擊桿 22: Impact bar
3:力道控制器 3: Force controller
32:力道刻度標示計 32: Force scale indicator
33:掛勾 33: hook
4:晶向感測器 4: Crystal orientation sensor
5:支撐架 5: Support frame
51:鎖固件 51: lock firmware
52:支撐臂 52: Support arm
53:頂抵桿 53: top bar

Claims (10)

  1. 一種晶圓橫向撞擊測試裝置,其包括:一承載座,具有位在一預定平面上的一撞擊口;其中,所述承載座用以供一待測晶圓平躺設置而落在所述預定平面上,並且所述待測晶圓定義有穿過其中心的一晶向;以及一撞擊器,其對應於所述撞擊口設置,並且所述撞擊器能沿著所述預定平面運作;其中,所述撞擊器的撞擊方向與所述晶向呈平行;其中,當所述待測晶圓平躺地設置於所述承載座時,所述撞擊器能沿所述預定平面穿過所述撞擊口、並沿所述晶向撞擊在所述待測晶圓的一預擊邊緣區,以使所述待測晶圓沿所述晶向而碎裂成兩個半晶圓;其中,所述預擊邊緣區為位於所述撞擊口的所述待測晶圓的邊緣部分。 A wafer lateral impact test device, comprising: a bearing seat with an impact opening located on a predetermined plane; wherein, the bearing seat is used for a wafer to be tested lying down on the predetermined plane. On a plane, and the wafer to be tested is defined with a crystal orientation passing through its center; and a striker, which is arranged corresponding to the striker, and the striker can operate along the predetermined plane; wherein , The impact direction of the striker is parallel to the crystal orientation; wherein, when the wafer to be tested is laid flat on the carrier, the striker can pass through the predetermined plane The impingement port and hit a pre-strike edge area of the wafer to be tested along the crystal direction, so that the wafer to be tested is broken into two half wafers along the crystal direction; The pre-strike edge area is an edge portion of the wafer to be tested located at the impact port.
  2. 如請求項1所述的晶圓橫向撞擊測試裝置,其中,所述晶圓橫向撞擊測試裝置進一步包括有可活動地安裝於所述承載座的一支撐架,並且所述支撐架能用來頂抵與定位任一個所述半晶圓的一碎裂邊緣。 The wafer lateral impact test device according to claim 1, wherein the wafer lateral impact test device further includes a support frame movably installed on the carrier, and the support frame can be used to top A chipped edge of any one of the half wafers is pressed and positioned.
  3. 如請求項1所述的晶圓橫向撞擊測試裝置,其中,所述晶圓橫向撞擊測試裝置進一步包括有安裝於所述承載座的一晶向感測器,並且所述晶向感測器與所述撞擊口分別位於所述承載座的側壁;其中,當所述待測晶圓平躺地設置於所述承載座時,所述晶向感測器能沿所述預定平面測得所述待測晶圓的所述晶向。 The wafer lateral impact test device according to claim 1, wherein the wafer lateral impact test device further includes a crystal orientation sensor installed on the carrier, and the crystal orientation sensor is connected to The impact openings are respectively located on the sidewalls of the supporting base; wherein, when the wafer to be tested is laid flat on the supporting base, the crystal orientation sensor can measure the The crystal orientation of the wafer to be tested.
  4. 如請求項1所述的晶圓橫向撞擊測試裝置,其中,所述撞擊 器包含有面向所述撞擊口的一撞擊頭,並且所述撞擊頭的外表面呈球面狀,以使所述撞擊頭能用來保持以點接觸的方式撞擊在所述預擊邊緣區。 The wafer lateral impact test device according to claim 1, wherein the impact The device includes an impact head facing the impact port, and the outer surface of the impact head is spherical, so that the impact head can be used to keep hitting the pre-strike edge area in a point contact manner.
  5. 如請求項4所述的晶圓橫向撞擊測試裝置,其中,所述撞擊頭的半徑大於所述待測晶圓的厚度。 The wafer lateral impact test device according to claim 4, wherein the radius of the impact head is greater than the thickness of the wafer to be tested.
  6. 如請求項4所述的晶圓橫向撞擊測試裝置,其中,所述承載座包含有形成有所述撞擊口的一晶圓載台及連接所述晶圓載台的一撞擊器載台,並且所述撞擊器固定於所述撞擊器載台,而所述撞擊頭呈懸空狀。 The wafer lateral impact test device according to claim 4, wherein the carrier includes a wafer stage on which the impact port is formed and an impactor stage connected to the wafer stage, and the The striker is fixed on the striker carrier, and the striker is suspended.
  7. 如請求項1所述的晶圓橫向撞擊測試裝置,其中,所述晶圓橫向撞擊測試裝置進一步包括有連接於所述撞擊器的一力道控制器,並且所述力道控制器能用來控制所述撞擊器運作時所釋放的力量。 The wafer lateral impact test device according to claim 1, wherein the wafer lateral impact test device further includes a force controller connected to the striker, and the force controller can be used to control all State the force released by the impactor during operation.
  8. 一種晶圓強度測試方法,其包括:一第一準備步驟:將一待測晶圓平躺地設置於一承載座上,並使所述待測晶圓的一預擊邊緣區對應於所述承載座的一撞擊口;其中,所述待測晶圓包含一第一晶向、及與所述第一晶向相夾形成非平行的一第二晶向;以及一第一撞擊步驟:以一撞擊器沿著垂直所述待測晶圓的一晶圓面法向量的一預定平面穿過所述撞擊口、並沿所述第一晶向撞擊在所述待測晶圓的所述預擊邊緣區,以使所述待測晶圓沿所述第一晶向而碎裂成兩個半晶圓;其中,所述撞擊器的撞擊方向與所述第一晶向呈平行; 其中,每個所述半晶圓包含有平行所述第一晶向的一碎裂邊緣,並且兩個所述半晶圓分別定義為一第一半晶圓與一第二半晶圓;其中,所述預擊邊緣區為位於所述撞擊口的所述待測晶圓的邊緣部分。 A method for testing the strength of a wafer, comprising: a first preparation step: lay a wafer to be tested on a carrier, and make a pre-strike edge area of the wafer to be tested correspond to the An impact port of the carrier; wherein the wafer to be tested includes a first crystal orientation and a second crystal orientation that is non-parallel to the first crystal orientation; and a first impact step: An impactor passes through the impact opening along a predetermined plane perpendicular to the normal vector of a wafer surface of the wafer to be tested, and strikes the pre-test of the wafer to be tested along the first crystal direction. Hitting the edge area, so that the wafer to be tested is broken into two half-wafers along the first crystal orientation; wherein the impact direction of the striker is parallel to the first crystal orientation; Wherein, each of the half-wafers includes a chipping edge parallel to the first crystal orientation, and the two half-wafers are defined as a first half-wafer and a second half-wafer respectively; wherein The pre-strike edge area is an edge portion of the wafer to be tested located at the impact port.
  9. 如請求項8所述的晶圓強度測試方法,其中,所述晶圓強度測試方法進一步包括:一第二準備步驟:將所述第一半晶圓平躺地設置於所述承載座上,並以安裝於所述承載座的一支撐架頂抵與定位所述第一半晶圓的所述碎裂邊緣,以使所述第一半晶圓的一預擊邊緣區對應於所述承載座的所述撞擊口;其中,所述第二晶向位於所述預擊邊緣區;及一第二撞擊步驟:以所述撞擊器沿著所述預定平面穿過所述撞擊口、並沿所述第二晶向撞擊在所述第一半晶圓的所述預擊邊緣區,以使所述第一半晶圓沿所述第二晶向而碎裂。 The wafer strength testing method according to claim 8, wherein the wafer strength testing method further comprises: a second preparation step: laying the first half wafer flat on the carrier, And a support frame installed on the carrier is used to abut and position the chipping edge of the first half-wafer so that a pre-strike edge area of the first half-wafer corresponds to the carrier The impact opening of the seat; wherein the second crystal orientation is located in the pre-strike edge region; and a second impact step: use the impactor to pass through the impact opening along the predetermined plane and along the The second crystal direction impinges on the pre-strike edge area of the first half-wafer, so that the first half-wafer is broken along the second crystal direction.
  10. 如請求項9所述的晶圓強度測試方法,其中,所述待測晶圓進一步包含一第三晶向,而且所述第三晶向分別與所述第一晶向以及所述第二晶向相夾不大於90度,所述晶圓強度測試方法進一步包括:一第三準備步驟:將所述第二半晶圓平躺地設置於所述承載座上,並以所述支撐架頂抵與定位所述第二半晶圓的所述碎裂邊緣,以使所述第二半晶圓的一預擊邊緣區對應於所述承載座的所述撞擊口;及一第三撞擊步驟:以所述撞擊器沿著所述預定平面穿過所述撞擊口、並沿所述第三晶向撞擊在所述第二半晶圓的所述 預擊邊緣區,以使所述第二半晶圓沿所述第三晶向而碎裂。 The wafer strength testing method according to claim 9, wherein the wafer to be tested further includes a third crystal orientation, and the third crystal orientation is respectively related to the first crystal orientation and the second crystal orientation. The wafer strength test method further includes: a third preparation step: lay the second half-wafer on the carrier and place it on top of the support frame. Abutting and positioning the chipping edge of the second half-wafer so that a pre-strike edge area of the second half-wafer corresponds to the impact opening of the carrier; and a third impact step : Use the striker to pass through the striker along the predetermined plane and strike the second half-wafer along the third crystal direction Pre-strike the edge area to make the second half-wafer fragment along the third crystal direction.
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