TWI727627B - Buried circuit board and method for manufacturing the same - Google Patents

Abstract

A method for manufacturing a buried circuit board includes: providing a buried substrate and performing a first surface pretreatment on the buried substrate, and manufacturing a first copper layer to form a first conductive circuit layer; performing a first browning treatment; pressing a first copper-clad substrate ; the first copper-clad substrate including a first base material layer and a third copper foil layer; forming a first and a second copper-added layers by electroplating; a thickness of the first or the second copper-added layer is equal to an etching amount of the first surface pretreatment and the f first browning treatment; performing a second surface pre-treatment and forming the second copper- added layer and the second copper layer to a second conductive circuit layer; performing a second browning treatment; and laminating a second copper-clad substrate; wherein the second copper-clad substrate includes a second base material layer and a fourth copper layer, a thicknesses of the first conductive circuit layer is equal to the second conductive circuit layers, a sum of a thickness of the second copper-cladded layer after the second browning treatment and a thickness of the third copper foil layer is equal to a thickness of the fourth copper foil layer. The manufacturing method can improve the board warping phenomenon and can improve the first-time success rate of the first piece.

Description

Embedded capacitance circuit board and manufacturing method thereof

The invention relates to a multilayer printed circuit board technology, in particular to a buried capacitance circuit board and a manufacturing method thereof.

With the development of electronic products in the direction of light, thin, short and small, more and more functions need to be realized. The usable area of PCB boards is getting smaller and smaller, but there are more and more corresponding electronic components on the PCB, thus giving birth to PCB products with embedded components.

To embed capacitors in PCB products, it is necessary to use embedded capacitance substrate materials. The embedded capacitance substrates used as capacitors are mostly high-permittivity, ultra-thin ceramic materials. The embedded capacitance substrates adopt the traditional double-sided etching method Due to the ultra-thin and fragile characteristics of the embedded capacitance material when making the inner circuit, the double-sided copper-free part is particularly easy to shatter, resulting in product scrap.

At present, the mainstream production method is to etch the embedded capacitor on one side, and laminate the prepreg and copper foil on the road surface for a single lamination. Then, the other side of the embedded capacitor is laminated with the prepreg and copper foil for the second laminate. Due to the de-synthesis, pre-processing and synthesis of the circuit will bite the copper foil layer, and the second copper foil layer of the core board of the embedded capacitor substrate undergoes one more de-browning and de-browning than the first copper foil layer opposite to it. Pre-processing and browning of the circuit will result in uneven thickness of the conductive circuit layer on both sides of the core board, which will cause the board warping of such products to be difficult to control, resulting in a high scrap rate and leading to the first time success The rate is low.

In view of this, the present invention provides a method for manufacturing a buried capacitance circuit board that can improve the warpage phenomenon of the board and can increase the first-time success rate of the first product.

It is also necessary to provide a buried capacitance circuit board manufactured by the method for manufacturing a buried capacitance circuit board as described above.

A method for manufacturing a buried capacitance circuit board includes providing a buried capacitance substrate, the buried capacitance substrate including a capacitor core layer and a first copper foil layer and a second copper foil formed on opposite surfaces of the capacitor core layer Layer; the first copper foil layer and the second copper foil layer are subjected to a first surface pretreatment and the first copper foil layer after the first surface pretreatment is made to form a first conductive circuit layer; A conductive circuit layer and the second copper foil layer after the first surface pretreatment are subjected to the first browning treatment; a first single-sided copper-clad substrate is laminated on the first conductive circuit layer; A single-sided copper-clad substrate includes a first substrate layer formed on the first conductive circuit layer and a third copper foil layer formed on the first substrate layer; A first copper-plated layer and a second copper-plated layer are respectively formed on the copper foil layer and the second copper foil layer; the thickness of the first copper-plated layer and the second copper-plated layer is equal to The biting amount of the first surface pretreatment and the first browning; the second surface pretreatment and the second surface pretreatment are performed on the first copper-plated layer and the second copper-plated layer After the second copper plating layer and the second copper foil layer are fabricated to form a second conductive circuit layer; the second conductive circuit layer and the first conductive circuit layer after the second surface pretreatment The copper-plated layer is subjected to a second browning treatment; and a second single-sided copper-clad substrate is laminated on the second conductive circuit layer, and the second single-sided copper-clad substrate includes a second conductive circuit layer formed on the The second substrate layer on the circuit layer and the fourth copper foil layer formed on the second substrate layer, wherein the thickness of the first conductive circuit layer is equal to the thickness of the second conductive circuit layer, so The sum of the thickness of the third copper foil layer and the first copper-plated layer after the second browning treatment is equal to the thickness of the fourth copper foil layer.

Further, after the step of pressing and bonding the first single-sided copper-clad substrate on the first conductive circuit layer, the method further includes the steps of: trimming the circuit substrate structure and making through holes.

Further, after the steps of trimming the circuit substrate structure and making through holes, it further includes the step of: debrowning the circuit substrate structure; wherein, the first copper plating layer and the The thickness of the second copper plating layer also includes the amount of bite during debrowning.

Further, before the step of performing the first surface pretreatment on the first copper foil layer and the second copper foil layer and making the first copper foil layer after the first surface pretreatment to form the first conductive circuit layer , It also includes the step of cutting the first copper foil layer and the second copper foil layer of the embedded capacitance substrate.

Further, the material of the capacitor core layer is ceramic.

Further, the thickness of the capacitor core layer is 2-12um.

Further, the materials of the first substrate layer and the second substrate layer are prepreg, polyimide, polyethylene terephthalate or polyethylene naphthalate, polyethylene, At least one of Teflon, liquid crystal polymer and polyvinyl chloride.

A buried capacitance circuit board is manufactured by the above-mentioned manufacturing method of the buried capacitance circuit board.

In the embedded capacitance circuit board and the manufacturing method thereof provided by the present invention, after pressing the first single-sided copper-clad substrate, a first coating is formed on the third copper foil layer and the second copper foil layer by electroplating. A copper-plated layer and a second copper-plated layer; the thickness of the first copper-plated layer and the second copper-plated layer is equal to the bite of the first surface pretreatment, the first browning and de-browning In the subsequent surface pretreatment and browning process, the thickness of the first conductive circuit layer is equal to the thickness of the second conductive circuit layer, and the third copper foil after the second browning treatment The thickness of the layer is equal to the thickness of the fourth copper foil layer, so that parameters such as the etching line body laser can be optimized, which is convenient for production and can increase productivity; it can also improve the process capability index and the warping phenomenon of each layer of copper thickness; the first conductive circuit The layer and the second conductive circuit layer are formed by a single-sided etching circuit, so as to ensure that the capacitor layer on the other side of the etching surface is attached with copper and will not be damaged.

In order to further explain the technical means and effects adopted by the present invention to achieve the intended purpose of the invention, the following describes the specific implementation, structure, and structure of the embedded capacitance circuit board and its manufacturing method provided by the present invention with reference to accompanying drawings 1-10 and preferred embodiments. The characteristics and effects are described in detail as follows. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to another element or a centrally arranged element may exist at the same time. When an element is considered to be "disposed on" another element, it can be directly disposed on another element or a centrally disposed element may also exist at the same time.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "and/or" as used herein includes any and all combinations of one or more related listed items.

1-10, the present invention provides a method for manufacturing a buried capacitance circuit board 100, which includes the steps:

In the first step, referring to FIG. 1, a buried capacitor substrate 10 is provided. The buried capacitor substrate 10 includes a capacitor core layer 11 and a first copper foil layer 12 formed on opposite surfaces of the capacitor core layer 11 and The second copper foil layer 13.

Wherein, the material of the capacitor core layer 11 is a high dielectric constant and ultra-thin material. In this embodiment, the material of the capacitor core layer 11 is a high dielectric constant, ultra-thin ceramic material.

Wherein, the thickness of the capacitor core layer 11 is 2.0-12.0um. The thickness of the first copper foil layer 12 and the second copper foil layer 13 are the same.

In this embodiment, the thickness of the capacitor core layer 11 is 2.0 um, and the thickness of the first copper foil layer 12 and the second copper foil layer 13 are both 25.0 um.

In the second step, referring to FIG. 2, the first copper foil layer 12 and the second copper foil layer 13 of the embedded capacitor substrate 10 are cut.

Wherein, the cutting may be cutting the shape of the embedded capacitance substrate 10, or may be reducing the thickness of the first copper foil layer 12 and the second copper foil layer 13.

In this embodiment, the thickness of the first copper foil layer 12 and the second copper foil layer 13 after shearing are both 20.0 um. In other words, the thickness loss of the first copper foil layer 12 and the second copper foil layer 13 after shearing are both 5 um.

In the third step, referring to FIG. 3, the first copper foil layer 12 and the second copper foil layer 13 after being cut are subjected to the first surface pretreatment and the first copper after the first surface pretreatment The foil layer 12 is fabricated to form the first conductive circuit layer 14.

Of course, in other embodiments, the cutting step may also be omitted. At this time, the objects for the first surface pretreatment are: the first copper foil layer 12 and the second copper foil layer 13.

Wherein, the surface pretreatment is to remove oxides on the surfaces of the first copper foil layer 12 and the second copper foil layer 13. The surface pretreatment generally includes at least one of tin spraying, organic solderability protective agent, full-board nickel-gold plating, immersion gold, immersion tin, immersion silver, electroless nickel-palladium-gold, and hard gold plating.

Wherein, the thickness of the first conductive circuit layer 14 and the second copper foil layer 13 after the first surface pretreatment has a certain loss. In this embodiment, the thickness loss of the first conductive circuit layer 14 and the second copper foil layer 13 after the first surface pretreatment is 0.5 um. In other words, the copper thickness of the first conductive circuit layer 14 and the second copper foil layer 13 after the first surface pretreatment is 19.5 um.

Wherein, the first copper foil layer 12 is fabricated by an image transfer process to form the first conductive circuit layer 14. Among them, the image transfer process includes lamination, exposure, development, etching, and film removal.

Among them, the spray pressure for developing and etching is less than or equal to 1.5kgf/cm2.

In the fourth step, referring to FIG. 4, a first browning treatment is performed on the first conductive circuit layer 14 and the second copper foil layer 13 after the first surface pretreatment.

Among them, the browning treatment is to remove grease, debris, etc. on the surface of the first conductive circuit layer 14 and the second copper foil layer 13 after the first surface pretreatment, so as to ensure that the first conductive circuit layer 14 and The cleanliness of the surface of the second copper foil layer 13 after the first surface pretreatment. After browning, there is a layer of uniform fluff on the surface of the first conductive circuit layer 14 and the second copper foil layer 13 after the first surface pretreatment, thereby increasing the base of the embedded capacitance substrate and the subsequent copper-clad substrate The bonding force between the material layers, so as to avoid problems such as delamination and bursting. In addition, it needs to be pressed within a certain period of time after browning to prevent the browning layer from absorbing water and causing board burst.

Among them, the spray pressure during the first browning is less than or equal to 1.5kgf/cm2.

Wherein, the thickness of the first conductive circuit layer 14 after the first browning treatment and the second copper foil layer 13 after the first surface pretreatment has a certain loss. In this embodiment, the thickness loss of the first conductive circuit layer 14 after the first browning treatment and the second copper foil layer 13 after the first surface pretreatment are both 1.4 um. That is to say, the copper thickness of the first conductive circuit layer 14 after the first browning treatment and the second copper foil layer 13 after the first surface pretreatment are both 18.1 um.

In the fifth step, referring to FIG. 5, a first single-sided copper-clad substrate 20 is pressed onto the first conductive circuit layer 14 to obtain a circuit substrate structure 110.

Wherein, the first single-sided copper-clad substrate 20 includes a first substrate layer 21 formed on the first conductive circuit layer 14 and a third copper foil formed on the first substrate layer 21 Layer 22.

In this embodiment, the material of the first substrate layer 21 is prepreg, polyimide, polyethylene terephthalate or polyethylene naphthalate, polyethylene, Teflon, At least one of the substrate materials commonly used in the industry such as liquid crystal polymer and polyvinyl chloride.

In this embodiment, the thickness of the first substrate layer 21 is 25.0 um, and the thickness of the third copper foil layer 22 is 18.0 um.

In the sixth step, referring to FIG. 6, the circuit substrate structure 110 is trimmed, through holes are made, and debrowning.

In other embodiments, the step of making the through hole can also be omitted.

Wherein, the copper thickness of the third copper foil layer 22 and the second copper foil layer 13 of the circuit substrate structure 110 after debrowning has a certain loss. In this embodiment, the thickness loss of the third copper foil layer 22 and the second copper foil layer 13 of the circuit substrate structure 110 after debrowning are both 1.0 um. In other words, the thickness of the third copper foil layer 22 after debrowning is 17.0 um, and the thickness of the second copper foil layer 13 after debrowning is 17.1 um.

In the seventh step, referring to FIG. 7, a first copper-plating layer 23 and a second copper-plating layer 23 are formed on the third copper foil layer 22 and the second copper foil layer 13 after debrowning, respectively. Copper-plated layer 24.

Wherein, the thickness of the first copper-plated layer 23 and the second copper-plated layer 24 is equal to the amount of biting of the first surface pretreatment, first browning and de-browning.

In this embodiment, the thickness of the first copper-plated layer 23 and the second copper-plated layer 24 are both 2.9 um. In other words, the sum of the thicknesses of the third copper foil layer 22 and the first copper-plated layer 23 is 19.9 um, and the thicknesses of the second copper foil layer 13 and the second copper-plated layer 24 The sum is 20.0 um.

In the eighth step, referring to FIG. 8, a second surface pretreatment is performed on the first copper-plated layer 23 and the second copper-plated layer 24, and the second surface pretreatment after the second surface pretreatment is performed The copper layer 24 and the second copper foil layer 13 are added to form a second conductive circuit layer 15.

Wherein, the first copper-plated layer 23 and the second copper-plated layer 24 after the second surface pretreatment have a certain copper thickness loss. In this embodiment, the copper thickness loss of the first copper-plated layer 23 and the second copper-plated layer 24 after the second surface pretreatment is 0.5 um. In other words, the sum of the thicknesses of the first copper plating layer 23 and the third copper foil layer 22 after the second surface pretreatment is 19.4 um, and the thickness of the second surface pretreatment is 19.4 um. The thickness of the second conductive circuit layer 15 is 19.5 um.

Wherein, the second copper-plated layer 24 and the second copper foil layer 13 after the second surface pretreatment are fabricated by an image transfer process to form a second conductive circuit layer 15. Among them, the image transfer process includes lamination, exposure, development, etching, and film removal.

Among them, the spray pressure for developing and etching is less than or equal to 1.5kgf/cm2.

In the ninth step, referring to FIG. 9, a second browning process is performed on the second conductive circuit layer 15 and the first copper-plated layer 23 after the second surface pretreatment.

Wherein, the thickness of the second conductive circuit layer 15 and the first copper plating layer 23 after the second browning treatment has a certain loss. In this embodiment, the thickness loss of the second conductive circuit layer 15 and the first copper plating layer 23 after the second browning treatment are both 1.4 um. That is to say, the thickness of the second conductive circuit layer 15 after the second browning treatment is 18.1um, and the first copper plating layer 23 and the third copper after the second browning treatment The total thickness of the foil layer 22 is 18.0um.

Among them, the spray pressure during the second browning is less than or equal to 1.5kgf/cm2.

In the tenth step, referring to FIG. 10, a second single-sided copper-clad substrate 40 is press-fitted on the second conductive circuit layer 15 to obtain the embedded capacitance circuit board 100.

Wherein, the second single-sided copper-clad substrate 40 includes a second substrate layer 41 formed on the second conductive circuit layer 15 and a fourth copper foil layer formed on the second substrate layer 41 42. Wherein, the thickness of the first conductive circuit layer 14 is equal to the thickness of the second conductive circuit layer 15, the third copper foil layer 22 and the first copper plating layer after the second browning The sum of the thickness of 23 is equal to the thickness of the fourth copper foil layer 42.

In this embodiment, the thickness of the first conductive circuit layer 14 and the second conductive circuit layer 15 are both 18.1 um, the thickness of the fourth copper foil layer 42 is 18.0 um, and the third copper foil The sum of the thickness of the layer 22 and the first copper-plated layer 23 after the second browning is 18.0 um.

The present invention also provides a buried capacitance circuit board 100 using the above-mentioned manufacturing method of the buried capacitance circuit board. The buried capacitance circuit board 100 includes a capacitor core layer 11 and a first conductive circuit layer formed on the capacitor core layer 11 14 and the second conductive circuit layer 15, a first base material layer 21 formed on the first conductive circuit layer 14, a first outer copper foil layer 25 formed on the first base material layer 21, formed on The second base material layer 41 on the second conductive circuit layer 15 and the second outer copper foil layer 43 formed on the second base material layer 41. The thickness of the first conductive circuit layer 14 is equal to the thickness of the second conductive circuit layer 15, and the first outer copper foil layer 25 is equal to the thickness of the second outer copper foil layer 43. Wherein, the first outer copper foil layer 25 is formed by stacking the third copper foil layer 22 and the first copper-plated layer 23 after surface pretreatment and browning, and the second outer copper foil layer 43 is The fourth copper foil layer 42.

In the embedded capacitance circuit board and the manufacturing method thereof provided by the present invention, after pressing the first single-sided copper-clad substrate, a first coating is formed on the third copper foil layer and the second copper foil layer by electroplating. A copper-plated layer and a second copper-plated layer; the thickness of the first copper-plated layer and the second copper-plated layer is equal to the bite of the first surface pretreatment, the first browning and de-browning In the subsequent surface pretreatment and browning process, the thickness of the first conductive circuit layer is equal to the thickness of the second conductive circuit layer, and the third copper foil after the second browning treatment The thickness of the layer is equal to the thickness of the fourth copper foil layer, so that parameters such as the etching line body laser can be optimized, which is convenient for production and can increase productivity; it can also improve the process capability index and the warping phenomenon of each layer of copper thickness; the first conductive circuit The layer and the second conductive circuit layer are formed by a single-sided etching circuit, so as to ensure that the capacitor layer on the other side of the etching surface is attached with copper and will not be damaged.

The above are only the preferred embodiments of the present invention and do not limit the present invention in any form. Although the present invention has been disclosed as the preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with the profession Without departing from the scope of the technical solution of the present invention, when the technical content disclosed above can be used to make some changes or modification into equivalent implementations of equivalent changes, but all that does not deviate from the technical solution of the present invention, according to the technical essence of the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solutions of the present invention.

100: Buried capacitance circuit board 10: Embedded capacitance substrate 11: Capacitor core layer 12: The first copper foil layer 13: The second copper foil layer 14: The first conductive circuit layer 20: The first single-sided copper clad substrate 21: The first substrate layer 22: The third copper foil layer 23: The first copper plating layer 24: The second copper plating layer 15: The second conductive circuit layer 40: The second single-sided copper clad substrate 41: The second substrate layer 42: The fourth copper foil layer 25: The first outer copper foil layer 43: The second outer copper foil layer 110: Circuit board structure

FIG. 1 is a cross-sectional view of an embedded capacitor substrate provided by a preferred embodiment of the present invention.

Fig. 2 is a cross-sectional view of the embedded capacitor substrate shown in Fig. 1 after debrowning treatment.

Figure 3 is the first copper foil layer and the second copper foil layer after the debrowning shown in Figure 2 are subjected to the first surface pretreatment and the first copper foil layer after the first surface pretreatment is produced A cross-sectional view after forming the first conductive circuit layer.

4 is a cross-sectional view of the second copper foil layer and the first conductive circuit layer after the debrowning shown in FIG. 3 are browned for the first time.

5 is a cross-sectional view of a first single-sided copper-clad substrate after pressing and bonding a first single-sided copper-clad substrate on the first conductive circuit layer described in FIG. 4.

6 is a cross-sectional view of the first single-sided copper-clad substrate shown in FIG. 5 after trimming and debrowning.

7 is a cross-sectional view of a first copper-plated layer and a second copper-plated layer formed on the debrowning copper foil layer shown in FIG. 6 respectively.

FIG. 8 is a second surface pre-treatment of the first copper-plated layer and the second copper-plated layer shown in FIG. 7 and the second surface pre-treatment after the second surface pre-treatment A cross-sectional view of the copper layer and the second copper foil layer after the second conductive circuit layer is formed.

9 is a cross-sectional view of the second conductive circuit layer shown in FIG. 8 and the first copper-plated layer after the second surface pretreatment after the second browning.

10 is a cross-sectional view of a second single-sided copper-clad substrate after pressing a second single-sided copper-clad substrate on the second conductive circuit layer after the second browning shown in FIG. 9.

100: Buried capacitance circuit board

11: Capacitor core layer

14: The first conductive circuit layer

21: The first substrate layer

22: The third copper foil layer

23: The first copper plating layer

15: The second conductive circuit layer

40: The second single-sided copper clad substrate

41: The second substrate layer

42: The fourth copper foil layer

25: The first outer copper foil layer

43: The second outer copper foil layer

Claims (8)

A method for manufacturing a buried capacitance circuit board, which includes providing a buried capacitance substrate, the buried capacitance substrate including a capacitor core layer and a first copper foil layer and a second copper foil layer formed on opposite surfaces of the capacitor core layer Copper foil layer Performing a first surface pretreatment on the first copper foil layer and the second copper foil layer, and fabricating the first copper foil layer after the first surface pretreatment to form a first conductive circuit layer; Performing the first browning treatment on the first conductive circuit layer and the second copper foil layer after the first surface pretreatment; A first single-sided copper-clad substrate is press-fitted on the first conductive circuit layer; the first single-sided copper-clad substrate includes a first base material layer formed on the first conductive circuit layer and A third copper foil layer on the first substrate layer; A first copper plating layer and a second copper plating layer are respectively formed on the third copper foil layer and the second copper foil layer after the first browning treatment by electroplating; The thickness of the copper-plated layer and the second copper-plated layer is equal to the amount of biting during the first surface pretreatment and the first browning; Perform a second surface pretreatment on the first copper-plated layer and the second copper-plated layer, and the second copper-plated layer and the second copper foil after the second surface pre-treatment Layer production to form a second conductive circuit layer; Performing a second browning treatment on the second conductive circuit layer and the first copper-plated layer after the second surface pretreatment; and A second single-sided copper-clad substrate is laminated on the second conductive circuit layer to obtain a circuit substrate structure. The second single-sided copper-clad substrate includes a second single-sided copper-clad substrate formed on the second conductive circuit layer. Two substrate layers and a fourth copper foil layer formed on the second substrate layer, wherein the thickness of the first conductive circuit layer is equal to the thickness of the second conductive circuit layer, and the third copper foil The sum of the thickness of the layer and the first copper-plated layer after the second browning treatment is equal to the thickness of the fourth copper foil layer. The method for manufacturing a buried capacitance circuit board according to claim 1, wherein after the step of pressing and bonding the first single-sided copper-clad substrate on the first conductive circuit layer, the method further comprises: The circuit substrate structure is trimmed and a through hole is made. The manufacturing method of the embedded capacitance circuit board according to claim 2, which further includes the following steps: Debrowning is performed on the circuit substrate structure; wherein the thicknesses of the first copper-plated layer and the second copper-plated layer also include the amount of biting during the debrowning. The manufacturing method of the embedded capacitance circuit board according to claim 1, wherein the first surface pretreatment is performed on the first copper foil layer and the second copper foil layer, and the first surface pretreatment is performed after the first surface pretreatment. Before the step of fabricating a copper foil layer to form the first conductive circuit layer, the method further includes the following steps: Cutting the first copper foil layer and the second copper foil layer of the embedded capacitance substrate. The manufacturing method of the embedded capacitor circuit board according to claim 1, wherein the material of the capacitor core layer is ceramic. The manufacturing method of the embedded capacitor circuit board according to claim 1, wherein the thickness of the capacitor core layer is 2-12um. The manufacturing method of the embedded capacitance circuit board according to claim 1, wherein the materials of the first substrate layer and the second substrate layer are prepreg, polyimide, polyethylene terephthalate At least one of ester or polyethylene naphthalate, polyethylene, Teflon, liquid crystal polymer and polyvinyl chloride. A buried capacitance circuit board, wherein the buried capacitance circuit board is manufactured by the manufacturing method of the buried capacitance circuit board according to any one of claims 1-7.

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