TWI723054B - 半導體元件的製作方法與半導體元件 - Google Patents

半導體元件的製作方法與半導體元件 Download PDF

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TWI723054B
TWI723054B TW105133922A TW105133922A TWI723054B TW I723054 B TWI723054 B TW I723054B TW 105133922 A TW105133922 A TW 105133922A TW 105133922 A TW105133922 A TW 105133922A TW I723054 B TWI723054 B TW I723054B
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elongated semiconductor
semiconductor structures
elongated
group
portions
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TW105133922A
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TW201715580A (zh
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肯尼斯 奧克蘭 理查
布萊戴恩杜瑞茲
馬克范達爾
馬汀克里斯多福荷蘭
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台灣積體電路製造股份有限公司
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Abstract

一種半導體元件的製作方法包括在一半導體基板上磊晶生長複數個長條形半導體結構之第一部分，長條形半導體結構垂直於此基板延伸。方法進一步包括在基板上形成閘極層，閘極層與長條形半導體結構接觸。方法進一步包括在閘極層及長條形半導體結構上執行平坦化製程，及磊晶生長複數個長條形半導體結構之第二部分，第二部分包含與第一部分不同的材料。

Description

半導體元件的製作方法與半導體元件
本揭露是關於一種半導體元件的製作方法與半導體元件。
在半導體積體電路(integrated circuit；IC)工業中，IC材料及設計之技術進步已產生數代IC，其中每一代均具有與前一代相比較小且較複雜的電路。在IC進化過程中，功能密度(即每晶片面積之互連裝置數目)已大體上增加，同時幾何尺寸(即可使用製造製程產生的最小元件(或接線))已減小。此按比例減小製程通常藉由增加生產效率及降低相關聯之成本來提供益處。此按比例減小亦已增加IC處理及製造之複雜性。
積體電路中之一種類型之元件為奈米接線。奈米接線為可用作電晶體之部分的長條形的半導體結構。特定言之，奈米接線之部分可經摻雜以形成源極及汲極區域。另外，可形成閘極層以使得其在奈米接線之源極與汲極區域之間的通道區域上圍繞奈米接線。
奈米接線可以多種方式形成。通常，使用磊晶製程來生長奈米接線。大體上，使用單個磊晶製程同時生長多個奈米接線。但歸因於各種製程特徵，在磊晶製程完成之後，奈米接線中之每一者可能不具有相同的高度。為達成較佳裝置操作，理想的是此等奈米接線具有實質上類似的高度。
本揭露之一實施例提供了一種半導體元件的製作方法，方法包括在半導體基板上磊晶生長複數個長條形半導體結構之第一部分，長條形半導體結構垂直於基板延伸。方法進一步包括在基板上形成閘極層，閘極層設置在長條形半導體結構上。方法進一步包括在閘極層及長條形半導體結構上執行平坦化製程，並在平坦化製程後，移除部分的閘極層。方法更包含磊晶生長複數個長條形半導體結構之第二部分，第二部分包含與第一部分不同的材料，其中第一部分與第二部分之間的接面自閘極層的邊緣偏移。
本揭露之另一實施例提供了一種半導體元件的製作方法，在半導體基板上形成第一組長條形半導體結構，第一組長條形半導體結構垂直於半導體基板延伸。在半導體基板上形成虛設閘極層，虛設閘極層設置在第一組長條形半導體結構上。在虛設閘極層及第一組長條形半導體結構上執行平坦化製程，以及在第一組長條形半導體結構上且與其對準形成第二組長條形半導體結構，第二組長條形半導體結構包含與第一組長條形半導體結構不同的材料。
本揭露之又一實施例提供了一種半導體元件，包含半導體基板、第一組長條形半導體結構與第二組長條形半導體結構。第一組長條形半導體結構以垂直於半導體基板之方向自半導體基板延伸。第二組長條形半導體結構直接設置在第一組長條形半導體結構上，第二組長條形半導體結構包含與第一組長條形半導體結構不同的材料，其中第一組長條形半導體結構與第二組長條形半導體結構之間的接面實質上共面。
102:半導體基板
104:圖案化模板層
106:長條形半導體結構
108:磊晶生長製程
110:虛設介電層
112:閘極層
114:平坦化製程
116:移除製程
118:高度
119:偏移
120:磊晶生長製程
121:接面
122:長條形半導體結構
124:介電層/覆蓋層
126:平坦化製程
128:額外介電層
202:移除製程
204:偏移
206:磊晶生長製程
302:溝槽
304:金屬閘極層
402:研磨停止層
404:研磨停止柱
502:研磨停止柱
504:長條形半導體結構
508:研磨停止柱
510:長條形半導體結構
602:光阻劑層
604:蝕刻製程
606:溝槽
608:長條形半導體結構
610:磊晶生長製程
612:平坦化製程
700:方法
702:步驟
704:步驟
706:步驟
708:步驟
當結合隨附圖式閱讀時，自以下詳細描述將最佳地理解本發明之態樣。應注意，根據工業中之標準實務，各特徵並非按比例繪製。事實上，出於論述清晰之目的，可任意增加或減小各種特徵之尺寸。
第1A圖、第1B圖、第1C圖、第1D圖、第1E圖、第1F圖、第1G圖、第1H圖、第1I圖及第1J圖為顯示根據本文所描述的原理之一個實施例的用於形成具有實質上類似高度之奈米接線之說明性製程的圖式。
第2A圖及第2B圖為顯示根據本文所描述的原理之一個實施例的用於形成在閘極層邊緣下方具有接面的雙材料奈米接線之說明性製程的圖式。
第3A圖及第3B圖為顯示根據本文所描述的原理之一個實施例的用於以金屬閘極層替代虛設閘極層之說明性製程的圖式。
第4A圖、第4B圖、第4C圖及第4D圖為顯示根據本文所描述的原理之一個實施例的用於形成研磨停止柱以控制奈米接線高度之說明性製程的圖式。
第5圖為顯示根據本文所描述的原理之一個實施例之具有不同高度的研磨停止柱的圖式。
第6A圖、第6B圖、第6C圖及第6D圖為顯示根據本文所描述的原理之一個實施例的用於形成N型及P型奈米接線之說明性製程之圖式。
第7圖為顯示根據本文所描述的原理之一個實施例的用於製造具有實質上共面接面之雙材料長條形半導體結構之說明性方法的流程圖。
以下揭示內容提供許多不同實施例或實施例用於實施所提供標的物之不同特徵。下文描述元件及佈置之特定實施例以簡化本發明。當然，此等僅為實施例且並不意欲為限制性。舉例而言，以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一及第二特徵的實施例，且亦可包括可在第一與第二特徵之間形成額外特徵以使得第一及第二特徵可不直接接觸的實施例。另外，本發明可在各種實施例中重複元件符號及/或字母。此重複係出於簡明性及清晰之目的，且本身並不指示所論述之各種實施例及/或配置之間的關係。
此外，為便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述圖式中所說明之一個部件或特徵與另一部件(或多個部件)或特徵(或多個特徵)之關係。除了圖式中所描繪之定向外，空間相對性術語意欲包含在使用或操作中之裝置之不同定向。設備可以其他方式定向(旋轉90度或其他定向)且因此可同樣地解釋本文所使用之空間相對性描述詞。
如上文所描述，歸因於各種磊晶製程特徵，在磊晶製程完成之後，奈米接線中之每一者可能不具有相同的高度。為達成較佳裝置操作，理想的是此等奈米接線具有實質上類似的高度。本文所描述的方法揭示產生具有實質上類似高度之奈米接線之製造製程。
根據一個實施例，在基板上形成雙材料長條形半導體結構(例如，奈米接線)。另外，在長條形半導體結構之兩種不同的半導體材料之間的接面實質上共面。在一個實施例中，第一磊晶製程用於形成長條形半導體結構之下部。如上文所描述，此等磊晶製程產生具有不同高度的半導體結構。為使長條形半導體結構之高度平坦化，首先沉積閘極層以使得其覆蓋長條形半導體結構中之每一者。隨後，執行平坦化製程(諸如化學機械研磨(chemical mechanical polishing；CMP)製程)以使得將閘極層減小至所要高度。另外，平坦化製程減小長條形半導體結構中之每一者之高度以匹配閘極層之高度。因此，在平坦化製程之後，長條形閘 極結構中之每一者具有類似高度。可隨後使用磊晶生長製程在下部之頂部上形成長條形半導體結構之上部。
第1A圖至第1J圖為顯示用於形成具有實質上類似高度之奈米接線之說明性製程。第1A圖說明半導體基板102及圖案化模板層104。半導體基板102可由多種半導體材料構成，諸如矽、鍺、砷化鎵、磷化銦及砷化銦。在一些實施例中，半導體基板102為半導體晶圓。
模板層104可藉由使基板102之某些區域曝露於磊晶生長製程來充當模板，如將在下文中更詳細地描述。模板層104可由多種材料構成。此等材料可為介電材料。此等材料可包括例如二氧化矽(SiO2)、氮化矽(SiNx)、氧化鋁(Al2O3)、氧化鉿(HfO2)或其任何組合。可藉由首先在半導體基板102上沉積材料形成模板層104。隨後，可使用各種微影術技術將模板層104圖案化。舉例而言，可沉積光阻劑且使用光罩使其曝露於光源。隨後，可使光阻劑顯影以使得圖案使下層模板層104曝露於蝕刻製程。模板層104可具有在約2奈米至40奈米(nm)範圍內之厚度。
第1B圖說明形成複數個長條形半導體結構106之磊晶生長製程108。長條形半導體結構106可為最終將形成的全部的長條形半導體結構之下部。磊晶生長製程包括在晶體基板上形成晶體結構。此處，晶體基板為半導體基板102。形成之晶體結構為長條形半導體結構106。長條形半導體結構106僅在基板102之經由模板層104曝露之部分上生長。如所說明，歸因於磊晶生長製程108之性質，不同的 結構可能以不同的速率生長。因此，當磊晶製程108完成時，長條形半導體結構106可能具有不同的高度。
長條形半導體結構106可由多種材料構成。此等材料可包括例如矽、鍺、矽鍺、砷化銦、砷化銦鎵、銻化銦及銻化銦鎵。另外，可摻雜長條形半導體結構106。長條形半導體結構之摻雜可原位發生。所用摻雜劑之類型係基於待形成之電晶體之類型。另外，原位摻雜可隨著磊晶生長製程108進行而變化。舉例而言，原位摻雜可隨著磊晶生長製程108進行而停止及重新開始。在一些情況下，可將摻雜分佈分級。然而，在一些實施例中，可將摻雜分佈分階梯。另外，原位摻雜可在磊晶生長製程108期間改變摻雜劑類型。長條形半導體結構106之摻雜濃度可在約1x1015cm3至5x1020cm3範圍內。在一些實施例中，若長條形半導體結構106包括兩種不同的材料(諸如矽鍺)，則一種材料與另一種材料之比率可在製程期間逐漸地改變。因此，第二材料之濃度可具有分級的分佈。此可例如藉由在磊晶生長製程期間改變前驅物之流動速率來進行。
長條形半導體結構可形成為具有自頂部視角看之多種形狀。舉例而言，自頂部視角看，長條形半導體結構106可實質上為圓形或橢圓形的。在一些實施例中，自頂部視角看，長條形半導體結構106可實質上為方形或矩形的。在一些實施例中，長條形半導體結構106之形狀可實質上為六邊形。在一些實施例中，長條形半導體結構106可具有自 頂部視角看之長條形形狀。在此等實施例中，長條形半導體結構106可稱為奈米棒。
第1C圖為說明在基板上形成之虛設介電層110之圖式。虛設介電層110直接沉積在模板層104上且直接沉積在長條形半導體結構106上。特定言之，虛設介電層110安置在長條形半導體結構之側壁上並且在長條形半導體結構106之頂部上。虛設介電層110可由多種介電材料構成，諸如二氧化矽(SiO2)、氮化矽(SiNx)、氧化鋁(Al2O3)、氧化鉿(HfO2)或其任何組合。
第1D圖為顯示閘極層112之說明性沉積之圖式。在一些實施例中，閘極層112為隨後將被金屬閘極替代之虛設閘極層。在此情形中，閘極層112可由聚矽構成。沉積閘極層112以使得其覆蓋長條形半導體結構106中之每一者。
第1E圖為顯示用於使閘極層112及長條形半導體結構106之表面平坦化之說明性平坦化製程114之圖式。在一個實施例中，平坦化製程114為CMP製程。CMP製程包括使用其中懸浮有研磨劑粒子之化學泥漿。泥漿經沉積在晶圓之表面上且使用研磨墊研磨表面。研磨劑粒子以及化學溶液移除材料以產生平坦表面。在平坦化製程114之後，閘極層112之頂表面實質上與長條形半導體結構106之頂表面共面。在本實施例中，CMP製程持續直至長條形半導體結構106具有最終高度。長條形半導體結構106可具有在約5nm至約150nm範圍內之最終高度。
第1F圖說明移除製程116(諸如蝕刻製程)以產生長條形半導體結構106與閘極層112之頂部之間的偏移。移除製程116為選擇性的以使得其移除閘極層112同時保持長條形半導體結構106實質上完整。移除製程116可為濕式蝕刻製程或乾式蝕刻製程。移除製程116減小閘極層112之高度118以使得在長條形閘極結構106之頂表面中在閘極層112之間存在偏移119。如將在下文中更詳細地解釋，將在長條形半導體結構106之頂部上形成第二材料。因此，兩種材料之間的接面自閘極層112之頂表面偏移。偏移119可在約0nm至50nm範圍內。
第1G圖說明形成長條形半導體結構122之上部的額外磊晶生長製程120。長條形半導體結構122係由與長條形半導體結構106不同的材料構成。換言之，奈米接線之上部係由與奈米接線之下部不同的材料構成。由於長條形半導體結構106經平坦化，因此在上部中之下部之間的接面121實質上共面。另外，在上部122中之下部106之間的接面121中之每一者均距閘極層112之頂表面實質上類似的距離(亦即，偏移)。此允許達成較佳裝置效能及一致性。此外，類似於上文描述之磊晶製程108，磊晶製程120產生具有不同高度之長條形半導體結構122。
長條形半導體結構122可由多種材料構成。此等材料可包括例如矽、鍺、矽鍺、砷化銦、砷化銦鎵、銻化銦及銻化銦鎵。另外，可摻雜長條形半導體結構122。長條形半導體結構之摻雜可原位發生。所用摻雜劑之類型係基於 待形成之電晶體之類型。另外，原位摻雜可隨著磊晶生長製程120進行而變化。舉例而言，原位摻雜可隨著磊晶生長製程120進行而停止及重新開始。另外，原位摻雜可在磊晶生長製程120期間改變摻雜劑類型。長條形半導體結構122之摻雜濃度可在約1x1015cm3至5x1020cm3範圍內。
第1H圖說明介電層124之沉積。介電層124亦可稱為覆蓋層。沉積介電層124以使得其覆蓋長條形半導體結構122中之每一者。
第1I圖說明平坦化製程126。平坦化製程126可例如為CMP製程。平坦化製程126使晶圓之表面平坦化以便使長條形半導體結構122中之每一者之頂表面曝露。因此，使得長條形半導體結構122中之每一者之高度實質上類似。
第1J圖為說明額外介電層128之沉積之圖式。在一個實施例中，額外介電層128為間層介電(inter-layer dielectric；ILD)層。在一些實施例中，可在額外介電層128中形成各種特徵。此等特徵可包括例如將長條形半導體結構122連接至電路內之其他元件之通孔及接觸件。
第2A圖及第2B圖為顯示用於形成在閘極層112邊緣下方具有接面之雙材料奈米接線之說明性製程的圖式。換言之，在閘極層112之頂表面與下部106與上部122之間的接面之間的偏移204為負的。根據本實施例，在執行平坦化製程114之後，應用移除製程202。如第2A圖中所示，移除製程202移除長條形半導體結構106之部分同時保 持閘極層112實質上完整。持續施加移除製程202移除所要數量之材料及產生所要偏移204所需之時間。舉例而言，移除製程可為乾式蝕刻製程或濕式蝕刻製程。
第2B圖說明形成長條形半導體結構106之上部之磊晶生長製程206。磊晶生長製程206類似於上文描述之磊晶生長製程120。然而，此處，上部122之生長在低於閘極層112之頂表面之一點處開始。製程隨後如上文在隨附第1H圖至第1J圖之文本中所描述繼續。
第3A圖至第3B圖為顯示用於以金屬閘極層替代虛設閘極層之說明性製程之圖式。在本實施例中，替換閘極層112在置放額外介電層128之後發生。然而，在一些情況下，替換閘極層112可在平坦化製程126之後且在形成額外介電層128之前發生。
第3A圖說明向下延伸至閘極層112之溝槽302之形成。在本實施例中，溝槽302延伸穿過額外介電層128及覆蓋層124。溝槽302可以多種方式形成。舉例而言，可在晶圓之表面上沉積圖案光阻劑層及/或硬遮罩層。經由光阻劑層或硬遮罩曝露之晶圓區域已曝露於蝕刻製程。蝕刻製程可為乾式蝕刻製程。乾式蝕刻製程為各向異性的且將因此以實質上為直線的方式向下蝕刻。
在使用乾式蝕刻製程使閘極層112曝露之後，可使用濕式蝕刻製程以移除閘極層112。濕式蝕刻製程為各向同性的且因此可以在所有方向上移除材料。濕式蝕刻可為選擇性的以便移除閘極層112材料(例如，聚矽)，同時保 持剩餘材料實質上完整。在一些實施例中，亦可移除環繞長條形半導體結構106之介電層110。
第3B圖說明在由閘極層112留下的間隔內沉積金屬材料。金屬材料形成金屬閘極層304。金屬閘極層304充當用於部分由長條形半導體結構106、122形成之電晶體之閘極。另外，溝槽302內之金屬材料可形成通孔以充當閘極接觸件。用於形成金屬閘極層304之金屬材料可為多種材料中之一者。舉例而言，金屬材料可為鎢。
第4A圖至第4D圖為顯示用於形成研磨停止柱404以控制奈米接線之高度之說明性製程的圖式。在一些實施例中，理想的是在特定高度處形成長條形半導體結構106。此可經由使用研磨停止柱404來進行。第4A圖說明在模板層經圖案化之前形成於模板層104之頂部上之研磨停止層402。研磨停止層402之厚度使得研磨停止層402之頂部對應於長條形半導體結構106之所要高度。研磨停止層402可由對CMP製程具有耐受性之硬質材料構成。此等材料之一個實施例可為氮化矽。
第4B圖說明在已經圖案化以形成停止柱404之後的停止層402。可使用各種微影術技術將研磨停止層402圖案化。當自頂部視角檢視時，研磨停止柱404可具有多種形狀。舉例而言，研磨停止柱404可為方形、矩形、圓形、橢圓形或可呈其他形狀。研磨停止柱404之大小亦可變化。研磨停止柱404可置放在未置放其他特徵(諸如長條形半導體結構106)之區域處。
第4C圖說明形成長條形半導體結構106。長條形半導體結構106可如上文所描述形成。第4D圖說明在上文描述之平坦化製程114之後的平坦化長條形半導體結構106。由於研磨停止柱404係由對CMP製程具有耐受性之材料構成，因此CMP製程將在其達至研磨停止柱404之頂部時被阻止向前移動。因此，研磨停止柱404可用於控制長條形半導體結構106之高度。
第5圖為顯示具有不同高度的研磨停止柱502、508的圖式。在一些情況下，理想的是具有高度不同的長條形半導體結構。因此，在一些實施例中，在晶圓之不同區域處的研磨停止柱502、508可具有不同的高度。在本實施例中，研磨停止柱502具有大於研磨停止柱508之高度。因此，靠近研磨停止柱502之長條形半導體結構504具有大於靠近研磨停止柱508之長條形半導體結構510之高度。
第6A圖至第6D圖為顯示用於形成N型及P型奈米接線之說明性製程之圖式。積體電路通常包括N型及P型電晶體，其一起形成互補金屬氧化物半導體(complementary metal oxide semiconductor；CMOS)電路。N型及P型奈米接線電晶體可使用不同類型的半導體材料並且經摻雜有不同類型的摻雜劑。
根據本實施例，光阻劑層602及/或遮罩層用於覆蓋長條形半導體結構106之子集，如第6A圖中所示。可在上文描述之平坦化製程114之後施加光阻劑層602。可隨後 使用蝕刻製程604移除長條形半導體結構106之曝露子集，如第6B圖中說明。蝕刻製程604可為選擇性的以使得其移除長條形半導體結構106同時保持其他材料(諸如閘極層112)實質上完整。移除曝露的長條形半導體結構106產生溝槽606，其使基板102曝露。
第6C圖說明生長長條形半導體結構608之磊晶生長製程610。用於形成長條形半導體結構608之材料與用於形成長條形半導體結構106之材料不同。特定言之，用於形成長條形半導體結構608之材料經設計以用於P型電晶體，且用於形成長條形半導體結構106之材料經設計以用於N型電晶體。
長條形半導體結構608可由適用於P型電晶體之多種材料構成。另外，可摻雜長條形半導體結構608。長條形半導體結構608之摻雜可原位發生。另外，原位摻雜可隨著磊晶生長製程108進行而變化。舉例而言，原位摻雜可隨著磊晶生長製程108進行而停止及重新開始。在一些情況下，可將摻雜分佈分級。然而，在一些實施例中，可將摻雜分佈分階梯。長條形半導體結構608之摻雜濃度可在約1x1015cm3至5x1020cm3範圍內。在一些實施例中，若長條形半導體結構608包括兩種不同的材料(諸如矽鍺)，則一種材料與另一種材料之比率可在製程期間逐漸地改變。因此，第二材料之濃度可具有分級的分佈。此可例如藉由在磊晶生長製程期間改變前驅物之流動速率來進行。
第6D圖說明平坦化製程612，其移除光阻劑602及/或硬遮罩層並且使長條形半導體結構608平坦化。長條形半導體結構106及長條形半導體結構608將具有相同的高度。彼高度對應於閘極層112之頂表面。
第7圖為顯示用於製造具有實質上共面接面之雙材料長條形半導體結構之說明性方法的流程圖。根據本實施例，方法700包括步驟702，其用於在半導體基板上磊晶生長複數個長條形半導體結構之第一部分。長條形半導體結構垂直於基板延伸。換言之，長條形半導體結構縱向形成。如上文所描述，在磊晶製程完成之後，長條形半導體結構中之每一者可具有稍微不同的高度。然而，理想的是長條形半導體結構中之每一者之頂表面實質上共面。
方法700進一步包括用於在基板上形成閘極層之步驟704。閘極層與長條形半導體結構接觸。特定言之，閘極層完全覆蓋長條形半導體結構中之每一者。閘極層可為虛設閘極層。舉例而言，閘極層可由將最後被金屬閘極層替代之聚矽構成。此替代製程可在執行其他可能不利地影響金屬閘極層之製程之後發生。
方法700進一步包括用於在閘極層及長條形半導體結構上執行平坦化製程之步驟706。平坦化製程可例如為CMP製程。平坦化製程使長條形半導體結構中之每一者之高度相等。
方法700進一步包括用於磊晶生長複數個長條形半導體結構之第二部分之步驟708。第二部分係由與第一 部分不同的半導體材料構成。磊晶製程將導致第二部分(上部)直接在長條形半導體結構之第一部分(下部)之曝露上表面上生長。合併之下部與上部可經適當地摻雜以使得其可充當電晶體之一部分。
根據一個實施例，方法包括在半導體基板上磊晶生長複數個長條形半導體結構之第一部分，長條形半導體結構垂直於基板延伸。方法進一步包括在基板上形成閘極層，閘極層與長條形半導體結構接觸。方法進一步包括在閘極層及長條形半導體結構上執行平坦化製程，及磊晶生長複數個長條形半導體結構之第二部分，第二部分包含與第一部分不同的材料。
前述內容概述若干實施例之特徵以使得熟習此項技術者可較佳地理解本發明之態樣。熟習此項技術者應理解，其可容易地使用本發明作為設計或修改其他製程及結構之基礎用於進行本文中所介紹之實施例之相同的目的及/或達成相同的優點。熟習此項技術者應同時意識到，此等等效建構不偏離本發明之精神及範疇，且其可在本文中進行各種變化、替代及修飾而不偏離本發明之精神及範疇。
102:半導體基板
104:圖案化模板層
106:長條形半導體結構
112:閘極層
404:研磨停止柱

Claims (10)

  1. 一種半導體元件的製作方法，包含：在一半導體基板上磊晶生長複數個長條形半導體結構之第一部分，該些長條形半導體結構垂直於該基板延伸；在該基板上形成一閘極層，該閘極層設置於該些長條形半導體結構上；在該閘極層及該些長條形半導體結構上執行一平坦化製程；在該平坦化製程後，移除部分的該閘極層；以及磊晶生長該些長條形半導體結構之第二部分，該些第二部分包含與該些第一部分不同的一材料，其中該些第一部分與該些第二部分之間的接面自該閘極層的邊緣偏移。
  2. 如請求項1所述之方法，更包含在該平坦化製程後，移除該些長條形半導體結構之該些第一部分的部分以形成偏移。
  3. 如請求項1所述之方法，更包含形成一第一介電層於該些長條形半導體結構之該些第二部分上；執行一化學研磨製程於該第一介電層上以平坦化該第一介電層及該些長條形半導體結構之該些第二部分；以及形成一第二介電層於該第一介電層上。
  4. 如請求項1所述之方法，更包含在形成該些長條形半導體結構之該些第一部分前，形成複數個研磨停止柱於該半導體基板上。
  5. 如請求項4所述之方法，其中在該半導體基板不同區域處的該些研磨停止柱具有不同的高度。
  6. 如請求項1所述之方法，其中該些長條形半導體結構之該些第一部分具有一第一電性，方法更包含在該平坦化製程之後，移除該些長條形半導體結構之該些第一部分的數個以形成複數個溝槽；以及形成該些長條形半導體結構之複數個第三部分於該些溝槽中，該些第三部分具有不同於該第一電性的一第二電性。
  7. 一種半導體元件的製作方法，包含：在一半導體基板上形成一第一組長條形半導體結構，該第一組長條形半導體結構垂直於該半導體基板延伸；在該半導體基板上形成一虛設閘極層，該虛設閘極層設置在該第一組長條形半導體結構上；在該虛設閘極層及該第一組長條形半導體結構上執行一平坦化製程；以及在該第一組長條形半導體結構上且與其對準形成一第二組長條形半導體結構，該第二組長條形半導體結構包含與該第一組長條形半導體結構不同的材料。
  8. 如請求項7所述之方法，其中形成該第一組長條形半導體結構與該第二組長條形半導體結構包含使用磊晶成長製程。
  9. 一種半導體元件，包含：一半導體基板；一第一組長條形半導體結構，以垂直於該半導體基板之方向自該半導體基板延伸；一第二組長條形半導體結構，直接設置在該第一組長條形半導體結構上，該第二組長條形半導體結構包含與該第一組長條形半導體結構不同的材料，其中該第一組長條形半導體結構與該第二組長條形半導體結構之間的接面實質上共面；以及複數個研磨停止柱，設置於該半導體基板上。
  10. 如請求項9所述之半導體元件，其中該第一組長條形半導體結構與該第二組長條形半導體結構用於源極、汲極或通道區域。
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