TWI722479B - Pixel circuit and pixel driving method - Google Patents

Abstract

A pixel circuit includes a driving circuit, a data writing circuit, and a modulation circuit. The driving circuit is turned on in response to a voltage level of a first node, in order to output a driving current to drive a light emitting element. The data writing circuit is turned on in response to a gate signal, in order to store a data voltage. The modulation circuit outputs a data voltage to a second node in response to a change in a voltage level of a time control signal, and adjusts the voltage level of the first node to a first voltage according to the voltage level of the second node, in order to turn on the driving circuit.

Description

Pixel circuit and pixel driving method

The present disclosure relates to a pixel circuit and a pixel driving method, and more particularly to a pixel circuit that responds to a time control signal.

The pixel circuit is used to drive and display different picture results. Since the size of the circuit area will affect the manufacturing process of the product, and the brightness of the pixel circuit in the market is generally dark at low frequencies, the user experience is reduced.

In order to solve the above-mentioned problems, one aspect of the present application is to provide a pixel circuit including a driving circuit, a data writing circuit, and a modulation circuit. The driving circuit responds to the conduction of the potential of the first node to output a driving current to drive the light emitting element. The data writing circuit is turned on in response to the gate signal to store the data voltage. The modulation circuit outputs a data voltage to the second node in response to a change in the potential of the time control signal, and adjusts the potential of the first node to the first voltage according to the potential of the second node to turn on the driving circuit.

One aspect of this case is to provide a pixel driving method, which includes the following operations: turning on the driving circuit in response to the potential of the first node to output Drive current to drive the light-emitting element; store the data voltage by the data writing circuit in response to the turn-on of the gate signal; and output the data voltage to the second node by the modulation circuit in response to the potential change of the time control signal, and according to The potential of the second node adjusts the potential of the first node to the first voltage to control the driving circuit to output a driving current.

In summary, the pixel circuit and pixel driving method provided by the embodiments of the present application can use a small number of signal lines and components to reduce the distribution area of the circuit, which is suitable for electronic devices with small screens, and can improve the picture at low frequencies. The brightness of the element circuit.

100‧‧‧Pixel circuit

110‧‧‧Drive circuit

120‧‧‧Data writing circuit

130‧‧‧Modulation circuit

140‧‧‧Filter circuit

200‧‧‧Working waveform

T1, T2‧‧‧Transistor

T3, T4‧‧‧Transistor

T5, T6‧‧‧Transistor

T7‧‧‧Transistor

C、CF‧‧‧Capacitor

R1, R2‧‧‧Resistor

D‧‧‧Light-emitting element

I‧‧‧Drive current

AMP‧‧‧First voltage

VDD‧‧‧Second voltage

TC‧‧‧Time control signal

G[N]‧‧‧Gate signal

Data[m]‧‧‧Data voltage

VSS‧‧‧Third voltage

N1‧‧‧First node

N2‧‧‧Second node

N3‧‧‧The third node

V1‧‧‧First pre-position

V2‧‧‧Second pre-level

V3‧‧‧Prohibition level

V4‧‧‧Enable level

RES‧‧‧Reset period

DW‧‧‧Data writing period

TSET‧‧‧Preparation period

EM‧‧‧Lighting period

Readout[m]‧‧‧Read signal

Sense[N]‧‧‧sensing signal

The schematic description of the present case is as follows: Figure 1A is a schematic diagram of a pixel circuit drawn according to some embodiments of the present case; Figure 1B is a schematic diagram of a pixel circuit drawn according to some embodiments of the present case in Figure 1A A schematic diagram of the waveform; Figure 2 is a schematic diagram of the pixel circuit according to some embodiments of the present case during the reset period; Figure 3 is a schematic diagram of the pixel circuit according to some embodiments of the present case during the data writing period Figure 4 is a schematic diagram of the operation of the pixel circuit in the preparation period according to some embodiments of the present case; Figure 5 is a schematic diagram of the pixel circuit drawn in the light-emitting period according to some embodiments of the present case Schematic diagram of the operation of the light-emitting element; Fig. 6 is a schematic diagram of a pixel circuit according to some embodiments of the present case; Fig. 7 is a schematic diagram of a pixel circuit according to other embodiments of the present case; and Fig. 8 is a schematic diagram of some pixel circuits according to the present case The flowchart of the pixel driving method shown in the embodiment.

In this article, the terms first, second, third, etc., are used to describe various elements, components, regions, layers, and/or blocks, and it is understandable. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to identify a single element, component, region, layer, and/or block. Therefore, in the following, a first element, component, region, layer and/or block may also be referred to as a second element, component, region, layer and/or block without departing from the original meaning of the present case.

In this article, unless the article is specifically limited in the context, "一" and "the" can generally refer to one or more. It will be further understood that the terms "include", "include", "have" and similar words used in this article indicate the recorded features, regions, integers, steps, operations, elements and/or components, but do not exclude The described or additional one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all words used in this article (including technical and scientific terms) have their usual meanings, and their meanings can be familiar with People in this field understand. Furthermore, the definitions of the above-mentioned words in commonly used dictionaries should be interpreted as meaning consistent with the relevant fields in this case in the content of this specification. Unless specifically defined, these terms will not be interpreted as idealized or overly formal meanings.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement and the A certain amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can select a more acceptable deviation range or standard deviation based on optical properties, etching properties or other properties, and not one standard deviation can be used for all properties .

When an element is called "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or an additional element may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no additional element in it.

Several implementations of this case will be disclosed in the following diagrams. For the sake of clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the case. In other words, in some implementations of this case, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventionally used structures and elements will be shown in a simple schematic manner in the drawings.

Referring to FIG. 1A, FIG. 1A is a schematic diagram of a pixel circuit 100 according to some embodiments of the present application. In some embodiments, The pixel circuit 100 can be applied to a display panel.

The pixel circuit 100 includes a driving circuit 110, a data writing circuit 120 and a modulation circuit 130. The driving circuit 110 is used for outputting a driving current I to drive a light emitting element D in response to the electric potential of the first node N1 being turned on. The data writing circuit 120 is used for storing the data voltage Data[m] in response to the gate signal G[N] being turned on. The modulation circuit 130 is used for outputting a data voltage Data[m] to the second node N2 in response to a change in the potential of a time control signal TC, and adjusting the potential of the first node N1 to the first voltage AMP according to the potential of the second node N2 , To turn on the driving circuit 110.

In some embodiments, the driving circuit 110 includes a transistor T1 and a light-emitting element D. The transistor T1 is used to receive the second voltage VDD and is turned on according to the potential of the first node N1 to generate a driving current I. The light emitting element D is coupled to the transistor T1 and emits light according to the driving current I.

In some embodiments, the data writing circuit 120 includes a capacitor C and a transistor T2. The first terminal of the capacitor C is used to receive the third voltage VSS, and the second terminal of the capacitor C is coupled to the modulation circuit 130. The transistor T2 is turned on in response to the gate signal G[N] to transmit the data voltage Data[m] to the second end of the capacitor C to store the data voltage Data[m] to the capacitor C. In some embodiments, the data writing circuit 120 and the modulation circuit 130 are coupled to the third node N3.

In some embodiments, the modulation circuit 130 includes a transistor T3, a transistor T4, a transistor T5, and a transistor T6. The transistor T3 is coupled between the second node N2 and the third node N3. The transistor T4 is coupled between the second node N2 and a terminal for providing the second voltage VDD. The transistor T5 is coupled to the first node N1, and the transistor T3, the transistor T4, and the transistor T5 The control signal TC is turned on according to the time. The transistor T6 is coupled between the first node N1 and a terminal for providing the first voltage AMP, and is turned on according to the potential of the second node N2 to control the potential of the first node N1. In some embodiments, the modulation circuit 130 is coupled between the first node N1 and the third node N3. In some embodiments, transistor T1, transistor T2, and transistor T3 can be implemented by P-type transistors, and transistor T4, transistor T5, and transistor T6 can be implemented by N-type transistors.

In some embodiments, the pixel circuit 100 can be implemented by a simple structure (ie, six transistors T1 to T6 and a capacitor C). In this way, the amount of signal lines and the area of the circuit in the display panel made of the pixel circuit 100 can be reduced, which is suitable for small-screen electronic devices.

In some embodiments, the pixel circuit 100 further includes a filter circuit 140. The filter circuit 140 includes a resistor R1, a resistor R2, and a capacitor CF. The capacitor CF is coupled between the resistor R1 and the resistor R2. The first end of the resistor R1 is used to receive the first voltage AMP, and the second end of the resistor R1 is coupled to the transistor T6. The first end of the resistor R2 is used to receive the second voltage VDD, and the second end of the resistor R2 is coupled to the transistor T1 and the transistor T4. In some embodiments, the pixel circuit 100 can directly receive the first voltage AMP and the second voltage VDD without the filter circuit 140. To simplify the description, the operations of the following embodiments (ie, FIGS. 2-7) will be described by taking the example of directly receiving the first voltage AMP and the second voltage VDD. It should be understood that the following embodiments can also be implemented together with the filter circuit 140.

The related circuit setting method of the pixel circuit 100 in FIG. 1A is used as an example, and the present case is not limited to this. Executable and pixel circuit The related circuit setting methods for the same operation of 100 are all covered by this project.

Referring to FIG. 1B, FIG. 1B is a schematic diagram of the waveform 200 of the pixel circuit 100 in FIG. 1A according to some embodiments of the present application. During one operation, the waveform 200 includes a reset period RES, a data writing period DW, and a light emitting period EM. During the reset period RES, the second voltage VDD, the third voltage VSS, and the gate signal G[N] have a disable level V3, and the time control signal TC has a first predetermined level V1 without any data voltage Data[m] is input to the data writing circuit 120. In the data writing period DW, the second voltage VDD and the third voltage VSS have a disable level V3, the time control signal TC has a first predetermined level V1, and the data voltage Data[m] is provided by the gate signal The control of G[N] is input to the writing circuit 120. Finally, in the light-emitting period EM, the second voltage VDD has a first predetermined level V1, the third voltage VSS and the gate signal G[N] have a disable level V3, and the potential of the time control signal TC changes from the first predetermined level. The level V1 drops to a second predetermined level V2 with time, and the data voltage Data[m] stops being input to the data writing circuit 120 according to the gate signal G[N] having a disable level V3. The detailed operation of each of the above periods will be described in the following paragraphs with reference to Figures 3 to 5 described below.

In some embodiments, between the data writing period DW and the light emitting period EM, the waveform 200 further includes a preparation period TSET. In this preparatory period TSET, the potential of the time control signal TC gradually decreases from the first predetermined level V1 to the second predetermined level V2 with time to prepare for entering the light emitting period EM.

In some embodiments, the first predetermined level V1 is greater than the second predetermined level V2, and the second predetermined level V2 is greater than the disable level V3. In some embodiments, the first predetermined level V1 may be approximately 12 volts, the second predetermined level V2 may be approximately 5 volts, and the disable level V3 may be approximately 0 volts, and this case does not take these values as limit. In some embodiments, the disable level V3 of the second voltage VDD, the disable level V3 of the third voltage VSS, and the disable level V3 of the gate signal G[N] may be completely different, or partially the same, or All three are the same. The various values of the first predetermined level V1, the second predetermined level V2, and/or the disable level V3 are all covered by this case.

Referring to FIG. 2, FIG. 2 is a schematic diagram of the pixel circuit 100 during the reset period RES according to some embodiments of the present application.

In some embodiments, the transistor T2 is turned off according to the gate signal G[N], and the transistor T3 is turned off in response to the time control signal TC having the first predetermined level V1 to reset the potential of the second node N2 .

In detail, during the reset period RES, the transistor T2 is turned off according to the gate signal G[N], so the data voltage Data[m] cannot be transmitted to the data writing circuit 120, so that the capacitor C does not store the data voltage Data [m]. The transistor T4 is turned on according to the time control signal TC with the first predetermined level V1 and the second voltage VDD with the disable level V3 to adjust the potential of the second node N2 to the disable level V3. In this way, the transistor T3 is turned off according to the time control signal TC with the first predetermined level V1 and the potential on the second node N2 (in the meantime, the disable level V3). The transistor T5 is turned on in response to the time control signal TC having the first predetermined level V1 to adjust the potential of the first node N1 to the first predetermined level V1. The transistor T6 is based on the potential of the second node N2 and The potential of the first node N1 (the first predetermined level V1 during this period) is turned off. Finally, the transistor T1 is turned off according to the potential of the first node N1 and the second voltage VDD with the disable level V3, so that the driving current I does not flow through the light emitting element D.

Referring to FIG. 3, FIG. 3 is a schematic diagram illustrating the operation of the pixel circuit 100 during the data writing period DW according to some embodiments of the present application. During the data writing period DW, the transistor T2 is turned on in response to the gate signal G[N], so that the data voltage Data[m] is transferred to the capacitor C and stored in the capacitor C.

In some embodiments, the data voltage Data[m] stored in the capacitor C has the potential of the second predetermined level V2.

In some embodiments, the transistor T3 is coupled between the second end of the capacitor C and the second node N2, and is used to respond to the time control signal TC having the first predetermined level V1 and the potential of the second node N2 Off. The transistor T4 is turned on in response to the time control signal TC with the first predetermined level V1 to transmit the third voltage VDD with the disable level V3 to the second node N2. The transistor T5 is continuously turned on in response to the time control signal TC to transmit the time control signal TC with the first predetermined level V1 to the first node N1 to adjust the potential of the first node N1 to the first predetermined level. In this way, the driving circuit 110 is still continuously turned off. The transistor T6 is turned off in response to the potential of the second node N2 and the first voltage AMP. The transistor T1 is turned off in response to the potential of the first node N1 (the first predetermined level V1 during this period) and does not allow the driving current I to flow through the driving circuit 110.

In some embodiments, the first voltage AMP may be about 3 volts, and this case is not limited to this value. In some embodiments, the first voltage AMP is a DC voltage associated with the three primary color signals. In some applications, the setting of the DC voltage can be used to increase the brightness of the picture of the pixel circuit 100. The whole range.

Referring to FIG. 4, FIG. 4 is a schematic diagram of the operation of the pixel circuit 100 in the preparation period TSET according to some embodiments of the present application. During the preparatory period TSET, the time control signal TC will start to fall from the first predetermined level V1. When the potential of the time control signal TC has not fallen to the second predetermined level V2, all the transistors T1 to T6 of the pixel circuit 100 will not be turned on, as shown in FIG. 4.

In some embodiments, the third voltage VDD is switched to the uniform energy level V4, and the transistor T4 and the transistor T5 are turned off in response to the potential change of the time control signal TC and the third voltage VDD with the enable level V4. In some embodiments, the enable level V4 may be about 10 volts, and the present case is not limited to this value. In some embodiments, the first voltage AMP is lower than the enable level V4.

Referring to FIG. 5, FIG. 5 is a schematic diagram illustrating the operation of the pixel circuit 100 driving the light-emitting element D in the light-emitting period EM according to some embodiments of the present application. In the light-emitting period EM, when the time control signal TC drops from the first predetermined level V1 to the second predetermined level V2, the transistor T3 will be turned on and the data voltage Data[m] stored in the capacitor C will pass through the transistor T3 It is transmitted to the second node N2 to increase the potential of the second node N2. When the potential of the second node N2 rises to be greater than the first voltage AMP, the transistor T6 is turned on to transmit the first voltage AMP to the first node N1. In this way, the potential of the first node N1 is adjusted to the first voltage AMP. Because the first voltage AMP is set to be lower than the enable level V4. The transistor T1 can be turned on according to the potential of the first node N1 to generate a driving current I to drive the light-emitting element D.

In some embodiments, the time control signal TC is predetermined by the first The level V1 changes to the second predetermined level V2, the transistor T3 is turned on in response to the change in the potential of the time control signal TC to transmit the data voltage Data[m] to the second node N2, and the transistor T6 is based on the second node N2 The potential of is turned on to transmit the first voltage AMP to the first node N1 to turn on the driving circuit 110 to drive the light emitting element D. In other words, the potential change of the time control signal TC can be used to control the light-emitting period of the light-emitting element D.

In some embodiments, the driving current I flowing through the driving circuit 110 can be controlled by the potential of the first node N1 to determine the uniformity of a picture of the pixel circuit 100.

In some embodiments, the period of the driving current I can be controlled based on the potential change of the time control signal TC to determine the grayscale value of a screen of the pixel circuit 100.

In some embodiments, when the pixel circuit 100 is in the light-emitting period EM, the second voltage VDD has the enable level V4. At this time, the potential of the first node N1 is equal to the first voltage AMP to stabilize the conduction of the transistor T1. When the transistor T1 is turned on steadily, it can effectively reduce the flicker of the picture when the pixel circuit 100 works at low frequencies.

In some embodiments, when the data voltage Data[m] stored in the capacitor C is completely released, it represents the end of the EM operation during the light-emitting period. At this time, the pixel circuit 100 will perform the reset period RES again.

Referring to FIG. 6, FIG. 6 is a schematic diagram of the pixel circuit 100 drawn according to some embodiments of the present application. In this example, compared to the previous embodiment, the transistor T4 is turned on in response to a sensing signal Sense[N] and a reading signal Readout[m] to transmit the data voltage Data[m] to the second Section Click N2. In this way, during the data writing period DW, the threshold voltages of the transistors T2 to T4 can be further compensated.

Referring to FIG. 7, FIG. 7 is a schematic diagram of a pixel circuit 100 drawn according to other embodiments of the present application. Compared with the foregoing embodiment, the pixel circuit 100 in this example further includes a transistor T7. The transistor T7 is coupled between the transistor T1 and the light emitting element D. In order to compensate the threshold voltage of the transistor T1, during the data writing period DW, the transistor T7 is turned on in response to the sensing signal Sense[N] and the reading signal Readout[m] to direct the driving current I to the reading signal Readout[m ] Of the endpoint.

In some embodiments, the transistors T1 to T6 can be implemented in thin-film transistors (TFT). In this embodiment. Transistor T1~transistor T3 take P-type TFT as an example, and transistor T4~transistor T6 take N-type TFT as an example, but this case is not limited to this.

In some embodiments, each of transistor T4~transistor T6 can be implemented by Indium Gallium Zinc Oxide (IGZO), and each of transistor T1~transistor T3 can be implemented by low-temperature polysilicon Transistor (LTPS) implementation. In some embodiments, each of the transistors T4 to T6 may be implemented by a low temperature poly-silicon (LTPS).

In some embodiments, each of the transistors T4 to T6 is implemented by an indium gallium zinc oxide thin film transistor (IGZO) to reduce the leakage current of the transistor to achieve the best driving effect of the pixel circuit 100.

According to different applications, various types of transistors are used in this case. Made. When the control terminal (for example, the gate) of each transistor receives a non-conducting signal (for example, a low voltage VSL), the voltage difference between the control terminal and the second terminal (for example, the source) (gate-to-source voltages) Below the threshold voltage Vth of the transistor, the transistor operates in the cutoff region or subthreshold region. Under this operating condition, different input signal sizes will affect the leakage current of the transistor (or called subthreshold leakage).

The foregoing numerical values regarding the number of implemented transistors are only examples, and this case is not limited to these numerical values.

Referring to FIG. 8, FIG. 8 is a flowchart of a pixel driving method 800 according to some embodiments of the present application.

In operation S810, the driving circuit 110 is turned on in response to the potential of the first node N1 to output the driving current I to drive the light emitting element D.

In operation S820, the data writing circuit 120 is turned on in response to a gate signal G[N] to store the data voltage Data[m].

In operation S830, the modulation circuit 130 outputs the data voltage Data[m] to the second node N2 in response to the potential change of the time control signal TC, and adjusts the potential of the first node N1 to the first voltage according to the potential of the second node N2 AMP to control the driving circuit 110 to output the driving current I.

The description of the above operations S810 to S830 can refer to the embodiments of the foregoing drawings, so the details will not be repeated. The multiple operations of the pixel driving method 800 described above are only examples, and are not limited to the sequential execution of the above examples. Without violating the operation mode and scope of the embodiments of the present case, various operations under the pixel driving method 800 can be appropriately added, replaced, omitted, or performed in a different order.

In summary, the pixel circuit 100 and the pixel driving method 800 provided by the embodiment of the present application can use a small number of signal lines and components to reduce the distribution area of the circuit, which is suitable for electronic devices with small screens, and can be used at low frequencies. Improve the brightness of the pixel circuit.

Although this case has been disclosed in the above implementation mode, it is not limited to this case. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this case. Therefore, the scope of protection of this case should be attached hereafter. Those defined in the scope of the patent application shall prevail.

100‧‧‧Pixel circuit

110‧‧‧Drive circuit

120‧‧‧Data writing circuit

130‧‧‧Modulation circuit

140‧‧‧Filter circuit

T1, T2‧‧‧Transistor

T3, T4‧‧‧Transistor

T5, T6‧‧‧Transistor

C、CF‧‧‧Capacitor

D‧‧‧Light-emitting element

I‧‧‧Drive current

AMP‧‧‧First voltage

VDD‧‧‧Second voltage

TC‧‧‧Time control signal

G[N]‧‧‧Gate signal

Data[m]‧‧‧Data voltage

VSS‧‧‧Third voltage

N1‧‧‧First node

N2‧‧‧Second node

N3‧‧‧The third node

R1, R2‧‧‧Resistor

Claims (20)

A pixel circuit includes: a driving circuit for outputting a driving current to drive a light-emitting element in response to the potential of a first node being turned on; and a data writing circuit for turning on in response to a gate signal Storing a data voltage; and a modulation circuit for outputting the data voltage to a second node in response to a potential change of a time control signal, and adjusting the potential of the first node to a second node according to the potential of the second node A first voltage is used to turn on the driving circuit. The pixel circuit according to claim 1, wherein the driving circuit comprises: a transistor for receiving a second voltage and conducting in response to the potential of the first node to generate the driving current; and a light emitting element , Coupled to the transistor, and emits light according to the driving current. The pixel circuit according to claim 1, wherein the data writing circuit comprises: a capacitor, wherein a first end of the capacitor is used to receive a third voltage, and a second end of the capacitor is coupled to the A modulation circuit; and a first transistor for conducting in response to the gate signal during a data writing period to transmit the data voltage to the second end of the capacitor for storage The data voltage to the capacitor. The pixel circuit according to claim 3, wherein the modulation circuit includes: a second transistor, coupled between the second end of the capacitor and the second node, and used for writing the data The period is turned off in response to the time control signal with a first predetermined level and the potential of the second node; a third transistor is used to turn on in response to the time control signal during the data writing period to transmit A third voltage of a disable level to the second node; a fourth transistor for turning on in response to the time control signal during the data writing period to transmit the time control with the first predetermined level Signal to the first node to turn off the driving circuit; and a fifth transistor for turning off in response to the potential of the second node during the data writing period. The pixel circuit according to claim 4, wherein during a reset period, the first transistor is turned off according to the gate signal, and the second transistor is responsive to the time control having the first predetermined level The signal is turned off to reset the potential of the second node. The pixel circuit according to claim 4, wherein during a light-emitting period, the time control signal is changed from the first predetermined level to a second predetermined level, and the second transistor is used to respond to the time control signal Of the The potential change is turned on to transmit the data voltage to the second node, and the fifth transistor is turned on according to the potential of the second node to transmit the first voltage to the first node to turn on the driving circuit. The pixel circuit according to claim 6, wherein during the light-emitting period, the third transistor and the fourth transistor are used to turn off in response to the potential change of the time control signal, and the third voltage is switched to Consistent energy level. The pixel circuit according to claim 3, wherein the modulation circuit includes: a second transistor, coupled between the second end of the capacitor and the second node, and used for writing the data During the period, the time control signal with a predetermined level is turned off and the potential of the second node is turned off; a third transistor is used to turn on in response to a sensing signal and a read signal during the data writing period, To transmit the data voltage to the second node; a fourth transistor is used to turn on in response to the time control signal during the data writing period to transmit the time control signal with the first predetermined level to the first Node to turn off the driving circuit; and a fifth transistor for turning off in response to the potential of the second node during the data writing period. The pixel circuit according to claim 8, further comprising a transistor, coupled to the driving circuit, for responding to the data writing period The sensing signal and the reading signal are conducted. The pixel circuit according to claim 4 or 8, wherein each of the third transistor, the fourth transistor, and the fifth transistor is implemented by an indium gallium zinc oxide thin film transistor, and the first Each of the transistor and the second transistor is implemented by a low temperature polysilicon transistor. The pixel circuit according to claim 4 or 8, wherein each of the third transistor, the fourth transistor, and the fifth transistor is implemented by a low temperature polysilicon transistor. The pixel circuit according to claim 1, wherein the first voltage is a DC voltage associated with a three-primary color signal. A pixel driving method includes: turning on a driving circuit in response to a potential of a first node to output a driving current to drive a light emitting element; and storing a data by a data writing circuit in response to a gate signal being turned on Voltage; and output the data voltage to a second node by a modulation circuit in response to a potential change of a time control signal, and adjust the potential of the first node to a first voltage according to the potential of the second node , To control the drive circuit to output the drive current. The pixel driving method according to claim 13, wherein storing the data voltage in response to the gate signal being turned on by the data writing circuit includes: turning on the data writing in response to the gate signal during a data writing period A first transistor of the input circuit is used to transmit the data voltage to a capacitor of the data writing circuit; and the data voltage is stored by the capacitor. The pixel driving method according to claim 14, wherein the modulation circuit includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor, and the modulation circuit Outputting the data voltage to the second node in response to the potential change of the time control signal includes: turning off the data voltage in response to the time control signal having a predetermined level and the potential of the second node during the data writing period A second transistor; in response to the time control signal during the data writing period, the third transistor is turned on to transmit a third voltage with a disable level to the second node; responding during the data writing period Turning on the fourth transistor during the time control signal to transmit the time control signal with the first predetermined level to the first node to turn off the driving circuit; and responding to the second transistor during the data writing period The potential of the node turns off the fifth transistor. The pixel driving method according to claim 15, wherein Turn off the first transistor according to the gate signal during a reset period, and turn off the second transistor in response to the time control signal having the first predetermined level to reset the potential of the second node . The pixel driving method according to claim 15, wherein in a light-emitting period, the time control signal changes from the first predetermined level to a second predetermined level, and turns on the time control signal in response to the potential change of the time control signal The second transistor transmits the data voltage to the second node, and turns on the fifth transistor according to the potential of the second node to transmit the first voltage to the first node to turn on the driving circuit. The pixel driving method according to claim 17, wherein during the light-emitting period, the third transistor and the fourth transistor are turned off in response to the potential change of the time control signal, and the third voltage is switched to the same Energy level. The pixel driving method according to claim 14, wherein the modulation circuit includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor, and the modulation circuit The way during the data writing period includes: turning off the second transistor in response to the time control signal having a predetermined level and the potential of the second node during the data writing period; and responding to the second transistor during the data writing period A sensing signal and a reading signal turn on the third transistor to transmit the data voltage to the second node; During the data writing period, the fourth transistor is turned on in response to the time control signal to transmit the time control signal with the first predetermined level to the first node to turn off the driving circuit; and during the data writing The fifth transistor is turned off in response to the potential of the second node during the start period. The pixel driving method according to claim 19, wherein a transistor is turned on in response to the sensing signal and the reading signal during the data writing period.

Images