TWI720682B - 畫素陣列基板 - Google Patents

畫素陣列基板 Download PDF

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TWI720682B
TWI720682B TW108140713A TW108140713A TWI720682B TW I720682 B TWI720682 B TW I720682B TW 108140713 A TW108140713 A TW 108140713A TW 108140713 A TW108140713 A TW 108140713A TW I720682 B TWI720682 B TW I720682B
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electrically connected
transistor
line
sensing
area
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TW108140713A
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TW202119378A (zh
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陳銘耀
曾淑雯
胡心麟
羅睿騏
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友達光電股份有限公司
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Priority to TW108140713A priority Critical patent/TWI720682B/zh
Priority to US16/840,435 priority patent/US11037504B2/en
Priority to CN202010382338.3A priority patent/CN111399296B/zh
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
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Abstract

一種畫素陣列基板，包括基板、多個顯示畫素、多個感測畫素及讀出電路。基板具有第一區及第二區，其中第二區位於第一區與基板的邊緣之間。多個顯示畫素設置於基板的第一區及第二區。多個感測畫素設置於基板的第一區。讀出電路電性連接至多個感測畫素，其中讀出電路的一部分設置於基板的第二區，且讀出電路的一部分位於多個顯示畫素的兩顯示畫素之間。

Description

畫素陣列基板
本發明是有關於一種畫素陣列基板，且特別是有關於包括感測畫素的畫素陣列基板。
高屏佔比與全面屏(Full-screen)的設計已成為中小尺寸面板規格的主流。為實現高屏占比與全面屏，可將指紋辨識用的多個感測畫素併入顯示面板的畫素陣列基板中，進而形成晶胞內的指紋辨識面板(in-cell Fingerprint Panel)。晶胞內的指紋辨識面板具有全屏式(也可稱，非固定點式)的指紋辨識功能，其可支援多種應用，能提升使用者體驗並增加顯示面板附加價值。在晶胞內的指紋辨識面板中，多個感測畫素的感測訊號需藉由讀出電路傳遞至外部處理電路。然而，讀出電路需佔用顯示面板的外腳接合(outer lead bonding；OLB)區，不利於顯示面板的屏佔比。
本發明提供一種顯示裝置，性能佳。
本發明的一種畫素陣列基板，包括基板、多個顯示畫素、 多個感測畫素及讀出電路。基板具有第一區及第二區，其中第二區位於第一區與基板的邊緣之間。多個顯示畫素設置於基板的第一區及第二區。多個感測畫素設置於基板的第一區。讀出電路電性連接至多個感測畫素，其中讀出電路的一部分設置於基板的第二區，且讀出電路的一部分位於多個顯示畫素的兩顯示畫素之間。
在本發明的一實施例中，上述的每一顯示畫素包括一資料線、一掃描線、一電晶體及一畫素電極，顯示畫素的電晶體電性連接至資料線及掃描線，畫素電極電性連接至顯示畫素的電晶體，一遮光圖案遮蔽兩顯示畫素之一者的掃描線及讀出電路的一部分。
在本發明的一實施例中，上述的基板更具有第三區，位於第二區與基板的邊緣之間。畫素陣列基板更包括多條感測扇出走線，電性連接至讀出電路且設置於基板的第三區。至少一顯示畫素位於讀出電路的一部分與多條感測扇出走線之間。
在本發明的一實施例中，上述的讀出電路的一部分包括重置電路的至少一部分。
在本發明的一實施例中，上述的讀出電路的一部分包括主動負載電路的至少一部分。
在本發明的一實施例中，上述的讀出電路的一部分包括多工器的至少一部分。
在本發明的一實施例中，上述的畫素陣列基板更包括電 性連接至多個感測畫素的多條讀出線。多工器包括多個選擇電晶體，其中多工器之多個選擇電晶體的多個第一端電性連接至多條讀出線。讀出電路的一部分包括多工器的多個選擇電晶體。
在本發明的一實施例中，上述的畫素陣列基板更包括電性連接至多個感測畫素的多條讀出線。多工器包括多個選擇電晶體及多條匯流線，其中多工器之多個選擇電晶體的多個第一端電性連接至多條讀出線，且多工器之多個選擇電晶體的多個第二端電性連接至多條匯流線。讀出電路的一部分包括多條匯流線。
在本發明的一實施例中，上述的畫素陣列基板更包括電性連接至多個感測畫素的多條讀出線。多工器包括多個選擇電晶體以及多條匯流線，其中多工器之多個選擇電晶體的多個第一端分別電性連接至多條讀出線，且多工器之多個選擇電晶體的多個第二端電性連接至多條匯流線。讀出電路的一部分包括多條匯流線的至少一者及多工器的多個選擇電晶體。
10:顯示裝置
100:畫素陣列基板
110:基板
110a:邊緣
112:第一區
112a:第一子區
112a-1、114a-1:顯示畫素區
112a-2:感測畫素區
114:第二區
114a:第二子區
114a-2:擬感測畫素區
116:第三區
120:感測扇出走線
130:讀出電路
131:重置電路
132:主動負載電路
133:多工器
140:顯示扇出走線
210、220:外部處理電路
BM:遮光圖案
DL:資料線
DPX:顯示畫素
FPX:感測畫素
G:選擇電晶體組
LVDD:電源供應線
LVSS:參考電壓線
LOUT:讀出線
LRST:重置訊號線
LVB:偏壓訊號線
LZSW:選擇線
LS、LS1、LS2、LSk-1、LSk、LSk+1:匯流線
LSR:感測掃描線
PE:畫素電極
PD:感光元件
RDPX:顯示畫素列
R、r、r’:局部
RST:重置訊號
SL:掃描線
SR:讀取電壓
T:電晶體
T1:第一電晶體
T2:第二電晶體
T3:重置電晶體
T4:負載電晶體
T5:選擇電晶體
Ta、T1a、T2a、T3a、T4a、T5a:第一端
Tb、T1b、T2b、T3b、T4b、T5b:第二端
Tc、T1c、T2c、T3c、T4c、T5c:控制端
VDD:電源電壓
VSS:參考電壓
VB:偏壓
W:寬度
ZSW:多工訊號
圖1為本發明一實施例之顯示裝置10的上視示意圖。
圖2為本發明一實施例之畫素陣列基板100之基板110的局部的上視示意圖。
圖3示出本發明一實施例之基板110之第一區112的一個第一子區112a上的至少一顯示畫素DPX及一個感測畫素FPX。圖3 對應圖2的一個第一子區112a。
圖4示出本發明一實施例之基板110之第二區114的相鄰兩第二子區114a上的多個顯示畫素DPX及其中一個第二子區114a上的讀出電路130的一部分(例如：重置電路131)。
圖5為本發明一實施例之畫素陣列基板100的等效電路示意圖。
圖6示出本發明一實施例之基板110之第二區114的相鄰兩第二子區114a上的多個顯示畫素DPX及其中一個第二子區114a上的讀出電路130的一部分(例如：主動負載電路132)。
圖7示出本發明一實施例之基板110之第二區114的相鄰兩第二子區114a上的多個顯示畫素DPX及其中一個第二子區114a上的讀出電路130的一部分(例如：多工器133的一部分)。
圖8示出本發明一實施例之基板110之第二區114的相鄰兩第二子區114a上的多個顯示畫素DPX及其中一個第二子區114a上的讀出電路130的一部分(例如：多工器133的一部分)。
現將詳細地參考本發明的示範性實施例，示範性實施例的實例說明於附圖中。只要有可能，相同元件符號在圖式和描述中用來表示相同或相似部分。
應當理解，當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時，其可以直接在另一元件上或 與另一元件連接，或者中間元件可以也存在。相反，當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時，不存在中間元件。如本文所使用的，“連接”可以指物理及/或電性連接。再者，“電性連接”或“耦合”可以是二元件間存在其它元件。
本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值，考慮到所討論的測量和與測量相關的誤差的特定數量(即，測量系統的限制)。例如，“約”可以表示在所述值的一個或多個標準偏差內，或±30%、±20%、±10%、±5%內。再者，本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質，來選擇較可接受的偏差範圍或標準偏差，而可不用一個標準偏差適用全部性質。
除非另有定義，本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是，諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義，並且將不被解釋為理想化的或過度正式的意義，除非本文中明確地這樣定義。
圖1為本發明一實施例之顯示裝置10的上視示意圖。
圖1繪出顯示裝置10的基板110、感測扇出走線120、顯示扇出走線140、與感測扇出走線120電性連接的外部處理電路210和與顯示扇出走線140電性連接的外部處理電路220，而省略 顯示裝置10的其它構件。此外，外部處理電路210與220亦可加以整合為單一構件。
圖2為本發明一實施例之畫素陣列基板100之基板110的局部的上視示意圖。圖2對應圖1的局部R。
圖3示出本發明一實施例之基板110之第一區112的一個第一子區112a上的至少一顯示畫素DPX及一個感測畫素FPX。圖3對應圖2的一個第一子區112a。
圖4示出本發明一實施例之基板110之第二區114的相鄰兩第二子區114a上的多個顯示畫素DPX及其中一個第二子區114a上的讀出電路130的一部分(例如：重置電路131)。圖4對應圖2的局部r。
圖5為本發明一實施例之畫素陣列基板100的等效電路示意圖。
須說明的是，圖5的等效電路圖是用以說明畫素陣列基板100之各構件的電性連接關係，圖5繪示之畫素陣列基板100之各構件的位置並不代表其實際設置的位置；畫素陣列基板100之各構件的設置位置，請參照其它圖式。
請參照圖1，顯示裝置10包括畫素陣列基板100、相對於畫素陣列基板100的對向基板(未繪示)以及設置於畫素陣列基板100與對向基板之間的顯示介質(未繪示)。
舉例而言，在本實施例中，顯示介質可以是液晶。然而，本發明不限於此，根據其它實施例，顯示介質也可以是有機發光 二極體(organic light emitting diode，OLED)、微型發光二極體(micro LED)、次毫米發光二極體(mini LED)、量子點發光二極體(quantum dot)或其它種類的顯示介質。
請參照圖1，畫素陣列基板100包括基板110。基板110具有第一區112及第二區114，其中第二區114位於第一區112與基板110的一邊緣110a之間。基板110主要是用以承載畫素陣列基板100的構件。在本實施例中，基板110的材質可以是玻璃、石英、有機聚合物、或是不透光/反射材料(例如：晶圓、陶瓷、或其它可適用的材料)、或是其它可適用的材料。
請參照圖1及圖2，在本實施例中，第一區112包括陣列排列的多個第一子區112a，且每一第一子區112a包括至少一顯示畫素區112a-1及一感測畫素區112a-2。請參照圖2及圖3，每一第一子區112a的至少一顯示畫素區112a-1用以設置至少一顯示畫素DPX，且每一第一子區112a的一感測畫素區112a-2用以設置一感測畫素FPX。請參照圖1，也就是說，第一區112為顯示裝置10之主要的一顯示暨感測區。
請參照圖1及圖2，在本實施例中，第二區114包括陣列排列的多個第二子區114a，且每一第二子區114a包括至少一顯示畫素區114a-1及一擬感測畫素區114a-2。請參照圖2及圖4，每一第二子區114a的至少一顯示畫素區114a-1用以設置至少一顯示畫素DPX，且每一第二子區114a的擬感測畫素區114a-2用以設置讀出電路130的一部分而非用以設置感測畫素FPX。請參照圖1， 也就是說，第二區114為顯示裝置10的一顯示暨擬感測區。
請參照圖1，在本實施例中，畫素陣列基板100的基板110更具有一第三區116，第三區116位於第二區114與基板110的邊緣110a之間。在本實施例中，畫素陣列基板100更包括多條感測扇出走線120，其中多條感測扇出走線120電性連接於讀出電路130(繪於圖5)與多個感測接墊(未繪示)之間，且多個感測接墊用以與一外部處理電路210接合；畫素陣列基板100更包括多條顯示扇出走線140，其中多條顯示扇出走線140電性連接於多個顯示畫素DPX與多個顯示接墊(未繪示)之間，且多個顯示接墊用以與一外部處理電路220接合；多條感測扇出走線120、用以與外部處理電路210接合的多個感測接墊(未繪示)、多條顯示扇出走線140和用以與外部處理電路220接合的多個顯示接墊(未繪示)設置於基板110的第三區116。也就是說，基板110的第三區116為顯示裝置10的外腳接合(outer lead bonding；OLB)區。
請參照圖2、圖3及圖4，多個顯示畫素DPX設置於基板110的第一區112及第二區114。具體而言，在本實施例中，多個顯示畫素DPX設置於顯示暨感測區(即第一區112)之多個第一子區112a的多個顯示畫素區112a-1及顯示暨擬感測區(即第二區114)之多個第二子區114a的多個顯示畫素區114a-1。
請參照圖3，舉例而言，在本實施例中，每一顯示畫素DPX可包括一資料線DL、一掃描線SL、一電晶體T及一畫素電極PE，顯示畫素DPX之電晶體T的第一端Ta及控制端Tc分別 電性連接至資料線DL及掃描線SL，且畫素電極PE電性連接至顯示畫素DPX之電晶體T的第二端Tb。
請參照圖2及圖3，多個感測畫素FPX設置於基板110的第一區112。具體而言，在本實施例中，多個感測畫素FPX設置於顯示暨感測區(即第一區112)之多個第一子區112a的多個感測畫素區112a-2，且未設置在顯示暨擬感測區(即第二區114)之多個第二子區114a的多個擬感測畫素區114a-2。多個感測畫素FPX設置於顯示裝置10之大部分的面積中，且用以感光。舉例而言，在本實施例中，多個感測畫素FPX可用以接收被生物特徵(例如但不限於：指紋)反射的光束，進而實現近乎全屏的生物特徵辨識。
請參照圖3及圖5，舉例而言，在本實施例中，每一感測畫素FPX可包括感光元件PD、第一電晶體T1、第二電晶體T2、用以提供參考電壓VSS的參考電壓線LVSS、用以提供讀取電壓SR的感測掃描線LSR、用以提供電源電壓VDD的電源供應線LVDD和用以接收感測輸出訊號的讀出線LOUT，其中第一電晶體T1的第一端T1a電性連接至參考電壓線LVSS，第一電晶體T1的控制端T1c電性連接至感測掃描線LSR，第一電晶體T1的第二端T1b電性連接至第二電晶體T2的控制端T2c及感光元件PD，第二電晶體T2的第一端T2a電性連接至電源供應線LVDD，且第二電晶體T2的第二端T2b電性連接至讀出線LOUT。然而，本發明不限於此，在其它實施例中，感測畫素FPX也可以是其它型式的電路。此外， 在本實施例中，感光元件PD可以是包括富矽氧化物(silicon-rich oxide；SRO)的光二極體，但本發明不以此為限。
請參照圖5，畫素陣列基板100還包括讀出電路130，電性連接至多個感測畫素FPX的多條讀出線LOUT。舉例而言，在本實施例中，讀出電路130可選擇性包括重置電路131、主動負載電路132及多工器133，但本發明不以此為限。此外，須說明的是，圖5所示之讀出電路130的型式僅是用以說明本發明而非用以限制本發明，在其它實施例中，讀出電路130也可以是其它型式。
請參照圖2、圖4及圖5，值得注意的是，讀出電路130的一部分是設置於基板110的第二區114，且讀出電路130的一部分位於兩顯示畫素DPX之間。也就是說，讀出電路130的一部分設置於至少一個擬感測畫素區114a-2中。
請參照圖4，在本實施例中，多個顯示畫素DPX排成多個顯示畫素列RDPX，讀出電路130的一部分位於相鄰的兩顯示畫素列RDPX之間，一遮光圖案BM遮蔽其中一顯示畫素列RDPX之顯示畫素DPX的掃描線SL及讀出電路130的一部分；也就是說，在本實施例中，讀出電路130的一部分可設置在遮光圖案BM下。遮光圖案BM例如是黑色矩陣(Black Matrix)之與掃描線SL重疊的一部分，但本發明不以此為限。遮光圖案BM可設置在畫素陣列基板100的基板110上，或設置在前述的對向基板上。
請參照圖1、圖2及圖4，在本實施例中，至少一顯示畫素DPX(例如圖4之下方的三個顯示畫素DPX)位於讀出電路130 的一部分(例如但不限於：圖4的重置電路131)與多條感測扇出走線120(繪於於圖1)之間。
以下配合圖4、圖6、圖7及圖8舉例說明設置於擬感測畫素區114a-2之讀出電路130的一部分可為何。
請參照圖2、圖4及圖5，在一實施例中，讀出電路130之重置電路131的至少一部分可設置於至少一擬感測畫素區114a-2，而位於多個顯示畫素DPX之間。舉例而言，重置電路131可包括至少一重置電晶體T3、用以提供重置訊號RST的一重置訊號線LRST和用以提供參考電壓VSS的一參考電壓線LVSS，其中每一重置電晶體T3的第一端T3a電性連接至參考電壓線LVSS，每一重置電晶體T3的控制端T3c電性連接至重置訊號線LRST，且每一重置電晶體T3的第二端T3b電性連接至對應的一條讀出線LOUT。請參照圖4，讀出電路130的至少一重置電晶體T3、一重置訊號線LRST及一參考電壓線LVSS可設置於其中一個擬感測畫素區114a-2中，但本發明不以此為限。
此外，須說明的是，與單一條讀出線LOUT電性連接之重置電路131的重置電晶體T3的數量不特別限制；與單一條讀出線LOUT電性連接之重置電路131的重置電晶體T3的數量可視重置電晶體T3的充放電能力需求與元件尺寸設計空間而定。
圖6示出本發明一實施例之基板110之第二區114的相鄰兩第二子區114a上的多個顯示畫素DPX及其中一個第二子區114a上的讀出電路130的一部分(例如：主動負載電路132)。圖 5對應圖2的局部r。
請參照圖2、圖5及圖6，在一實施例中，讀出電路130之主動負載電路132的至少一部分可設置至少一擬感測畫素區114a-2，而位於多個顯示畫素DPX之間。舉例而言，在本實施例中，主動負載電路132可包括用以形成電阻的一負載電晶體T4、用以提供偏壓VB的一偏壓訊號線LVB及用以提供參考電壓VSS的一參考電壓線LVSS，其中每一負載電晶體T4的第一端T4a電性連接至參考電壓線LVSS，每一負載電晶體T4的控制端T4c電性連接至偏壓訊號線LVB，且每一負載電晶體T4的第二端T4b電性連接至對應的一條讀出線LOUT。請參照圖6，讀出電路130的一負載電晶體T4、一偏壓訊號線LVB及一參考電壓線LVSS可設置於一擬感測畫素區114a-2中，但本發明不以此為限。
圖7示出本發明一實施例之基板110之第二區114的相鄰兩第二子區114a上的多個顯示畫素DPX及其中一個第二子區114a上的讀出電路130的一部分(例如：多工器133的一部分)。圖7對應圖2的局部r。
請參照圖2、圖5及圖7，在一實施例中，讀出電路130之多工器133的至少一部分可設置至少一擬感測畫素區114a-2，而位於多個顯示畫素DPX之間。多工器133也可稱畫面分區電路(Zone-switch circuit)。請參照圖5及圖7，舉例而言，在本實施例中，多工器133包括n個選擇電晶體組G、用以提供多工訊號ZSW的n條選擇線LZSW及m條匯流線LS，n個選擇電晶體組G 分別電性連接至n條選擇線LZSW，每一選擇電晶體組G之多個選擇電晶體T5的多個控制端T5c電性連接至同一條選擇線LZSW，每一選擇電晶體組G之多個選擇電晶體T5的多個第一端T5a電性連接多條讀出線LOUT，每一選擇電晶體組G之多個選擇電晶體T5的多個第二端T5b電性連接第1~m條匯流線LS，其中n及m為大於或等於2的正整數。
請參照圖5及圖7，在一實施例中，多工器133之一選擇電晶體組G之多個選擇電晶體T5、一條選擇線LZSW、第1條匯流線LS1及第2條匯流線LS2可設置於一擬感測畫素區114a-2，而位於多個顯示畫素DPX之間，但本發明不以此為限。
此外，須說明的是，與單一條讀出線LOUT電性連接之多工器133的選擇電晶體T5的數量不特別限制；與單一條讀出線LOUT電性連接之多工器133的選擇電晶體T5的數量可視選擇電晶體T5的充放電能力需求與元件尺寸設計空間而定。
圖8示出本發明一實施例之基板110之第二區114的相鄰兩第二子區114a上的多個顯示畫素DPX及其中一個第二子區114a上的讀出電路130的一部分(例如：多工器133的一部分)。圖8對應圖2的局部r’。
請參照圖2、圖5及圖8，在一實施例中，讀出電路130之多工器133的至少一部分可設置至少一擬感測畫素區114a-2，而位於多個顯示畫素DPX之間。請參照圖5及圖8，舉例而言，在本實施例中，多工器133的第k-1條匯流線LSk-1、第k條匯流 線LSk及第k+1條匯流線LSk+1可設置於一擬感測畫素區114a-2，而位於多個顯示畫素DPX之間；其中k為大於或等於2的正整數。
值得一提的是，在前述的各實施例中，讀出電路130的一部分設置於基板110的第二區114，且讀出電路130的一部分位於多個顯示畫素DPX之間。亦即，讀出電路130的至少一部分是設置於顯示暨擬感測區(即第二子區114a)的至少一擬感測畫素區114a-2。藉此，讀出電路130的至少一部分不需設置於基板110的第三區116(即，外腳接合(outer lead bonding；OLB)區)，而使基板110之第三區116的寬度W(標示於圖1)得以縮減，進而實現高屏佔比的顯示裝置10。
114:第二區
114a:第二子區
114a-1:顯示畫素區
114a-2:擬感測畫素區
130:讀出電路
131:重置電路
BM:遮光圖案
DL:資料線
DPX:顯示畫素
LVSS:參考電壓線
LOUT:讀出線
LRST:重置訊號線
PE:畫素電極
RDPX:顯示畫素列
r:局部
SL:掃描線
T:電晶體
T3:重置電晶體
Ta、T3a:第一端
Tb、T3b:第二端
Tc、T3c:控制端

Claims (8)

  1. 一種畫素陣列基板，包括：一基板，具有一第一區及一第二區，其中該第二區位於該第一區與該基板的一邊緣之間；多個顯示畫素，設置於該基板的該第一區及該第二區；多個感測畫素，設置於該基板的該第一區，其中每一該感測畫素可包括一感光元件、一第一電晶體、一第二電晶體、一第一參考電壓線、一感測掃描線、一電源供應線和一讀出線，該第一電晶體的一第一端電性連接至該第一參考電壓線，該第一電晶體的一控制端電性連接至該感測掃描線，該第一電晶體的一第二端電性連接至該第二電晶體的一控制端及該感光元件，該第二電晶體的一第一端電性連接至該電源供應線，且該第二電晶體的一第二端電性連接至該讀出線；以及一讀出電路，電性連接至該些感測畫素，其中該讀出電路包括一重置電晶體、一重置訊號線和一第二參考電壓線，其中該每該重置電晶體的一第一端電性連接至該第二參考電壓線，該重置電晶體的一控制端電性連接至該重置訊號線，該重置電晶體的一第二端電性連接至對應之至少一該感測畫素的該讀出線；該讀出電路的一部分設置於該基板的該第二區，該讀出電路的該部分位於該些顯示畫素的兩顯示畫素之間，且該讀出電路的該部分包括該重置電晶體、該重置訊號線和該第二參考電壓線。
  2. 如申請專利範圍第1項所述的畫素陣列基板，其中每一該顯示畫素包括一資料線、一掃描線、一電晶體及一畫素電極，該顯示畫素的該電晶體電性連接至該資料線及該掃描線，該畫素電極電性連接至該顯示畫素的該電晶體，一遮光圖案遮蔽該兩顯示畫素之一者的該掃描線及該讀出電路的該部分。
  3. 如申請專利範圍第1項所述的畫素陣列基板，其中該基板更具有一第三區，該第三區位於該第二區與該基板的該邊緣之間，該畫素陣列基板更包括：多條感測扇出走線，電性連接至該讀出電路，且設置於該基板的該第三區；其中，至少一該顯示畫素位於該讀出電路的該部分與該些感測扇出走線之間。
  4. 如申請專利範圍第1項所述的畫素陣列基板，其中該讀出電路的該部分更包括一負載電晶體、一偏壓訊號線及一第三參考電壓線，其中該負載電晶體的一第一端電性連接至該第三參考電壓線，該負載電晶體的一控制端電性連接至該偏壓訊號線，且該負載電晶體的一第二端電性連接至對應之至少一該感測畫素的該讀出線。
  5. 如申請專利範圍第1項所述的畫素陣列基板，其中該讀出電路的該部分包括一多工器的至少一部分。
  6. 如申請專利範圍第5項所述的畫素陣列基板，更包括電性連接至該些感測畫素的多條讀出線，其中該多工器包括： 多個選擇電晶體，其中該多工器之該些選擇電晶體的多個第一端電性連接至該些讀出線；該讀出電路的該部分包括該多工器的該些選擇電晶體。
  7. 如申請專利範圍第5項所述的畫素陣列基板，更包括電性連接至該些感測畫素的多條讀出線，其中該多工器包括：多個選擇電晶體，其中該多工器之該些選擇電晶體的多個第一端電性連接至該些讀出線；以及多條匯流線，其中該多工器之該些選擇電晶體的多個第二端電性連接至該些匯流線；該讀出電路的該部分包括該些匯流線。
  8. 如申請專利範圍第5項所述的畫素陣列基板，更包括電性連接至該些感測畫素的多條讀出線，其中該多工器包括：多個選擇電晶體，其中該多工器之該些選擇電晶體的多個第一端分別電性連接至該些讀出線；以及多條匯流線，其中該多工器之該些選擇電晶體的多個第二端電性連接至該些匯流線；該讀出電路的該部分包括該些匯流線的至少一者及該多工器的該些選擇電晶體。
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