TWI719848B - Reference voltage holding circuit and sense amplifier circuit having reference voltage holding circuit - Google Patents

Abstract

A reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide for the standby bias current and to maintain the standby bias voltage which drives the sense amplifier reference voltage when reference voltage holding circuit operates under a standby operation and approximates the sense amplifier reference voltage as long as the sense amplifier reference voltage remains enabled.

Description

Reference voltage holding circuit and sense amplifier circuit with reference voltage holding circuit

The present invention relates to a memory circuit, and more particularly to a reference voltage holding circuit and a sense amplifier circuit with the reference voltage holding circuit.

For traditional non-volatile memory volumetric circuits, the sense amplifier is generally an essential part of the reading mechanism, which enables the binary data stored in the storage unit to be read. The sense amplifier is designed to sense a low-power signal representing binary 1 or binary 0 stored in the storage unit from the bit line, and amplify the low-power signal to a recognizable voltage potential, so as to be part of the reading mechanism The circuit can distinguish the binary data stored in the storage unit.

The sense amplifier architecture can have many implementations. An implementation may employ the use of a plurality of main sense amplifier circuits that are not limited to each being connected to the storage unit and a sense amplifier reference circuit that provides a reference voltage for each of the plurality of main sense amplifier circuits. Each of the main sense amplifier circuits is connected to the storage unit. The main sense amplifier circuit may include but is not limited to a comparator and a current-to-voltage converter (IV converter), and the sense amplifier reference circuit may include but is not limited to an IV converter. The output of the sense reference circuit may be connected to the input of each of the comparators of the main sense amplifier circuit. Generally, the comparator compares the voltage signal stored in the storage unit of the main sense amplifier circuit with the reference voltage generated by the sense amplifier reference circuit. If the voltage signal stored in the storage unit is less than the reference voltage, the comparator will generate binary 1; otherwise, the comparator will generate binary 0.

The main sense amplifier circuit and the sense amplifier reference circuit will normally be turned off during the standby mode to save power, but will be turned on during the active read mode (active read mode). When the chip enters the active read mode from the standby mode, there is a time limit for the reference voltage to reach the voltage target. If the voltage target is not reached within the time limit, the main sense amplifier circuit may operate incorrectly. However, there is a trend to place more and more main sense amplifier circuits in the area of the integrated circuit. Because from the perspective of the sense amplifier reference circuit, increasing the number of main sense amplifier circuits connected to the sense amplifier reference circuit may result in a higher total capacitive load, so as the number of main sense amplifier circuits increases and drives the memory The external clock of the bulk wafer becomes faster, and this time limit may become increasingly difficult to reach.

An alternative solution to the above-mentioned challenges is to divide the main sense amplifier circuit into multiple groups, where a smaller number of main sense amplifier circuits are connected to the reference sense amplifier circuit. However, because the entire system may require higher current consumption and more sense amplifier reference circuits, this solution may not be satisfactory. Therefore, other solutions can still be proposed to meet the above-mentioned challenges.

In view of this, the present invention provides a reference voltage holding circuit and a sense amplifier circuit having the reference voltage holding circuit.

In an embodiment of the present invention, a reference voltage holding circuit is provided, which is used to maintain a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes, but is not limited to: a reference voltage generating circuit, configured To provide a bias reference voltage; a current generating circuit, electrically coupled to the reference voltage generating circuit, and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit, electrically coupled to The current generating circuit (current mirror circuit) is configured to provide a standby bias current and maintain a standby bias voltage. When the reference voltage holding circuit operates in a standby operation, the standby bias voltage drives the sense amplifier reference voltage. As long as the reference voltage of the enabling sense amplifier is maintained, the standby bias voltage will approach the reference voltage of the sense amplifier.

In an embodiment of the present invention, a sense amplifier circuit is provided. The sense amplifier circuit includes, but is not limited to: a sense amplifier reference circuit, configured to generate a sense amplifier reference voltage; a main sense amplifier circuit, configured to receive the sense amplifier reference voltage, and will store the storage unit of the sense amplifier circuit. The voltage signal is compared with the sense amplifier reference voltage; and a reference voltage holding circuit configured to maintain the sense amplifier reference voltage when the sense amplifier is operating in standby operation, wherein the reference voltage holding circuit includes: a reference voltage generating circuit configured to Provide a bias reference voltage; a current generation circuit (current mirror circuit), electrically coupled to the reference voltage generation circuit, and configured to receive the bias reference voltage to output the standby bias voltage and the standby bias current; and a voltage pull-up circuit, It is electrically coupled to the current generating circuit (current mirror circuit), and is configured to provide a standby bias current and pull up the standby bias voltage. When the reference voltage holding circuit operates in a standby operation, the standby bias voltage drives the sense amplifier reference voltage. As long as the reference voltage of the enabling sense amplifier is maintained, the standby bias voltage will approach the reference voltage of the sense amplifier.

Based on the above, the present invention is suitable for use as part of the reading mechanism of a non-volatile memory storage device, and the present invention can achieve at least one of the following advantages, including lower hardware cost and lower standby current The burden and the dissociation between the reading speed and the number of sense amplifiers.

In order to make the above-mentioned features and advantages of the present disclosure more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Reference will now be made in detail to the current embodiment of the present invention, an example of which is shown in the accompanying drawings.

As previously described, because future non-volatile memory storage devices require higher and higher speeds and more data processing capacity, as the number of sense amplifiers increases, the time limit requirements become more difficult to meet. In addition, as the number of sense amplifiers increases, the total capacitance of the sense amplifiers also increases, which will result in a slower rate of increase of the sense amplifier reference voltage. The slowing down of the rate of increase of the sense amplifier reference voltage can cause dysfunction of the initial read operation. In order to meet the challenge of having an increased number of sense amplifiers and at the same time alleviate the negative consequences of this increase, the present invention proposes to adjust the sense amplifier circuit by adding a reference voltage holding circuit. When operating in the standby mode, the reference voltage holding circuit holds the sense amplifier reference voltage, and during the standby mode, both the sense amplifier reference circuit and the main sense amplifier circuit are turned off to avoid unnecessary power consumption. In the present invention, when the non-volatile memory storage device undergoes a transition from a standby mode to an active read mode, the reference voltage holding circuit maintains the voltage potential of the sense amplifier reference voltage to avoid a slow rise in the sense amplifier reference voltage. High rate.

FIG. 1 shows a conceptual diagram of a reference voltage holding circuit 100 configured to maintain a sense amplifier reference voltage provided by a sense amplifier reference circuit (not shown in FIG. 1) (it is not shown as a sense amplifier reference circuit) Connect to the reference voltage holding circuit 100, but outside the reference voltage holding circuit 100). The reference voltage holding circuit 100 will include but is not limited to: a reference voltage generating circuit 101 configured to provide a bias reference voltage; a current generating circuit 102 electrically coupled to the reference voltage generating circuit 101 and configured to receive a bias reference voltage to output Standby bias voltage and standby bias current; and a voltage pull-up circuit 103, electrically coupled to the current generating circuit 102, and configured to provide standby bias current and pull up the standby bias voltage, when the reference voltage holding circuit 100 is in standby During operation, the standby bias voltage drives the sense amplifier reference voltage, and as long as the sense amplifier reference circuit is enabled, the standby bias voltage will approach the sense amplifier reference voltage. When the sense amplifier reference circuit is turned off during the standby operation, the sense amplifier reference voltage is maintained by the reference voltage holding circuit 100.

According to an embodiment, the reference voltage generating circuit 101 may include a bandgap voltage reference circuit that generates a bias reference voltage, the bandgap voltage reference circuit being activated when the reference voltage holding circuit 100 operates in both standby operation and read operation . According to an embodiment, the current generating circuit 102 may be a current mirror circuit including a plurality of transistors. The current mirror circuit is configured to receive a bias reference voltage and convert the bias reference voltage into a standby bias current. The standby bias current is set It is N times smaller than the reference current of the reference cell of the sense amplifier reference circuit. Alternatively, the current generating circuit 102 may also be a resistor that converts the bias reference voltage into a standby bias current, and the standby bias current is set to be N times smaller than the reference current of the reference cell of the sense amplifier reference circuit.

According to an embodiment, the voltage pull-up circuit 103 may include a first P-type transistor. The first P-type transistor is set to have a wider width than the corresponding P-type transistor of the sense amplifier reference circuit. The aspect ratio that is N times smaller than the aspect ratio pulls up the standby bias voltage. The number N may be set to meet the current consumption target of the reference voltage holding circuit (for example, the reference voltage holding circuit 302) during the standby mode. According to an embodiment, the voltage pull-up circuit 103 may further include a second P-type transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the drain-to-drain voltage (vdd), and the second terminal is connected to the drain-to-drain voltage (vdd). The terminal is connected to the first P-type transistor, and the third terminal is configured to receive a deep power down signal. As long as the reference voltage holding circuit is not deeply powered down, the deep power down signal will remain low to maintain the second P The type transistor starts. If the deep power down signal is pulled high to turn off the second P-type transistor, the voltage pull-up circuit 103 will stop supplying the standby bias current during the deep power down mode.

According to an embodiment, the switch circuit 104 will be configured to couple the standby bias voltage to the sense amplifier reference voltage during the standby mode, but to decouple the standby bias voltage from the sense amplifier reference voltage during the read operation During the read operation, the sense amplifier reference voltage is driven by the sense amplifier reference circuit and is not driven by the reference voltage holding circuit.

Please refer to Figure 2 and Figure 3. The sense amplifier circuits 200, 300 will include, but are not limited to: sense amplifier reference circuits 201, 301, configured to generate a sense amplifier reference voltage sainr; main sense amplifier circuits 203, 303, configured to convert from the main sense amplifier The cell current 322 of the storage unit of the circuits 203 and 303 receives the sense amplifier reference voltage sainr and generates a voltage signal sain, and compares the voltage signal sain voltage with the sense amplifier reference voltage sainr; and the reference voltage holding circuit 302 is configured to The sense amplifier reference voltage sainr is maintained when the sense amplifiers 200, 300 are operating in standby operation.

The reference voltage holding circuits 202 and 302 will include but are not limited to: a reference voltage generating circuit 211 configured to provide a bias reference voltage nbias; a current generating circuit 212 electrically connected to the reference voltage generating circuit 211 and configured to receive a bias reference The voltage nbias outputs the standby bias voltage sainr_stby and the standby bias current Ibias3; and the voltage pull-up circuit 213, which is electrically coupled to the current generation circuit 212, and is configured to provide the standby bias current Ibias3 and pull up the standby bias voltage sainr_stby, When the reference voltage holding circuits 202 and 302 operate in standby operation, the standby bias voltage sainr_stby drives the sense amplifier reference voltage sainr, and as long as the sense amplifier reference circuits 201 and 301 are enabled, the standby bias voltage sainr_stby approaches The sense amplifier reference voltage sainr.

It is worth noting that the sense amplifier reference circuits 201, 301 and the main sense amplifier circuits 203, 303 are all turned off during the standby mode to reduce power consumption. During the standby mode, the sense amplifier reference circuits 201 and 301 can be floating, and the sense amplifier reference voltage sainr is determined by the competition between the first Ioff current 316 and the second Ioff current 320. For example, if the first Ioff current 316 is higher than the second Ioff current 320, the sense amplifier reference voltage sainr can approach vdd. Otherwise, if the first Ioff current 316 is less than the second Ioff current 320, the sense amplifier reference voltage sainr can approach ground. When the sense amplifier reference circuits 201, 301 and the main sense amplifier circuits 203, 303 exit the standby mode and enter the active read mode, because any one of the reference voltage holding circuits 202, 302 maintains the sense amplifier reference voltage sainr, So the sense amplifier reference voltage sainr hardly needs any time to charge or discharge. Therefore, even if the sense amplifier reference circuit 201, 301 must provide the sense amplifier reference voltage sainr to many main sense amplifier circuits (for example, the main sense amplifier circuit 203, 303), the sense amplifier reference voltage sainr will need to be significantly less It is not necessary to slow down the clock frequency to perform read operations or help-seeking strategies, such as adding additional dummy clocks before the first data output appears.

According to an embodiment, the reference voltage generating circuit 211 may be a bandgap voltage reference circuit 311 that is activated when the reference voltage holding circuits 202 and 302 are both in the standby operation and the read operation.

According to an embodiment, the current generating circuit 212 may include a first transistor 312 that receives the bias reference voltage nbias to generate the first bias current Ibias1, and generates the second bias current Ibias2 by mirroring the first bias current Ibias1. The second transistor 313 and the third transistor 314 mirroring the second bias current Ibias2 to generate the standby bias current Ibias3. The standby bias current Ibias3 is set to be higher than the reference cell RC of the sense amplifier reference circuits 201 and 301. The reference current Iref (ie, the second Ioff current 320) is N times smaller.

According to an embodiment, the voltage pull-up circuit 213 may include a first P-type transistor 315. The first P-type transistor 315 is set to have a corresponding value than the sense amplifier reference circuit 301. The width-to-length ratio of the P-type transistor PT is N times smaller to pull up the standby bias voltage sainr_stby. N may be set to meet the current consumption target of the reference voltage holding circuit 302 during the standby mode. The voltage pull-up circuit 213 may further include a second P-type transistor 317 having a gate terminal, a drain terminal, and a source terminal. The source terminal can be connected to vdd, the drain terminal can be connected to the first P-type transistor 315, and the gate terminal can be configured to receive the deep power-down signal dpdown, as long as the reference voltage holding circuit 302 is not in deep power-down (or not in deep power-down mode) Next operation), the deep power-down signal remains low to keep the first P-type transistor 315 and the second P-type transistor 317 activated. However, when operating in the deep power-down mode, the deep power-down signal dpdown is pulled high to turn off the second P-type transistor 317 to disconnect the standby bias current Ibias3.

According to an embodiment, the reference voltage holding circuit 202 may further include a switch circuit 214 configured to decompose the standby bias voltage sainr_stby and the sense amplifier reference voltage sainr during a read operation (ie, active read mode). During the read operation, the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuits 201 and 301 and is not driven by the reference voltage holding circuits 202 and 302. However, during the standby operation (ie, standby mode), the switch circuit 214 is activated to enable the sense amplifier reference voltage sainr to be coupled to the standby bias voltage sainr_stby, so that the sense amplifier reference voltage sainr is maintained by the standby bias voltage sainr_stby.

According to an embodiment, the sense amplifier reference circuits 201 and 301 and the main sense amplifier circuits 203 and 303 have multiple terminals which receive the sense amplifier enable signal saeb signal. During the read operation, the sense amplifier enable signal saeb is pulled down. During the read operation, the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuits 201 and 301 and not driven by the reference voltage holding circuits 202 and 302. , So the standby bias voltage sainr_stby is decoupled from the sense amplifier reference voltage sainr. According to an embodiment, the sense amplifier reference circuits 201, 301 can be connected to multiple main sense amplifier circuits (for example, the main sense amplifier circuit 303), resulting in the sense amplifier reference voltage sainr of the sense amplifier reference circuits 201, 301 appearing Large capacitance value.

The principle of operation of FIG. 3 is further elucidated as follows. For the bandgap voltage reference circuit 311, a low-power consumption bandgap reference voltage generation (BGR) circuit can be used, and it can be used in both standby operation (ie standby mode) and read operation (ie active read mode). The low power consumption bandgap reference voltage generating circuit will always be enabled. The bandgap voltage reference circuit 311 will provide a bias reference voltage nbias, and the bias reference voltage nbias is used to generate the first bias current Ibias1 by the first transistor 312. The first bias current Ibias1 is then mirrored by the second transistor 313 into the second bias current Ibias2 current, which is then mirrored by the third transistor 314 into the standby bias current Ibias3.

The standby bias current Ibias3 may be set to be approximately N times smaller than the reference current Iref, and as an example, N may be 100. In other words, Ibias3=Ibias1=Ibias2=Iref/100, and about 1/100 of the reference current Iref is generated to bias the standby bias voltage sainr_stby. In addition, it has been determined that when the sense amplifier reference circuit 301 is enabled, the length of the first P-type transistor 315 can be N times longer than the corresponding P-type transistor PT in the sense amplifier reference circuit 301 to make the standby bias voltage sainr_stby is very similar to the sense amplifier reference voltage sainr. However, it should be noted that 100 is only an exemplary number, and may be adjusted based on design changes or based on changes in requirements for the sense amplifier circuit 300.

During the standby mode and the active read mode, the standby bias voltage sainr_stby is always activated. However, when operating in the standby mode, the standby bias voltage sainr_stby drives the sense amplifier reference voltage sainr, which may have a large capacitive load, in order to transition from the standby mode to the active read mode The boost operation is accelerated by maintaining the sense amplifier reference voltage sainr. Mainly speaking, when the sense amplifier reference circuit 301 and the main sense amplifier circuit are both turned off during the standby mode, the SAINR holder (ie, reference voltage holding circuits 202, 302) is used to maintain the node "sense amplifier reference voltage sainr" .

When operating in the active read mode, because the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuit 301, the standby bias voltage sainr_stby is decoupled from the sense amplifier reference voltage sainr. This decoupling can be achieved by a switch circuit 214, which can include a transmission gate 318 and an inverter 319. The P-type gate terminal of the transmission gate 318 can receive the idle enable signal idleb, and when it is confirmed that the sense amplifier enable signal saeb signal is low, the idle enable signal idleb is pulled high. By setting the idle enable signal idleb to high, the transmission gate 318 will be closed to decouple the sense amplifier reference voltage sainr from the standby bias voltage sainr_stby. When operating in the standby mode, it is confirmed that the idle enable signal idleb is low.

When operating in the deep power-down mode, it is confirmed that the deep power-down signal dpdown is high to turn off the second P-type transistor 317, which in turn will cause the standby bias current Ibias3 to be disconnected. During the deep power-down mode, the sense amplifier reference circuit 301, the reference voltage holding circuit 302, and the main sense amplifier circuit 303 are turned off. When not operating in the deep power down mode, confirm that the deep power down signal dpdown is low.

In summary, the present invention is suitable for use as part of the reading mechanism of a non-volatile memory storage device, and the present invention can achieve at least one of the following advantages, including lower hardware cost and lower The standby current burden and the dissociation between the reading speed and the number of sense amplifiers. The hardware cost reduction can be achieved by adding a reference voltage holding circuit 302 to the sense amplifier reference circuit (such as the sense amplifier reference circuit 301) and one or more main sense amplifier circuits (such as the main sense amplifier). In circuit 303), it is not necessary to divide the main sense amplifier circuit (for example, the main sense amplifier circuit 303) into multiple groups to reduce the main sense to be served by the sense amplifier reference circuit (for example, the sense amplifier reference circuit 301) The number of amplifier circuits (for example, the main sense amplifier circuit 303), and it is not necessary to add additional dummy clocks before the first data output appears.

100: electronic device 100, 202, 302: reference voltage holding circuit; 101, 211: reference voltage generating circuit; 102, 212: current generating circuit; 103, 213: voltage pull-up circuit; 104, 214: switch circuit; 200, 300: sense amplifier circuit; 201, 301: sense amplifier reference circuit; 203, 303: main sense amplifier circuit; 311: Bandgap voltage reference circuit; 312: The first transistor; 313: second transistor; 314: the third transistor; 315: The first P-type transistor; 316: the first Ioff current; 317: The second P-type transistor; 318: Transmission gate; 319: inverter; 320: the second Ioff current; 322: Unit current. sainr: sense amplifier reference voltage sain: voltage signal

FIG. 1 is a schematic diagram of a reference voltage holding circuit in an embodiment of the disclosure. FIG. 2 is a schematic diagram of a sense amplifier circuit in an embodiment of the disclosure. FIG. 3 is a schematic diagram of a sense amplifier with a reference voltage holding circuit in an embodiment of the disclosure.

100: Reference voltage holding circuit

101: Reference voltage generating circuit

102: current generating circuit

103: Voltage pull-up circuit

104: switch circuit

Claims (12)

A reference voltage holding circuit is used to maintain a sense amplifier reference voltage provided by a sense amplifier reference circuit. The reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit, electrical Coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current generating circuit and configured to The standby bias current is provided and the standby bias voltage is maintained. When the reference voltage holding circuit is operated in standby operation, the standby bias voltage drives the sense amplifier reference voltage, and as long as it remains enabled In the sense amplifier reference circuit, the standby bias voltage approaches the sense amplifier reference voltage. The reference voltage holding circuit according to claim 1, wherein the current generating circuit includes: a first transistor that receives the bias reference voltage to generate a first bias current; and a second transistor that mirrors the A first bias current to generate a second bias current; and a third transistor that mirrors the second bias current to generate a third bias current, the third bias current is set to be higher than the sensing The reference current of the reference unit of the amplifier reference circuit is N times smaller. The reference voltage holding circuit according to claim 2, wherein the voltage pull-up circuit includes: The first P-type transistor is pulled up by setting the first P-type transistor to have an aspect ratio that is N times smaller than that of the corresponding P-type transistor of the sense amplifier reference circuit. Standby bias voltage. The reference voltage holding circuit according to claim 3, wherein N is a number set to meet the current consumption target of the reference voltage holding circuit during the standby mode. The reference voltage holding circuit according to claim 1, wherein the reference voltage generating circuit is a band gap voltage reference circuit, and the band gap voltage reference circuit is activated when the reference voltage holding circuit is in the standby operation, and It is also activated when the reference voltage holding circuit is performing a read operation. The reference voltage holding circuit according to claim 3, wherein the voltage pull-up circuit further includes a second P-type transistor, and the second P-type transistor includes a first terminal, a second terminal, and a third terminal, wherein The first terminal is connected to the source-to-source voltage (vdd), the second terminal is connected to the first P-type transistor, and the third terminal is configured to receive a deep power-down signal, as long as the reference voltage holding circuit If there is no deep power-down, the deep power-down signal remains low. The reference voltage holding circuit according to claim 6, wherein the deep power-down signal is pulled high to turn off the second P-type transistor, thereby turning off the third bias current. The reference voltage holding circuit according to claim 1, further comprising: a switch circuit configured to decouple the standby bias voltage from the sense amplifier reference voltage during the read operation, and during the read operation , The sensing put The amplifier reference voltage is driven by the sense amplifier reference circuit and is not driven by the reference voltage holding circuit. The reference voltage holding circuit according to claim 1, wherein the current generating circuit includes a resistor configured to generate the bias reference voltage to output the standby bias voltage and the standby bias current . A sense amplifier circuit includes: a sense amplifier reference circuit, configured to generate a sense amplifier reference voltage; a main sense amplifier circuit, configured to receive the sense amplifier reference voltage, and transfer from the main sense amplifier circuit Comparing the voltage signal of the storage unit with the reference voltage of the sense amplifier; and a reference voltage holding circuit configured to maintain the reference voltage of the sense amplifier when the sense amplifier is operating in a standby operation, wherein the reference The voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and Standby bias current; and a voltage pull-up circuit electrically coupled to the current generating circuit and configured to provide the standby bias current and pull up the standby bias voltage, when the reference voltage holding circuit is in the standby During operation, the standby bias voltage drives the sense amplifier reference voltage, and as long as the sense amplifier reference circuit remains enabled, the standby bias voltage approaches the sense amplifier reference voltage. The sense amplifier circuit according to claim 10, wherein the sense amplifier reference circuit and the main sense amplifier circuit receive a sense amplifier enable signal that is pulled down in a read operation, and During this period, the standby bias voltage is decoupled from the sense amplifier reference voltage, and the sense amplifier reference voltage is driven by the sense amplifier reference circuit and not by the reference voltage holding circuit. The sense amplifier circuit according to claim 10, wherein the sense amplifier reference circuit is connected to a plurality of main sense amplifier circuits, and the sense amplifier reference voltage of the sense amplifier reference circuit has a large capacitance value .

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