CN1928766A - Reference voltage generating circuit, a semiconductor integrated circuit and a semiconductor integrated circuit apparatus - Google Patents
Reference voltage generating circuit, a semiconductor integrated circuit and a semiconductor integrated circuit apparatus Download PDFInfo
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- CN1928766A CN1928766A CN 200610151372 CN200610151372A CN1928766A CN 1928766 A CN1928766 A CN 1928766A CN 200610151372 CN200610151372 CN 200610151372 CN 200610151372 A CN200610151372 A CN 200610151372A CN 1928766 A CN1928766 A CN 1928766A
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Abstract
The present invention provides a band gap type reference voltage generating circuit and a semiconductor integrated circuit having the same, capable of generating a reference voltage of about 1.2V or less whose temperature dependency is low, and realizing reduced offset voltage dependency of a differential amplifier. A band gap part has: a first resistor and a first bipolar transistor; a second resistor, a second bipolar transistor, and a third resistor; and a differential amplifier. The output part has a third bipolar transistor, a fourth resistor, a current mirror circuit, and a fifth resistor and a diode.
Description
Cross reference to related application
Therefore the right of priority that the application requires to be filed in the Japanese patent application No. 2006-168393 on June 19th, 2006 and is filed in the Japanese patent application No. 2005-258870 on September 7th, 2005 is combined in their content in the application by reference.
Technical field
The present invention relates to be used to produce the technology of the reference voltage of SIC (semiconductor integrated circuit), and more specifically, relate to the band gap type generating circuit from reference voltage of under low suppling voltage, operating.The present invention relates to be applicable to effectively the technology of the generating circuit from reference voltage that produces the required reference voltage of A/D converter for example or D/A converter.
Background technology
Because reference voltage is that the conversion operations in A/D converter or the D/A converter is necessary, for the SIC (semiconductor integrated circuit) that wherein has A/D converter or D/A converter provides generating circuit from reference voltage.It is known using the generating circuit from reference voltage of the various circuit forms of voltage stabilizing diode, differentiating amplifier etc.In these circuit, the circuit that is called as bandgap reference circuit can produce the stable reference voltage with low suppling voltage correlativity and low temperature correlativity.Therefore, bandgap reference circuit is generally used for such as the mimic channel of A/D converter, D/A converter etc. and comprises in the circuit that obtains the required analog-and digital-element of high precision.
On the other hand, in recent years, in SIC (semiconductor integrated circuit),, reducing supply voltage in order to obtain lower power consumption and higher processing speed.Therefore, just developing the generating circuit from reference voltage in the SIC (semiconductor integrated circuit) of being provided at that can produce low reference voltage.
As about producing the example of the present invention that hangs down the generating circuit from reference voltage of reference voltage, in the Jap.P. spy number of opening 2004-206633 a kind of generating circuit from reference voltage is disclosed.Fig. 9 shows the example of disclosed generating circuit from reference voltage among the Jap.P. spy number of the opening 2004-206633.In this generating circuit from reference voltage, the output voltage of differentiating amplifier AMP0 (Vc) is applied to the gate terminal of MOS (metal-oxide semiconductor (MOS)) transistor MT1, MT2 and MT0.Therefore, if these transistorized sizes are identical, then flow through the electric current I 0 of equal number.
In this generating circuit from reference voltage, the drain voltage of transistor MT1 and MT2 is applied to a pair of differential input terminal of differentiating amplifier AMP0.Feedback is carried out in imaginary short action by differentiating amplifier AMP0, thereby the difference between input Vc1 and the Vc2 becomes 0.Therefore, in resistance R 1, produce the voltage that the difference between base-emitter voltage VBE2 with the base-emitter voltage VBE1 of bipolar transistor BT1 and bipolar transistor BT2 equates.Determine the drain current I0 of transistor MT1 and MT2, so that keep this state.
By the transistor MT0 copy current I0 that cooperates with transistor MT1 and MT2 and form current mirror, and it is delivered to comprises resistance R a, be connected with diode transistor BT3 and with the output circuit of resistance R a and transistor BT3 parallel resistor Rb, thereby can obtain low voltage output.Because the base-emitter voltage VBE0 of transistor BT3 has negative temperature characteristic, thereby base-emitter voltage VBE0 descends when temperature raises, compensate corresponding to the output voltage V bgout that the voltage of the terminal by will striding resistance R a is added to the voltage that obtains on the VBE0 with 0 pair of the electric current I that in resistance R a and Rb, flows with positive temperature characterisitic, and it is set to not have the desirable magnitude of voltage of temperature dependency.
Summary of the invention
It is very little so that can be left in the basket that the operation of the generating circuit from reference voltage in the application of submitting to is described to the skew of differentiating amplifier AMP0.Yet obtain under the situation of high precision reference voltage attempting, the offset voltage between the input terminal of differentiating amplifier AMP0 can not be left in the basket.When being Vos, the generating circuit from reference voltage operation in the application of submission concerns Vc2-Vc1=Vos so that satisfy when the input off-set voltage of differentiating amplifier AMP0 (below abbreviate skew as).Therefore, the quantity that the electric current that flows in the resistance R 1 is pressed Vos changes, and causes the variation in the output.
When thermal voltage is expressed as VT=KT/q (T: absolute temperature, K: Boltzmann system constant, q: the quantity of electric charge), and when Is represents the opposite direction saturation current of bipolar transistor, under situation about flowing between the base stage of transistor BT1 and BT2 and emitter, VBE1 and VBE2 are expressed as follows at forward current.
VBE1＝VT*In(I0/Is)
VBE2＝VT*In(I0/(n*Is))
In this expression formula, " * " represents multiplication sign, and "/" expression division sign.When considering that differentiating amplifier has skew, Vc2-Vc1=Vos.Because Vc1=VBE1, and Vc2=VBE2+I0*R1 bring them into these equation, and are organized as follows.
I0＝VT*R1*In(n)+Vos/R1……(1)
For output voltage V bgout, satisfy equation Vbgout/Rb+ (Vbgout-VBE3)/Ra=I0.Be rearranged as this equation as follows for output voltage V bgout.
Vbgout＝Ra*Rb/(Ra+Rb)*I0+Rb/(Ra+Rb)*VBE3
When the electric current I 0 in the alternative equation (1), obtain following formula.
Vbgout＝Ra*Rb/(Ra+Rb)*(VT*R1*In(n)+Vos/R1)+Rb/(Ra+Rb)*VBE3
According to the above, be expressed as follows for the change scope of the Vbgout of Vos.
DVbgout/dVos＝Ra*Rb/((Ra+Rb)*R1)……(2)
Because the change of this quantity takes place in the skew of differentiating amplifier in output.
An object of the present invention is to provide a kind of and the band gap type generating circuit from reference voltage of offset voltage correlativity that can reduce differentiating amplifier and SIC (semiconductor integrated circuit) with this band gap type generating circuit from reference voltage compensation that can produce about 1.2V or lower reference voltage through temperature compensation and supply voltage.
From the description of instructions and accompanying drawing, will understand above and other objects of the present invention and new feature more.
Representational those the general introduction of invention disclosed among the application will be described below.
Generating circuit from reference voltage according to the present invention comprises band gap part and output.Band gap partly has: be connected on first resistance and first bipolar transistor between the supply voltage terminal; Be connected on second resistance between the supply voltage terminal, second bipolar transistor and the 3rd resistance; And the differentiating amplifier that receives the voltage that produces by first and second resistance.The output of differentiating amplifier is applied to described two transistorized base stages.Described output has the bipolar transistor of the base stage of the output that has been applied in differentiating amplifier, with the resistance of this transistor series, be used to be delivered in the current mirroring circuit of the electric current that flows in this transistor and the current conversion that is used for transmitting is the resistance and the diode of voltage.
Use device recited above, negative feedback is carried out in the input that outputs to of the differentiating amplifier from the band gap part, thereby the output of differentiating amplifier becomes the base-emitter voltage VBE that equals this bipolar transistor.Even there is offset voltage in differentiating amplifier, and the output of differentiating amplifier changes, and also mainly is that the voltage that produces in first resistance changes.Therefore, according to long-pending (magnification) of the resistance of the gm (conductivity) of differentiating amplifier and first resistance, the output of differentiating amplifier has been reduced with respect to the change of offset voltage.
Is electric current by described bipolar transistor, resistance and current mirror with voltage transitions, and further, is voltage by the output circuit with resistance and diode with current conversion, and this voltage has promptly obtained to have reduced the voltage of the variation that caused by offset voltage.The temperature characterisitic of the voltage that the terminal place of resistance in being connected on output and diode produces is opposite each other, thereby cancels each other out according to the voltage change of temperature change, and has obtained to have the output voltage of low temperature dependency.In addition, current mirror has such characteristic, even supply voltage fluctuates, electric current can not change yet.Therefore, be voltage by the current conversion that will produce again by current mirror by the output circuit that constitutes with described resistance and diode, obtained to have the output voltage of low supply voltage correlativity.
Preferably, it is in parallel to be used for the resistance and the diode of current-voltage conversion in resistance and the output.More preferably, a start-up circuit is provided, it has when the operation of generating circuit from reference voltage begins from/the first or second resistance reception/delivered current in the band gap part, and after the output of differentiating amplifier is elevated to predetermined voltage, interrupt the function of received current or delivered current.With this configuration, avoided generating circuit from reference voltage to be stable at not being a kind of situation of state of the state of the desirable output voltage of output, and can obtain output voltage accurately.
With the effect of concise and to the point description as described below by a representational acquisition of invention disclosed in the application of the present invention.
According to the present invention, can realize to produce through about 1.2V of temperature compensation and supply voltage compensation or lower reference voltage, and realize the generating circuit from reference voltage of the band gap type of the differentiating amplifier offset voltage correlativity that reduces.
Description of drawings
Fig. 1 shows the circuit diagram according to first embodiment of band gap type generating circuit from reference voltage of the present invention.
Fig. 2 shows the circuit diagram to the modification of the band gap type generating circuit from reference voltage of first embodiment.
Fig. 3 shows the performance plot of offset voltage correlativity of output voltage V bgout of the band gap type generating circuit from reference voltage of first embodiment.
Fig. 4 shows before this performance plot of offset voltage correlativity of output voltage of the generating circuit from reference voltage of an invention in the application.
Fig. 5 shows the circuit diagram according to second embodiment of band gap type generating circuit from reference voltage of the present invention.
Fig. 6 shows the circuit diagram according to the modification of the band gap type generating circuit from reference voltage of second embodiment.
Fig. 7 shows the circuit diagram according to the 3rd embodiment of band gap type generating circuit from reference voltage of the present invention.
Fig. 8 shows the circuit diagram to the modification of the band gap type generating circuit from reference voltage of the 3rd embodiment.
Fig. 9 shows the circuit diagram according to the configuration example of the generating circuit from reference voltage of an invention in the application before this.
Figure 10 A and 10B show respectively as the layout of the example of the npn bipolar transistor of the assembly of the generating circuit from reference voltage of the embodiment of Fig. 1 and sectional view.
Figure 11 A and 11B show layout and the sectional view as the example of the P channel MOS transistor of the assembly of the generating circuit from reference voltage of the embodiment of Fig. 1 respectively.
Figure 12 A and 12B show layout and the sectional view as the transistorized example of N-channel MOS of the assembly of the generating circuit from reference voltage of the embodiment of Fig. 1 respectively.
Figure 13 A and 13B show respectively as the layout of the example of the resistive element of the assembly of the generating circuit from reference voltage of the embodiment of Fig. 1 and sectional view.
Figure 14 A and 14B show layout and the sectional view as the example of the PNP bipolar transistor of the assembly of the generating circuit from reference voltage of the embodiment of Fig. 5 respectively.
Embodiment
Fig. 1 shows first embodiment according to generating circuit from reference voltage of the present invention.
Generating circuit from reference voltage shown in this figure has to be connected on and has been applied in such as the power supply terminal of the supply voltage Vdd of 1.5V and has been applied in such as resistance R 1 and npn bipolar transistor BT1 between the power supply terminal of the supply voltage Vss of earth potential (0V).This generating circuit from reference voltage also has the resistance R 2 that is connected between power supply terminal, npn bipolar transistor BT2 and resistance R 3.Resistance R 1 has identical resistance value R0 with R2.Transistor BT1 and BT2 are provided with like this, make the size of emitter have 1: the ratio of n.For example select the value of " 10 " conduct " n ".Replacement emitter size is set to 1: n, and can be with n parallel connection of the transistor with the identical size of transistor BT1 as transistor BT2.
In addition, differentiating amplifier AMP1 is provided, wherein the current potential Vc1 with the connected node N1 place between resistance R 1 and transistor BT1 is applied to non-inverting input, and the current potential Vc2 at the connected node N2 place between resistance R 2 and transistor BT2 is applied to reverse input end.The output of differentiating amplifier AMP1 is applied to the base terminal of transistor BT1 and BT2, and electric current I 1 and I0 be passed to transistor BT1 and BT2, thereby to become with Vc2 be identical (Vc1=Vc2) to the current potential Vc1 at connected node N1 and N2 place.By resistance R 1, R2 and R3, transistor BT1 and BT2 and differentiating amplifier AMP1 are formed for the band gap part 11 according to the base-emitter voltage VBE1 output voltage of bipolar transistor BT1.With this configuration, electric current I 0 is in direct ratio with absolute temperature.
In order to transmit the electric current identical, the npn bipolar transistor BT3 and the resistance R 4 that have with the identical size of transistor BT2 are provided with the electric current I 0 of transistor BT2.Between the collector side and supply voltage Vdd of transistor BT3, provide P channel type MOS transistor (isolated-gate field effect transistor (IGFET)) MT1 that forms current mirror.Resistance R 4 has the reference value R1 identical with resistance R 3.Grid and drain electrode MOS transistor MT1 connected to one another play electric current-voltage conversion device.Voltage by will conversion is applied to the gate terminal as another P channel type MOS transistor MT2 of the assembly of current mirror, and the electric current according to described size (grid width ratio) between MOS transistor MT1 and the MT2 is passed to MOS transistor MT2.
In this embodiment, by making MOS transistor MT1 and MT2 have identical size, the electric current identical with the electric current of MOS transistor MT1 is passed to MOS transistor MT2.Resistance R 5 and the so-called bipolar transistor BT4-that is connected with diode wherein base stage and collector are connected to each other-are cascaded with MOS transistor MT2.Provide resistance R 6 concurrently with resistance R 5 and bipolar transistor BT3.By transistor BT3, resistance R 4, current mirror (MT1 and MT2), resistance R 5 constitutes output 12 with the transistor BT4 that is connected with diode.
In output 12, by with the directly proportional electric current I 0 of the voltage of absolute temperature and resistance R 5 and R6 (promptly, Ia and Ib) negative temperature characteristic of base-emitter voltage VBE0 of offseting transistor BT4, obtained to have the output voltage V bgout of low temperature dependency.Again produce the electric current of transistor BT3 with the current mirror that constitutes by MOS transistor MT1 and MT2, and with its transistor BT4 that is delivered to resistance in series R5 and is connected with diode.Even, obtained to have the output voltage V bgout of low supply voltage correlativity because this electric current does not change yet when the supply voltage Vdd of current mirror fluctuation.
Resistance R 5 can reciprocally be connected with the transistor BT4 that is connected with diode.Replace MOS transistor MT1 and MT2, can use the PNP bipolar transistor to constitute current mirror.Constitute differentiating amplifier AMP1 by MOS transistor.Use has the differentiating amplifier level that a pair of differential transistor that connected jointly by source class constitutes, be connected to the constant current source of this public source class, circuit with the passive element that is connected to differential transistor drain side, or the source class earthing type, the output that source class is followed type etc. is connected to the circuit of differentiating amplifier level.
In the generating circuit from reference voltage in Fig. 1, when not having offset voltage among the differentiating amplifier AMP1, electric current flows through transistor BT1 and BT2, thereby Vc1 equals Vc2.On the other hand, when among the differentiating amplifier AMP1 offset voltage being arranged, output Vc changes.Substantially, Vc1 changes according to statement Δ Vc1/ Δ Vc=gm*R0, and Δ Vc2/ Δ Vc is close to and equals R0/R1, and Vc with respect to offset voltage=| it is close to Δ Vc1-Δ Vc2|-and equals | the change of Δ Vc1|-is reduced to 1/gm*R0.That is, by will being connected to output, and Voltage Feedback is fed back into the control offset voltage, thinks the change that has reduced output Vc by the amplifier that bipolar transistor BT1 and resistance R 1 constitute.
In this embodiment,, and export its result, the output voltage V c of differentiating amplifier AMP1 is converted to electric current by bipolar transistor BT3 and resistance R 3 with resistance value R1 for the electric current that in bipolar transistor BT2, flows by current mirror copy.In order to make it possible to (Vss) reference point seizure output on ground, the current mirror that the collector current of transistor BT3 is formed by MOS transistor M1 and M0 returns.To by resistance R a and Rb and connect into the output circuit that the bipolar transistor BT4 of diode constitutes, obtained the voltage that obtains by the change that reduces offset voltage by the current delivery that will return.In the superincumbent equation, gm represents the conductivity of differentiating amplifier AMP1.
Below, will be described in the operation of the generating circuit from reference voltage among Fig. 1 under the situation that has offset voltage in the differentiating amplifier AMP1.
In the generating circuit from reference voltage of Fig. 1, when the offset voltage of differentiating amplifier AMP1 is set to Vos, and the reverse saturation current of bipolar transistor is when being set to Is, Vos=Vc2-Vc1.According to concerning Vc2=Vdd-I0R0 and Vc1=Vdd-I1R0, satisfy relations I 1=I0+Vos/R0 between electric current I 1 that in resistance R 1 and R2, flows and I0.Therefore, under situation about flowing between base stage in forward current each in transistor BT1 and BT2 and emitter, base-emitter voltage VBE1 and VBE2 in transistor BT1 and the BT2 are expressed as follows.
VBE1＝VT*In((I0+Vos/R0)/Is)
VBE2＝VT*In(I0/(n*Is))
The output voltage V c of differentiating amplifier AMP1 is expressed as follows.
Vc＝VBE1
＝VBE2+I0*R1
Behind cancellation VBE1 and VBE2 from top expression formula, obtain following formula.
Vc＝VT*In((I0+Vos/R0)/Is)
＝VT*In(I0/(n*Is))+I0*R1
Following formula is organized as follows.
VT*In(1+Vos/(I0*R0))＝I0*R1-VT*In(n)
Vos is enough little when hypothesis, and satisfies and concern at Vos (I0*R0)＜＜1 o'clock, equals Vos/ (I0*R0) because In (1+Vos (I0*R0)) is intimate, satisfies following formula.
VT*Vos/(I0*R0)＝I0*R1-VT*In(n)
This expression formula is written as following formula again.
I0*I0-I0*VT/R1*In(n)-VT*Vos/(R0*R1)＝0
In order to understand the change of I0 with respect to Vos, following execution is to the differential of Vos.
2I0*dI0/dVos-VT/R1*In(n)*dI0/dVos-VT/(R0*R1)＝0
Be organized as following formula.
dI0/dVos＝VT/(R0*(2I0*R1-VT*In(n)))
By the current delivery that will obtain by copy I0 to resistance R 5, the parallel circuit generation output voltage V bgout between transistor BT4 and the resistance R 6.Therefore, when the resistance of resistance R 5 is set to Ra, the base-emitter voltage of transistor BT4 is set to VBE0, and the resistance of resistance R 6 is when being Rb, according to relation
Ra*(I0-Vbgout/Rb)＝Vbgout-VBE0
Obtain following expression.
Vbgout＝Ra*Rb/(Ra+Rb)*I0+Rb/(Ra+Rb)*VBE0……(3)
By resistance Ra and Rb and the electric current I 0 that resistance R 5 and R6 correctly are set, the generating circuit from reference voltage of this embodiment can produce about 1.2V or lower output voltage V bgout under such as the 1.5V supply voltage.For example, at Ra=26 Ω, Rb=65 Ω, and under the situation of I0=20 μ A, when hypothesis VBE0=0.7V, Vbgout becomes the intimate 0.87V that equals.
According to equation (3), output voltage V bgout is expressed as follows with respect to the change speed dVbgout/dVos of skew Vos.
dVbgout/dVos＝Ra*Rb/(Ra+Rb)*dI0/dVos
＝Ra*Rb/(Ra+Rb)*VT/(R0*(2I0*R1-VT*In(n)))
＝Ra*Rb/(Ra+Rb)*1/R1*1(2I0*R/VT-R0/R1*In(n))
＝Ra*Rb/((Ra+Rb)*R1)*1/(2I0*R0/VT-R0/R1*In(n))
Wherein Ra*Rb/ ((Ra+Rb) * R1) is and the identical value (reference expression formula (2)) of inventive circuit in the former application.Therefore, when 2I0*R0/VT-R0/R1*In (n)＞1, the change speed of dVbgout/dVos raises.
As an example, consider I0=20 μ A, R0=25K Ω, R1=3K Ω, n=10 and T=25 ℃.Because it is 26mV that VT=KT/q is close to, and following expression is arranged.
2I0*R0/VT-R0/R1*In(n)
＝2*20*10
-6*25*10
3/26*10
-3-25*10
3/3*10
3*InI0
＝38.5-19.2
＝19.3＞1
Should be appreciated that and easily to realize this target.
In addition, under the situation of Ra=26K Ω and Rb=65K Ω, changing speed dVbgout/dVos is 0.321.On the other hand, in the generating circuit from reference voltage of the invention before Fig. 9, be close to and t=20 μ A in condition, R1=3K Ω, n=10, T=25 ℃, under the identical situation of Ra=26K Ω and Rb=52K Ω, changing speed dVbgout/dVos is 5.777.Therefore, should be appreciated that with the inventive circuit in the former application and compare, can reduce the fluctuation of output voltage widely with respect to the change of the skew of differentiating amplifier.
In this embodiment, can in bipolar integrated circuit, use common double gated transistors as transistor BT1, BT2 and BT3 with vertical stratification.Yet because MOS transistor and the mixed installation of bipolar transistor, this processing is complicated.Therefore in this embodiment, use can be handled the transistor that forms as transistor BT1 by CMOS, BT2 and BT3.Therefore, this processing can be simplified, and the increase of cost can be avoided.Resistance R 1 to R6 can be the formed film such as polysilicon layer or diffusion layer (well).
Fig. 3 shows the offset voltage correlativity of the output voltage V bgout in the generating circuit from reference voltage of embodiment of Fig. 1.As a comparison, Fig. 4 shows the offset voltage correlativity of the output voltage V bgout in the generating circuit from reference voltage of the invention in the former application of Fig. 9.Should be appreciated that by the comparison between Fig. 3 and Fig. 4, the gradient among Fig. 3 is milder, thereby output voltage is little with respect to the fluctuation of change of skew.Because the ratio of the coordinate axis among Fig. 3 is compared with the figure among Fig. 4 and has been exaggerated, should be noted that output voltage fluctuation ratio they look little.
Fig. 2 shows the modification to the generating circuit from reference voltage of the embodiment of Fig. 1.In this is revised, eliminated the resistance R 6 in the output in the circuit of Fig. 1, thereby compared with the circuit of Fig. 1, output voltage V bgout is slightly high.Other configuration is identical with the circuit of Fig. 1, and similarly, can reduce the fluctuation of output voltage with respect to the change of the skew among the differentiating amplifier AMP1 in the band gap part.During Rb=∞, obtain the output voltage V bgout of the circuit of Fig. 2 in the equation (3).With the circuit of Fig. 1 in the similar Ra=26K Ω of description and the situation of the setting of I0=20 μ A under, when hypothesis VBE0 is 0.7V, if Rb=∞, Ra＜＜Rb.Ra+Rb can be approximated to be Rb, thereby equation (3) can be revised as follows.
Vbgout＝Ra*I0+VBE0
As a result, Vbgout is close to and equals 1.22V.
Fig. 5 shows second embodiment according to generating circuit from reference voltage of the present invention.In a second embodiment, replacing NPN transistor uses the PNP transistor as transistor BT1, BT2 and BT3 among first embodiment.Replacing the P channel mosfet uses N-channel MOS FET as MOS transistor MT1 and MT2.
Change according to this,, on supply voltage Vdd side, provide transistor BT1 for the electric potential relation in the embodiment of the Fig. 1 that reverses, BT2 and BT3 and resistance R 3 and R4, and resistance R 1 and R2 and transistor MT1 and MT2 are provided on supply voltage Vss side.In addition, used the P channel MOS transistor as the circuit of differential input transistors as differentiating amplifier AMP1.Because the principle of operation of the generating circuit from reference voltage of second embodiment is identical with the generating circuit from reference voltage of the embodiment of Fig. 1, will not repeat the detailed description of this operation.
Fig. 6 shows the modification to the generating circuit from reference voltage of second embodiment of Fig. 5.In this is revised, omitted the resistance R 6 in the output in the circuit of Fig. 5, and output voltage V bgout is lower than the circuit of Fig. 5 slightly.Similarly, can reduce the fluctuation of output voltage with respect to the change in the skew of differentiating amplifier.
Fig. 7 shows the 3rd embodiment according to generating circuit from reference voltage of the present invention.In the 3rd embodiment, give and have the generating circuit from reference voltage 10 increase start-up circuits 20 that similarly dispose with first embodiment, avoiding when generating circuit from reference voltage 10 begins to operate, stable operation is in undesirable operating point, and can not obtain the situation of desirable output voltage.
Start-up circuit 20 has MOS transistor MT3, its source class terminal is connected to resistance R 2 in the generating circuit from reference voltage 10 and the connected node N2 between transistor BT2, and be used to receive the not electric current by transistor BT2, and the differentiating amplifier AMP2 of effect of comparer that is used from the ON/OFF control of transistor MT3 from resistance R 2.Start-up circuit 20 also has the resistor voltage divider circuit 21 that is used for reference voltage Vref is applied to differentiating amplifier AMP2 that is made of resistance R 7 and R8; be used for based on the current mirroring circuit 22 of Control current Ibs reception from the electric current of MOS transistor MT3 and resistor voltage divider circuit 21, and the transistor BT5 that is connected with diode that is used to protect that provides in parallel with resistance R 7 and R8.
To be applied to non-inverting input of differentiating amplifier AMP2 by the reference voltage Vref that resistor voltage divider circuit 21 produces, the current potential at the node N1 place of generating circuit from reference voltage 10 will be applied to reverse input end of differentiating amplifier AMP2.By the MOS transistor MT4 that is connected with diode, MOS transistor MT5 and MT6 form current mirroring circuit 22, the grid and the drain electrode that are connected with the MOS transistor MT4 of diode are connected to each other, and Ibs is converted to voltage with Control current, in MT5 and MT6 the voltage identical with the grid voltage of MOS transistor MT4 is applied on the grid.In the 3rd embodiment, MOS transistor MT4 is the N channel type to MT6.
Before starting generating circuit from reference voltage 10, do not have electric current in resistance R 1, to flow, thereby the current potential Vc1 at node N1 place is in the Vdd level.Therefore, the output Vol of differentiating amplifier AMP2 is a low level.Under the situation that generating circuit from reference voltage 10 starts, at first, Control current is passed to start-up circuit 20.By by the MOS transistor MT3 of the output Vol conducting of differentiating amplifier AMP2 with current delivery to resistance R 2, and the current potential Vc2 at node N2 place descends.Therefore, the output Vc of differentiating amplifier AMP1 changes into high level, and transistor BT1 is to the BT3 conducting, and electric current flows in resistance R 1 and R2.
Under this state, the current potential Vc1 at node N1 place becomes lower than the reference voltage Vref that is produced by resistor voltage divider circuit 21, inserts the output Vol of differentiating amplifier AMP2, and the MOS transistor MT3 that is used for bypass ends.This makes generating circuit from reference voltage 10 enter the state that is equal to the state that is not activated circuit 20, and the electric current I 0 of Jia She desired quantity and I1 flow in resistance R 1 and R2 in advance, and export desirable voltage Vbgout.In case generating circuit from reference voltage 10 is transformed into this state, even Control current Ibs interrupts, generating circuit from reference voltage 10 also can keep normal running.Therefore, Control current Ibs can be used as current impulse.
In the start-up circuit 20 of the 3rd embodiment, be used to receive MOS transistor MT3 from the electric current of generating circuit from reference voltage 10 and be connected to connected node N2 between resistance R 2 and transistor BT2.Replacedly, MOS transistor MT3 can be connected to connected node N1 between resistance R 1 and transistor BT1.In this case, the current potential Vc2 at the connected node N2 place between resistance R 2 and transistor BT2 is applied to reverse input end of differentiating amplifier AMP2.
Fig. 8 shows the modification to the generating circuit from reference voltage of the start-up circuit with Fig. 7.In this is revised, be provided for current delivery to the divider resistance R7 of the reference potential Vref that is used to produce differentiating amplifier AMP2 and the MOS transistor MT7 of R8 in supply voltage Vdd side rather than earth potential Vss side.Send back in order to flow to the electric current that flows in MOS transistor MT4-and the MOS transistor MT5, second current mirroring circuit 23 with MOS transistor MT8 and MT7 is provided at the MOS transistor MT4-Control current Ibs that forms current mirror.To be delivered to the current delivery of MOS transistor MT7 to divider resistance R7 and R8 by current mirroring circuit 23.Because the function of the start-up circuit in should revising and operation are intimate identical with start-up circuit among Fig. 7, no longer repeat detailed description.
In this is revised, can be connected to connected node N1 between resistance R 1 and transistor BT1 from the MOS transistor MT3 of generating circuit from reference voltage 10 current drawn with being used for.In Fig. 7 and 8, show the generating circuit from reference voltage 10 that has with the similar configuration shown in Fig. 1.Yet the present invention can also be applied to use Fig. 2, the situation of the generating circuit from reference voltage 10 shown in 5 or 6.
When applying the present invention to use the situation of the generating circuit from reference voltage 10 shown in Fig. 5 and 6, on supply voltage Vdd side rather than earth potential Vss side, provide the MOS transistor MT4 that constitutes current mirror to MT6.MOS transistor MT3 is connected to the connected node N2 between resistance R 2 and transistor BT2, and by differentiating amplifier AMP2 operation control ON/OFF, thereby current delivery is arrived resistance R 2.
In the generating circuit from reference voltage that uses MOS transistor and bipolar transistor, using under the situation of bipolar transistor as the diode shown in Fig. 9, the amplification coefficient of equipment may be low.Therefore, can use and can handle the so-called horizontal type bipolar transistor that forms by CMOS, wherein operating current mainly flows in the substrate plane direction.
On the other hand, use bipolar transistor BT1 in as the generating circuit from reference voltage of embodiments of the invention under the situation of BT3 as amplifier element, the amplification coefficient of this equipment is preferably high to certain degree.Therefore, wish to use so-called vertical bipolar transistor, wherein operating current mainly flows in the vertical direction of substrate.Form general vertical bipolar transistor by the processing that is different from the CMOS integrated circuit.Generating circuit from reference voltage in the embodiments of the invention uses and can handle the vertical bipolar transistor that forms by CMOS.Below, will the structure of this vertical bipolar transistor be described.
Figure 10 A and 10B show the example of the transistor BT1 of the generating circuit from reference voltage that is used as the embodiment that forms Fig. 1 to the npn bipolar transistor of BT3.Figure 11 A and 11B show as the transistor MT1 among Fig. 1, the example of the P channel MOS transistor of MT2 etc.Figure 12 A and 12B show the transistorized example of N-channel MOS as the assembly of the differentiating amplifier AMP1 among Fig. 1.
As shown in Figure 10 B, npn bipolar transistor has the N type buried regional 32 that forms in the Semiconductor substrate of being made by monocrystalline silicon etc. 31, the N type zone 33 and the p type island region territory 34 that on buried regional 32, form, the N type zone 35 that in the surface in N type zone 33, forms, and the N type zone 37 that in the surface in p type island region territory 34, forms.
In this embodiment, Semiconductor substrate 31 is the P type.Buried regional 32 play the collector region, and N type zone 33 contacts with buried regional 32, and play a part to draw on the collector regional.Base region is played in p type island region territory 34, and emitter region is played in N type zone 37.In addition, the contact layer of zone (33) is played to draw on the collector in N type zone 35, and the contact layer of base region (34) is played in p type island region territory 36.
Form simultaneously as the N type zone 33 of drawing the zone on the collector with identical processing and N type well area 43, in N type well area 43, form the P channel MOS shown in Figure 11 B.Form p type island region territory 34 simultaneously with identical processing and p type wells zone 44, in p type wells zone 44, form the N-channel MOS transistor shown in Figure 12 B as base region.
Side by side form p type island region territory 36 with identical processing and p type diffusion region territory 46 as the base stage contact layer as the source class/drain region of the P channel MOS transistor shown in Figure 11 B.With identical processing with side by side form as the N type diffusion zone 45 of the source class/drain region in the N-channel MOS transistor shown in Figure 12 B as the N type zone 35 of collector contact layer with as the N type zone 37 of emitter region.
Forming buried regional 32 the processing of N type is the processing that is not included in traditional general CMOS processing.Particularly, N type impurity is injected on the surface of P-type semiconductor substrate 31.After this, form the semiconductor layer that is used as N type well area 43 and p type wells zone 44 by Epitaxial Growth.With the part of N type impurity injection as N type well area 43, or with the part of p type impurity injection as p type wells zone 44.After this, form transistorized regional 35,36 and 37.
As shown in Figure 10 A, form as the N type zone 33 of drawing the zone on the collector, thereby surround p type island region territory 34, and form N type zone 37 as emitter region in central authorities as the p type island region territory 34 of base region as base region.In Figure 10 A, CH1, CH2 and CH3 represent collector electrode respectively, the contact hole in base electrode and the emitter electrode.
In Figure 11 A and 11B, N type zone 45C is the zone that becomes the contact layer that contacts with an electrode, and the supply voltage Vdd that will be used for the reverse biased PN junction is applied to this electrode, so that be applied to the N type well area 43 as the back grid of P type MOS transistor.In Figure 12 A and 12B, p type island region territory 46C is the zone that becomes the contact layer that contacts with an electrode, and the earth potential Vss that will be used for the reverse biased PN junction is applied to this electrode, so that be applied to the p type wells zone 44 as the back grid of N type MOS transistor.
Shown in Figure 11 A and 11B and Figure 12 A and 12B, in this embodiment, forming the 44 times formation in the transistorized N type of P channel MOS transistor and N-channel MOS well area 43 and p type wells zone N type insulating regions 42 respectively.Yet, N type insulating regions 42 can be provided.By N type insulating regions 42 being provided and applying predetermined current potential, can reduce the leakage current that in substrate, flows in the part of MOS transistor.With with identical processing forms N type insulating regions 42 in this part of MOS transistor as the N type buried regional 32 of the collector of bipolar transistor.
Figure 13 A and 13B show the example of the resistance R 1 to R6 among the Fig. 1 that constitutes generating circuit from reference voltage.Shown in Figure 13 A and 13B, by on the surface that is formed on the N type well area 53 on the Semiconductor substrate 31, forming dielectric film 59 such as silicon oxide film (SiO2), constitute resistance R 1 to R6, and on dielectric film 59, form polysilicon layer 58 with thermal oxide etc.Can use with identical processing forms polysilicon layer 58 as the polysilicon layer 48 of the transistorized gate electrode of N-channel MOS shown in the p channel transistor shown in Figure 11 B and Figure 12 B.
In order to obtain desirable sheet resistance, the impurity concentration of polysilicon layer 58 can be different from the polysilicon layer 48 as gate electrode.For example, in polysilicon layer 48 as the gate electrode of MOS transistor, implanted dopant when the ion that is used to form source class/drain region is implanted, thus reduce resistance.By covering polysilicon layer 58, thereby when implanting, impurity is not injected in ion polysilicon layer 58 as the resistance that on dielectric film 59, forms, and can be so that impurity concentration differs from one another.
The N type zone 55 that forms in the part of N type well area 53 is the zones as contact layer, and this contact layer contacts with an electrode, is applied to N type well area 53 thereby the supply voltage Vdd of reverse biased PN junction is applied to this electrode.By the current potential of fix N type well area 53, N type zone 55 has the capacitance that prevents as the polysilicon layer 58 of resistance and the stray capacitance between substrate owing to being applied to the function that this ohmically voltage fluctuates.
Figure 14 A and 14B show pie graph 5 generating circuit from reference voltage as the example of transistor BT1 to the PNP bipolar transistor of BT3 etc.
As shown in Figure 14B, the PNP bipolar transistor has the P type buried regional 32 ' that is formed in the Semiconductor substrate 31 that is made of monocrystalline silicon etc., be formed on the N type zone 34 ' on buried regional 32 ', be formed on the interior p type island region territory 35 ', surface in p type island region territory 33 ', and interior N type zone 36 ' and the p type island region territory 37 ', surface that is formed on N type zone 34 '.
In this embodiment, Semiconductor substrate 31 is the N type.Buried regional 32 ' plays the collector region, and p type island region territory 33 ' is connected to buried regional 32 ', and plays to draw on the collector zone.Base region is played in N type zone 34 ', and emitter region is played in p type island region territory 37 '.In addition, the contact layer in zone (33 ') is played to draw on the collector in p type island region territory 35 ', and the contact layer of base region (34 ') is played in N type zone 36 '.
To form the processing of the N-channel MOS transistor shown in Figure 12 B-identical therein with p type wells zone 44-and to form simultaneously with it as the p type island region territory 33 ' of drawing the zone on the collector.To form the processing of the P channel MOS transistor shown in Figure 11 B-identical therein with N type well area 43-and to form N type zone 34 ' with it simultaneously as base region.
With with as the identical processing of the N type diffusion zone 45 of the transistorized source class/drain region of N-channel MOS shown in Figure 12 B and form N type zone 36 ' with it simultaneously as the base stage contact layer.With with as the identical processing in the p type diffusion region territory 46 of the source class/drain region of the P channel MOS transistor shown in Figure 11 B and form simultaneously with it as the p type island region territory 35 ' of collector contact layer with as the p type island region territory 37 ' of emitter region.
Though specifically described the present invention that the inventor realizes herein, obviously, the invention is not restricted to these embodiment, but can differently be revised and do not break away from main idea of the present invention based on embodiment.For example, replace the bipolar transistor that is connected with diode of the output that forms generating circuit from reference voltage, can use the PN junction diode.Replace MOS transistor MT1 to MT6, can use bipolar transistor.
The present invention can be widely used for having generating circuit from reference voltage and use with reference to electricity The cut down output semiconductor integrated circuit of electronic circuit of living circuit.
According to generating circuit from reference voltage of the present invention effectively for generation of wherein having A/D A/D converter in the Analogous Integrated Electronic Circuits of converter or D/A converter or D/A converter The circuit of required reference voltage. It can also be for generation of employed relatively electricity in the comparator The circuit of pressing.
Claims (16)
1, a kind of generating circuit from reference voltage with band gap part and output,
Wherein said band gap partly has: be connected on first resistance and first bipolar transistor between the first supply voltage terminal and the second supply voltage terminal; Be connected on second resistance, second bipolar transistor and the 3rd resistance between the first supply voltage terminal and the second supply voltage terminal; And the differentiating amplifier that receives the voltage that produces by first and second resistance,
Wherein an end of first resistance is connected to the first supply voltage terminal, first bipolar transistor is connected to the second supply voltage terminal, one end of second resistance is connected to the first supply voltage terminal, one end of the 3rd resistance is connected to the second supply voltage terminal, second bipolar transistor is connected between the second and the 3rd resistance
Wherein the current potential at the tie point place between first resistance and first bipolar transistor is applied to first input end of described differentiating amplifier circuit, the current potential at the tie point place between second resistance and second bipolar transistor is applied to second input terminal of described differentiating amplifier circuit, the output of differentiating amplifier is applied to the base stage of first and second bipolar transistors, and
Wherein said output has the 3rd bipolar transistor of the base stage of the output that has been applied in described differentiating amplifier, the 4th resistance of connecting with the 3rd bipolar transistor, be used to be transmitted in the current mirroring circuit of the electric current that flows in the 3rd bipolar transistor, and the 5th resistance and the knot kinds of passive elements that are used for electric current transmitted is converted to the series connection of voltage.
2, generating circuit from reference voltage as claimed in claim 1, wherein first and second resistance have identical resistance, and third and fourth resistance has identical resistance, and second comprises the emitter of identical size with the 3rd bipolar transistor.
3, generating circuit from reference voltage as claimed in claim 2, wherein the 6th resistance is in parallel with the 5th resistance and described knot kinds of passive elements connected in series.
4, as any one generating circuit from reference voltage in the claim 1 to 3,
Wherein said current mirroring circuit has first MOS transistor that is connected with diode of connecting with the 3rd bipolar transistor, and second MOS transistor with the gate terminal that has been applied in the voltage identical with the grid voltage of first MOS transistor, and
Wherein constitute described differentiating amplifier by MOS transistor.
5, generating circuit from reference voltage as claimed in claim 4,
Wherein first, second is a npn type bipolar transistor with the 3rd bipolar transistor, and
Wherein first and second MOS transistor are P channel type MOS transistor.
6, generating circuit from reference voltage as claimed in claim 4,
Wherein first, second is the positive-negative-positive bipolar transistor with the 3rd bipolar transistor, and
Wherein first and second MOS transistor are N channel type MOS transistor.
7, the knot kinds of passive elements in the generating circuit from reference voltage as claimed in claim 6, wherein said output is the bipolar transistor that is connected with diode, and wherein base terminal and collector terminal are coupled to each other.
8, generating circuit from reference voltage as claimed in claim 6, the knot kinds of passive elements in the wherein said output is the PN junction diode.
9, as any one generating circuit from reference voltage in the claim 1 to 8, also comprise start-up circuit, it has when the operation of described generating circuit from reference voltage begins from/the first or second resistance reception/delivered current in described band gap part, and interrupts the function of received current or delivered current after the output of described differentiating amplifier is elevated to predetermined level.
10, a kind of SIC (semiconductor integrated circuit), have in it according to any one generating circuit from reference voltage and A/D converter or the D/A converter in the claim 1 to 9, wherein will offer described A/D converter or D/A converter as reference voltage by the voltage that described generating circuit from reference voltage produces.
11, a kind of conductor integrated circuit device has generating circuit from reference voltage in it,
Wherein said generating circuit from reference voltage has band gap part and output,
Wherein said band gap partly has: be connected on first resistance and first bipolar transistor between the first supply voltage terminal and the second supply voltage terminal; Be connected on second resistance, second bipolar transistor and the 3rd resistance between the described first supply voltage terminal and the second supply voltage terminal; And the differentiating amplifier that receives the voltage that produces by first and second resistance,
Wherein an end of first resistance is connected to the first supply voltage terminal, first bipolar transistor is connected to the second supply voltage terminal, one end of second resistance is connected to the first supply voltage terminal, one end of the 3rd resistance is connected to the second supply voltage terminal, second bipolar transistor is connected between the second and the 3rd resistance
Wherein the current potential at the tie point place between first resistance and first bipolar transistor is applied to first input end of described differentiating amplifier circuit, the current potential at the tie point place between second resistance and second bipolar transistor is applied to second input terminal of described differentiating amplifier circuit, the output of differentiating amplifier is applied to the base stage of first and second bipolar transistors, and
Wherein said output has the 3rd bipolar transistor of the base stage of the output that has been applied in described differentiating amplifier, the 4th resistance of connecting with the 3rd bipolar transistor, be used to be transmitted in the current mirroring circuit of the electric current that flows in the 3rd bipolar transistor, and the 5th resistance and the knot kinds of passive elements that are used for electric current transmitted is converted to the series connection of voltage
Wherein said differentiating amplifier comprises as the N channel type MOS transistor of passive element and P channel type MOS transistor, and
Wherein each in first, second and the 3rd bipolar transistor has the buried semiconductor regions as the collector region, and be formed vertical transistor, operating current mainly flows on perpendicular to the direction of substrate in this vertical transistor, and emitter region is the semiconductor regions that is formed by the processing identical with the processing of the semiconductor regions of the source class/drain region that forms N channel type MOS transistor or P channel type MOS transistor at least.
12, as the conductor integrated circuit device of claim 11, wherein as first, second with the 3rd bipolar transistor in each in the semiconductor regions of base region be to form by the processing identical with the processing that forms well area, in described well area, form the source class/drain region of described N channel type MOS transistor or P channel type MOS transistor.
13, as the conductor integrated circuit device of claim 11,
Wherein first, second is a npn type bipolar transistor with the 3rd bipolar transistor,
Wherein provide as the semiconductor regions that draws the zone on the collector, it is connected to as each the buried semiconductor regions of collector region in first, second and the 3rd bipolar transistor,
Wherein as first, second with the 3rd bipolar transistor in each in the semiconductor regions of base region be to form by the processing identical with the processing that forms the p type wells zone, in described p type wells zone, form the source class/drain region of described N channel type MOS transistor, and
Be the N-type semiconductor zone that forms by the processing identical wherein, in described N type well area, form the source class/drain region in the described P channel type MOS transistor with the processing that forms N type well area as the semiconductor regions that draws the zone on the described collector.
14, as the conductor integrated circuit device of claim 11,
Wherein first, second is the positive-negative-positive bipolar transistor with the 3rd bipolar transistor,
Wherein provide as the semiconductor regions that draws the zone on the collector, it is connected to as each the buried semiconductor regions of collector region in first, second and the 3rd bipolar transistor,
Wherein as first, second with the 3rd bipolar transistor in each in the semiconductor regions of base region be the N-type semiconductor zone that forms by the processing identical with the processing that forms N type well area, in described N type well area, form the source class/drain region of P channel type MOS transistor, and
Wherein form as the semiconductor regions that draws the zone on the described collector, in described p type wells zone, form the source class/drain region in the described N channel type MOS transistor by the processing identical with the processing that forms the p type wells zone.
15, as any one the conductor integrated circuit device in the claim 11 to 14, wherein between well area and Semiconductor substrate, provide by with the semiconductor regions that forms as the identical processing of the processing of the buried semiconductor regions of the collector region of described bipolar transistor, in described well area, form each the source class/drain region in described N channel type MOS transistor and the described P channel type MOS transistor.
16, as any one the conductor integrated circuit device in the claim 11 to 15, wherein said first to the 5th resistance is made with the conductive layer on the lip-deep dielectric film that is formed on Semiconductor substrate, and described conductive layer is by making with the material identical materials of the conductive layer of the gate electrode of described N channel type MOS transistor and P channel type MOS transistor.
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| JP2005258870 | 2005-09-07 | ||
| JP2005258870 | 2005-09-07 | ||
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| CN101859160A (en) * | 2010-06-17 | 2010-10-13 | 复旦大学 | Band-gap reference source of ultra-low power supply voltage |
| US8089260B2 (en) | 2008-12-26 | 2012-01-03 | Novatek Microelectronics Corp. | Low voltage bandgap reference circuit |
| CN101770249B (en) * | 2008-12-30 | 2013-06-05 | 联咏科技股份有限公司 | Low-voltage energy band gap reference circuit |
| CN102033566B (en) * | 2009-09-24 | 2013-10-23 | 上海华虹Nec电子有限公司 | Bipolar NPN type band-gap reference voltage circuit |
| CN103645769A (en) * | 2013-12-10 | 2014-03-19 | 电子科技大学 | low-voltage band-gap reference source circuit |
| CN105700609A (en) * | 2016-04-22 | 2016-06-22 | 中国电子科技集团公司第二十四研究所 | Reference voltage generation circuit |
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| CN110262606A (en) * | 2019-06-21 | 2019-09-20 | 芯创智（北京）微电子有限公司 | Band gap reference voltage source circuit |
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| US8089260B2 (en) | 2008-12-26 | 2012-01-03 | Novatek Microelectronics Corp. | Low voltage bandgap reference circuit |
| CN101770249B (en) * | 2008-12-30 | 2013-06-05 | 联咏科技股份有限公司 | Low-voltage energy band gap reference circuit |
| CN102033566B (en) * | 2009-09-24 | 2013-10-23 | 上海华虹Nec电子有限公司 | Bipolar NPN type band-gap reference voltage circuit |
| CN101859160B (en) * | 2010-06-17 | 2012-05-30 | 复旦大学 | Band-gap reference source of ultra-low power supply voltage |
| CN101859160A (en) * | 2010-06-17 | 2010-10-13 | 复旦大学 | Band-gap reference source of ultra-low power supply voltage |
| CN103645769A (en) * | 2013-12-10 | 2014-03-19 | 电子科技大学 | low-voltage band-gap reference source circuit |
| CN107135002A (en) * | 2016-02-29 | 2017-09-05 | 精工半导体有限公司 | Switched-capacitor input circuit, switched capacitor amplifier and switching capacity voltage comparator |
| CN105700609A (en) * | 2016-04-22 | 2016-06-22 | 中国电子科技集团公司第二十四研究所 | Reference voltage generation circuit |
| CN111221370A (en) * | 2018-11-16 | 2020-06-02 | 力旺电子股份有限公司 | Band-gap reference starting circuit and reference voltage generator |
| CN111221370B (en) * | 2018-11-16 | 2021-11-09 | 力旺电子股份有限公司 | Band-gap reference starting circuit and reference voltage generator |
| CN110262606A (en) * | 2019-06-21 | 2019-09-20 | 芯创智（北京）微电子有限公司 | Band gap reference voltage source circuit |
| TWI719848B (en) * | 2020-03-03 | 2021-02-21 | 華邦電子股份有限公司 | Reference voltage holding circuit and sense amplifier circuit having reference voltage holding circuit |
| CN113539307A (en) * | 2020-04-17 | 2021-10-22 | 美光科技公司 | Current regulation technique based on operating parameters |
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