CN113496718B - Reference voltage holding circuit and sense amplifier circuit having the same - Google Patents

Abstract

In one aspect of the invention, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by the sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generation circuit configured to provide a bias reference voltage; a current generation circuit electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide a standby bias current and maintain a standby bias voltage that drives the sense amplifier reference voltage when the reference voltage holding circuit is operating in standby operation, and approaches the sense amplifier reference voltage as long as the sense amplifier reference voltage is held enabled.

Description

Reference voltage holding circuit and sense amplifier circuit having the same

Technical field

The present invention relates to a reference voltage holding circuit and a sense amplifier circuit having the reference voltage holding circuit.

Background technique

For conventional non-volatile memory integrated circuits, the sense amplifier is generally an essential part of the readout mechanism that enables the binary data stored in the memory cell to be read. The sense amplifier is designed to sense a low power signal from the bit line representing a binary 1 or binary 0 stored in the memory cell and amplify the low power signal to a recognizable voltage level such that the circuitry that is part of the reading mechanism Able to identify binary data stored in memory cells.

Sense amplifier architectures can have many implementations. One embodiment may employ the use of a plurality of main sense amplifier circuits each connected to a memory cell without limitation and a sense amplifier reference circuit that provides a reference voltage for each of the plurality of main sense amplifier circuits. Each of the main sense amplifier circuits is connected to a memory cell. The main sense amplifier circuit may include, but is not limited to, a comparator and a current-to-voltage converter (IV converter), and the sense amplifier reference circuit may include, but is not limited to, an IV converter. The output of the sense reference circuit may be connected to the input of each of the comparators of the main sense amplifier circuit. Generally speaking, a comparator compares a voltage signal stored in a memory cell of a main sense amplifier circuit with a reference voltage generated by a sense amplifier reference circuit. If the voltage signal stored in the memory cell is less than the reference voltage, then the comparator will produce a binary 1; otherwise, the comparator will produce a binary 0.

The main sense amplifier circuit and the sense amplifier reference circuit will normally be turned off during standby mode to save power, but will be turned on during active read mode. When the chip enters active read mode from standby mode, the reference voltage reaches the voltage target within the time limit. If the voltage target is not reached within the time limit, the main sense amplifier circuit may not be operating correctly. However, the trend has been to place more and more of the main sense amplifier circuit within the area of the integrated circuit. Because increasing the number of main sense amplifier circuits connected to the sense amplifier reference circuit may result in a higher total capacitive load from a sense amplifier reference circuit perspective, as the number of main sense amplifier circuits increases and the drive memory As the chip's external clock becomes faster, deadlines may become increasingly difficult to meet.

An alternative solution to the above challenges could be to split the main sense amplifier circuit into multiple groups, where a smaller number of main sense amplifier circuits are connected to the reference sense amplifier circuit. However, this effort may not be satisfactory because the overall system may require higher current consumption and more sense amplifier reference circuitry. Therefore, alternative solutions can still be proposed to address the above challenges.

Contents of the invention

Accordingly, the present invention relates to a reference voltage holding circuit and a sense amplifier circuit having the reference voltage holding circuit.

In one aspect of the present invention, a reference voltage holding circuit is provided for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes but is not limited to: a reference voltage generating circuit, configured to provide a bias reference voltage; a current generation circuit electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to a current generation circuit (current mirror circuit) and configured to provide a standby bias current and maintain a standby bias voltage that drives the sense amplifier reference voltage when the reference voltage holding circuit operates in standby operation, and As long as the sense amplifier reference voltage remains enabled, the standby bias voltage approaches the sense amplifier reference voltage.

In another embodiment of the invention, a sense amplifier circuit is provided. The sense amplifier circuit includes, but is not limited to: a sense amplifier reference circuit configured to generate a sense amplifier reference voltage; a main sense amplifier circuit configured to receive the sense amplifier reference voltage and store data from the main sense amplifier circuit The voltage signal of the unit is compared with the sense amplifier reference voltage; and the reference voltage holding circuit is configured to maintain the sense amplifier reference voltage when the sense amplifier operates in a standby operation, wherein the reference voltage holding circuit includes: a reference voltage generating circuit, configured to provide a bias reference voltage; a current generation circuit (current mirror circuit) electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up Circuitry electrically coupled to a current generating circuit (current mirror circuit) and configured to provide a standby bias current and pull up a standby bias voltage that drives the standby bias voltage when the reference voltage holding circuit operates in standby operation. The sense amplifier reference voltage, and as long as the sense amplifier reference voltage remains enabled, the standby bias voltage approaches the sense amplifier reference voltage.

In order to facilitate understanding of the foregoing features and advantages of the present invention, exemplary embodiments with accompanying drawings are described in detail below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.

It should be understood, however, that this summary may not encompass all aspects and embodiments of the invention, and is therefore not meant to be limited or restricted in any way. Furthermore, the present invention will incorporate improvements and modifications that will be apparent to those skilled in the art.

Description of the drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

1 shows a conceptual diagram of a reference voltage holding circuit according to an exemplary embodiment of the present invention;

2 shows a conceptual diagram of a sense amplifier circuit according to an exemplary embodiment of the present invention;

3 illustrates a sense amplifier with a reference voltage holding circuit according to an exemplary embodiment of the present invention.

Explanation of reference numbers

100, 202, 302: Reference voltage holding circuit;

101, 211: Reference voltage generation circuit;

102, 212: Current generation circuit;

103, 213: Voltage pull-up circuit;

104, 214: switch circuit;

200, 300: Sense amplifier circuit;

201, 301: Sense amplifier reference circuit;

203, 303: Main sense amplifier circuit;

311: Bandgap voltage reference circuit;

312: first transistor;

313: second transistor;

314: third transistor;

315: The first P-type transistor;

316: First Ioff current;

317: second P-type transistor;

318: Transmission gate;

319: Inverter;

320: Second Ioff current;

322: Unit current.

sainr: sense amplifier reference voltage

sain: voltage signal

Detailed ways

Reference will now be made in detail to a current embodiment of the invention, examples of which are illustrated in the accompanying drawings.

As previously described, as the number of sense amplifiers increases, timing requirements become more difficult to meet because future non-volatile memory storage devices will require ever higher speeds and more data processing. Additionally, as the number of sense amplifiers increases, the total capacitance of the sense amplifiers also increases, which will result in a slower rise rate of the sense amplifier reference voltage. A slowdown in the rate of increase of the sense amplifier reference voltage can result in dysfunction of the initial read operation. To address the challenge of having an increased number of sense amplifiers while mitigating the negative consequences of this increase, the present invention proposes to modulate the sense amplifier circuit by adding a reference voltage holding circuit that when operating in standby mode The sense amplifier reference voltage is maintained, and during standby mode, both the sense amplifier reference circuit and the main sense amplifier circuit are turned off to avoid unnecessary power consumption. In the present invention, the reference voltage holding circuit avoids slowing down of the sense amplifier reference voltage by maintaining the voltage level of the sense amplifier reference voltage when the non-volatile memory storage device undergoes a transition from the standby mode to the active read mode. Rise rate.

1 illustrates a conceptual diagram of a reference voltage hold circuit 100 configured to maintain a sense amplifier reference voltage provided by a sense amplifier reference circuit (it is not shown that the sense amplifier reference circuit is connected to the reference voltage hold circuit 100 , but outside the reference voltage holding circuit 100). The reference voltage holding circuit 100 will include, but is not limited to: a reference voltage generating circuit 101 configured to provide a bias reference voltage; a current generating circuit 102 electrically coupled to the reference voltage generating circuit 101 and configured to receive the bias reference voltage for output. a standby bias voltage and a standby bias current; and a voltage pull-up circuit 103 electrically coupled to the current generating circuit 102 and configured to provide a standby bias current and pull up the standby bias voltage when the reference voltage holding circuit 100 is in standby During operation, the standby bias voltage drives the sense amplifier reference voltage, and as long as the sense amplifier reference circuitry remains enabled, the standby bias voltage approaches the sense amplifier reference voltage. When the sense amplifier reference circuit is turned off during standby operation, the sense amplifier reference voltage is maintained by the reference voltage holding circuit 100 .

According to an embodiment, the reference voltage generation circuit 101 may include a bandgap voltage reference circuit that generates a bias reference voltage that is activated when the reference voltage holding circuit 100 operates in both standby operation and read operation. . According to an embodiment, the current generating circuit 102 may be a current mirror circuit including a plurality of transistors. The current mirror circuit is configured to receive a bias reference voltage and convert the bias reference voltage into a standby bias current. The standby bias current is set is N times smaller than the reference current of the reference cell of the sense amplifier reference circuit. Alternatively, the current generating circuit 102 may also be a resistor that converts the bias reference voltage into a standby bias current, and the standby bias current is set to be N times smaller than the reference current of the reference unit of the sense amplifier reference circuit.

According to an embodiment, the voltage pull-up circuit 103 may include a first P-type transistor by setting the first P-type transistor to have a smaller width-to-length ratio than a corresponding P-type transistor of the sense amplifier reference circuit. N times the width-to-length ratio to pull up the standby bias voltage. The number N may be set to meet the current consumption target of the reference voltage holding circuit (eg, reference voltage holding circuit 302 ) during standby mode. According to an embodiment, the voltage pull-up circuit 103 may further include a second P-type transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the drain-to-drain voltage (vdd), and the second terminal Connected to the first P-type transistor, and the third terminal is configured to receive a deep power down signal. As long as the reference voltage holding circuit does not deeply power down, the deep power-down signal remains low to maintain the second P-type transistor. transistor starts. If the deep power-down signal is pulled high to turn off the second P-type transistor, the voltage pull-up circuit 103 will stop providing standby bias current during deep power down mode.

According to one embodiment, the switch circuit 104 will be configured to couple the standby bias voltage to the sense amplifier reference voltage during standby mode, but decouple the standby bias voltage from the sense amplifier reference voltage during read operations. , during read operations, the sense amplifier reference voltage is driven by the sense amplifier reference circuit and is not driven by the reference voltage holding circuit.

Please refer to Figure 2 and Figure 3. Figure 2 is referenced together with Figure 3 in the following disclosure. The sense amplifier circuit 200 (300) will include, but is not limited to: a sense amplifier reference circuit 201 (301) configured to generate the sense amplifier reference voltage sainr; a main sense amplifier circuit 203 (303) configured to convert from the main The cell current 322 of the memory cell of the sense amplifier circuit 203 (303) receives the sense amplifier reference voltage sainr and generates the voltage signal sain, and compares the voltage signal sain voltage with the sense amplifier reference voltage sainr; and the reference voltage holding circuit 302, configured to maintain the sense amplifier reference voltage sainr when the sense amplifier 200 (300) operates in standby operation.

The reference voltage holding circuit 202 (302) will include, but is not limited to: a reference voltage generating circuit 211 configured to provide a bias reference voltage nbias; a current generating circuit 212 electrically connected to the reference voltage generating circuit 211 and configured to receive a bias voltage The reference voltage nbias is used to output the standby bias voltage sainr_stby and the standby bias current Ibias3; and the voltage pull-up circuit 213 is electrically coupled to the current generation circuit 212 and is configured to provide the standby bias current Ibias3 and pull up the standby bias voltage sainr_stby. , when the reference voltage holding circuit 202 (302) operates in standby operation, the standby bias voltage sainr_stby drives the sense amplifier reference voltage sainr, and as long as the sense amplifier reference circuit 201 (301) remains enabled, then the standby bias voltage sainr_stby sainr_stby approaches the sense amplifier reference voltage sainr.

It is worth noting that both the sense amplifier reference circuit 201 (301) and the main sense amplifier circuit 203 (303) are turned off during standby mode to reduce power consumption. During standby mode, the sense amplifier reference circuit 201 (301) may be floating, and the sense amplifier reference voltage sainr is determined by competition between the first Ioff current 316 and the second Ioff current 320. For example, if the first Ioff current 316 is higher than the second Ioff current 320, then the sense amplifier reference voltage sainr can approach vdd. Otherwise, if the first Ioff current 316 is less than the second Ioff current 320, the sense amplifier reference voltage sainr can approach ground. When sense amplifier reference circuit 201 (301) and main sense amplifier circuit 203 (303) exit standby mode and enter active read mode, because either of reference voltage hold circuits 202 (302) maintains the sense amplifier reference voltage sainr, so the sense amplifier reference voltage sainr takes almost no time to charge or discharge. Therefore, even though sense amplifier reference circuit 201 (301) must provide sense amplifier reference voltage sainr to many main sense amplifier circuits (eg, 203 (303)), sense amplifier reference voltage sainr will take significantly less time to charging without having to slow down the clock frequency for read operations or resorting to strategies such as adding additional dummy clocks before the first data output occurs.

According to an embodiment, the reference voltage generating circuit 211 may be a bandgap voltage reference circuit 311 that is enabled when the reference voltage holding circuit 202 (302) is in both standby operation and read operation.

According to an embodiment, the current generating circuit 212 may include a first transistor 312 that receives a bias reference voltage nbias to generate a first bias current Ibias1, a third transistor that generates a second bias current Ibias2 by mirroring the first bias current Ibias1. two transistors 313 and a third transistor 314 that mirrors the second bias current Ibias2 to generate a standby bias current Ibias3, which is set to be larger than the reference cell RC of the sense amplifier reference circuit 201 (301). The reference current Iref (ie, the second Ioff current 320) is N times smaller.

According to an embodiment, the voltage pull-up circuit 213 may include a first P-type transistor 315 by setting the first P-type transistor 315 to have a higher voltage than the corresponding P-type of the sense amplifier reference circuit 301 . The width-to-length ratio of the transistor PT is N times smaller to pull up the standby bias voltage sainr_stby. N may be set to meet the current consumption target of the reference voltage holding circuit 302 during standby mode. The voltage pull-up circuit 213 may further include a second P-type transistor 317 having a gate terminal, a drain terminal, and a source terminal. The source terminal may be connected to the drain-to-drain voltage (vdd), the drain terminal may be connected to the first P-type transistor 315, and the gate terminal may be configured to receive the deep power-down signal dpdown, as long as the reference voltage holding circuit 302 does not deeply power down (or not operating in deep power-down mode), then the deep power-down signal remains low to keep the first P-type transistor 315 and the second P-type transistor 317 enabled. But when operating in the deep power-down mode, the deep power-down signal dpdown is pulled high to turn off the second P-type transistor 317 to cut off the standby bias current Ibias3.

According to an embodiment, the reference voltage holding circuit 202 may further include a switching circuit 214 configured to decouple the standby bias voltage sainr_stby from the sense amplifier reference voltage sainr during a read operation (ie, active read mode). Coupling, during the read operation, the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuit 201 (301) and is not driven by the reference voltage holding circuit 202 (302). But during standby operation (ie, standby mode), the switching circuit 214 is enabled to couple the sense amplifier reference voltage sainr to the standby bias voltage sainr_stby, such that the sense amplifier reference voltage sainr is maintained by the standby bias voltage sainr_stby.

According to an embodiment, the sense amplifier reference circuit 201 (301) and the main sense amplifier circuit 203 (303) have multiple terminals that receive the sense amplifier enable signal saeb signal. The sense amplifier enable signal saeb is pulled low during the read operation because the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuit 201 (301) and is not driven by the reference voltage holding circuit 202 (302 ) drive, so the standby bias voltage sainr_stby is decoupled from the sense amplifier reference voltage sainr. According to an embodiment, the sense amplifier reference circuit 201 (301) may be connected to multiple main sense amplifier circuits (eg, 303), resulting in a large capacitance value for the sense amplifier reference voltage sainr of the sense amplifier reference circuit 201 (301). .

The principle of operation of Figure 3 is further explained below. For the bandgap voltage reference circuit 311, a low-power bandgap reference voltage generation (BGR) circuit can be used, and both in standby operation (i.e., standby mode) and read operation (i.e., active read mode) The low-power bandgap reference voltage generation circuit will always be enabled. The bandgap voltage reference circuit 311 will provide a bias reference voltage nbias, which is used to generate the first bias current Ibias1 by the first transistor 312 . The first bias current Ibias1 is then mirrored by the second transistor 313 into the second bias current Ibias2 current, which is then mirrored by the third transistor 314 into the standby bias current Ibias3.

The standby bias current Ibias3 may be set to be approximately N times smaller than the reference current Iref, and N may be 100 as an example. In other words, Ibias3=Ibias1=Ibias2=Iref/100, and approximately 1/100 of the reference current Iref is generated to bias the standby bias voltage sainr_stby. Furthermore, it has been determined that when the sense amplifier reference circuit 301 is enabled, the length of the first P-type transistor 315 may be N times longer than the corresponding P-type transistor PT in the sense amplifier reference circuit 301, such that the standby bias voltage sainr_stby is extremely Similar to the sense amplifier reference voltage sainr. However, it should be noted that 100 is only an exemplary number and may be adjusted based on design changes or based on changes in requirements for the sense amplifier circuit 300 .

The standby bias voltage sainr_stby is always enabled during both standby mode and active read mode. However, when operating in standby mode, the standby bias voltage sainr_stby drives the sense amplifier reference voltage sainr, which may appear to be heavily capacitively loaded when transitioning from standby mode to active read mode. Boost operation is accelerated by maintaining the sense amplifier reference voltage sainr. Basically, when the sense amplifier reference circuit 301 and the main sense amplifier circuit are both turned off during standby mode, the SAINR holder (i.e., the reference voltage holding circuit 202 (302)) is used to maintain the node "sense amplifier reference voltage sainr" ".

When operating in the active read mode, the standby bias voltage sainr_stby is decoupled from the sense amplifier reference voltage sainr because the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuit 301. This decoupling may be achieved by switching circuit 214, which may include transmission gate 318 and inverter 319. The P-type gate terminal of the transmission gate 318 can receive the idle enable signal idleb. When it is confirmed that the sense amplifier enable signal saeb signal is low, the idle enable signal idleb is pulled high. By setting the idle enable signal idleb high, the transmission gate 318 will be closed to decouple the sense amplifier reference voltage sainr from the standby bias voltage sainr_stby. When operating in standby mode, verify that the idle enable signal idleb is low.

When operating in the deep power-down mode, the deep power-down signal dpdown is confirmed to be high to turn off the second P-type transistor 317, which in turn will cause the standby bias current Ibias3 to be turned off. During deep power-down mode, the sense amplifier reference circuit 301, the reference voltage holding circuit 302, and the main sense amplifier circuit 303 are turned off. When not operating in deep power-down mode, verify that the deep power-down signal dpdown is low.

In view of the foregoing description, the present invention is suitable for use as part of a reading mechanism of a non-volatile memory storage device, and the present invention can achieve at least one of the following advantages, including lower hardware cost, lower standby current burden and the dissociation between read speed and number of sense amplifiers. Hardware cost reduction can be achieved by adding a reference voltage holding circuit 302 to the sense amplifier reference circuit (e.g., 301) and one or more main sense amplifier circuits (e.g., 303) without having to add the main sense Splitting amplifier circuits (e.g., 303) into multiple groups reduces the number of main sense amplifier circuits (e.g., 303) to be serviced by sense amplifier reference circuits (e.g., 301) without having to add additional dummies before the first data output occurs clock.

No element, act, or instruction used in the detailed description of the embodiments disclosed herein should be construed as absolutely critical or essential to the invention unless explicitly so described. Additionally, as used herein, each of the indefinite articles "a/an" may include more than one item. If only one item is desired, the term "single" or similar language will be used. Furthermore, as used herein, the term "any of" preceding a list of a plurality of items and/or a plurality of item categories is intended to encompass such items and/or item categories individually or in combination Other items and/or other item categories "any of", "any combination of", "any more of" and/or " "any combination of more than one of". Furthermore, as used herein, the term "set" is intended to encompass any number of items, including zero. Furthermore, as used herein, the term "amount" is intended to include any quantity, including zero.

It will be apparent to those skilled in the art that various modifications and changes can be made in the structure of the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (12)

1. A reference voltage holding circuit for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, the reference voltage holding circuit comprising: a reference voltage generating circuit configured to provide a bias reference voltage; a current generation circuit electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current generating circuit and configured to provide the standby bias current and maintain the standby bias voltage when the reference voltage holding circuit operates in standby operation. A piezo voltage drives the sense amplifier reference voltage, and the standby bias voltage approaches the sense amplifier reference voltage as long as the sense amplifier reference circuit remains enabled. 2. The reference voltage holding circuit of claim 1, wherein the current generating circuit includes: a first transistor that receives the bias reference voltage to generate a first bias current; a second transistor that generates a second bias current by mirroring the first bias current; and A third transistor mirrors the second bias current to generate a third bias current, where the third bias current is set to be N times smaller than the reference current of the reference unit of the sense amplifier reference circuit. 3. The reference voltage holding circuit according to claim 2, wherein the voltage pull-up circuit includes: A first P-type transistor that pulls up the standby bias by setting the first P-type transistor to have an aspect ratio that is N times smaller than the aspect ratio of the corresponding P-type transistor of the sense amplifier reference circuit. voltage. 4. The reference voltage holding circuit of claim 3, wherein N is a number set to meet a current consumption target of the reference voltage holding circuit during standby mode. 5. The reference voltage holding circuit of claim 1, wherein the reference voltage generating circuit is a bandgap voltage reference circuit activated when the reference voltage holding circuit is in the standby operation. , and is also activated when the reference voltage holding circuit is performing a read operation. 6. The reference voltage holding circuit according to claim 3, wherein the voltage pull-up circuit further comprises a second P-type transistor, the second P-type transistor includes a first terminal, a second terminal and a third terminal, wherein The first terminal is connected to the drain-to-drain voltage, the second terminal is connected to the first P-type transistor, and the third terminal is configured to receive a deep power-down signal as long as the reference voltage holding circuit is not deeply powered down , then the deep power-down signal remains low. 7. The reference voltage holding circuit of claim 6, wherein the deep power-down signal is pulled high to turn off the second P-type transistor, thereby disconnecting the third bias current. 8. The reference voltage holding circuit according to claim 1, further comprising: A switching circuit configured to decouple the standby bias voltage from the sense amplifier reference voltage during read operations, the sense amplifier reference voltage being referenced by the sense amplifier during the read operation circuit driven and not driven by the reference voltage holding circuit. 9. The reference voltage holding circuit of claim 1, wherein the current generating circuit includes a resistor configured to generate the bias reference voltage to output the standby bias voltage and the standby bias voltage. voltage current. 10. A sense amplifier circuit, comprising: a sense amplifier reference circuit configured to generate a sense amplifier reference voltage; a main sense amplifier circuit configured to receive the sense amplifier reference voltage and compare a voltage signal from a memory cell of the main sense amplifier circuit to the sense amplifier reference voltage; and a reference voltage holding circuit configured to maintain the sense amplifier reference voltage when the sense amplifier operates in standby operation, wherein The reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generation circuit electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current generating circuit and configured to provide the standby bias current and pull up the standby bias voltage, when the reference voltage holding circuit operates in the standby operation, the The standby bias voltage drives the sense amplifier reference voltage and approaches the sense amplifier reference voltage as long as the sense amplifier reference circuit remains enabled. 11. The sense amplifier circuit of claim 10, wherein the sense amplifier reference circuit and the main sense amplifier circuit receive a sense amplifier enable signal that is pulled low during a read operation. During fetch operation, the standby bias voltage is decoupled from the sense amplifier reference voltage, and the sense amplifier reference voltage is driven by the sense amplifier reference circuit and not by the reference voltage holding circuit. 12. The sense amplifier circuit of claim 10, wherein a sense amplifier reference circuit is connected to a plurality of main sense amplifier circuits, and the sense amplifier reference voltage of the sense amplifier reference circuit has a large capacitance value .