CN113496718B - Reference voltage holding circuit and sense amplifier circuit having the same - Google Patents
Reference voltage holding circuit and sense amplifier circuit having the same Download PDFInfo
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- CN113496718B CN113496718B CN202010265535.7A CN202010265535A CN113496718B CN 113496718 B CN113496718 B CN 113496718B CN 202010265535 A CN202010265535 A CN 202010265535A CN 113496718 B CN113496718 B CN 113496718B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
In one aspect of the invention, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by the sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generation circuit configured to provide a bias reference voltage; a current generation circuit electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide a standby bias current and maintain a standby bias voltage that drives the sense amplifier reference voltage when the reference voltage holding circuit is operating in standby operation, and approaches the sense amplifier reference voltage as long as the sense amplifier reference voltage is held enabled.
Description
Technical Field
The present invention relates to a reference voltage holding circuit and a sense amplifier circuit having the reference voltage holding circuit.
Background
For conventional nonvolatile memory integrated circuits, the sense amplifier is typically an integral part of a reading mechanism that enables binary data stored in the memory cells to be read. The sense amplifier is designed to sense a low power signal representing a binary 1 or binary 0 stored in the memory cell from the bit line and amplify the low power signal to an identifiable voltage level so as to enable circuitry that is part of the reading mechanism to discern the binary data stored within the memory cell.
The sense amplifier architecture may have many implementations. One implementation may employ a sense amplifier reference circuit that uses a plurality of main sense amplifier circuits that are not limited to each being connected to a memory cell and that provides a reference voltage for each of the plurality of main sense amplifier circuits. Each of the main sense amplifier circuits is connected to a memory cell. The main sense amplifier circuit may include, but is not limited to, a comparator and a current-to-voltage converter (IV converter), and the sense amplifier reference circuit may include, but is not limited to, an IV converter. The output of the sense reference circuit may be connected to the input of each of the comparators of the main sense amplifier circuit. In general, a comparator compares a voltage signal stored in a memory cell of a main sense amplifier circuit with a reference voltage generated by a sense amplifier reference circuit. If the voltage signal stored in the memory cell is less than the reference voltage, the comparator will generate a binary 1; otherwise, the comparator will generate a binary 0.
The main sense amplifier circuit and the sense amplifier reference circuit will normally be turned off during standby mode to achieve power saving, but will be turned on during active read mode (active read mode). When the chip enters the active read mode from standby mode (standby mode), the reference voltage reaches the voltage target present time limit. If the voltage target is not reached within the time limit, the main sense amplifier circuit may not function properly. However, the trend has been to place more and more main sense amplifier circuits within the area of the integrated circuit. Because increasing the number of main sense amplifier circuits connected to the sense amplifier reference circuit may result in a higher total capacitive load from the perspective of the sense amplifier reference circuit, the time limit may become increasingly difficult to reach as the number of main sense amplifier circuits increases and the external clock driving the memory chip becomes faster.
An alternative solution to the above challenges may be to divide the main sense amplifier circuits into multiple groups, with a smaller number of main sense amplifier circuits connected to the reference sense amplifier circuit. However, this effort may be unsatisfactory because the overall system may require higher current consumption and more sense amplifier reference circuits. Accordingly, alternative solutions may still be proposed to address the challenges described above.
Disclosure of Invention
Accordingly, the present invention relates to a reference voltage holding circuit and a sense amplifier circuit having the reference voltage holding circuit.
In one aspect of the invention, a reference voltage holding circuit is provided for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and includes, but is not limited to: a reference voltage generation circuit configured to provide a bias reference voltage; a current generation circuit electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current generation circuit (current mirror circuit) and configured to provide a standby bias current and maintain a standby bias voltage that drives the sense amplifier reference voltage when the reference voltage holding circuit operates in standby operation and approaches the sense amplifier reference voltage as long as the sense amplifier reference voltage is held enabled.
In another embodiment of the present invention, a sense amplifier circuit is provided. The sense amplifier circuit includes, but is not limited to: a sense amplifier reference circuit configured to generate a sense amplifier reference voltage; a main sense amplifier circuit configured to receive the sense amplifier reference voltage and compare a voltage signal from a memory cell of the main sense amplifier circuit with the sense amplifier reference voltage; and a reference voltage holding circuit configured to maintain the sense amplifier reference voltage when the sense amplifier is operating in standby operation, wherein the reference voltage holding circuit comprises: a reference voltage generation circuit configured to provide a bias reference voltage; a current generation circuit (current mirror circuit) electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current generation circuit (current mirror circuit) and configured to provide a standby bias current and pull up a standby bias voltage that drives the sense amplifier reference voltage when the reference voltage holding circuit operates in standby operation and approaches the sense amplifier reference voltage as long as the sense amplifier reference voltage is held enabled.
So that the manner in which the above recited features and advantages of the present invention are attained and can be understood in detail, exemplary embodiments thereof are described in detail. It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.
However, it should be understood that this summary may not contain all aspects and embodiments of the present invention, and thus is not meant to be limiting or restrictive in any way. Further, the present invention will include improvements and modifications apparent to those skilled in the art.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1 illustrates a conceptual diagram of a reference voltage holding circuit according to an exemplary embodiment of the present invention;
FIG. 2 illustrates a conceptual diagram of a sense amplifier circuit according to an exemplary embodiment of the invention;
fig. 3 illustrates a sense amplifier with a reference voltage holding circuit according to an exemplary embodiment of the present invention.
Description of the reference numerals
100. 202, 302: a reference voltage holding circuit;
101. 211: a reference voltage generating circuit;
102. 212: a current generating circuit;
103. 213: a voltage pull-up circuit;
104. 214: a switching circuit;
200. 300: a sense amplifier circuit;
201. 301: a sense amplifier reference circuit;
203. 303: a main sense amplifier circuit;
311: a bandgap voltage reference circuit;
312: a first transistor;
313: a second transistor;
314: a third transistor;
315: a first P-type transistor;
316: a first Ioff current;
317: a second P-type transistor;
318: a transmission gate;
319: an inverter;
320: a second Ioff current;
322: cell current.
sainr: sense amplifier reference voltage
sain: voltage signal
Detailed Description
Reference will now be made in detail to a present embodiment of the invention, examples of which are illustrated in the accompanying drawings.
As previously described, as future non-volatile memory storage devices require higher and higher speeds and more data processing, timing requirements become more difficult to meet as the number of sense amplifiers increases. Furthermore, as the number of sense amplifiers increases, the total capacitance of the sense amplifiers also increases, which will result in a slower rate of rise of the sense amplifier reference voltage. The slow down of the rate of rise of the sense amplifier reference voltage may cause dysfunction of the initial read operation. In order to address the challenges of having an increased number of sense amplifiers while mitigating the negative consequences of this increase, the present invention proposes to adjust the sense amplifier circuit by adding a reference voltage holding circuit that holds the sense amplifier reference voltage when operating in standby mode, during which both the sense amplifier reference circuit and the main sense amplifier circuit are turned off to avoid unnecessary power consumption. In the present invention, the reference voltage holding circuit avoids a slow rise rate of the sense amplifier reference voltage by maintaining the voltage level of the sense amplifier reference voltage when the non-volatile memory storage device undergoes a transition from the standby mode to the active read mode.
Fig. 1 illustrates a conceptual diagram of a reference voltage holding circuit 100 configured to maintain a sense amplifier reference voltage provided by a sense amplifier reference circuit (which is not illustrated as the sense amplifier reference circuit being connected to the reference voltage holding circuit 100, but external to the reference voltage holding circuit 100). The reference voltage holding circuit 100 will include, but is not limited to: a reference voltage generation circuit 101 configured to provide a bias reference voltage; a current generation circuit 102 electrically coupled to the reference voltage generation circuit 101 and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit 103 electrically coupled to the current generation circuit 102 and configured to provide a standby bias current and pull up a standby bias voltage that drives the sense amplifier reference voltage when the reference voltage holding circuit 100 is operating in standby operation, and approaches the sense amplifier reference voltage as long as the sense amplifier reference circuit is held enabled. When the sense amplifier reference circuit is turned off during standby operation, the sense amplifier reference voltage is maintained by the reference voltage holding circuit 100.
According to an embodiment, the reference voltage generation circuit 101 may include a bandgap voltage reference circuit that generates a bias reference voltage that is enabled when the reference voltage holding circuit 100 is operating in both standby and read operations. According to an embodiment, the current generation circuit 102 may be a current mirror circuit including a plurality of transistors, the current mirror circuit configured to receive a bias reference voltage and convert the bias reference voltage into a standby bias current, the standby bias current being set to be N times smaller than a reference current of a reference cell of the sense amplifier reference circuit. Alternatively, the current generation circuit 102 may be a resistor that converts the bias reference voltage into a standby bias current that is set to be N times smaller than the reference current of the reference cell of the sense amplifier reference circuit.
According to an embodiment, the voltage pull-up circuit 103 may include a first P-type transistor that pulls up the standby bias voltage by setting the first P-type transistor to have a width-to-length ratio that is N times smaller than the width-to-length ratio of the corresponding P-type transistor of the sense amplifier reference circuit. The number N may be set to meet a current consumption target of the reference voltage holding circuit (e.g., the reference voltage holding circuit 302) during the standby mode. According to an embodiment, the voltage pull-up circuit 103 may further include a second P-type transistor having a first terminal connected to the drain-to-drain voltage (vdd), a second terminal connected to the first P-type transistor, and a third terminal configured to receive a deep power down signal (deep power down) that remains low to keep the second P-type transistor enabled so long as the reference voltage holding circuit is not deep powered down. If the deep power down signal is pulled high to turn off the second P-type transistor, the voltage pull-up circuit 103 will cease providing standby bias current during the deep power down mode (deep power down mode).
According to an embodiment, the switch circuit 104 will be configured to couple the standby bias voltage to the sense amplifier reference voltage during a standby mode, but decouple the standby bias voltage from the sense amplifier reference voltage (sense) during a read operation, the sense amplifier reference voltage being driven by the sense amplifier reference circuit and not by the reference voltage holding circuit during a read operation.
Please refer to fig. 2 and 3. Fig. 2 is referenced in the following disclosure along with fig. 3. The sense amplifier circuit 200 (300) will include, but is not limited to: a sense amplifier reference circuit 201 (301) configured to generate a sense amplifier reference voltage sainr; a main sense amplifier circuit 203 (303) configured to receive a sense amplifier reference voltage sainr and generate a voltage signal sain by converting a cell current 322 from a memory cell of the main sense amplifier circuit 203 (303), and compare the voltage signal sain voltage with the sense amplifier reference voltage sainr; and a reference voltage holding circuit 302 configured to maintain the sense amplifier reference voltage sainr when the sense amplifier 200 (300) is operating in standby operation.
The reference voltage holding circuit 202 (302) will include, but is not limited to: a reference voltage generation circuit 211 configured to provide a bias reference voltage nbias; a current generation circuit 212 electrically connected to the reference voltage generation circuit 211 and configured to receive the bias reference voltage nbias to output a standby bias voltage sainr_stby and a standby bias current Ibias3; and a voltage pull-up circuit 213 electrically coupled to the current generation circuit 212 and configured to provide a standby bias current Ibias3 and pull up the standby bias voltage sainr_stby, the standby bias voltage sainr_stby driving the sense amplifier reference voltage sainr when the reference voltage holding circuit 202 (302) is operating in standby operation, and approaching the sense amplifier reference voltage sainr as long as the sense amplifier reference circuit 201 (301) is enabled.
Notably, both the sense amplifier reference circuit 201 (301) and the main sense amplifier circuit 203 (303) are turned off during standby mode to reduce power consumption. During standby mode, the sense amplifier reference circuit 201 (301) may float (float), and the sense amplifier reference voltage sainr is determined by the competition between the first Ioff current 316 and the second Ioff current 320. For example, if the first Ioff current 316 is higher than the second Ioff current 320, the sense amplifier reference voltage sainr may approach vdd. Otherwise, if the first Ioff current 316 is less than the second Ioff current 320, the sense amplifier reference voltage sainr may approach ground. When the sense amplifier reference circuit 201 (301) and the main sense amplifier circuit 203 (303) exit the standby mode and enter the active read mode, the sense amplifier reference voltage sainr requires little time to charge or discharge because any one of the reference voltage holding circuits 202 (302) maintains the sense amplifier reference voltage sainr. Thus, even though the sense amplifier reference circuit 201 (301) must provide the sense amplifier reference voltage sainr to many main sense amplifier circuits (e.g., 203 (303)), the sense amplifier reference voltage sainr will require significantly less time to charge without having to slow down the clock frequency to perform a read operation or resort to strategies such as adding an additional dummy clock (additional dummy clocks) before the first data output occurs.
According to an embodiment, the reference voltage generating circuit 211 may be a bandgap voltage reference circuit 311, the bandgap voltage reference circuit 311 being enabled when the reference voltage holding circuit 202 (302) is in both standby operation and read operation.
According to an embodiment, the current generation circuit 212 may include a first transistor 312 that receives the bias reference voltage nbias to generate a first bias current Ibias1 current, a second transistor 313 that generates a second bias current Ibias2 by mirroring the first bias current Ibias1, and a third transistor 314 that mirrors the second bias current Ibias2 to generate a standby bias current Ibias3, the standby bias current Ibias3 being set to be N times smaller than a reference current Iref (i.e., a second Ioff current 320) of the reference cell RC of the sense amplifier reference circuit 201 (301).
According to an embodiment, the voltage pull-up circuit 213 may include a first P-type transistor 315, the first P-type transistor 315 pulling up the standby bias voltage sainr_stby by setting the first P-type transistor 315 to have a width-to-length ratio that is N times smaller than a width-to-length ratio of a corresponding P-type transistor PT of the sense amplifier reference circuit 301. N may be set to meet the current consumption target of the reference voltage holding circuit 302 during standby mode. The voltage pull-up circuit 213 may further include a second P-type transistor 317 having a gate terminal, a drain terminal, and a source terminal. The source terminal may be connected to a drain-to-drain voltage (vdd), the drain terminal may be connected to the first P-type transistor 315, and the gate terminal may be configured to receive a deep power down signal dpdown that remains low to keep the first P-type transistor 315 and the second P-type transistor 317 active as long as the reference voltage holding circuit 302 is not deep powered down (or is not operating in a deep power down mode). But when operating in the deep power down mode, the deep power down signal dpdown is pulled high to turn off the second P-type transistor 317 to turn off the standby bias current Ibias3.
According to an embodiment, the reference voltage holding circuit 202 may further include a switching circuit 214, the switching circuit 214 being configured to decouple the standby bias voltage sainr_stby from the sense amplifier reference voltage sainr during a read operation (i.e., an active read mode) during which the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuit 201 (301) and not driven by the reference voltage holding circuit 202 (302). During standby operation (i.e., standby mode), however, switching circuit 214 is activated to enable coupling of sense amplifier reference voltage sainr to standby bias voltage sainr_stby such that sense amplifier reference voltage sainr is maintained by standby bias voltage sainr_stby.
According to an embodiment, the sense amplifier reference circuit 201 (301) and the main sense amplifier circuit 203 (303) have multiple terminals that receive the sense amplifier enable signal saeb signal. The sense amplifier enable signal saeb is pulled low in a read operation during which the standby bias voltage sainr_stby is decoupled from the sense amplifier reference voltage sainr because the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuit 201 (301) and not driven by the reference voltage holding circuit 202 (302). According to an embodiment, the sense amplifier reference circuit 201 (301) may be connected to multiple main sense amplifier circuits (e.g., 303) resulting in a large capacitance value of the sense amplifier reference voltage sainr of the sense amplifier reference circuit 201 (301).
The principle of operation of fig. 3 is further elucidated as follows. For the bandgap voltage reference circuit 311, a low power bandgap reference voltage generation (bandgap reference voltage generation, BGR) circuit may be used and will always be enabled both in standby operation (i.e., standby mode) and in read operation (i.e., active read mode). The bandgap voltage reference circuit 311 will provide a bias reference voltage nbias, which is used to generate the first bias current Ibias1 from the first transistor 312. The first bias current Ibias1 is then mirrored by the second transistor 313 to a second bias current Ibias2 current, which is then mirrored by the third transistor 314 to a standby bias current Ibias3.
The standby bias current Ibias3 may be set to be about N times smaller than the reference current Iref, and N may be 100 as an example. In other words, ibias 3=ibias 1=ibias 2=iref/100, and a reference current Iref of about 1/100 is generated to bias the standby bias voltage sainr_stby. In addition, it has been determined that when the sense amplifier reference circuit 301 is enabled, the length of the first P-type transistor 315 may be N times longer than the corresponding P-type transistor PT in the sense amplifier reference circuit 301 such that the standby bias voltage sainr_stby is very similar to the sense amplifier reference voltage sainr. It should be noted, however, that 100 is merely an exemplary number and may be adjusted based on design changes or based on changes in the requirements of the sense amplifier circuit 300.
The standby bias voltage sainr_stby is always activated during both standby mode and active read mode. However, when operating in the standby mode, the standby bias voltage sainr_stby drives the sense amplifier reference voltage sainr, which may present a large capacitive load to accelerate the boosting operation by maintaining the sense amplifier reference voltage sainr when transitioning from the standby mode to the active read mode. Principally, the SAINR keeper (i.e., reference voltage keeper circuit 202 (302)) is used to keep the node "sense amplifier reference voltage SAINR" when both the sense amplifier reference circuit 301 and the main sense amplifier circuit are turned off during standby mode.
When operating in the active read mode, the standby bias voltage sainr_stby is decoupled from the sense amplifier reference voltage sainr because the sense amplifier reference voltage sainr is driven by the sense amplifier reference circuit 301. This decoupling may be achieved by the switching circuit 214, which switching circuit 214 may include a transmission gate 318 and an inverter 319. The P-type gate of transfer gate 318 may receive the idle enable signal idleb and pull the idle enable signal idleb high when the sense amplifier enable signal saeb signal is asserted low. By setting the idle enable signal idleb high, the transfer gate 318 will be turned off to decouple the sense amplifier reference voltage sainr from the standby bias voltage sainr_stby. When operating in standby mode, the idle enable signal idleb is asserted low.
When operating in the deep power down mode, the deep power down signal dpdown is asserted high to turn off the second P-type transistor 317, which in turn will cause the standby bias current Ibias3 to turn off. During the deep power down mode, the sense amplifier reference circuit 301, the reference voltage holding circuit 302, and the main sense amplifier circuit 303 are turned off. When not operating in the deep power down mode, the deep power down signal dpdown is asserted low.
In view of the foregoing, the present invention is applicable to be employed as part of a read mechanism of a nonvolatile memory storage device, and the present invention can realize at least one of the advantages including lower hardware cost, lower standby current burden, and dissociation between read speed and the number of sense amplifiers. The reduction of hardware cost can be achieved by: one reference voltage holding circuit 302 is added to the sense amplifier reference circuit (e.g., 301) and one or more main sense amplifier circuits (e.g., 303) without having to divide the main sense amplifier circuits (e.g., 303) into multiple groups to reduce the number of main sense amplifier circuits (e.g., 303) to be serviced by the sense amplifier reference circuit (e.g., 301) and without having to add an additional dummy clock before the first data output occurs.
No element, act, or instruction used in the detailed description of the embodiments disclosed herein should be construed as critical or essential to the invention unless explicitly described as such. Furthermore, as used herein, each of the indefinite articles "a" and "an" may include more than one item. If only one item is desired, the term "single" or similar language will be used. Further, as used herein, the term "..the term" preceding a list of a plurality of items and/or a plurality of item categories "is intended to encompass any one of the items and/or item categories, individually or in combination with other items and/or other item categories", any of a plurality of "and/or any combination of a plurality of" in the term. Furthermore, as used herein, the term "collection" is intended to encompass any number of items, including zero. Furthermore, as used herein, the term "number" is intended to include any number, including zero.
Those skilled in the art will appreciate that various modifications and changes may be made to the structures of the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.
Claims (12)
1. A reference voltage holding circuit for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, the reference voltage holding circuit comprising:
a reference voltage generation circuit configured to provide a bias reference voltage;
a current generation circuit electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and
a voltage pull-up circuit electrically coupled to the current generation circuit and configured to provide the standby bias current and maintain the standby bias voltage that drives the sense amplifier reference voltage when the reference voltage holding circuit is operating in standby operation and approaches the sense amplifier reference voltage as long as the sense amplifier reference circuit remains enabled.
2. The reference voltage holding circuit of claim 1, wherein the current generating circuit comprises:
a first transistor receiving the bias reference voltage to generate a first bias current;
a second transistor generating a second bias current by mirroring the first bias current; and
and a third transistor mirroring the second bias current to generate a third bias current, the third bias current being set to be N times smaller than a reference current of a reference cell of the sense amplifier reference circuit.
3. The reference voltage holding circuit of claim 2, wherein the voltage pull-up circuit comprises:
a first P-type transistor that pulls up the standby bias voltage by setting the first P-type transistor to have a width-to-length ratio that is N times smaller than a width-to-length ratio of a corresponding P-type transistor of the sense amplifier reference circuit.
4. The reference voltage holding circuit of claim 3, wherein N is a number set to meet a current consumption target of the reference voltage holding circuit during standby mode.
5. The reference voltage holding circuit of claim 1, wherein the reference voltage generating circuit is a bandgap voltage reference circuit that is activated when the reference voltage holding circuit is in the standby operation and is also activated when the reference voltage holding circuit is performing a read operation.
6. The reference voltage holding circuit of claim 3, wherein the voltage pull-up circuit further comprises a second P-type transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to a drain-to-drain voltage, the second terminal is connected to the first P-type transistor, and the third terminal is configured to receive a deep power down signal that remains low as long as the reference voltage holding circuit is not deep powered down.
7. The reference voltage holding circuit of claim 6, wherein the deep power down signal is pulled high to turn off the second P-type transistor to turn off the third bias current.
8. The reference voltage holding circuit of claim 1, further comprising:
a switching circuit configured to decouple the standby bias voltage from the sense amplifier reference voltage during a read operation, the sense amplifier reference voltage being driven by the sense amplifier reference circuit and not being driven by the reference voltage holding circuit during the read operation.
9. The reference voltage holding circuit of claim 1, wherein the current generating circuit comprises a resistor configured to generate the bias reference voltage to output the standby bias voltage and the standby bias current.
10. A sense amplifier circuit comprising:
a sense amplifier reference circuit configured to generate a sense amplifier reference voltage;
a main sense amplifier circuit configured to receive the sense amplifier reference voltage and compare a voltage signal from a memory cell of the main sense amplifier circuit with the sense amplifier reference voltage; and
a reference voltage holding circuit configured to maintain the sense amplifier reference voltage when the sense amplifier is operating in standby operation, wherein
The reference voltage holding circuit includes:
a reference voltage generation circuit configured to provide a bias reference voltage;
a current generation circuit electrically coupled to the reference voltage generation circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and
a voltage pull-up circuit electrically coupled to the current generation circuit and configured to provide the standby bias current and pull up the standby bias voltage that drives the sense amplifier reference voltage when the reference voltage holding circuit is operating in the standby operation and approaches the sense amplifier reference voltage as long as the sense amplifier reference circuit remains enabled.
11. The sense amplifier circuit of claim 10, wherein the sense amplifier reference circuit and the main sense amplifier circuit receive a sense amplifier enable signal that is pulled low in a read operation during which the standby bias voltage is decoupled from the sense amplifier reference voltage and the sense amplifier reference voltage is driven by the sense amplifier reference circuit and not driven by the reference voltage holding circuit.
12. The sense amplifier circuit of claim 10, wherein a sense amplifier reference circuit is connected to a plurality of main sense amplifier circuits, and the sense amplifier reference voltage of the sense amplifier reference circuit has a large capacitance value.
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