TWI713591B - Laminate substrate, conductive substrate, manufacturing method of multilayer substrate, manufacturing method of conductive substrate - Google Patents

Laminate substrate, conductive substrate, manufacturing method of multilayer substrate, manufacturing method of conductive substrate Download PDF

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TWI713591B
TWI713591B TW105131030A TW105131030A TWI713591B TW I713591 B TWI713591 B TW I713591B TW 105131030 A TW105131030 A TW 105131030A TW 105131030 A TW105131030 A TW 105131030A TW I713591 B TWI713591 B TW I713591B
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layer
low
copper
substrate
reflectivity alloy
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TW201726401A (en
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永田純一
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日商住友金屬礦山股份有限公司
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00Layered products comprising a layer of metal
    • B32B15/01Layered products comprising a layer of metal all layers being exclusively metallic
    • B32B15/013Layered products comprising a layer of metal all layers being exclusively metallic one layer being formed of an iron alloy or steel, another layer being formed of a metal other than iron or aluminium
    • B32B15/015Layered products comprising a layer of metal all layers being exclusively metallic one layer being formed of an iron alloy or steel, another layer being formed of a metal other than iron or aluminium the said other metal being copper or nickel or an alloy thereof
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00Layered products comprising a layer of metal
    • B32B15/01Layered products comprising a layer of metal all layers being exclusively metallic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/18Metallic material, boron or silicon on other inorganic substrates
    • C23C14/185Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/20Metallic material, boron or silicon on organic substrates
    • C23C14/205Metallic material, boron or silicon on organic substrates by cathodic sputtering
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/35Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/021Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material including at least one metal alloy layer
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/02Local etching
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01BCABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B13/00Apparatus or processes specially adapted for manufacturing conductors or cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01BCABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B13/00Apparatus or processes specially adapted for manufacturing conductors or cables
    • H01B13/0026Apparatus for manufacturing conducting or semi-conducting layers, e.g. deposition of metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01BCABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B5/00Non-insulated conductors or conductive bodies characterised by their form
    • H01B5/14Non-insulated conductors or conductive bodies characterised by their form comprising conductive layers or films on insulating-supports
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00Electrical equipment
    • B32B2457/20Displays, e.g. liquid crystal displays, plasma displays
    • B32B2457/208Touch screens

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  • Engineering & Computer Science (AREA)
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  • Laminated Bodies (AREA)
  • Manufacturing Of Electric Cables (AREA)
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Abstract

提供一種積層體基板,其具備:透明基材、及積層體,其形成在該透明基材之至少一個面側。該積層體具有:低反射率合金層,其含有銅和鎳;及銅層。該低反射率合金層中所含有之該銅和該鎳中之該鎳之比率為30質量%以上且85質量%以下。 Provided is a laminated body substrate including a transparent base material and a laminated body formed on at least one surface side of the transparent base material. This laminate has: a low-reflectivity alloy layer containing copper and nickel; and a copper layer. The ratio of the copper contained in the low-reflectivity alloy layer to the nickel in the nickel is 30% by mass or more and 85% by mass or less.

Description

積層體基板、導電性基板、積層體基板之製造方法、導電性基板之製造方法 Laminate substrate, conductive substrate, manufacturing method of multilayer substrate, and manufacturing method of conductive substrate

本發明涉及積層體基板、導電性基板、積層體基板之製造方法及導電性基板之製造方法。 The present invention relates to a multilayer substrate, a conductive substrate, a method of manufacturing a multilayer substrate, and a method of manufacturing a conductive substrate.

如專利文獻1所述,先前技術中使用了一種在透明高分子膜等透明基材之表面形成ITO(氧化銦-錫)膜之觸控板用透明導電性膜作為透明導電膜。 As described in Patent Document 1, in the prior art, a transparent conductive film for touch panels in which an ITO (indium oxide-tin) film is formed on the surface of a transparent substrate such as a transparent polymer film is used as a transparent conductive film.

然,近年具備觸控板之顯示器正趨於大畫面化,與此相對應地,觸控板用透明導電性膜等導電性基板也正被要求大面積化。然由於ITO之電阻值較高,故存在不能與導電性基板之大面積化進行對應之問題。 However, in recent years, displays equipped with touch panels are becoming larger screens. Correspondingly, conductive substrates such as transparent conductive films for touch panels are also being required to have larger areas. However, due to the high resistance value of ITO, there is a problem that it cannot cope with the larger area of the conductive substrate.

為此,例如,如專利文獻2、3所述進行了使用銅等配線取代ITO配線之研討。然例如在配線中使用銅之情況下,由於銅具有金屬光澤,故存在因反射導致顯示器之視認性下降之問題。 For this reason, for example, as described in Patent Documents 2 and 3, studies have been conducted to replace ITO wiring with wiring such as copper. However, for example, in the case of using copper in wiring, since copper has metallic luster, there is a problem that the visibility of the display decreases due to reflection.

因此,研究與銅等配線一起在配線之與透明基材之表面平行之面上形成由黑色材料構成之黑化層之導電性基板。 Therefore, a conductive substrate in which a blackened layer made of black material is formed on the surface of the wiring parallel to the surface of the transparent substrate together with wiring such as copper has been studied.

【先行技術文獻】 【Advanced Technical Literature】 〔專利文獻〕 〔Patent Literature〕

〔專利文獻1〕日本特開2003-151358號公報 [Patent Document 1] Japanese Patent Application Publication No. 2003-151358

〔專利文獻2〕日本特開2011-018194號公報 [Patent Document 2] Japanese Patent Application Publication No. 2011-018194

〔專利文獻3〕日本特開2013-069261號公報 [Patent Document 3] JP 2013-069261 A

然透明基材上具備銅配線之導電性基板,是在獲得了於透明基材表面形成了銅層之積層體基板之後,藉由將銅層蝕刻為預期之配線圖案以形成銅配線之方式而獲得。又,在透明基材上具有黑化層和銅配線之導電性基板,是在獲得了於透明基材表面依次進行了黑化層和銅層之積層之積層體基板後,藉由將黑化層和銅層蝕刻為預期之配線圖案以形成配線之方式而獲得。 However, a conductive substrate with copper wiring on a transparent substrate is a method of forming a copper wiring by etching the copper layer into a desired wiring pattern after obtaining a laminate substrate with a copper layer formed on the surface of the transparent substrate. obtain. In addition, a conductive substrate with a blackened layer and copper wiring on a transparent substrate is obtained by combining the blackened layer and the copper layer on the surface of the transparent substrate. The layer is etched into the desired wiring pattern to obtain the wiring pattern.

藉由對黑化層和銅層進行蝕刻,例如,如圖1A所示可形成在透明基材1上積層經圖案化了之黑化層2和藉由對銅層進行圖案化而獲得之銅配線3的導電性基板。在此情況下,經圖案化了之黑化層2之寬度WA和銅配線3之寬度WB較佳為大致相同。 By etching the blackened layer and the copper layer, for example, as shown in FIG. 1A, a patterned blackened layer 2 and a copper wiring obtained by patterning the copper layer can be formed on the transparent substrate 1 3 conductive substrate. In this case, the patterned width of the black layer 2 of copper wiring width W A and W B 3 is preferably of substantially the same.

然存在銅層和黑化層對蝕刻液之反應性大不相同之問題。即,如果想同時對銅層和黑化層進行蝕刻,則存在無論哪個層都不能被蝕刻成如圖1A所示之想要之形狀的問題。 However, there is a problem that the reactivity of the copper layer and the blackened layer to the etching solution is very different. That is, if it is desired to simultaneously etch the copper layer and the blackened layer, there is a problem that neither layer can be etched into the desired shape as shown in FIG. 1A.

例如,在與銅層相比,黑化層之蝕刻速度很慢之情況下,如圖1B所示,作為經圖案化了之銅層之銅配線3之側面會被蝕刻,產生所謂之側蝕。因此,金屬配線3之剖面形狀容易變成下部較寬之梯形形狀,如果蝕刻至可確保金屬配線3之間之電氣絕緣性,則存在配線間距寬度過寬之問題。 For example, in the case where the etching speed of the blackened layer is very slow compared with the copper layer, as shown in FIG. 1B, the side surface of the copper wiring 3 as the patterned copper layer will be etched, resulting in so-called undercut . Therefore, the cross-sectional shape of the metal wiring 3 is likely to become a wider trapezoid shape at the lower part. If the metal wiring 3 is etched to ensure electrical insulation between the metal wirings 3, there is a problem that the wiring pitch width is too wide.

又,在與銅層相比,黑化層之蝕刻速度很快之情況下,如圖1C所示,經圖案化了之黑化層2之寬度(底部寬度)WA會變為小於銅配線3之寬度WB之狀態,存在會發生所謂之底切之情況。發生了此種底切後,與所定之銅配線3之寬度WB相比,作為與透明基材1進行密接之密接寬度即經圖案化了之黑化層2之底部寬度WA視情況變小,如果密接寬度之比率低至必須程度以下,則存在無法獲得充分之配線密接強度之問題。 Moreover, when the etching speed of the blackened layer is faster than that of the copper layer, as shown in FIG. 1C, the width (bottom width) W A of the patterned blackened layer 2 becomes smaller than that of the copper wiring In the state of width W B of 3, the so-called undercut may occur. Such undercutting occurred after the comparison with a predetermined copper wiring width of 3 W B, and the transparent substrate 1 as adhesion i.e. the adhesion width of the patterned black layer width W A of the bottom 2, as the case becomes If the ratio of the bonding width is lower than necessary, there is a problem that sufficient wiring bonding strength cannot be obtained.

又,如果不同時對銅層和黑化層進行蝕刻,而是採用個別步驟來進行銅層之蝕刻和黑化層之蝕刻,則存在步驟數增加之問題。 Moreover, if the copper layer and the blackened layer are not etched at the same time, but separate steps are used to perform the etching of the copper layer and the blackened layer, there is a problem that the number of steps increases.

鑑於上述先前技術之問題,本發明之目的在於提供一種具備可同時進行蝕刻處理之銅層和低反射率合金層之積層體基板。 In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a laminate substrate having a copper layer and a low-reflectivity alloy layer that can be etched simultaneously.

為了解決上述課題,本發明提供一種積層體基板,其具備:透明基材、及積層體,其形成在該透明基材之至少一個面側;該積層體具有:含有銅和鎳之低反射率合金層、及銅層,該低反射率合金層中所含有之該銅和該鎳中之該鎳之比率為30質量%以上且85質量%以下。 In order to solve the above-mentioned problems, the present invention provides a laminate substrate comprising: a transparent substrate and a laminate formed on at least one surface side of the transparent substrate; the laminate has: low reflectance containing copper and nickel In the alloy layer and the copper layer, the ratio of the copper contained in the low-reflectivity alloy layer to the nickel in the nickel is 30% by mass or more and 85% by mass or less.

根據本發明,能夠提供一種具備可同時進行蝕刻處理之銅層和低反射率合金層之積層體基板。 According to the present invention, it is possible to provide a laminate substrate provided with a copper layer and a low-reflectivity alloy layer that can be simultaneously etched.

10A、10B、20A、20B‧‧‧積層體基板 10A, 10B, 20A, 20B‧‧‧Laminate substrate

11‧‧‧透明基材 11‧‧‧Transparent substrate

12、12A、12B‧‧‧銅層 12, 12A, 12B‧‧‧copper layer

13、13A、13B、131、132、131A、131B、132A、132B‧‧‧低反射率合金層 13, 13A, 13B, 131, 132, 131A, 131B, 132A, 132B‧‧‧Low reflectivity alloy layer

30‧‧‧導電性基板 30‧‧‧Conductive substrate

31A、31B‧‧‧銅配線層 31A, 31B‧‧‧Copper wiring layer

321A、321B、322A、322B‧‧‧低反射率合金配線層 321A, 321B, 322A, 322B‧‧‧Low reflectivity alloy wiring layer

〔圖1A〕在先前導電性基板中同時對銅層和黑化層進行蝕刻之情況之說明圖。 [FIG. 1A] An explanatory diagram of the case where the copper layer and the blackened layer are simultaneously etched in the conventional conductive substrate.

〔圖1B〕在先前導電性基板中同時對銅層和黑化層進行蝕刻之情況之說明圖。 [Fig. 1B] An explanatory diagram of the case where the copper layer and the blackened layer are simultaneously etched on the conventional conductive substrate.

〔圖1C〕在先前導電性基板中同時對銅層和黑化層進行蝕刻之情況之說明圖。 [FIG. 1C] An explanatory diagram of the case where the copper layer and the blackened layer are simultaneously etched in the conventional conductive substrate.

〔圖2A〕本發明實施方式之積層體基板之剖面圖。 [FIG. 2A] A cross-sectional view of a laminate substrate according to an embodiment of the present invention.

〔圖2B〕本發明實施方式之積層體基板之剖面圖。 [FIG. 2B] A cross-sectional view of a laminate substrate according to an embodiment of the present invention.

〔圖3A〕本發明實施方式之積層體基板之剖面圖。 [FIG. 3A] A cross-sectional view of a laminate substrate according to an embodiment of the present invention.

〔圖3B〕本發明實施方式之積層體基板之剖面圖。 [FIG. 3B] A cross-sectional view of a laminate substrate according to an embodiment of the present invention.

〔圖4〕本發明實施方式之具備網狀配線之導電性基板之俯視圖。 [FIG. 4] A plan view of a conductive substrate with mesh wiring according to an embodiment of the present invention.

〔圖5〕沿第4圖之A-A’線之剖面圖。 [Figure 5] A cross-sectional view along the line A-A' in Figure 4.

〔圖6〕輥對輥濺鍍裝置之說明圖。 [Figure 6] An explanatory diagram of a roll-to-roll sputtering device.

以下對本發明之積層體基板、導電性基板、積層體基板之製造方法及導電性基板之製造方法之一實施方式進行說明。 Hereinafter, one embodiment of the multilayer substrate, the conductive substrate, the manufacturing method of the multilayer substrate, and the manufacturing method of the conductive substrate of the present invention will be described.

(積層體基板和導電性基板) (Laminate substrate and conductive substrate)

本實施方式之積層體基板可具備透明基材和在透明基材之至少一個面側形成之積層體。又,積層體具有:含有銅和鎳之低反射率合金層、及銅層,低反射率合金層中所含有之銅和鎳中之鎳之比率可為30質量%以上且85質量%以下。 The laminate substrate of the present embodiment may include a transparent substrate and a laminate formed on at least one surface side of the transparent substrate. In addition, the laminate has a low-reflectivity alloy layer containing copper and nickel, and a copper layer. The ratio of copper contained in the low-reflectivity alloy layer and nickel in nickel may be 30% by mass or more and 85% by mass or less.

需要說明的是,本實施方式之積層體基板是指在透明基材表 面具有圖案化前之銅層或低反射率合金層之基板。又,導電性基板是指在透明基材表面上具有經圖案化為配線形狀之銅配線層或低反射率合金配線層之配線基板。 It should be noted that the laminate substrate of this embodiment refers to the surface of the transparent substrate A substrate with a copper layer or a low-reflectivity alloy layer before patterning. In addition, the conductive substrate refers to a wiring substrate having a copper wiring layer or a low-reflectivity alloy wiring layer patterned into a wiring shape on the surface of a transparent substrate.

這裡首先對本實施方式之積層體基板中所含有之各構件在以下進行說明。 Here, first, each member contained in the laminate substrate of this embodiment will be described below.

作為透明基材對其並無特別限定,較佳可使用可視光能穿透之高分子膜或玻璃基板等。 The transparent substrate is not particularly limited, and it is preferable to use a polymer film or a glass substrate that can penetrate visible light.

作為可視光能穿透之高分子膜,例如較佳可使用聚醯胺(PA)系薄膜、聚對苯二甲酸乙二酯(PET)系薄膜,聚萘二甲酸乙二醇酯(PEN)系薄膜、環烯烴系薄膜、聚醯亞胺(PI)系薄膜及聚碳酸酯(PC)系薄膜等樹脂膜。 As a polymer film that can penetrate visible light, for example, a polyamide (PA)-based film, a polyethylene terephthalate (PET)-based film, and polyethylene naphthalate (PEN) are preferably used. Resin films such as films, cycloolefin films, polyimide (PI) films, and polycarbonate (PC) films.

對透明基材厚度並無特別限定,在作為導電性基板使用之情況下,可根據所要求之強度或光之穿透率等進行任意選擇。作為透明基材厚度例如可為10μm以上且250μm以下。特別在用於觸控板之用途之情況下,較佳為20μm以上且200μm以下,優選為20μm以上且120μm以下。在用於觸控板之用途之情況下,例如特別是在需要使顯示器之整體厚度變薄之用途中,透明基材厚度較佳為20μm以上且100μm以下。 The thickness of the transparent substrate is not particularly limited, and when it is used as a conductive substrate, it can be arbitrarily selected according to the required intensity or light transmittance. The thickness of the transparent substrate may be, for example, 10 μm or more and 250 μm or less. Especially in the case of use for a touch panel, it is preferably 20 μm or more and 200 μm or less, and preferably 20 μm or more and 120 μm or less. In the case of use for a touch panel, for example, particularly in applications where the overall thickness of the display needs to be reduced, the thickness of the transparent substrate is preferably 20 μm or more and 100 μm or less.

接下來對積層體進行說明。積層體形成在透明基材之至少一個面側,並可具有低反射率合金層和銅層。 Next, the laminate will be described. The laminate is formed on at least one surface side of the transparent substrate, and may have a low reflectivity alloy layer and a copper layer.

這裡首先對銅層進行說明。 First, the copper layer will be described.

對銅層並無特別限定,然為了不降低光之穿透率,銅層和透明基材之間或銅層和低反射率合金層之間較佳為不配置接著劑。即,銅層 較佳為直接形成在其他構件之上表面。 The copper layer is not particularly limited, but in order not to reduce the light transmittance, it is preferable that no adhesive is disposed between the copper layer and the transparent substrate or between the copper layer and the low-reflectivity alloy layer. That is, the copper layer It is preferably formed directly on the upper surface of other members.

為了在其他構件之上表面直接形成銅層,可採用濺鍍法,離子鍍法或蒸鍍法等乾式鍍法形成銅薄膜層,並將該銅薄膜層作為銅層。 In order to directly form a copper layer on the upper surface of other components, a dry plating method such as sputtering, ion plating, or evaporation may be used to form a copper thin film layer, and the copper thin film layer can be used as the copper layer.

又,在使銅層較厚之情況下,較佳為在採用乾式鍍法形成銅薄膜層之後使用濕式鍍法。即,例如在透明基材或低反射率合金層上採用乾式鍍法形成銅薄膜層後,可將該銅薄膜層作為供電層,並採用濕式鍍法形成鍍銅層。在此情況下,銅層具有銅薄膜層及鍍銅層。 Moreover, in the case of making the copper layer thick, it is preferable to use the wet plating method after forming the copper thin film layer by the dry plating method. That is, for example, after a copper thin film layer is formed by a dry plating method on a transparent substrate or a low-reflectivity alloy layer, the copper thin film layer can be used as a power supply layer, and a wet plating method can be used to form the copper plating layer. In this case, the copper layer has a copper thin film layer and a copper plating layer.

如上所述,藉由僅採用乾式鍍法或採用乾式鍍法和濕式鍍法之組合來形成銅層,可在透明基材或低反射率合金層上不使用接著劑地直接形成銅層,故為較佳。 As mentioned above, by using only the dry plating method or a combination of dry plating and wet plating to form the copper layer, the copper layer can be directly formed on the transparent substrate or the low-reflectivity alloy layer without using an adhesive. Therefore, it is better.

對銅層厚度並無特別限定,在將銅層使用為配線之情況下,可根據該配線之電阻值或配線寬度等任意選擇。特別地,為了可充分地進行電氣流動,銅層厚度較佳為50nm以上,優選為60nm以上,進而較佳為150nm以上。對銅層厚度之上限值並無特別限定,然如果銅層變厚,則由於為了形成配線而進行蝕刻時該蝕刻所需之時間變長,故會發生側蝕,並容易產生蝕刻途中光阻剝離等之問題。為此,銅層厚度較佳為5000nm以下,優選為3000nm以下。需要說明的是,在銅層如上所述地具有銅薄膜層和鍍銅層之情況下,銅薄膜層之厚度和鍍銅層厚度之合計較佳為位於上述範圍內。 The thickness of the copper layer is not particularly limited, and when the copper layer is used as wiring, it can be arbitrarily selected according to the resistance value of the wiring or the wiring width. In particular, in order to allow sufficient electrical flow, the thickness of the copper layer is preferably 50 nm or more, preferably 60 nm or more, and more preferably 150 nm or more. The upper limit of the thickness of the copper layer is not particularly limited. However, if the copper layer becomes thicker, the time required for the etching when etching to form wiring becomes longer, so side etching may occur and light during etching is likely to occur. Problems such as resistance to peeling. For this reason, the thickness of the copper layer is preferably 5000 nm or less, preferably 3000 nm or less. In addition, when the copper layer has a copper thin film layer and a copper plating layer as mentioned above, the sum of the thickness of a copper thin film layer and the thickness of a copper plating layer is preferably in the said range.

接下來對低反射率合金層進行說明。 Next, the low-reflectivity alloy layer will be described.

由於銅層具有金屬光澤,若在透明基材上僅對銅層進行蝕刻以形成作為配線之銅配線層,如上所述,銅會反射光,例如在作為觸控板 用配線基板使用之情況下,會存在顯示器之視認性下降之問題。因此,進行了設置黑化層之研討,然,由於存在黑化層相對蝕刻液之反應性不足之情況,故難以將銅層和黑化層同時蝕刻為預期之形狀。 Since the copper layer has metallic luster, if only the copper layer is etched on a transparent substrate to form a copper wiring layer as wiring, as mentioned above, copper will reflect light, for example, when used as a touch panel In the case of using a wiring board, the visibility of the display will decrease. Therefore, a study on the provision of a blackened layer was conducted. However, due to the insufficient reactivity of the blackened layer with respect to the etching solution, it is difficult to simultaneously etch the copper layer and the blackened layer into a desired shape.

相對於此,本實施方式之積層體基板上所配置之低反射率合金層具有銅和鎳。因此,本實施方式之積層體基板上所配置之低反射率合金層對蝕刻液之反應性與銅層對蝕刻液之反應性基乎無差異,蝕刻性也較好。因此,在本實施方式之積層體基板中可同時對銅層及含有銅和鎳之低反射率合金層進行蝕刻。 In contrast, the low-reflectivity alloy layer disposed on the laminate substrate of the present embodiment has copper and nickel. Therefore, the reactivity of the low-reflectivity alloy layer disposed on the laminate substrate of the present embodiment to the etching solution is almost the same as the reactivity of the copper layer to the etching solution, and the etching performance is also better. Therefore, in the laminate substrate of this embodiment, the copper layer and the low-reflectivity alloy layer containing copper and nickel can be simultaneously etched.

以下對本實施方式之積層體基板所配置之低反射率合金層可與銅層同時進行蝕刻這點進行說明。 Hereinafter, the point that the low-reflectivity alloy layer disposed on the laminate substrate of the present embodiment can be etched simultaneously with the copper layer will be described.

本發明之發明人等最初對作為可抑制銅層表面之光反射之黑化層之、對銅層之一部分進行了氧化之氧化銅層之形成方法進行了研討,並發現在對銅層之一部分進行氧化以將其作為黑化層時,存在該黑化層中會包含不定比例之銅氧化物或未被氧化之銅之情況。 The inventors of the present invention first studied the method of forming a copper oxide layer that oxidizes a part of the copper layer, which is a blackening layer that can suppress light reflection on the surface of the copper layer, and found that a part of the copper layer When it is oxidized to use it as a blackened layer, the blackened layer may contain an indefinite proportion of copper oxide or unoxidized copper.

在對具備銅層及黑化層之積層體基板之銅層及黑化層同時進行蝕刻之情況下,作為蝕刻液,例如可較佳使用能對銅層進行蝕刻之蝕刻液。又,根據本發明之發明人之研究可知,在黑化層中含有不定比例之銅氧化物之情況下,其比較容易溶解至可對銅層進行蝕刻之蝕刻液中。 When simultaneously etching the copper layer and the blackened layer of the laminate substrate provided with the copper layer and the blackened layer, as the etching solution, for example, an etching solution capable of etching the copper layer can be preferably used. In addition, according to the research of the inventor of the present invention, it is known that when the blackened layer contains copper oxide in an indefinite proportion, it is relatively easy to dissolve into an etching solution that can etch the copper layer.

如此,在黑化層中含有容易溶解至蝕刻液中之不定比例之銅氧化物之情況下,黑化層對蝕刻液之反應性較高,與銅層相比,黑化層之蝕刻速度大幅提高。因此,在同時對銅層和黑化層進行蝕刻處理之情況下,黑化層容易發生底切。 In this way, when the blackened layer contains an indefinite proportion of copper oxide that is easily dissolved in the etching solution, the blackened layer is more reactive to the etching solution. Compared with the copper layer, the etching speed of the blackened layer is greater improve. Therefore, when the copper layer and the blackened layer are simultaneously etched, the blackened layer is prone to undercut.

因此,在本實施方式之積層體基板中,為了對底切進行抑制,黑化層可為不使用氧且除了銅之外還含有不易被蝕刻液溶解之鎳成分之低反射率合金層。如此,藉由使本實施方式之積層體基板之低反射率合金層不使用氧並含有銅和鎳,其對蝕刻液之反應性可與銅層相同,據此可同時對低反射率合金層和銅層進行蝕刻。需要說明的是,由於低反射率合金層中不使用氧,故不含有氧,然也不能排除作為不可避免成分而含有極微量之情況。 Therefore, in the laminate substrate of this embodiment, in order to suppress undercutting, the blackening layer may be a low-reflectivity alloy layer that does not use oxygen and contains a nickel component that is not easily dissolved by an etching solution in addition to copper. In this way, by making the low-reflectivity alloy layer of the laminate substrate of the present embodiment not use oxygen and contain copper and nickel, its reactivity to the etching solution can be the same as that of the copper layer, so that the low-reflectivity alloy layer can be treated simultaneously And the copper layer is etched. It should be noted that since oxygen is not used in the low-reflectivity alloy layer, it does not contain oxygen, but it cannot be ruled out that it contains a very small amount as an inevitable component.

對低反射率合金層中所含有之銅和鎳中之鎳之比率並無特別限定,然,低反射率合金層中所含有之銅和鎳中之鎳之比率較佳為30質量%以上且85質量%以下。需要說明的是,鎳之比率是指如上所述在低反射率合金層中之銅和鎳之含有量合計為100質量%之情況下之比率。 The ratio of copper contained in the low reflectivity alloy layer to nickel contained in nickel is not particularly limited, however, the ratio of copper contained in the low reflectivity alloy layer to nickel contained in nickel is preferably 30% by mass or more and 85% by mass or less. It should be noted that the nickel ratio refers to the ratio when the total content of copper and nickel in the low-reflectivity alloy layer is 100% by mass as described above.

其原因在於,在低反射率合金層中所含有之銅和鎳中之鎳之比率小於30質量%之情況下,波長為400nm以上且700nm以下之光之正反射率之平均值不能設為55%以下。 The reason is that when the ratio of copper and nickel in the low-reflectivity alloy layer is less than 30% by mass, the average value of the specular reflectance of light with a wavelength of 400nm or more and 700nm or less cannot be set to 55 %the following.

另一方面,如果低反射率合金層中所含有之銅和鎳中之鎳之比率超過85質量%,則鎳會過剩,難以對低反射率合金層進行蝕刻。即,低反射率合金層至蝕刻液之溶解速度與銅層相比較慢,不能成為可與銅層同時進行蝕刻之低反射率合金層。又,如後所述,低反射率合金層例如可採用濺鍍法形成,然如果鎳之比率超過85質量%,則不能進行磁控濺鍍成膜。 On the other hand, if the ratio of the copper contained in the low-reflectivity alloy layer to the nickel in the nickel exceeds 85% by mass, nickel will be excessive and it is difficult to etch the low-reflectivity alloy layer. That is, the dissolution rate of the low-reflectivity alloy layer to the etching solution is slower than that of the copper layer, and it cannot be a low-reflectivity alloy layer that can be etched simultaneously with the copper layer. In addition, as described later, the low-reflectivity alloy layer can be formed by, for example, sputtering. However, if the ratio of nickel exceeds 85% by mass, magnetron sputtering cannot be performed.

又,在積層體基板中如後所述可在透明基材上進行低反射率合金層和銅層之積層,據此,藉由對該低反射率合金層和銅層進行圖案化, 可形成導電性基板。如果低反射率合金層中所含有之銅和鎳中之鎳之比率超過85質量%,則在對低反射率合金層或銅層進行蝕刻以形成開口部時,利用蝕刻之除去處理不足,存在可觀察到透明基材之表面變為黃色之情況。因此,如上所述,低反射率合金層中所含有之銅和鎳中之鎳之比率較佳為85質量%以下。 In addition, in the laminate substrate, as described later, a low-reflectivity alloy layer and a copper layer can be laminated on a transparent substrate. According to this, by patterning the low-reflectivity alloy layer and the copper layer, A conductive substrate can be formed. If the ratio of the copper contained in the low-reflectivity alloy layer to the nickel in the nickel exceeds 85% by mass, when the low-reflectivity alloy layer or the copper layer is etched to form an opening, the removal process by etching is insufficient, and there is It can be observed that the surface of the transparent substrate turns yellow. Therefore, as described above, the ratio of copper contained in the low-reflectivity alloy layer to nickel in nickel is preferably 85% by mass or less.

低反射率合金層中作為金屬可含有銅和鎳,這裡需要說明的是,低反射率合金層中所含有之金屬雖可僅由銅和鎳組成,然並不僅限定於銅和鎳。例如,低反射率合金層中作為金屬也可存在1質量%以下之不可避免之雜質。 The low-reflectivity alloy layer may contain copper and nickel as metals. It should be noted here that although the metal contained in the low-reflectivity alloy layer may only consist of copper and nickel, it is not limited to copper and nickel. For example, in the low-reflectivity alloy layer, as a metal, there may be inevitable impurities less than 1% by mass.

又,低反射率合金層只要含有銅和鎳即可,對各成分以何狀態含於其中並無特別限定。 In addition, the low-reflectivity alloy layer only needs to contain copper and nickel, and the state in which each component is contained is not particularly limited.

根據本實施方式之積層體基板獲得之導電性基板之銅配線層和低反射率合金配線層分別可維持本實施方式之積層體基板之銅層和低反射率合金層之特徵。 The copper wiring layer and the low-reflectivity alloy wiring layer of the conductive substrate obtained from the laminated substrate of this embodiment can maintain the characteristics of the copper layer and the low-reflectivity alloy layer of the laminated substrate of this embodiment, respectively.

對本實施方式之導電性基板上所配置之低反射率合金層之成膜方法並無特別限定。低反射率合金層例如較佳採用濺鍍法等乾式成膜法形成。 The method of forming the low-reflectivity alloy layer disposed on the conductive substrate of the present embodiment is not particularly limited. The low-reflectivity alloy layer is preferably formed by a dry film forming method such as a sputtering method.

在對低反射率合金層採用濺鍍法進行成膜之情況下,例如可使用銅-鎳合金靶材,一邊向腔體內供給作為濺鍍氣體而使用之非活性氣體,一邊進行成膜。 When the low-reflectivity alloy layer is formed by sputtering, for example, a copper-nickel alloy target may be used, and the film may be formed while supplying an inert gas used as a sputtering gas into the cavity.

在濺鍍時使用銅-鎳合金靶材之情況下,銅-鎳合金中所含有之銅和鎳中之鎳之比率較佳為30質量%以上且85質量%以下。據此,可使 所成膜之低反射率合金層中所含有之銅和鎳中之鎳之比率與對該低反射率合金層進行成膜時所使用之銅-鎳合金靶材之銅-鎳合金中所含有之銅和鎳中之鎳之比率相同。 In the case of using a copper-nickel alloy target during sputtering, the ratio of copper contained in the copper-nickel alloy to nickel in nickel is preferably 30% by mass or more and 85% by mass or less. According to this, The ratio of the copper and nickel in the formed low-reflectivity alloy layer to the ratio of the copper-nickel alloy in the copper-nickel alloy target used when forming the low-reflectivity alloy layer The ratio of nickel in copper and nickel is the same.

需要說明的是,作為進行低反射率合金層成膜時之非活性氣體,對其並無特別限定,例如較佳可使用氬氣或氙氣,優選可使用氬氣。 It should be noted that the inert gas used in the formation of the low-reflectivity alloy layer is not particularly limited. For example, argon gas or xenon gas is preferably used, and argon gas is preferably used.

對本實施方式之積層體基板中所形成之低反射率合金層之厚度並無特別限定,例如,可根據銅層表面之光反射之抑制程度等任意選擇。 The thickness of the low-reflectivity alloy layer formed in the laminate substrate of this embodiment is not particularly limited, and for example, it can be arbitrarily selected according to the degree of suppression of light reflection on the surface of the copper layer.

低反射率合金層厚度之下限值例如較佳為10nm以上,優選為15nm以上。上限值例如較佳為70nm以下,優選為50nm以下。 The lower limit of the thickness of the low-reflectivity alloy layer is, for example, preferably 10 nm or more, and preferably 15 nm or more. The upper limit is preferably 70 nm or less, and preferably 50 nm or less, for example.

低反射率合金層如上所述可發揮對銅層表面之光反射進行抑制之層之功能,然在低反射率合金層之厚度較薄之情況下,存在不能對銅層之光反射進行充分抑制之情況。對此,藉由使低反射率合金層之厚度為10nm以上,可確實地對銅層表面之光反射進行抑制。 As mentioned above, the low-reflectivity alloy layer can function as a layer that suppresses light reflection on the surface of the copper layer. However, when the thickness of the low-reflectivity alloy layer is thin, it cannot sufficiently suppress the light reflection of the copper layer. The situation. In this regard, by making the thickness of the low-reflectivity alloy layer 10 nm or more, the light reflection on the surface of the copper layer can be reliably suppressed.

對低反射率合金層厚度之上限值並無特別限定,然如果厚至必要程度以上,則成膜所需要之時間或形成配線時該蝕刻所需要之時間變長,會導致成本上昇。為此,低反射率合金層之厚度較佳為70nm以下,優選為50nm以下。 The upper limit of the thickness of the low-reflectivity alloy layer is not particularly limited. However, if it is thicker than necessary, the time required for film formation or the time required for etching during wiring formation becomes longer, leading to increased costs. For this reason, the thickness of the low-reflectivity alloy layer is preferably 70 nm or less, and preferably 50 nm or less.

接下來,對本實施方式之積層體基板之構成例進行說明。 Next, a configuration example of the laminate substrate of this embodiment will be described.

如上所述,本實施方式之積層體基板可具有:透明基材、及具銅層和低反射率合金層之積層體。此時,對積層體內之銅層和低反射率合金層在透明基材上之配置順序或其層數並無特別限定。即,例如可在透 明基材之至少一個面側依照任意之順序進行銅層和低反射率合金層各為一層之積層。又,還可在積層體內形成複數層之銅層及/或低反射率合金層。 As described above, the laminate substrate of this embodiment may have a transparent base material, and a laminate having a copper layer and a low-reflectivity alloy layer. At this time, the arrangement order of the copper layer and the low-reflectivity alloy layer on the transparent substrate or the number of layers in the laminate is not particularly limited. That is, for example, the The copper layer and the low-reflectivity alloy layer are laminated in an arbitrary order on at least one side of the substrate. In addition, a plurality of copper layers and/or low-reflectivity alloy layers may be formed in the laminate.

然在積層體內進行銅層和低反射率合金層之配置時,為了對銅層表面之光反射進行抑制,較佳在銅層表面中之特別要對光反射進行抑制之面配置低反射率合金層。 However, when arranging the copper layer and the low-reflectivity alloy layer in the laminate, in order to suppress the light reflection on the surface of the copper layer, it is better to arrange the low-reflectivity alloy on the surface of the copper layer where the light reflection is particularly suppressed. Floor.

特別地,優選為具有低反射率合金層形成在銅層表面之積層構造,具體而言,例如較佳為積層體具有作為低反射率合金層之第1低反射率合金層和第2低反射率合金層之兩層,並且銅層配置在第1低反射率合金層和第2低反射率合金層之間。 In particular, it is preferable to have a laminated structure in which a low-reflectivity alloy layer is formed on the surface of the copper layer. Specifically, for example, it is preferable that the laminated body has a first low-reflectivity alloy layer and a second low-reflectivity alloy layer as the low-reflectivity alloy layer. The copper layer is arranged between the first low-reflectivity alloy layer and the second low-reflectivity alloy layer.

關於具體構成例,參考圖2A、圖2B、圖3A及圖3B,以下進行說明。圖2A、圖2B、圖3A及圖3B示出了本實施方式之積層體基板之與透明基材、銅層及低反射率合金層之積層方向平行之面之剖面圖之例子。 Regarding specific configuration examples, the following description will be given with reference to FIGS. 2A, 2B, 3A, and 3B. 2A, FIG. 2B, FIG. 3A, and FIG. 3B show examples of cross-sectional views of a surface parallel to the laminate direction of the transparent base material, the copper layer, and the low-reflectivity alloy layer of the laminate substrate of the present embodiment.

例如,如圖2A所示之積層體基板10A,可在透明基材11之一個面11a側依次進行銅層12和低反射率合金層13各一層之積層。又,如圖2B所示之積層體基板10B,也可在透明基材11之一個面11a側和另一個面(另一面)11b側分別依次進行銅層12A、12B和低反射率合金層13A、13B各一層之積層。需要說明的是,銅層12(12A、12B)和低反射率合金層13(13A、13B)之積層順序並不限定於圖2A和圖2B之例子,還可從透明基材11側開始依次進行低反射率合金層13(13A、13B)和銅層12(12A、12B)之積層。 For example, in the laminated substrate 10A shown in FIG. 2A, the copper layer 12 and the low-reflectivity alloy layer 13 can be laminated in order on one surface 11a side of the transparent base material 11. In addition, as shown in FIG. 2B for the laminate substrate 10B, the copper layers 12A, 12B and the low-reflectivity alloy layer 13A may be successively formed on one surface 11a side and the other surface (the other surface) 11b side of the transparent substrate 11, respectively. , 13B each layer of accumulation. It should be noted that the stacking sequence of the copper layer 12 (12A, 12B) and the low-reflectivity alloy layer 13 (13A, 13B) is not limited to the example of FIG. 2A and FIG. 2B, and it can also start from the transparent substrate 11 side in order. The low-reflectivity alloy layer 13 (13A, 13B) and the copper layer 12 (12A, 12B) are stacked.

又,如上所述,例如還可為在透明基材11之一個面側設置 複數個低反射率合金層之結構。例如,如圖3A所示之積層體基板20A,可在透明基材11之一個面11a側依次進行第1低反射率合金層131、銅層12及第2低反射率合金層132之積層。 Also, as described above, for example, it may also be provided on one side of the transparent substrate 11. The structure of multiple low-reflectivity alloy layers. For example, in the laminate substrate 20A shown in FIG. 3A, the first low-reflectivity alloy layer 131, the copper layer 12, and the second low-reflectivity alloy layer 132 can be laminated on one surface 11a of the transparent substrate 11 in this order.

如此,作為低反射率合金層具有第1低反射率合金層131和第2低反射率合金層132,並且,銅層12配置在第1低反射率合金層131和第2低反射率合金層132之間,據此,可更確實地對從銅層12之上表面側和下面側入射之光之反射進行抑制。 In this way, the low-reflectivity alloy layer has a first low-reflectivity alloy layer 131 and a second low-reflectivity alloy layer 132, and the copper layer 12 is arranged on the first low-reflectivity alloy layer 131 and the second low-reflectivity alloy layer According to this, the reflection of light incident from the upper surface side and the lower surface side of the copper layer 12 can be suppressed more reliably.

在此情況下,也可為在透明基材11之兩個表面上進行了銅層、第1低反射率合金層及第2低反射率合金層之積層之結構。具體而言,如圖3B所示之積層體基板20B,可在透明基材11之一個面11a側和另一個面(另一面)11b分別依次進行第1低反射率合金層131A、131B、銅層12A、12B、及第2低反射率合金層132A、132B之積層。 In this case, it may be a structure in which a copper layer, a first low-reflectivity alloy layer, and a second low-reflectivity alloy layer are laminated on both surfaces of the transparent substrate 11. Specifically, the laminate substrate 20B shown in FIG. 3B can be sequentially provided with the first low-reflectivity alloy layers 131A, 131B, and copper on one surface 11a side and the other surface (the other surface) 11b of the transparent substrate 11, respectively. The layers 12A, 12B, and the second low-reflectivity alloy layer 132A, 132B are stacked.

需要說明的是,第1低反射率合金層131(131A、131B)和第2低反射率合金層132(132A、132B)均可為含有銅和鎳之低反射率合金層,並可藉由相同製造方法製造。 It should be noted that both the first low-reflectivity alloy layer 131 (131A, 131B) and the second low-reflectivity alloy layer 132 (132A, 132B) can be low-reflectivity alloy layers containing copper and nickel, and can be Manufactured in the same manufacturing method.

又,在透明基材之兩個面上進行了銅層和低反射率合金層之積層之圖2B和圖3B之構成例中,雖示出了在透明基材11之上下進行了積層之層以透明基材11為對稱面呈對稱之配置例,然並不限定於該形態。例如,在圖3B中,也可將透明基材11之一個面11a側之結構形成為與圖2B之結構同樣地依次進行銅層12A和低反射率合金層13A之積層之形態,並將另一個面(另一面)11b側形成為依次進行第1低反射率合金層131B、銅層12B及第2低反射率合金層132B之積層之形態,如此,在透明基材11 之上下進行了積層之層亦可呈非對稱結構。 In addition, in the configuration examples of Figs. 2B and 3B in which a copper layer and a low-reflectivity alloy layer are laminated on both surfaces of the transparent substrate, although the layers are laminated on the transparent substrate 11 An example of a symmetrical arrangement with the transparent substrate 11 as the symmetry plane is not limited to this form. For example, in FIG. 3B, the structure on one surface 11a side of the transparent substrate 11 may be formed in the same way as the structure of FIG. 2B in which the copper layer 12A and the low-reflectivity alloy layer 13A are sequentially laminated, and another One surface (the other surface) 11b side is formed in a form in which the first low-reflectivity alloy layer 131B, the copper layer 12B, and the second low-reflectivity alloy layer 132B are laminated in this order. Thus, the transparent substrate 11 The layers stacked on top and bottom can also have an asymmetric structure.

對本實施方式之積層體基板之光反射之程度並無特別限定,例如,波長為400nm以上且700nm以下之光之正反射率之平均值較佳為55%以下,優選為40%以下,進而較佳為30%以下。其原因在於,在波長為400nm以上且700nm以下之光之正反射率之平均值為55%以下之情況下,例如即使在將本實施方式之積層體基板作為觸控板用導電性基板使用時,也可特別地對顯示器之視認性之下降進行抑制。 The degree of light reflection of the laminate substrate of this embodiment is not particularly limited. For example, the average value of the specular reflectance of light having a wavelength of 400 nm or more and 700 nm or less is preferably 55% or less, preferably 40% or less, and more Preferably, it is 30% or less. The reason is that when the average value of the specular reflectance of light having a wavelength of 400 nm or more and 700 nm or less is 55% or less, for example, even when the laminate substrate of this embodiment is used as a conductive substrate for touch panels , It can also especially suppress the decrease of the visibility of the display.

積層體基板之正反射率之測定可藉由向低反射率合金層照射光之方式來進行。即,可從積層體基板中所含有之銅層和低反射率合金層中之低反射率合金層側照射光以進行測定。具體而言,例如,如圖2A所示,在透明基材11之一個面11a依次進行了銅層12和低反射率合金層13之積層之情況下,可藉由對低反射率合金層13進行光照射之方式,以對低反射率合金層13之表面A照射光,據此可進行測定。又,在交換了圖2A之銅層12和低反射率合金層13之配置順序,並在透明基材11之一個面11a側依次進行了低反射率合金層13和銅層12之積層之情況下,可藉由對低反射率合金層13進行光照射之方式,以從透明基材11之面11b側對低反射率合金層照射光,據此可進行正反射率之測定。 The regular reflectance of the laminate substrate can be measured by irradiating light to the low reflectance alloy layer. That is, the measurement can be performed by irradiating light from the side of the low-reflectivity alloy layer among the copper layer and the low-reflectivity alloy layer contained in the laminate substrate. Specifically, for example, as shown in FIG. 2A, when a copper layer 12 and a low-reflectivity alloy layer 13 are sequentially laminated on one surface 11a of the transparent substrate 11, the low-reflectivity alloy layer 13 can be The light irradiation method is to irradiate the surface A of the low-reflectivity alloy layer 13 with light, and the measurement can be performed accordingly. In addition, in the case where the arrangement order of the copper layer 12 and the low-reflectivity alloy layer 13 in FIG. 2A is exchanged, and the low-reflectivity alloy layer 13 and the copper layer 12 are sequentially laminated on one surface 11a side of the transparent substrate 11 By irradiating the low-reflectivity alloy layer 13 with light, the low-reflectivity alloy layer can be irradiated with light from the surface 11b side of the transparent substrate 11, so that the regular reflectance can be measured.

又,波長為400nm以上且700nm以下之光之正反射率之平均值是指,在400nm以上且700nm以下之範圍內改變波長並進行測定時之測定結果之平均值。測定時,對波長之變化幅度並無特別限定,例如,較佳為每10nm之幅度改變波長並對上述波長範圍之光進行測定,優選為每1nm之幅度改變波長並對上述波長範圍之光進行測定。 In addition, the average value of the specular reflectance of light with a wavelength of 400 nm or more and 700 nm or less refers to the average value of the measurement results when the wavelength is changed within the range of 400 nm or more and 700 nm or less. During the measurement, there is no particular limitation on the variation range of the wavelength. For example, it is preferable to change the wavelength every 10 nm and measure the light in the above-mentioned wavelength range, and it is preferable to change the wavelength every 1 nm and measure the light in the above-mentioned wavelength range. Determination.

需要說明的是,如後所述,積層體基板可藉由基於對銅層和低反射率合金層進行蝕刻之配線加工以形成金屬細線之方式成為導電性基板。此時導電性基板之光之正反射率是指,在除去透明基材之情況下之配置在最外表面之低反射率合金層之光入射側之表面之正反射率。 It should be noted that, as described later, a laminate substrate can be a conductive substrate by forming thin metal wires by wiring processing based on etching the copper layer and the low-reflectivity alloy layer. At this time, the light specular reflectance of the conductive substrate refers to the specular reflectance of the surface of the light incident side of the low-reflectivity alloy layer arranged on the outermost surface with the transparent substrate removed.

因此,如果是進行了蝕刻處理後之導電性基板,則較佳為殘存了銅層和低反射率合金層之部分之測定結果之平均值滿足上述範圍。 Therefore, if it is a conductive substrate that has been etched, it is preferable that the average value of the measurement results of the portion where the copper layer and the low-reflectivity alloy layer remain is within the above range.

接下來,對本實施方式之導電性基板進行說明。 Next, the conductive substrate of this embodiment will be described.

本實施方式之導電性基板可具備:透明基材和在透明基材之至少一個面側所形成之金屬細線。又,金屬細線為具備含有銅和鎳之低反射率合金配線層及銅配線層的積層體,並且,低反射率合金配線層中所含有之銅和鎳中之鎳之比率可為30質量%以上且85質量%以下。 The conductive substrate of the present embodiment may include a transparent base material and thin metal wires formed on at least one surface side of the transparent base material. In addition, the thin metal wire is a laminate with a low-reflectivity alloy wiring layer containing copper and nickel and a copper wiring layer, and the ratio of copper contained in the low-reflectivity alloy wiring layer to nickel in nickel can be 30% by mass Above and 85% by mass or less.

就本實施方式之導電性基板而言,例如,如上所述可藉由對積層體基板進行配線加工之方式獲得。又,在本實施方式之導電性基板中,由於透明基材上設置了銅配線層和低反射率合金配線層,故可對銅配線層所導致之光反射進行抑制。因此,藉由設置低反射率合金配線層,例如在使用於觸控板等之情況下,顯示器可具有良好之之視認性。 The conductive substrate of the present embodiment can be obtained, for example, by performing wiring processing on a laminate substrate as described above. Furthermore, in the conductive substrate of the present embodiment, since the copper wiring layer and the low-reflectivity alloy wiring layer are provided on the transparent base material, light reflection by the copper wiring layer can be suppressed. Therefore, by providing a low-reflectivity alloy wiring layer, for example, when used in a touch panel, the display can have good visibility.

本實施方式之導電性基板例如可較佳作為觸控板用導電性基板來使用。在此情況下,導電性基板可為具有藉由在上述積層體基板之銅層和低反射率合金層設置開口部而形成之配線圖案的結構。優選為具備網狀配線圖案之結構。 The conductive substrate of this embodiment can be suitably used as a conductive substrate for touch panels, for example. In this case, the conductive substrate may have a structure having a wiring pattern formed by providing openings in the copper layer and the low-reflectivity alloy layer of the laminate substrate. Preferably, it has a structure with a mesh wiring pattern.

形成了具備開口部之配線圖案之導電性基板可藉由對至此所說明之積層體基板之銅層和低反射率合金層進行蝕刻之方式獲得。又, 例如也可為具有基於兩層金屬細線之網狀配線圖案之導電性基板。具體構成例示於圖4。圖4示出了對具備網狀配線圖案之導電性基板30從銅配線層和低反射率合金配線層之積層方向之上表面側進行觀察時之圖。圖4所示之導電性基板30具有透明基材11、與圖中X軸方向平行之複數個銅配線層31B、及與圖中Y軸方向平行之銅配線層31A。需要說明的是,銅配線層31A、31B可藉由對上述之積層體基板進行蝕刻而形成,並且,在銅配線層31A、31B之上表面和/或下面上還形成了圖中未示之低反射率合金配線層。又,低反射率合金配線層被蝕刻為具有與銅配線層31A、31B大致相同之形狀。 The conductive substrate on which the wiring pattern with openings is formed can be obtained by etching the copper layer and the low-reflectivity alloy layer of the laminate substrate described so far. also, For example, it may be a conductive substrate having a mesh wiring pattern based on two layers of thin metal wires. A specific configuration example is shown in FIG. 4. FIG. 4 shows a view when the conductive substrate 30 provided with a mesh wiring pattern is viewed from the upper surface side in the direction of the laminate of the copper wiring layer and the low-reflectivity alloy wiring layer. The conductive substrate 30 shown in FIG. 4 has a transparent substrate 11, a plurality of copper wiring layers 31B parallel to the X-axis direction in the figure, and copper wiring layers 31A parallel to the Y-axis direction in the figure. It should be noted that the copper wiring layers 31A, 31B can be formed by etching the above-mentioned laminate substrate, and the copper wiring layers 31A, 31B are also formed on the upper surface and/or the lower surface, which are not shown in the figure. Low reflectivity alloy wiring layer. In addition, the low-reflectivity alloy wiring layer is etched to have approximately the same shape as the copper wiring layers 31A and 31B.

對透明基材11和銅配線層31A、31B之配置並無特別限定。透明基材11和銅配線層之配置之構成例示於圖5。圖5是沿圖4之A-A’線之剖面圖。 The arrangement of the transparent substrate 11 and the copper wiring layers 31A, 31B is not particularly limited. The configuration example of the arrangement of the transparent substrate 11 and the copper wiring layer is shown in FIG. 5. Fig. 5 is a sectional view taken along the line A-A' of Fig. 4;

例如,如圖5所示,可在透明基材11之上下表面分別配置銅配線層31A、31B。需要說明的是,在圖5所示之導電性基板之情況下,在銅配線層31A、31B之透明基材11側配置了被蝕刻為具有與銅配線層31A、31B大致相同形狀之第1低反射率合金配線層321A、321B。又,在銅配線層31A、31B之與透明基材11相反之一側之表面上還配置了第2低反射率合金配線層322A、322B。 For example, as shown in FIG. 5, copper wiring layers 31A and 31B may be arranged on the upper and lower surfaces of the transparent substrate 11, respectively. It should be noted that in the case of the conductive substrate shown in FIG. 5, a first etched to have approximately the same shape as the copper wiring layers 31A, 31B is arranged on the transparent substrate 11 side of the copper wiring layers 31A, 31B. Low-reflectivity alloy wiring layers 321A and 321B. In addition, second low-reflectivity alloy wiring layers 322A, 322B are also arranged on the surface of the copper wiring layers 31A, 31B on the side opposite to the transparent base material 11.

因此,在圖5所示之導電性基板中,金屬細線具有作為低反射率合金配線層之第1低反射率合金配線層321A、321B和第2低反射率合金配線層322A、322B,並且,銅配線層31A、31B配置在第1低反射率合金配線層321A、321B和第2低反射率合金配線層322A、322B之間。 Therefore, in the conductive substrate shown in FIG. 5, the thin metal wires have first low-reflectivity alloy wiring layers 321A, 321B and second low-reflectivity alloy wiring layers 322A, 322B as low-reflectivity alloy wiring layers, and, The copper wiring layers 31A, 31B are arranged between the first low-reflectivity alloy wiring layers 321A, 321B and the second low-reflectivity alloy wiring layers 322A, 322B.

需要說明的是,此處雖示出了設置第1低反射率合金配線層和第2低反射率合金配線層之例子,然並不限定於該形態。例如,也可僅設置第1低反射率合金配線層和第2低反射率合金配線層中之任意一個。 It should be noted that although an example in which the first low-reflectivity alloy wiring layer and the second low-reflectivity alloy wiring layer are provided is shown here, it is not limited to this form. For example, only one of the first low-reflectivity alloy wiring layer and the second low-reflectivity alloy wiring layer may be provided.

圖4所示之具有網狀配線之導電性基板,可例如如圖2B和圖3B所示,根據在透明基材11之兩個面具備銅層12A、12B和低反射率合金層13A、13B(131A、132A、131B及132B)之積層體基板來形成。 The conductive substrate with mesh wiring shown in FIG. 4 can be, for example, as shown in FIG. 2B and FIG. 3B, based on the provision of copper layers 12A, 12B and low-reflectivity alloy layers 13A, 13B on both sides of the transparent substrate 11 (131A, 132A, 131B, and 132B) laminated substrates are formed.

需要說明的是,例如,圖5所示之具備第1低反射率合金配線層和第2低反射率合金配線層之導電性基板可自圖3B所示之積層體基板形成。 It should be noted that, for example, the conductive substrate including the first low-reflectivity alloy wiring layer and the second low-reflectivity alloy wiring layer shown in FIG. 5 can be formed from the laminate substrate shown in FIG. 3B.

以下,以使用圖3B之積層體基板形成之情況為例進行說明。 Hereinafter, a case where the laminate substrate of FIG. 3B is used is used as an example for description.

首先,對透明基材11之一個面11a側之銅層12A、第1低反射率合金層131A及第2低反射率合金層132A進行蝕刻,以使與圖3B中Y軸方向平行之複數個線狀圖案沿X軸方向被配置為隔開所定間隔。需要說明的是,圖3B中之Y軸方向是指與紙面垂直之方向。又,圖3B中之X軸方向是指與各層之寬度方向平行之方向。 First, the copper layer 12A, the first low-reflectivity alloy layer 131A, and the second low-reflectivity alloy layer 132A on one surface 11a side of the transparent substrate 11 are etched so that a plurality of them are parallel to the Y-axis direction in FIG. 3B The linear patterns are arranged at predetermined intervals along the X-axis direction. It should be noted that the Y-axis direction in FIG. 3B refers to the direction perpendicular to the paper surface. In addition, the X-axis direction in FIG. 3B refers to a direction parallel to the width direction of each layer.

接下來,對透明基材11之另一面11b側之銅層12B、第1低反射率合金層131B及第2低反射率合金層132B進行蝕刻,以使與圖3B中X軸方向平行之複數個線狀圖案沿Y軸方向被配置為隔開所定間隔。 Next, the copper layer 12B, the first low-reflectivity alloy layer 131B, and the second low-reflectivity alloy layer 132B on the other side 11b of the transparent substrate 11 are etched so as to be parallel to the X-axis direction in FIG. 3B. The linear patterns are arranged at a predetermined interval along the Y-axis direction.

藉由以上操作,可形成圖4和圖5所示之具有網狀配線之導電性基板。需要說明的是,也可同時對透明基材11之兩個面進行蝕刻。即,銅層12A、12B、第1低反射率合金層131A、131B及第2低反射率合金層132A、132B之蝕刻也可同時進行。 Through the above operations, the conductive substrate with mesh wiring shown in FIGS. 4 and 5 can be formed. It should be noted that it is also possible to etch both surfaces of the transparent substrate 11 at the same time. That is, the etching of the copper layers 12A, 12B, the first low-reflectivity alloy layers 131A, 131B, and the second low-reflectivity alloy layers 132A, 132B may be performed simultaneously.

圖4所示之具有網狀配線之導電性基板還可使用兩個圖2A或圖3A所示之積層體基板來形成。如果以使用圖3A之導電性基板之情況為例進行說明,則可首先對兩個圖3A所示之導電性基板分別進行銅層12、第1低反射率合金層131及第2低反射率合金層132之蝕刻,以使與X軸方向平行之複數個線狀圖案沿Y軸方向被配置為隔開所定間隔。接下來,以將藉由上述蝕刻處理在各導電性基板上所形成之線狀圖案相互交叉配置之方式,對兩個導電性基板進行貼合,據此可獲得具有網狀配線之導電性基板。此處對貼合兩個導電性基板時之貼合面並無特別限定。 The conductive substrate with mesh wiring shown in FIG. 4 can also be formed using two laminate substrates shown in FIG. 2A or FIG. 3A. If the case of using the conductive substrate of FIG. 3A is used as an example for description, the two conductive substrates shown in FIG. 3A can be firstly subjected to the copper layer 12, the first low-reflectivity alloy layer 131, and the second low-reflectivity alloy layer. The alloy layer 132 is etched so that a plurality of linear patterns parallel to the X-axis direction are arranged at predetermined intervals along the Y-axis direction. Next, the two conductive substrates are bonded together in such a way that the linear patterns formed on each conductive substrate by the above-mentioned etching process are arranged to cross each other, thereby obtaining a conductive substrate with meshed wiring. . The bonding surface when bonding two conductive substrates is not particularly limited here.

例如,就兩個導電性基板而言,可藉由將圖3A中之透明基材11之未積層銅層12等之面11b相互貼合,以獲得圖5所示之結構。 For example, for two conductive substrates, the unlaminated copper layer 12 and other surfaces 11b of the transparent substrate 11 in FIG. 3A can be attached to each other to obtain the structure shown in FIG. 5.

需要說明的是,對圖4所示之具有網狀配線之導電性基板之金屬細線之寬度或金屬細線之間之距離並無特別限定,例如,可根據金屬細線所需要之電阻值等進行選擇。 It should be noted that the width of the thin metal wires or the distance between the thin metal wires of the conductive substrate with mesh wiring shown in FIG. 4 is not particularly limited. For example, it can be selected according to the required resistance value of the thin metal wires. .

然為了使透明基材和金屬細線具有充分之密接性,較佳為對金屬細線之寬度等進行選擇。 However, in order to provide sufficient adhesion between the transparent substrate and the thin metal wires, it is preferable to select the width of the thin metal wires.

本實施方式之導電性基板具有藉由對上述積層體基板進行配線加工並在積層體基板之銅層和低反射率合金層設置開口部而形成之配線圖案。為此,在配線圖案中所含有之金屬細線之間設置了使透明基材露出之開口部。 The conductive substrate of this embodiment has a wiring pattern formed by performing wiring processing on the above-mentioned laminate substrate and providing openings in the copper layer and the low-reflectivity alloy layer of the laminate substrate. For this reason, openings for exposing the transparent base material are provided between the thin metal wires contained in the wiring pattern.

又,該開口部之波長為400nm以上且700nm以下之光之穿透率之平均值與透明基材之波長為400nm以上且700nm以下之光之穿透率之平均值相比的減少率較佳為3.0%以下。 In addition, the average value of the light transmittance of the opening having a wavelength of 400 nm or more and 700 nm or less has a better reduction rate than the average value of the light transmittance of the transparent substrate having a wavelength of 400 nm or more and 700 nm or less. It is 3.0% or less.

其原因在於,上述開口部之波長為400nm以上且700nm以下之光之穿透率之平均值與供積層體基板使用之透明基材之波長為400nm以上且700nm以下之光之穿透率之平均值相比之減少率如果超過3.0%,則存在藉由目視對透明基材進行觀察時會看出顏色變為黃色之情況。又,如果上述減少率超過3.0%,則還會導致對低反射率合金層和銅層進行蝕刻時低反射率合金層之蝕刻速度變慢,進而不能同時對低反射率合金層和銅層進行蝕刻。為此,如上所述,低反射率合金層中所含有之銅和鎳中之鎳之比率較佳為85質量%以下。 The reason is that the average value of the transmittance of light with a wavelength of 400nm or more and 700nm or less in the above-mentioned opening and the average of the transmittance of light with a wavelength of 400nm or more and 700nm or less of the transparent substrate used for the laminate substrate If the reduction rate from the value exceeds 3.0%, the color may change to yellow when the transparent substrate is visually observed. In addition, if the reduction rate exceeds 3.0%, the etching speed of the low-reflectivity alloy layer when the low-reflectivity alloy layer and the copper layer are etched will also become slow, and the low-reflectivity alloy layer and the copper layer cannot be etched at the same time. For this reason, as described above, the ratio of copper and nickel contained in the low-reflectivity alloy layer is preferably 85% by mass or less.

需要說明的是,在取代低反射率合金層而使用包含鎳和銅之非化學計量氧化物之黑化層之情況下,鎳和銅之含有比率或其氧化狀態會導致蝕刻性下降,若上述減少率超過3.0%,則對透明基材目視觀察時也會存在可看到變為黃色之情況。如此,具有使用了非化學計量氧化物之黑化層之積層體基板由於需要對黑化層成膜時之濺鍍環境進行控制,故還存在難以對製造條件進行最佳化之情況。 It should be noted that in the case of using a blackened layer containing non-stoichiometric oxides of nickel and copper in place of the low-reflectivity alloy layer, the content ratio of nickel and copper or its oxidation state will cause the etching performance to decrease. If it exceeds 3.0%, it may turn to yellow when the transparent substrate is visually observed. In this way, a laminate substrate having a blackened layer using a non-stoichiometric oxide requires control of the sputtering environment during the formation of the blackened layer, so it is difficult to optimize the manufacturing conditions.

另一方面,本實施方式之積層體基板中,由於黑化層中使用了低反射率合金層,故僅需對鎳和銅之組成成分進行控制即可,因此,可容易地進行製造條件之最佳化。 On the other hand, in the laminate substrate of this embodiment, since the low-reflectivity alloy layer is used for the blackening layer, only the composition of nickel and copper needs to be controlled. Therefore, it is possible to easily optimize the manufacturing conditions. Jiahua.

又,對本實施方式之導電性基板之光反射之程度並無特別限定,例如波長為400nm以上且700nm以下之光之正反射率之平均值較佳為55%以下,優選為40%以下,進而較佳為30%以下。其原因在於,在波長為400nm以上且700nm以下之光之正反射率之平均值為55%以下之情況下,例如即使用作觸控板用導電性基板時,也可特別地對顯示器之視認性之降 低進行抑制。 In addition, the degree of light reflection of the conductive substrate of this embodiment is not particularly limited. For example, the average value of the specular reflectance of light having a wavelength of 400 nm or more and 700 nm or less is preferably 55% or less, preferably 40% or less, and further Preferably it is 30% or less. The reason is that when the average value of the specular reflectance of light with a wavelength of 400 nm or more and 700 nm or less is 55% or less, for example, even when it is used as a conductive substrate for a touch panel, the display can be particularly visually recognized Sex drop Low to suppress.

就至此所說明之本實施方式之具有由兩層配線所構成之網狀配線之導電性基板而言,其例如可較佳作為投影型靜電容量方式之觸控板用導電性基板來使用。 Regarding the conductive substrate having mesh wiring composed of two layers of wiring in the present embodiment described so far, it can be preferably used as a conductive substrate for a touch panel of a projection type capacitance method, for example.

(積層體基板之製造方法和導電性基板之製造方法) (Manufacturing method of laminated substrate and manufacturing method of conductive substrate)

接下來,對本實施方式之積層體基板之製造方法之構成例進行說明。 Next, a configuration example of the method of manufacturing the laminate substrate of the present embodiment will be described.

本實施方式之積層體基板之製造方法可具有以下步驟。 The manufacturing method of the laminated body substrate of this embodiment can have the following steps.

準備透明基材之透明基材準備步驟。 The transparent substrate preparation step of preparing the transparent substrate.

在透明基材之至少一個面側形成積層體之積層體形成步驟。 A layered body forming step of forming a layered body on at least one side of the transparent substrate.

又,上述積層體形成步驟可包含以下步驟。 In addition, the step of forming the laminate may include the following steps.

銅層形成步驟,其藉由沉積銅之銅層成膜手段形成銅層。 The copper layer forming step is to form the copper layer by means of depositing a copper layer of copper.

低反射率合金層形成步驟,其藉由沉積含有銅鎳之低反射率合金層之低反射率合金層成膜手段而成膜低反射率合金層。 The low-reflectivity alloy layer forming step includes forming a low-reflectivity alloy layer by depositing a low-reflectivity alloy layer containing copper-nickel low-reflectivity alloy layer.

又,低反射率合金層形成步驟較佳在減壓環境下實施。又,低反射率合金層中所含有之銅和鎳中之鎳之比率較佳為30質量%以上且85質量%以下。 In addition, the step of forming the low-reflectivity alloy layer is preferably carried out under a reduced pressure environment. In addition, the ratio of copper contained in the low-reflectivity alloy layer to nickel in nickel is preferably 30% by mass or more and 85% by mass or less.

以下對本實施方式之積層體基板之製造方法進行說明,但就以下所說明之各點以外而言,由於其可為與上述積層體基板同樣之構成,故省略其說明。 Hereinafter, the manufacturing method of the laminate substrate of the present embodiment will be described, but except for the points described below, since it can have the same configuration as the above-mentioned laminate substrate, the description is omitted.

如上所述,在本實施方式之積層體基板中,對將銅層和低反射率合金層配置在透明基材上時之積層順序並無特別限定。又,銅層和低反射率合金層也可分別形成為複數層。為此,對上述銅層形成步驟和低反 射率合金層形成步驟之實施順序或實施次數並無特別限定,可根據所要形成之積層體基板之結構在任意時機實施任意次數。 As described above, in the laminate substrate of the present embodiment, the order of the laminate when the copper layer and the low-reflectivity alloy layer are arranged on the transparent base material is not particularly limited. In addition, the copper layer and the low-reflectivity alloy layer may be formed as plural layers, respectively. For this reason, the above-mentioned copper layer formation steps and low reflection The execution order or the number of executions of the emissivity alloy layer forming step is not particularly limited, and it can be carried out any number of times at any timing according to the structure of the laminate substrate to be formed.

準備透明基材之步驟例如為,準備由能使可視光穿透之高分子膜或玻璃基板等構成之透明基材之步驟,對其具體操作並無特別限定。例如可根據後續各步驟之要求而將其切斷為任意尺寸等。需要說明的是,由於作為能使可視光穿透之高分子膜之優選者已敘述,故此處省略說明。 The step of preparing a transparent substrate is, for example, a step of preparing a transparent substrate composed of a polymer film or a glass substrate that can penetrate visible light, and the specific operation is not particularly limited. For example, it can be cut into any size according to the requirements of the subsequent steps. It should be noted that since the preferred polymer film capable of transmitting visible light has been described, the description is omitted here.

接下來對積層體形成步驟進行說明。積層體形成步驟是在透明基材之至少一個面側形成積層體之步驟,並具有銅層形成步驟和低反射率合金形成步驟。為此,以下對各步驟進行說明。 Next, the step of forming the laminate will be described. The layered body forming step is a step of forming a layered body on at least one surface side of the transparent substrate, and has a copper layer forming step and a low-reflectivity alloy forming step. For this reason, the steps are described below.

首先,對銅層形成步驟進行說明。 First, the copper layer forming step will be described.

在銅層形成步驟中,可在透明基材之至少一個面側採用沉積銅之銅層成膜手段形成銅層。 In the copper layer forming step, the copper layer can be formed on at least one side of the transparent substrate by using a copper layer film-forming means of depositing copper.

在銅層形成步驟中,較佳採用乾式鍍法形成銅薄膜層。又,在要使銅層更厚之情況下,較佳為先採用乾式鍍法形成銅薄膜層後,再採用濕式鍍法形成鍍銅層。 In the copper layer forming step, a dry plating method is preferably used to form the copper thin film layer. Furthermore, in the case of making the copper layer thicker, it is preferable to form the copper thin film layer by dry plating, and then form the copper plating layer by wet plating.

為此,銅層形成步驟可具有例如採用乾式鍍法形成銅薄膜層之步驟。又,銅層形成步驟也可具有採用乾式鍍法形成銅薄膜層之步驟、及、將該銅薄膜層作為供電層並採用濕式鍍法形成鍍銅層之步驟。 To this end, the copper layer forming step may include, for example, a step of forming a copper thin film layer by a dry plating method. In addition, the copper layer forming step may include a step of forming a copper thin film layer by a dry plating method and a step of using the copper thin film layer as a power supply layer and forming a copper plating layer by a wet plating method.

因此,作為上述銅層成膜手段,並不限定於一個成膜手段,也可組合使用複數個成膜手段。 Therefore, the above-mentioned copper layer film forming means is not limited to one film forming means, and a plurality of film forming means may be used in combination.

如上所述,藉由僅使用乾式鍍法、或組合使用乾式鍍法和濕式鍍法之方式來形成銅層,可在透明基材或低反射率合金層上不藉由接著 劑地直接形成銅層,故為較佳。 As mentioned above, by using only the dry plating method or a combination of the dry plating method and the wet plating method to form the copper layer, it is possible to form a copper layer on a transparent substrate or a low-reflectivity alloy layer without bonding It is preferable to form the copper layer directly on the chemical ground.

作為乾式鍍法對其並無特別限定,在減壓環境下,可較佳使用濺鍍法、離子鍍法或蒸鍍法等。 The dry plating method is not particularly limited, and in a reduced pressure environment, a sputtering method, an ion plating method, an evaporation method, or the like can be preferably used.

特別地,作為形成銅薄膜層時所使用之乾式鍍法,由於使用濺鍍法可容易地進行厚度控制,故較佳使用濺鍍法。即,在此情況下,作為銅層形成步驟中之沉積銅之銅層成膜手段,可較佳使用濺鍍成膜手段(濺鍍成膜法)。 In particular, as the dry plating method used when forming the copper thin film layer, since the sputtering method can be used to easily control the thickness, the sputtering method is preferably used. That is, in this case, as a means for forming a copper layer by depositing copper in the copper layer forming step, a sputtering film forming means (sputtering film forming method) can be preferably used.

銅薄膜層可優選使用例如圖6所示之輥對輥濺鍍裝置60進行成膜。以下以採用輥對輥濺鍍裝置之情況為例,對銅薄膜層之形成步驟進行說明。 The copper thin film layer can preferably be formed into a film using, for example, a roll-to-roll sputtering device 60 shown in FIG. 6. Hereinafter, a case where a roll-to-roll sputtering device is used is taken as an example to describe the steps of forming the copper film layer.

圖6示出了輥對輥濺鍍裝置60之一構成例。輥對輥濺鍍裝置60具有可將其構成部品基本上都收藏於其內之框體61。圖6中所示之框體61之形狀為長方體形狀,然,對框體61之形狀並無特別限定,可根據其內部收藏之裝置、設置場所或耐壓性能等將其設計成任意形狀。例如框體61之形狀也可為圓筒形狀。然,為了在成膜開始時可對與成膜無關之殘留氣體進行去除,框體61之內部較佳為減壓至1Pa以下,優選為減壓至10-3Pa以下,進而較佳為減壓至10-4Pa。需要說明的是,並不需要將框體61之內部全都減壓至上述壓力,也可構成為,僅將配置了進行濺鍍之後述之成膜輥(can roll)63之圖中下側之區域減壓至上述壓力。 FIG. 6 shows an example of the configuration of the roll-to-roll sputtering device 60. The roll-to-roll sputtering device 60 has a frame 61 in which basically all its constituent parts can be stored. The shape of the frame body 61 shown in FIG. 6 is a rectangular parallelepiped shape. However, the shape of the frame body 61 is not particularly limited, and can be designed into any shape according to its internal storage device, installation location, pressure resistance, etc. For example, the shape of the frame 61 may be a cylindrical shape. However, in order to remove residual gas that has nothing to do with film formation at the beginning of film formation, the inside of the frame 61 is preferably reduced to 1 Pa or less, preferably 10 -3 Pa or less, and more preferably reduced Press to 10 -4 Pa. It should be noted that it is not necessary to decompress all the inside of the frame 61 to the above-mentioned pressure, and it may be configured such that only the lower side of the can roll 63 in the figure is arranged for sputtering. The area is depressurized to the above pressure.

框體61內可配置用於供給進行銅薄膜層之成膜之基材之卷出輥62、成膜輥63、濺鍍電極64a~64d、前饋輥65a、後饋輥65b、張力輥66a、66b及卷取輥67。又,在用於搬送進行銅薄膜層之成膜之基材之搬送 經路上,除了上述各輥之外,還可任意地設置導輥68a~68h及加熱器69等。 The frame 61 can be equipped with an unwinding roller 62, a film forming roller 63, sputtering electrodes 64a~64d, a feed-forward roller 65a, a post-feed roller 65b, and a tension roller 66a for supplying the substrate for forming the copper film layer. , 66b and take-up roller 67. In addition, it is used in the transportation of the substrate for the film formation of the copper thin film layer In addition to the above-mentioned rollers, guide rollers 68a to 68h, heater 69, etc. can be arbitrarily provided on the route.

卷出輥62、成膜輥63、前饋輥65a及卷取輥67可藉由伺服電動機提供動力。卷出輥62和卷取輥67可藉由基於粉末離合器等之扭矩控制,對成膜銅薄膜層之基材之張力平衡進行保持。 The unwinding roller 62, the film forming roller 63, the feed forward roller 65a, and the winding roller 67 can be powered by a servo motor. The unwinding roller 62 and the winding roller 67 can maintain the tension balance of the base material of the film-forming copper film layer by torque control based on a powder clutch or the like.

對成膜輥63之構成並無特限定,然較佳被構成為,例如在其表面上進行鍍硬質鉻之處理,並在其內部對從框體61之外部所供給之冷媒或溫媒進行循環,以可將溫度調整至一定之溫度。 The structure of the film forming roller 63 is not particularly limited, but it is preferably configured such that, for example, a hard chromium plating process is performed on the surface thereof, and the refrigerant or warming medium supplied from the outside of the frame 61 is treated inside it. Cycle to adjust the temperature to a certain temperature.

張力輥66a、66b例如優選在其表面進行鍍硬質鉻之處理,並具有張力感測器。又,前饋輥65a、後饋輥65b或導輥68a~68h之表面也優選進行鍍硬質鉻之處理。 The tension rollers 66a and 66b are preferably subjected to a hard chromium plating treatment on the surface thereof, and have tension sensors, for example. In addition, the surfaces of the forward feed roller 65a, the rear feed roller 65b, or the guide rollers 68a to 68h are also preferably treated with hard chromium plating.

濺鍍陰極64a~64d優選為磁電管陰極式,並與成膜輥63相對配置。對濺鍍電極64a~64d之尺寸並無特別限定,然濺鍍電極64a~64d之成膜銅薄膜層之基材寬度方向之尺寸優選為大於相對向之成膜銅薄膜層之基材寬度。 The sputtering cathodes 64 a to 64 d are preferably magnetron cathodes, and are arranged opposite to the film forming roller 63. The size of the sputtering electrodes 64a to 64d is not particularly limited. However, the size of the substrate width direction of the deposited copper film layer of the sputtering electrodes 64a to 64d is preferably larger than the substrate width of the opposing deposited copper film layer.

成膜銅薄膜層之基材被搬送至作為輥對輥真空成膜裝置之輥對輥濺鍍裝置60內後,可藉由與成膜輥63相對向之濺鍍電極64a~64d進行銅薄膜層之成膜。 After the base material of the film-forming copper film layer is transported to the roll-to-roll sputtering device 60 as a roll-to-roll vacuum film forming device, the copper film can be formed by sputtering electrodes 64a~64d facing the filming roll 63 Layer of film formation.

接下來,對使用輥對輥濺鍍裝置60進行銅薄膜層之成膜之步驟進行說明。 Next, the procedure of forming a copper thin film layer using the roll-to-roll sputtering apparatus 60 is demonstrated.

首先,將銅靶材安放在濺鍍電極64a~64d上,並藉由真空泵70a、70B對框體61之內部進行真空排氣,其中該框體61內之卷出輥62上安放了要進行銅薄膜層之成膜之基材。 First, the copper target is placed on the sputtering electrodes 64a~64d, and the inside of the frame 61 is evacuated by vacuum pumps 70a, 70B. The unwinding roller 62 in the frame 61 is placed on the The base material of the copper film layer.

接下來,將非活性氣體例如氬氣等濺鍍氣體藉由氣體供給手段71導入框體61內。需要說明的是,對氣體供給手段71之構成並無特別限定,可具有圖中未示之氣體貯藏罐。又,還可構成為,在氣體貯藏罐和框體61之間按照氣體種類分別設置質量流量控制器(MFC)711a、711b及閥712a、712b,以對各氣體之供給至框體61內之供給量進行控制。圖6示出了設置兩組質量流量控制器和閥之實例,然對設置數量並無特別限定,可根據所使用之氣體種類選擇所要設置之數量。 Next, an inert gas such as argon or other sputtering gas is introduced into the housing 61 by the gas supply means 71. It should be noted that the configuration of the gas supply means 71 is not particularly limited, and a gas storage tank not shown in the figure may be provided. In addition, it can also be configured that mass flow controllers (MFC) 711a, 711b and valves 712a, 712b are provided between the gas storage tank and the frame 61 according to the gas type to supply each gas to the frame 61 The supply volume is controlled. Figure 6 shows an example of setting two sets of mass flow controllers and valves. However, the number of settings is not particularly limited, and the number to be set can be selected according to the type of gas used.

又,在採用氣體供給手段71將濺鍍氣體供給至框體61內時,優選對濺鍍氣體之流量、及真空泵70B和框體61之間所設置之壓力調整閥72之開度進行調整,以將裝置內保持在例如0.13Pa以上且1.3Pa以下之壓力,並在此條件下實施成膜。 Furthermore, when the gas supply means 71 is used to supply the sputtering gas into the frame 61, it is preferable to adjust the flow rate of the sputtering gas and the opening of the pressure regulating valve 72 provided between the vacuum pump 70B and the frame 61. The inside of the device is maintained at a pressure of, for example, 0.13 Pa or more and 1.3 Pa or less, and film formation is performed under these conditions.

在此狀態下,可一邊藉由卷出輥62以例如每分鐘1m以上且20m以下之速度搬送基材,一邊藉由與濺鍍電極64a~64d連接之濺鍍用直流電源施加電力以進行濺鍍放電。據此,可在基材上連續地成膜預期之銅薄膜層。 In this state, while the unwinding roller 62 is used to transport the substrate at a speed of 1 m or more and 20 m or less per minute, the sputtering DC power supply connected to the sputtering electrodes 64a to 64d can be sputtered by applying power. Plating discharge. Accordingly, the desired copper thin film layer can be continuously formed on the substrate.

需要說明的是,輥對輥濺鍍裝置60還可根據需要配置上述以外之各種構件。例如,可設置用於對框體61內之壓力進行測定之壓力計73a、73b或排氣閥74a、74b。 It should be noted that the roll-to-roll sputtering device 60 may also be equipped with various components other than the above as required. For example, pressure gauges 73a, 73b or exhaust valves 74a, 74b for measuring the pressure in the frame 61 can be provided.

又,如上所述,還可在實施乾式鍍後再採用濕式鍍法成膜銅層(鍍銅層)。 In addition, as described above, the copper layer (copper plating layer) may be formed by wet plating after the dry plating.

在藉由濕式鍍法進行鍍銅層之成膜之情況下,可將採用上述乾式鍍法所成膜了之銅薄膜層作為供電層。在此情況下,作為銅層形成步 驟中之對沉積銅之銅層成膜手段,可較佳地使用電鍍成膜手段。 In the case of forming a copper-plated layer by a wet plating method, the copper thin film layer formed by the above-mentioned dry plating method can be used as the power supply layer. In this case, as the copper layer formation step For the film forming means of the copper layer of the deposited copper in the step, the electroplating film forming means can be preferably used.

對將銅薄膜層作為供電層並採用濕式鍍法形成鍍銅層之步驟之條件、即、電鍍處理之條件並無特別限定,可採用常規方法中之各種條件。例如,可藉由將形成了銅薄膜層之基材供給至裝入銅鍍液之鍍槽,並對電流密度或基材之搬送速度進行控制之方式來形成鍍銅層。 The conditions of the step of using the copper thin film layer as the power supply layer and forming the copper-plated layer by wet plating, that is, the conditions of the electroplating treatment, are not particularly limited, and various conditions in conventional methods can be used. For example, the copper plating layer can be formed by supplying the substrate on which the copper thin film layer is formed to a plating tank filled with a copper plating solution, and controlling the current density or the transport speed of the substrate.

接下來,對低反射率合金層形成步驟進行說明。 Next, the step of forming the low-reflectivity alloy layer will be described.

低反射率合金形成步驟如上所述,是在透明基材之至少一個面側藉由成膜含有銅和鎳之低反射率合金層之低反射率合金層成膜手段來形成低反射率合金層之成膜步驟。對低反射率合金層形成步驟中之沉積含有銅和鎳之低反射率合金層之低反射率合金層成膜手段並無特別限定,然較佳採用例如減壓環境下之濺鍍成膜手段、即濺鍍成膜法。 As mentioned above, the low-reflectivity alloy forming step is to form the low-reflectivity alloy layer by forming a low-reflectivity alloy layer containing copper and nickel on at least one surface side of the transparent substrate. The film forming step. The method for forming a low-reflectivity alloy layer by depositing a low-reflectivity alloy layer containing copper and nickel in the forming step of the low-reflectivity alloy layer is not particularly limited, but it is preferable to use, for example, a sputtering method under a reduced pressure environment. , Namely sputtering film forming method.

低反射率合金層可較佳地採用例如圖6所示之輥對輥濺鍍裝置60進行成膜。由於上面已經對輥對輥濺鍍裝置之構成進行敘述,此處省略其說明。 The low-reflectivity alloy layer may preferably be formed by using, for example, a roll-to-roll sputtering device 60 as shown in FIG. 6. Since the structure of the roll-to-roll sputtering device has been described above, its description is omitted here.

對使用輥對輥濺鍍裝置60進行低反射率合金層之成膜之步驟之構成例進行說明。 A configuration example of the step of forming a low-reflectivity alloy layer using the roll-to-roll sputtering device 60 will be described.

首先,將銅-鎳合金靶材安放在濺鍍電極64a~64d上,並藉由真空泵70a、70b對框體61內進行真空排氣,在該框體61內,卷出輥62上安放了要進行低反射率合金層之成膜之基材。之後,將非活性氣體、例如、由氬氣組成之濺鍍氣體藉由氣體供給手段71導入框體61內。此時,較佳為藉由對濺鍍氣體之流量及真空泵70b和框體61之間所設置之壓力調整閥72之開度進行調整,以使框體61內之壓力例如保持在0.13Pa以上且13Pa 以下,並在此條件下進行成膜。 First, the copper-nickel alloy target is placed on the sputtering electrodes 64a to 64d, and the frame 61 is evacuated by vacuum pumps 70a, 70b. In the frame 61, the unwinding roller 62 is placed The base material for film formation of the low-reflectivity alloy layer. After that, an inert gas, for example, a sputtering gas composed of argon gas, is introduced into the housing 61 by the gas supply means 71. At this time, it is preferable to adjust the flow rate of the sputtering gas and the opening degree of the pressure regulating valve 72 provided between the vacuum pump 70b and the frame 61 so that the pressure in the frame 61 is maintained at 0.13 Pa or more, for example. And 13Pa Below, film formation is performed under these conditions.

在此狀態下,一邊從卷出輥62對基材例如以每分鐘0.5m以上且10m以下左右之速度進行搬送,一邊從與濺鍍電極64a~64d連接之濺鍍用直流電源施加電力以進行濺鍍放電。據此,可在基材上連續地成膜預期之低反射率合金層。 In this state, while conveying the base material from the unwinding roller 62 at a speed of, for example, 0.5 m or more and 10 m or less per minute, power is applied from the sputtering DC power supply connected to the sputtering electrodes 64a to 64d. Sputtering discharge. Accordingly, the desired low-reflectivity alloy layer can be continuously formed on the substrate.

至此對本實施方式之積層體基板之製造方法中所包含之各步驟進行了說明。 So far, the steps included in the method of manufacturing the laminate substrate of the present embodiment have been described.

藉由本實施方式之積層體基板之製造方法獲得之積層體基板與上述積層體基板同樣,銅層厚度較佳為50nm以上,優選為60nm以上,進而較佳為150nm以上。對銅層厚度之上限值並無特別限定,然銅層厚度較佳為5000nm以下,優選為3000nm以下。需要說明的是,在銅層如上所述具有銅薄膜層和鍍銅層之情況下,銅薄膜層之厚度和鍍銅層厚度之合計較佳位於上述範圍內。 The laminated substrate obtained by the method of manufacturing the laminated substrate of the present embodiment is the same as the above-mentioned laminated substrate, and the thickness of the copper layer is preferably 50 nm or more, preferably 60 nm or more, and more preferably 150 nm or more. The upper limit of the thickness of the copper layer is not particularly limited, but the thickness of the copper layer is preferably 5000 nm or less, and preferably 3000 nm or less. It should be noted that when the copper layer has a copper thin film layer and a copper plating layer as described above, the total thickness of the copper thin film layer and the copper plating layer thickness is preferably within the above range.

又,對低反射率合金層之厚度並無特別限定,例如,較佳為10nm以上,優選為15nm以上。對低反射率合金層厚度之上限值並無特別限定,然較佳為70nm以下,優選為50nm以下。 In addition, the thickness of the low-reflectivity alloy layer is not particularly limited. For example, it is preferably 10 nm or more, and preferably 15 nm or more. The upper limit of the thickness of the low-reflectivity alloy layer is not particularly limited, but it is preferably 70 nm or less, and preferably 50 nm or less.

又,就藉由本實施方式之積層體基板之製造方法獲得之積層體基板而言,其波長為400nm以上且700nm以下之光之正反射率之平均值較佳為55%以下,優選為40%以下,較而較佳為30%以下。 In addition, for the laminated substrate obtained by the method of manufacturing the laminated substrate of this embodiment, the average value of the specular reflectance of light having a wavelength of 400 nm or more and 700 nm or less is preferably 55% or less, preferably 40% Below, it is more preferably 30% or less.

使用藉由本實施方式之積層體基板之製造方法獲得之積層體基板可形成導電性基板,其形成有在銅層和低反射率合金層上具備開口部之配線圖案。導電性基板優選為可具備網狀配線之結構。 A conductive substrate can be formed using the laminate substrate obtained by the method of manufacturing the laminate substrate of this embodiment, and the conductive substrate is formed with a wiring pattern having openings in the copper layer and the low-reflectivity alloy layer. The conductive substrate preferably has a structure that can be provided with mesh wiring.

本實施方式之導電性基板之製造方法可具有藉由對上述積層體基板之製造方法獲得之積層體基板之銅層和低反射率合金層進行蝕刻,以形成具有金屬細線之配線圖案之蝕刻步驟,該金屬細線為具備銅配線層和低反射率合金配線層之積層體。又,藉由該蝕刻步驟,還可在銅層和低反射率合金層上形成開口部。 The manufacturing method of the conductive substrate of this embodiment may have an etching step of etching the copper layer and the low-reflectivity alloy layer of the multilayer substrate obtained by the above-mentioned manufacturing method of the multilayer substrate to form a wiring pattern with thin metal wires , The thin metal wire is a laminate with a copper wiring layer and a low-reflectivity alloy wiring layer. Furthermore, by this etching step, openings can also be formed in the copper layer and the low-reflectivity alloy layer.

在蝕刻步驟中,例如首先在積層體基板之最外表面形成具有與要藉由蝕刻進行去除之部分相對應之開口部之光阻。例如,在圖2A所示之積層體基板10A之情況下,可在積層體基板10A所配置之低反射率合金層13之所露出之表面A上形成光阻。需要說明的是,對具有與要藉由蝕刻進行去除之部分相對應之開口部之光阻之形成方法並無特別限定,然例如可採用光微影法形成。 In the etching step, for example, first, a photoresist having an opening corresponding to the portion to be removed by etching is formed on the outermost surface of the laminate substrate. For example, in the case of the laminated substrate 10A shown in FIG. 2A, a photoresist can be formed on the exposed surface A of the low reflectivity alloy layer 13 on the laminated substrate 10A. It should be noted that the formation method of the photoresist having the opening corresponding to the portion to be removed by etching is not particularly limited, but for example, it can be formed by photolithography.

接下來,藉用從光阻上面供給蝕刻液,可對銅層12和低反射率合金層13實施蝕刻。 Next, by supplying an etching solution from above the photoresist, the copper layer 12 and the low-reflectivity alloy layer 13 can be etched.

需要說明的是,在如圖2B所示於透明基材11之兩面都配置了銅層和低反射率合金層之情況下,可在積層體基板之表面A及表面B上分別形成具有所定形狀之開口部之光阻,並可對透明基材11之兩面所形成之銅層和低反射率合金層同時進行蝕刻。又,還可對透明基材11之兩側所形成之銅層和低反射率合金層一側一側地進行蝕刻處理。即,例如可在對銅層12A及低反射率合金層13A進行蝕刻後,再對銅層12B及低反射率合金層13B進行蝕刻。 It should be noted that when the copper layer and the low-reflectivity alloy layer are arranged on both sides of the transparent base material 11 as shown in FIG. 2B, a predetermined shape can be formed on the surface A and the surface B of the laminate substrate. The photoresist of the opening part can simultaneously etch the copper layer and the low-reflectivity alloy layer formed on both sides of the transparent substrate 11. In addition, the copper layer and the low-reflectivity alloy layer formed on both sides of the transparent substrate 11 can be etched on one side. That is, for example, after the copper layer 12A and the low-reflectivity alloy layer 13A are etched, the copper layer 12B and the low-reflectivity alloy layer 13B may be etched.

藉由本實施方式之積層體基板之製造方法所形成之低反射率合金層示出了與銅層同樣之相對蝕刻液之反應性。為此,對蝕刻步驟中 所使用之蝕刻液並無特別限定,較佳可使用一般常用之蝕刻銅層時所使用之蝕刻液。 The low-reflectivity alloy layer formed by the manufacturing method of the laminate substrate of the present embodiment shows the same reactivity to the etching solution as the copper layer. For this reason, in the etching step The etching solution used is not particularly limited, and it is preferable to use the etching solution commonly used in etching copper layers.

作為蝕刻步驟中所使用之蝕刻液,例如可較佳地使用包含選自硫酸、過氧化氫水、鹽酸、二氯化銅及三氯化鐵中之1種之水溶液、或包含選自上述硫酸等中2種以上之混合水溶液。此處對蝕刻液中之各成分之含量並無特別限定。 As the etching solution used in the etching step, for example, an aqueous solution containing one selected from sulfuric acid, hydrogen peroxide water, hydrochloric acid, copper dichloride, and ferric chloride, or an aqueous solution containing one selected from the above sulfuric acid can be preferably used. A mixture of more than two kinds of aqueous solutions. The content of each component in the etching solution is not particularly limited here.

蝕刻液可在室溫下使用,然為了提高反應性,較佳對其進行加溫,例如可加熱至40℃以上且50℃以下。 The etching solution can be used at room temperature, but in order to improve the reactivity, it is better to heat it, for example, it can be heated to 40°C or more and 50°C or less.

就藉由上述蝕刻步驟獲得之網狀配線之具體形態而言,其與上述相同,此處省略其說明。 Regarding the specific form of the mesh wiring obtained by the above-mentioned etching step, it is the same as the above, and its description is omitted here.

又,在將兩個如圖2A、圖3A所示之於透明基材11之一個面側具有銅層和低反射率合金層之積層體基板提供至蝕刻步驟以形成導電性基板後,再對兩個導電性基板進行貼合以形成具有網狀配線之導電性基板之情況下,還可設置導電性基板貼合步驟。此時,對2個導電性基板之貼合方法並無特別限定,例如可使用光學接著劑(OCA)等進行接著。 In addition, after two laminate substrates having a copper layer and a low-reflectivity alloy layer on one surface side of the transparent substrate 11 as shown in FIGS. 2A and 3A are provided to the etching step to form a conductive substrate, In the case where two conductive substrates are bonded to form a conductive substrate with mesh wiring, a conductive substrate bonding step may also be provided. At this time, the bonding method of the two conductive substrates is not particularly limited. For example, an optical adhesive (OCA) or the like can be used for bonding.

需要說明的是,就藉由本實施方式之導電性基板之製造方法獲得之導電性基板而言,其波長為400nm以上且700nm以下之光之正反射率之平均值較佳為55%以下,優選為40%以下,進而較佳為30%以下。 It should be noted that, for the conductive substrate obtained by the method of manufacturing the conductive substrate of this embodiment, the average value of the specular reflectance of light having a wavelength of 400 nm or more and 700 nm or less is preferably 55% or less, preferably It is 40% or less, more preferably 30% or less.

其原因在於,在波長為400nm以上且700nm以下之光之正反射率之平均值為55%以下之情況下,例如即使在作為觸控板用導電性基板使用時,也可特別地對顯示器之視認性之降低進行抑制。 The reason is that when the average value of the specular reflectance of light with a wavelength of 400 nm or more and 700 nm or less is 55% or less, for example, even when it is used as a conductive substrate for a touch panel, it can be particularly effective for the display The decrease in visibility is suppressed.

以上對本實施方式之積層體基板、導電性基板、積層體基板 之製造方法及導電性基板之製造方法進行了說明。根據該積層體基板或藉由積層體基板之製造方法獲得之積層體基板可知,銅層和低反射率合金配線層示出了相對於蝕刻液之大致相同之反應性。為此,能夠提供一種具備可同時被蝕刻之銅層和低反射率合金層之積層體基板。又,由於可同時對銅層和低反射率合金層進行蝕刻,故可容易地形成預期形狀之銅配線層和低反射率合金配線層。 The above description of the laminate substrate, conductive substrate, and laminate substrate of this embodiment The manufacturing method and the manufacturing method of the conductive substrate are described. According to the laminate substrate or the laminate substrate obtained by the method of manufacturing the laminate substrate, the copper layer and the low-reflectivity alloy wiring layer show approximately the same reactivity with respect to the etching solution. For this reason, it is possible to provide a laminate substrate having a copper layer and a low-reflectivity alloy layer that can be etched at the same time. In addition, since the copper layer and the low-reflectivity alloy layer can be etched at the same time, the copper wiring layer and the low-reflectivity alloy wiring layer of a desired shape can be easily formed.

又,藉由設置低反射率合金配線層,可對銅配線層之光反射進行抑制,例如在作為觸控板用導電性基板使用之情況下,可對視認性之降低進行抑制。為此,藉由設置低反射率合金配線層,可獲得具有良好視認性之導電性基板。 In addition, by providing a low-reflectivity alloy wiring layer, the light reflection of the copper wiring layer can be suppressed. For example, when it is used as a conductive substrate for a touch panel, the decrease in visibility can be suppressed. For this reason, by providing a low-reflectivity alloy wiring layer, a conductive substrate with good visibility can be obtained.

【實施例】 [Example]

以下根據本發明之實施例和比較例對本發明進行更詳細之說明,然本發明並不限於該等實施例。 Hereinafter, the present invention will be described in more detail based on the embodiments and comparative examples of the present invention, but the present invention is not limited to these embodiments.

(評價方法) (Evaluation method)

(1)正反射率 (1) Regular reflectance

對以下各實施例和比較例中所製作之積層體基板進行了正反射率之測定。 The regular reflectance was measured for the laminate substrates produced in the following examples and comparative examples.

測定是藉由在紫外可視分光光度計(島津製作所股份有限公司製 型號:UV-2550)設置反射率測定單元而進行之。 The measurement was performed by installing a reflectance measurement unit on an ultraviolet visible spectrophotometer (Model: UV-2550, manufactured by Shimadzu Corporation).

在各實施例中製作了具有圖3A之結構之積層體基板,反射率之測定則是藉由針對圖3A之第2低反射率合金層132之外部所露出之表面C以入射角為5°、受光角為5°之方式照射波長為400nm以上且700nm以 下之範圍之光來實施。需要說明的是,測定時,使照向積層體基板之光之波長在波長400nm以上且700nm以下之範圍內按照每1nm之幅度進行變化,並對各波長之光之正反射率進行測定,之後將測定結果之平均值作為該積層體基板之正反射率之平均值。 In each embodiment, a laminate substrate with the structure of FIG. 3A was produced, and the reflectance was measured by using the exposed surface C of the second low-reflectivity alloy layer 132 of FIG. 3A at an incident angle of 5° 、When the light receiving angle is 5°, the irradiation wavelength is 400nm or more and 700nm or less The light of the scope below is implemented. It should be noted that during the measurement, the wavelength of the light irradiated on the laminate substrate is changed in a range of 1 nm within the wavelength range of 400nm or more and 700nm or less, and the regular reflectance of the light of each wavelength is measured. The average value of the measurement results was taken as the average value of the regular reflectance of the laminate substrate.

(2)開口部的全光線穿透率的減少率 (2) Reduction rate of the total light transmittance of the opening

對各實施例和比較例中所製作之導電性基板之露出透明基材之金屬細線之間之開口部進行了全光線穿透率之測定。 The total light transmittance was measured for the openings between the thin metal wires of the conductive substrates exposing the transparent substrates of the conductive substrates produced in the respective examples and comparative examples.

測定是藉由在進行正反射率測定時之紫外可視分光光度計設置積分球附屬裝置來進行之。測定時,使照射之光之波長在波長400nm以上且700nm以下之範圍內以每1nm之幅度進行變化,並對各波長之光之穿透率進行測定,之後將測定結果之平均值作為該導電性基板之開口部的全光線穿透率之平均值。 The measurement is performed by installing an integrating sphere accessory device on the ultraviolet visible spectrophotometer when measuring the specular reflectance. In the measurement, the wavelength of the irradiated light is changed in the range of 400nm or more and 700nm or less in the range of 1nm, and the transmittance of the light of each wavelength is measured, and then the average of the measurement results is used as the conductivity The average value of the total light transmittance of the opening of the flexible substrate.

又,對預先製作積層體基板時所使用之透明基材也同樣地進行了全光線穿透率之平均值之測定。 In addition, the average value of the total light transmittance was measured in the same way for the transparent base material used when the laminate substrate was produced in advance.

接下來,對各實施例和比較例中所製作之導電性基板之開口部的全光線穿透率之平均值與透明基材之全光線穿透率之平均值相比之減少率(以下和表1中也記載為「開口部的全光線穿透率的減少率」)進行計算。 Next, the reduction rate of the average value of the total light transmittance of the openings of the conductive substrates produced in each of the examples and comparative examples and the average value of the total light transmittance of the transparent substrate (the following and Table 1 is also described as "the reduction rate of the total light transmittance of the opening") for calculation.

(試料之製作條件) (Production conditions of samples)

作為實施例和比較例,在以下所說明之條件下製作了積層體基板及導電性基板,並藉由上述評價方法對其進行了評價。 As an example and a comparative example, a laminate substrate and a conductive substrate were produced under the conditions described below, and they were evaluated by the above-mentioned evaluation method.

〔實施例1〕 [Example 1]

製作具有圖3A所示結構之積層體基板。 A laminate substrate having the structure shown in FIG. 3A is produced.

首先,實施透明基材準備步驟。 First, a transparent substrate preparation step is implemented.

具體而言,準備了寬度為500mm、厚度為100μm之光學用聚對苯二甲酸乙二酯樹脂(PET)製之透明基材。 Specifically, a transparent substrate made of polyethylene terephthalate resin (PET) for optics with a width of 500 mm and a thickness of 100 μm was prepared.

接下來,實施積層體形成步驟。 Next, a layered body forming step is implemented.

作為積層體形成步驟,實施了第1低反射率合金層形成步驟、銅層形成步驟、及第2低反射率合金層形成步驟。以下具體地進行說明。 As the layered body forming step, a first low-reflectivity alloy layer forming step, a copper layer forming step, and a second low-reflectivity alloy layer forming step were performed. This will be specifically described below.

首先實施第1低反射率合金層形成步驟。 First, the first low-reflectivity alloy layer forming step is performed.

將所準備之透明基材安放在圖6所示之輥對輥濺鍍裝置60。又,在濺鍍電極64a~64d上安放了銅-30質量%Ni之合金靶材(住友金屬礦山(股)製)。 The prepared transparent substrate is placed in the roll-to-roll sputtering device 60 shown in FIG. 6. In addition, an alloy target of copper -30 mass% Ni (manufactured by Sumitomo Metal Mining Co., Ltd.) was placed on the sputtering electrodes 64a to 64d.

接下來,使輥對輥濺鍍裝置60之加熱器69加熱至100℃,對透明基材進行加熱,以將基材中所含之水分除去。 Next, the heater 69 of the roll-to-roll sputtering device 60 is heated to 100° C. to heat the transparent substrate to remove the moisture contained in the substrate.

接下來,採用真空泵70a、70b將框體61之內部排氣至1×10-4Pa後,藉由氣體供給手段71,以氬氣之流量為240sccm之方式向框體61內進行氬氣之導入。接下來,一邊藉由卷出輥62以每分鐘2m之速度搬送透明基材,一邊從與濺鍍電極64a~64d連接之濺鍍用直流電源施加電力以進行濺鍍放電,據此在基材上連續地成膜預期之第1低反射率合金層。藉由該操作,在透明基材上形成了厚度為20nm之第1低反射率合金層131。 Next, after evacuating the inside of the frame 61 to 1×10 -4 Pa with vacuum pumps 70a and 70b, the argon gas is fed into the frame 61 by the gas supply means 71 at a flow rate of 240 sccm. Import. Next, while transporting the transparent substrate by the unwinding roller 62 at a speed of 2m per minute, power is applied from the sputtering DC power supply connected to the sputtering electrodes 64a to 64d to perform sputtering discharge. The expected first low-reflectivity alloy layer is continuously formed on the upper surface. By this operation, the first low-reflectivity alloy layer 131 with a thickness of 20 nm was formed on the transparent substrate.

接下來實施銅層形成步驟。 Next, a copper layer formation step is implemented.

在銅層形成步驟中,將安放在磁控濺鍍電極上之靶材置換為 銅靶材(住友金屬礦山(股)製),除此之外,與第1低反射率合金層同樣地在第1低反射率合金層之上面形成了厚度為200nm之銅層。 In the copper layer forming step, replace the target placed on the magnetron sputtering electrode with A copper target (manufactured by Sumitomo Metal Mining Co., Ltd.), except that a copper layer with a thickness of 200 nm was formed on the first low-reflectivity alloy layer in the same manner as the first low-reflectivity alloy layer.

需要說明的是,作為形成銅層之基材,使用了在第1低反射率合金層形成步驟中於透明基材上形成了第1低反射率合金層之基材。 It should be noted that, as the substrate for forming the copper layer, a substrate in which the first low-reflectivity alloy layer was formed on the transparent substrate in the first low-reflectivity alloy layer forming step was used.

接下來實施第2低反射率合金層形成步驟。 Next, a second low-reflectivity alloy layer forming step is performed.

在第2低反射率合金層形成步驟中,在與形成第1低反射率合金層131時相同之條件下於銅層12之上表面形成了第2低反射率合金層132(參照圖3A)。 In the second low-reflectivity alloy layer forming step, a second low-reflectivity alloy layer 132 is formed on the upper surface of the copper layer 12 under the same conditions as when forming the first low-reflectivity alloy layer 131 (see FIG. 3A) .

對所製作之積層體基板之波長為400nm以上且700nm以下之光之正反射率之平均值採用上述步驟進行了測定可知,其波長為400nm以上且700nm以下之光之正反射率之平均值為55%。 The average value of the specular reflectance of light with a wavelength of 400nm or more and 700nm or less of the fabricated laminate substrate was measured using the above steps, and the average value of the specular reflectance of light with a wavelength of 400nm or more and 700nm or less is 55%.

又,對獲得之積層體基板進行了正反射率之測定後,實施蝕刻步驟,製作導電性基板。 Furthermore, after measuring the specular reflectance of the obtained laminate substrate, an etching step was performed to produce a conductive substrate.

在蝕刻步驟中,首先,在所製作之積層體基板之圖3A之表面C上形成具有與要藉由蝕刻進行除去之部分相對應之開口部之光阻。接下來,將其浸漬在由10重量%之三氯化鐵、10重量%之鹽酸、及剩餘為水所組成之蝕刻液中1分鐘,製作了導電性基板。 In the etching step, first, a photoresist having an opening corresponding to the portion to be removed by etching is formed on the surface C of FIG. 3A of the produced laminate substrate. Next, it was immersed in an etching solution composed of 10% by weight of ferric chloride, 10% by weight of hydrochloric acid, and the remainder of water for 1 minute to produce a conductive substrate.

之後,對所製作之導電性基板進行了開口部的全光線穿透率的測定。 After that, the total light transmittance of the opening was measured for the produced conductive substrate.

評價結果示於表1。 The evaluation results are shown in Table 1.

〔實施例2~實施例6〕 [Example 2~Example 6]

除了將第1、第2低反射率合金層成膜時所使用之濺鍍靶材之組成變更 為表1所示之值之外,與實施例1同樣地製作了積層體基板,並進行評價。 Except for the composition change of the sputtering target used when forming the first and second low-reflectivity alloy layers Except for the values shown in Table 1, a laminate substrate was produced in the same manner as in Example 1, and evaluated.

又,基於所製作之積層體基板,與實施例1同樣地製作了導電性基板,並進行評價。 Moreover, based on the produced laminate substrate, a conductive substrate was produced in the same manner as in Example 1, and evaluated.

結果示於表1。 The results are shown in Table 1.

〔比較例1~比較例3〕 [Comparative Example 1~Comparative Example 3]

比較例1中,除了將第1、第2低反射率合金層成膜時所使用之濺鍍靶材之組成變更為表1所示之值之外,與實施例1同樣地製作了積層體基板,並進行評價。 In Comparative Example 1, a laminate was produced in the same manner as in Example 1, except that the composition of the sputtering target used in forming the first and second low-reflectivity alloy layers was changed to the values shown in Table 1. Substrate and evaluate it.

又,在比較例2、3中,取代第1、第2低反射率合金層形成了第1、第2黑化層。就第1、第2黑化層之成膜而言,除了將成膜時所使用之濺鍍靶材之組成變更為表1所示之值、及進行黑化層成膜時同時供給氬氣和氧氣之外,與實施例1之低反射率合金層同樣地進行了成膜。又,黑化層以外之部分都與實施例1相同,據此製作了積層體基板。 In addition, in Comparative Examples 2 and 3, the first and second blackened layers were formed instead of the first and second low-reflectivity alloy layers. Regarding the film formation of the first and second blackened layers, except that the composition of the sputtering target used in the film formation was changed to the values shown in Table 1, and the argon gas was also supplied when the blackened layer was formed. Except for oxygen, film formation was carried out in the same manner as the low-reflectivity alloy layer of Example 1. In addition, the parts other than the blackened layer were the same as in Example 1, and a laminate substrate was produced accordingly.

需要說明的是,在比較例2、3中,低反射率合金層成膜時採用表1所示之氧供給量進行了氧氣之供給。 It should be noted that in Comparative Examples 2 and 3, the oxygen supply amount shown in Table 1 was used for the oxygen supply when the low-reflectivity alloy layer was formed.

根據在比較例1~比較例3中所製作之積層體基板,與實施例1同樣地製作了導電性基板,並進行評價。 Based on the laminate substrates produced in Comparative Examples 1 to 3, conductive substrates were produced in the same manner as in Example 1, and evaluated.

結果示於表1。 The results are shown in Table 1.

Figure 105131030-A0202-12-0033-1
Figure 105131030-A0202-12-0033-1

由表1所示結果可知,就實施例1~實施例6而言,開口部的全光線穿透率的減少率為3.0%以下。即,可同時對銅層和第1、第2低反射率合金層進行蝕刻。 From the results shown in Table 1, it can be seen that in Examples 1 to 6, the reduction rate of the total light transmittance of the opening is 3.0% or less. That is, the copper layer and the first and second low-reflectivity alloy layers can be simultaneously etched.

其原因在於,由於第1、第2低反射率合金層成膜時所使用之濺鍍靶材中所含有之銅和鎳中之鎳之比率為30質量%以上且85質量%以下,故成膜後之低反射率合金層中也具有同樣之組成成分。即,可認為低反射率合金層之對蝕刻液之反應性與銅層相同。 The reason is that the ratio of copper and nickel contained in the sputtering target material used when forming the first and second low-reflectivity alloy layers is 30% by mass or more and 85% by mass or less. The low-reflectivity alloy layer after the film also has the same composition. That is, it can be considered that the reactivity of the low-reflectivity alloy layer to the etching solution is the same as that of the copper layer.

相對於此,在比較例1中,低反射率合金層成膜時所使用之濺鍍靶材中所含有之銅和鎳中之鎳之比率為小於30質量%,故成膜後之低 反射率合金層中也具有同樣之組成成分。因此,正反射率超過了55%。 In contrast, in Comparative Example 1, the ratio of copper and nickel contained in the sputtering target used in the formation of the low-reflectivity alloy layer is less than 30% by mass, so the ratio after film formation is low The reflectivity alloy layer also has the same composition. Therefore, the regular reflectance exceeds 55%.

又,在比較例2中,開口部的全光線穿透率的減少率超過了3.0%,可確認到與銅層相比,黑化層之蝕刻速度變慢,因此開口部的全光線穿透率的減少率變為3.5%,目視可確認到黃色。 In addition, in Comparative Example 2, the reduction rate of the total light transmittance of the opening exceeded 3.0%, and it was confirmed that the etching rate of the blackened layer was slower than that of the copper layer, so the total light transmitted through the opening The reduction rate of the rate becomes 3.5%, and the yellow color can be confirmed visually.

在比較例3中,確認到底切,還確認到了與銅層相比,黑化層之蝕刻速度變快。 In Comparative Example 3, the undercut was confirmed, and it was also confirmed that the etching rate of the blackened layer was faster than that of the copper layer.

故就比較例2、3而言,確認到不能形成同時可被進行蝕刻處理之銅層和黑化層。 Therefore, in Comparative Examples 2 and 3, it was confirmed that the copper layer and the blackened layer that could be etched at the same time could not be formed.

以上對積層體基板、導電性基板、積層體基板之製造方法及導電性基板之製造方法參照實施方式及實施例等進行了說明,然本發明並不限定於上述實施方式及實施例等。在申請專利範圍記載之本發明之要旨之範圍內,還可進行各種各樣之變形和變更。 As mentioned above, the multilayer substrate, the conductive substrate, the manufacturing method of the multilayer substrate, and the manufacturing method of the conductive substrate have been described with reference to the embodiments and examples, but the present invention is not limited to the above embodiments and examples. Various modifications and changes can be made within the scope of the gist of the present invention described in the scope of the patent application.

本申請基於2015年9月28日向日本專利廳申請之特願2015-189936號主張優先權,並將特願2015-189936號之全部內容引用於本國際申請。 This application claims priority based on Japanese Patent Application No. 2015-189936 filed to the Japan Patent Office on September 28, 2015, and the entire content of Japanese Patent Application No. 2015-189936 is cited in this international application.

10A‧‧‧積層體基板 10A‧‧‧Laminate substrate

11‧‧‧透明基材 11‧‧‧Transparent substrate

11a‧‧‧一個面 11a‧‧‧One side

11b‧‧‧另一個面 11b‧‧‧The other side

12‧‧‧銅層 12‧‧‧Copper layer

13‧‧‧低反射率合金層 13‧‧‧Low reflectivity alloy layer

A‧‧‧表面 A‧‧‧surface

X、Y‧‧‧X軸、Y軸 X, Y‧‧‧X axis, Y axis

Claims (11)

一種積層體基板,其具備:透明基材、及積層體,其直接形成在該透明基材之至少一個面側;該積層體由含有銅和鎳之低反射率合金層及銅層構成,該低反射率合金層所含有之該銅和該鎳中之該鎳之比率為30質量%以上且85質量%以下。 A laminated body substrate comprising: a transparent substrate and a laminated body directly formed on at least one surface side of the transparent substrate; the laminated body is composed of a low-reflectivity alloy layer containing copper and nickel and a copper layer, the The ratio of the copper contained in the low-reflectivity alloy layer to the nickel in the nickel is 30% by mass or more and 85% by mass or less. 如申請專利範圍第1項之積層體基板,其中,該積層體具有第1低反射率合金層和第2低反射率合金層作為該低反射率合金層,該銅層配置在該第1低反射率合金層和該第2低反射率合金層之間。 For example, the laminated body substrate of the first item of the patent application, wherein the laminated body has a first low-reflectivity alloy layer and a second low-reflectivity alloy layer as the low-reflectivity alloy layer, and the copper layer is arranged on the first low-reflectivity alloy layer. Between the reflectance alloy layer and the second low reflectance alloy layer. 如申請專利範圍第1或2項之積層體基板,其中,波長為400nm以上且700nm以下之光之正反射率之平均值為55%以下。 For example, the laminated substrate of item 1 or 2 in the scope of patent application, wherein the average value of the specular reflectance of light with a wavelength of 400nm or more and 700nm or less is 55% or less. 一種導電性基板,其具備:透明基材、及金屬細線,其直接形成在該透明基材之至少一個面側,該金屬細線為由含有銅和鎳之低反射率合金配線層及銅配線層構成的積層體,該低反射率合金配線層所含有之該銅和該鎳中之該鎳之比率為30質量%以上且85質量%以下。 A conductive substrate comprising: a transparent base material and a thin metal wire formed directly on at least one surface side of the transparent base material, the thin metal wire being made of a low-reflectivity alloy wiring layer containing copper and nickel and a copper wiring layer In the laminate formed, the ratio of the copper contained in the low-reflectivity alloy wiring layer and the nickel in the nickel is 30% by mass or more and 85% by mass or less. 如申請專利範圍第4項之導電性基板,其中,該金屬細線具有第1低反射率合金配線層和第2低反射率合金配線層作為該低反射率合金配線層,該銅配線層配置在該第1低反射率合金配線層和該第2低反射率合金配線層之間。 For example, the conductive substrate of item 4 of the scope of patent application, wherein the thin metal wire has a first low-reflectivity alloy wiring layer and a second low-reflectivity alloy wiring layer as the low-reflectivity alloy wiring layer, and the copper wiring layer is disposed on Between the first low-reflectivity alloy wiring layer and the second low-reflectivity alloy wiring layer. 如申請專利範圍第4或5項之導電性基板,其中,該金屬細線之間設置有露出該透明基材之開口部,該開口部之波長為400nm以上且700nm以下之光之穿透率之平均值與該透明基材之波長為400nm以上且700nm以下之光之穿透率之平均值相比的減少率為3.0%以下。 For example, the conductive substrate of item 4 or 5 of the scope of patent application, wherein an opening portion exposing the transparent substrate is provided between the thin metal wires, and the wavelength of the opening portion is greater than 400nm and less than 700nm. The reduction rate of the average value compared to the average value of the transmittance of light having a wavelength of 400 nm or more and 700 nm or less of the transparent substrate is 3.0% or less. 一種積層體基板之製造方法,其具有以下步驟:準備透明基材之透明基材準備步驟、及在該透明基材之至少一個面側直接形成積層體之積層體形成步驟,該積層體形成步驟包含以下步驟:銅層形成步驟,其藉由沉積銅之銅層成膜手段形成銅層、及低反射率合金層形成步驟,其藉由沉積含有銅和鎳之低反射率合金層之低反射率合金層成膜手段,而成膜低反射率合金層;該積層體由該低反射率合金層及該銅層構成,該低反射率合金層形成步驟在減壓環境下實施,該低反射率合金層中所含有之該銅和該鎳中之該鎳之比率為30質量%以上且85質量%以下。 A method for manufacturing a laminate substrate, which has the following steps: a transparent substrate preparation step for preparing a transparent substrate, a laminate formation step for directly forming a laminate on at least one side of the transparent substrate, the laminate formation step It includes the following steps: a copper layer forming step, which forms a copper layer by depositing a copper layer of copper, and a low reflectivity alloy layer forming step, which is formed by depositing a low reflectivity alloy layer containing copper and nickel Means for forming a low-reflectivity alloy layer to form a low-reflectivity alloy layer; the laminate is composed of the low-reflectivity alloy layer and the copper layer, and the low-reflectivity alloy layer forming step is carried out under a reduced pressure environment. The ratio of the copper contained in the alloy layer to the nickel in the nickel is 30% by mass or more and 85% by mass or less. 如申請專利範圍第7項之積層體基板之製造方法,其中, 該低反射率合金層成膜手段為濺鍍成膜法。 For example, the manufacturing method of laminated substrate of item 7 of the scope of patent application, in which, The method for forming the low-reflectivity alloy layer is a sputtering method. 如申請專利範圍第7或8項之積層體基板之製造方法,其中,該低反射率合金層之厚度為10nm以上。 For example, the manufacturing method of the laminated substrate of the 7th or 8th patent application, wherein the thickness of the low-reflectivity alloy layer is 10nm or more. 一種導電性基板之製造方法,其具有以下步驟:對藉由申請專利範圍第7至9項中之任一項之積層體基板之製造方法獲得之積層體基板之該銅層和該低反射率合金層進行蝕刻,以形成具有金屬細線之配線圖案之蝕刻步驟,該金屬細線為具備銅配線層和低反射率合金配線層之積層體;且藉由該蝕刻步驟於該銅層和該低反射率合金層形成開口部。 A method of manufacturing a conductive substrate, which has the following steps: the copper layer and the low reflectivity of a multilayer substrate obtained by the method of manufacturing a multilayer substrate of any one of the 7th to 9th patents The alloy layer is etched to form an etching step of a wiring pattern with thin metal wires, the thin metal wires being a laminate with a copper wiring layer and a low-reflectivity alloy wiring layer; and the etching step is performed on the copper layer and the low reflection The rate alloy layer forms an opening. 如申請專利範圍第10項之導電性基板之製造方法,其中,獲得之導電性基板之波長為400nm以上且700nm以下之光之正反射率之平均值為55%以下。 For example, the method for manufacturing a conductive substrate in the scope of the patent application, wherein the obtained conductive substrate has an average value of the specular reflectance of light with a wavelength of 400 nm or more and 700 nm or less of 55% or less.
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