TWI711090B - 在氧化物接合晶圓堆疊中的晶粒封裝 - Google Patents

在氧化物接合晶圓堆疊中的晶粒封裝 Download PDF

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TWI711090B
TWI711090B TW106143303A TW106143303A TWI711090B TW I711090 B TWI711090 B TW I711090B TW 106143303 A TW106143303 A TW 106143303A TW 106143303 A TW106143303 A TW 106143303A TW I711090 B TWI711090 B TW I711090B
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wafer
cavity
semiconductor
assembly
die
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TW106143303A
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TW201907493A (zh
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約翰 德瑞普
傑森 米爾恩
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美商雷神公司
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Abstract

製造半導體晶圓組件的結構及方法，其將一或多個晶粒封裝於被蝕刻進入氧化物接合之半導體晶圓堆疊的孔腔中。該等方法大致上包括以下步驟：將該晶粒定位在該孔腔中、將該晶粒機械地及電安裝至該晶圓堆疊、及藉由以多數個方式之其中一者將蓋體晶圓接合至該晶圓堆疊而把該晶粒封裝在該孔腔內。半導體處理步驟被應用，以根據上述實施例製成該等組件(例如沈積、退火、化學及機械拋光、蝕刻等)及連接該晶粒(例如凸塊接合、引線互連、超音波接合、氧化物接合等)。

Description

在氧化物接合晶圓堆疊中的晶粒封裝
本揭示內容有關積體電路、半導體裝置及其他小型化裝置的製造，且更特別地是，有關三維積體電路(3D-ICs)之製造包括被封裝於氧化物接合晶圓堆疊中的半導體晶粒。
因半導體裝置尺寸已減少，3D裝置整合已變成用於增加積體電路及/或半導體裝置之密度的想要方法，隨同比較於2D設計較高之性能及較低的功率提供遠較小之形狀因數。3D-IC組件係使用水平內疊及直立(矽穿孔、TSVs)中間層連接件，由有效電子零組件(例如感測器及讀出電路)的二或更多堆疊層所組成，以致它們充當作單一裝置。封裝間堆疊及晶粒間(D2D)堆疊允許用於堆疊之“已知良好晶粒”的選擇，且比較於3D能提供較高產出但有限之性能改善。2D方式有時候使用需要長連接的線接合，該長連接使該速率慢下來及限制可能連接之數目。更簡練確切的2.5D解決方法使用凸塊接合至中介器，其提供電路間之選路，但仍然導致比真實的3D電路較高之功率及較低的性能。亦，由於該晶粒之超薄本質，D2D堆疊係難以處理及易於破壞及污染。晶圓間(W2W)3D堆疊允許TSVs被按比例縮減至較小直徑，具有較薄的晶圓，允許較高之3D連接密度，導致較高的頻寬、性能、及功率改善，且提供較低之製造成本。然而，因為，如果3D-IC中的N個晶片之任一者係有缺陷的，該整個3D-IC將為有缺陷，3D堆疊能遭受減少之產出。此外，具有相同尺寸的晶圓，該晶圓堆疊係最佳，且既然非矽材料(例如III-V’s)典型係在比矽CMOS邏輯或DRAM較小之晶圓上製成，晶圓級異質模組整合能對製造及產出造成挑戰。
使用氧化物接合的3D整合主要已被使用於接合整個晶圓，因該處理係不如用於在該晶粒級之接合般成熟。銲接密封晶圓級 封裝已被示範，如具有設有孔腔的晶圓之接合。習知技術係可用於積體電路晶粒至矽晶圓上之直接的金屬間之接合，但該等技術對於高層計數晶圓堆疊晶粒具有限制，以處理應力、產出、互連密度及熱限制。其他技術已整合多數晶粒至中介器上，但在該z軸中未進一步延伸該堆疊至超過2-3層，也未達成異質或全封閉的密封裝置。
本揭示內容考慮用於3D-ICs之製造的新及改良方法，並使用克服目前限制之晶粒封裝。一些實施例亦致力於用在片上熱管理的需要，而允許較高之功率消耗及較大的封裝密度。
本揭示內容係針對封裝一或多個裝置晶粒之氧化物接合半導體晶圓組件、及用於形成它們的製程。於一實施例中，該晶圓組件包括第一晶圓，具有包括氧化物層之第一表面；第二晶圓，具有第一表面及第二表面，該第一表面包括被接合至該第一晶圓的氧化物層之氧化物層；及其中該第一及第二晶圓界定一孔腔。半導體晶粒係在該孔腔中機械地及電連接至該第一晶圓，且具有被接合至該第二晶圓的第二表面之第一表面的第三晶圓封裝該晶粒。該晶粒可為藉由凸塊接合、引線互連、超音波接合、及/或氧化物接合所連接。該封裝可包含密閉式密封。該等晶圓之每一個可包括積體電路(IC)及一或多個矽穿孔(TSVs)，用於電連接該等晶圓之中的ICs與該晶粒、及至外部裝置與晶圓。
在另一實施例中，熱介面可被形成於該半導體晶粒及該等晶圓的一或多個之間。
在另一實施例中，該第二(中間)晶圓及該第三(蓋體)晶圓被凸塊接合，以便界定提供與該孔腔熱隔離的氣隙。
於另一實施例中，該第二(中間)晶圓之第二表面及該第三(蓋體)晶圓的第一表面之每一個包括氧化物層。該第二及第三晶圓可為在其個別氧化物層被接合在一起的氧化物。
於另一實施例中，該第一、第二及第三晶圓之一或多個可具有由該晶圓組件的外部至該孔腔之管道。該管道及該孔腔可為至少局部地充填以熱傳導性或另一功能性材料。該管道及孔腔可被排空 及密封，而提供真空包裝以增強熱隔離。該管道及孔腔可在該孔腔被密封之前被排空及回填以液體或氣體。
於另一態樣中，提供製造半導體晶圓組件的方法，其在被蝕刻進入氧化物接合之半導體晶圓堆疊的孔腔中封裝一或多個晶粒。該等方法大致上包括藉由以多數個方式之其中一者將蓋體晶圓接合至該晶圓堆疊，將該晶粒定位在該孔腔中、將該晶粒機械地及電安裝至該晶圓堆疊、及將該晶粒封裝在該孔腔內的步驟。半導體處理步驟根據上述實施例被應用至製成該等組件(例如光刻、沈積、退火、化學及機械拋光、蝕刻等)及連接該晶粒(例如凸塊接合、引線互連、超音波接合、氧化物接合等)。
所揭示之實施例其它目的及優點將由以下之詳細敘述被較佳了解。
10、12、14、16、18、20、22、24、26、30、32、34、36、40、42、44、46‧‧‧步驟
100‧‧‧晶圓組件
102‧‧‧底部晶圓
104‧‧‧中間晶圓
106‧‧‧頂部晶圓
108‧‧‧晶粒
110‧‧‧孔腔
112‧‧‧凸塊
114‧‧‧墊片
116‧‧‧底部表面
118‧‧‧頂部表面
120‧‧‧底部表面
122‧‧‧頂部表面
124‧‧‧IC
126‧‧‧IC
128‧‧‧IC
130‧‧‧TSV
130a‧‧‧TSV
130b‧‧‧TSV
132‧‧‧中介晶圓堆疊
134‧‧‧凸塊墊片
136‧‧‧氧化物層
138‧‧‧氧化物層
139‧‧‧共價接合線
140‧‧‧端部
142‧‧‧互連墊片
144‧‧‧硬保護遮罩
146‧‧‧區域
148‧‧‧BOX層
150‧‧‧直立側壁
152‧‧‧直立側壁
154‧‧‧底部表面
156‧‧‧IC
158‧‧‧凸塊
160‧‧‧介面
162‧‧‧介面
164‧‧‧介面
166‧‧‧IC
168‧‧‧管道
170‧‧‧導熱材料
200‧‧‧晶圓堆疊
202‧‧‧裝置晶粒
204‧‧‧孔腔
206‧‧‧底部晶圓
208‧‧‧中間晶圓
210‧‧‧蓋體晶圓
212‧‧‧凸塊墊片
214‧‧‧凸塊
216‧‧‧底部表面
218‧‧‧背後
220‧‧‧接點
222‧‧‧半導體晶圓組件
224‧‧‧氣隙
226‧‧‧電連接部
400‧‧‧晶圓堆疊
402‧‧‧裝置晶粒
404‧‧‧孔腔
406‧‧‧底部晶圓
408‧‧‧中間晶圓
410‧‧‧蓋體晶圓
412‧‧‧熱介面層
414‧‧‧表面
416‧‧‧表面
418‧‧‧表面
420‧‧‧電凸塊
422‧‧‧表面
424‧‧‧晶圓組件
本揭示內容的至少一實施例之各種態樣係在下面參考所附圖面被討論。其將被了解用於說明的單純及清楚，被顯示在該等圖面中之元件不需被精確地或按一定比例地畫出。譬如，該等元件的部份之尺寸可為了清楚相對其他元件被誇大，或數個實體零組件可被包括在一功能性部件或元件中。在此被適當地考慮，參考數字可在該等圖面之中被重複，以指示對應或類似元件。用於清楚之目的，並非每一個零組件可在每一圖示中被標明。用於說明及解釋之目的，該等圖面被提供，且係不意欲為本發明之限制的定義。於該等圖面中：圖1係根據說明性實施例，用於將一或多個裝置晶粒封裝於氧化物接合3D-IC晶圓堆疊中之三個替代方法的流程圖；圖2A-2F係3D-IC晶圓堆疊之未組裝及局部組裝的零組件之概要截面圖解，且圖2G及2H係根據某些實施例的3D-IC半導體晶圓組件之概要截面圖解；圖3A-3C係3D-IC晶圓堆疊的局部組裝零組件之概要截面圖解，且圖3D係根據某些實施例的3D-IC晶圓組件之概要截面圖解；及圖4A-4C係3D-IC晶圓堆疊的局部組裝零組件之概要截 面圖解，且圖4D係根據某些實施例的3D-IC晶圓組件之概要截面圖解。
在以下的詳細敘述中，極多特定細節被提出，以便提供本揭示內容之態樣的完全理解。其將被那些普通熟習該技術領域者所了解，這些可沒有這些特定細節之獨立地一些細節而被實踐。於其他情況中，熟知方法、程序、零組件及結構可能尚未被詳細地敘述，以便不會使該等實施例含糊不清。
較佳實施例之以下敘述本質上係僅只示範的，且係絕無意欲限制該揭示內容、其應用、或使用。應了解的是在此中所採用之用語及術語亦係僅只用於敘述之目的，且不應被當作限制。應了解的是為清楚故，某些特色在分開實施例之背景下被敘述，但亦可被組合地提供於單一實施例中。反之，為簡潔故，各種特色在單一實施例的背景下被敘述，但亦可被分開地或以任何合適之次組合來提供。
沒有在此中所使用的元件、作用、或指示應被解釋為緊要的或必不可少的，除非如此被明確地敘述。如在此中所使用，該等冠詞“一(a)”及“一(an)”係意欲包括一或多個項目，並能與“一或多個”可交換地使用。再者，該片語“基於”係意欲意指“至少局部地基於”，除非以別的方式明確地陳述。其將被進一步了解該“包含”、“具有”、“包括”、及“含有”等詞、及這些名詞之任何形式係廣泛的連結動詞。其結果是，“包含”、“具有”、“包括”、或“含有”一或多個步驟或元件之方法或裝置擁有那些一或多個步驟或元件，但不被限制於僅只擁有那些一或多個步驟或元件。再者，被敘述為以某一方式建構的裝置或晶圓結構係至少以該方式被建構，但亦可被以未顯示之方式建構。
用於下文敘述之目的，該“上”、“下”、“頂部”、“底部”、“直立”、“水平”、“正面”、“背後”等詞及其衍生詞將有關所揭示之結構及方法，如於該等圖形中被定向。“在頂部上”、“鄰接”、“定位在...上”或“定位置在頂部上”等詞意指第一元件、諸如第一裝置結構或層係存在第二元件、諸如第二裝置結構或層上或接近該第二元件，其中介入元件、諸如介面結構或層可為存在， 且不須意指譬如第一晶圓層及第二晶圓層正彼此直接地接觸，而在該二層的介面沒有任何中間傳導、隔離或半導體層。
半導體元件、諸如球柵陣列封裝(BGA)能被用作航太感測器架構及/或其他半導體架構之一部份。在該光子學領域中，由於與這些材料的直接能帶隙有關聯之優異的光激性質，基於III-V材料的磷化銦(InP)及砷化鎵(GaAs)已為一關鍵技術。在大多數情況下，該等半導體元件之每一者被軟焊至建立該半導體陣列的主要電路板(例如主機板、陣列等)。如在此中所使用，該“晶粒”一詞意指已被製成具有IC之一小塊半導體材料，其包括、但不限於CMOS、光電子器件、紅外線偵測器、MEMS、與類似者等，且該“晶圓”一詞被使用於意指半導體材料的薄片，其可包含基板層及/或被使用於ICs之製造。晶圓典型被建構成圓形，但可為與氧化物接合處理相容的任何尺寸或形狀，包括、但不限於長方形面板尺寸或方塊形狀及尺寸。該“凸塊”及“凸起部”意指半導體封裝技術，其將焊料球附接至晶圓或晶粒之接合墊(例如在TSV連接器墊片)，形成至晶圓堆疊或組件中的其他裝置及/或晶圓之連接點。該接合墊可被以氧化物接合至支援晶圓、諸如經過DBH接合、在凸塊金屬化之下的無電鍍鎳浸金等。僅只用於清楚之目的，該“半導體晶圓組件”一詞意指多數個半導體晶圓及被封裝在其中之至少一晶粒的合成結構，其係源自根據目前所揭示之方法的任何實施例所製造，而該“晶圓堆疊”一詞被使用於意指在該半導體晶圓組件之製造的任何中介階段之晶圓及晶粒結構。
於大部分D2W應用中，電子零組件被建立在二半導體晶圓上。一晶圓被切成方塊形，且該單切晶粒被對齊與連接(例如藉由接合引線互連等)至該第二晶圓的晶粒位址上。如於W2W方法中，薄化及TSV互連設立係在接合之前或之後於D2W應用中施行。
參考圖1，流程圖說明用於形成半導體晶圓組件的方法10(具有多數個另外選擇之實施例)，其中裝置晶粒被封裝在三個半導體晶圓內，其每一者可包括IC。方法10的實施例之個別步驟在下文參考圖2A-2H、3A-3D及4A-4D被詳細地敘述。該等實施例包括未示出的步驟，用於傳統上在被使用於製造晶圓組件中之一或多個半導體晶圓上 建立電路系統(例如跡線、零組件、電氣導通孔)。方法10的實施例以共同之最初步驟12(在二個矽晶圓的相反面中形成對應之TSV)、步驟14(形成及直接鍵雜化(DBH)氧化物接合TSV凸塊墊片至該等晶圓上及將氧化物層沈積在該相反面上)、步驟16(平坦化及接合該等晶圓)、及18(於製備中顯露該TSV、形成及DBH氧化物接合TSV墊片、沈積及平坦化該晶圓堆疊的頂部表面上之氧化物層，且接著平坦化硬保護遮罩，用於蝕刻該頂部表面)開始。方法10的實施例接著稍微分岔，以容納該等晶圓及該已完成之晶圓組件的被封裝晶粒間之變動連接選擇。每一實施例包括步驟(例如分別步驟20、30、40)，用於將一或多個孔腔蝕刻進入該晶圓堆疊、移去該硬保護遮罩、及製備被用作孔腔密封蓋的第三晶圓之變型。
該完成的半導體晶圓組件之相異組構係經過方法10的三個示範實施例之變動的最後步驟來達成。於第一實施例中，步驟22(安裝及接合晶粒、蓋體晶圓拋光)、步驟24(蓋體晶圓接合)、及選擇性步驟26(管道蝕刻、熱充填、切成方塊形)形成該晶圓組件，使得被接合至該底部晶圓之一或多個晶粒凸塊被全封閉地密封在已蝕刻的孔腔中。於第二實施例中，步驟32(晶粒與孔腔製備)、步驟34(晶粒附接與蓋體晶圓凸起)、及步驟36(蓋體晶圓附接、底部晶圓TSV凸起、切成方塊形)形成該晶圓組件，使得蓋體晶圓封裝及被凸塊接合至該已安裝好之晶粒、以及該中間晶圓。方法10的第三實施例係類似於該第一實施例，除了步驟42(晶粒安裝及接合、熱介面形成)、44(清洗、氧化物接合蓋體晶圓)及46(底部晶圓TSV凸起、切成方塊形)導致該蓋體晶圓及被接合至所封裝晶粒的熱介面間之氧化物接合以外。當管道(或通氣孔)的選擇性蝕刻及以熱材料底部充填僅只被顯示在步驟26中，其被了解此等操作可於任何實施例中被採用。
圖2A-2H、3A-3D及4A-4D概要地顯示對應於方法10之實施例的連續個別製程步驟之晶圓結構。參考圖2A中所顯示的半導體晶圓組件100之第一實施例的概要截面說明圖，在此中所揭示者係能夠使晶圓(基板)接合3D-IC整合於一裝置封裝中之技術，其使用一或多個半導體晶圓(例如底部晶圓102、中間晶圓104及蓋體晶圓106)的氧化物 接合，以如果如此想要將晶粒108全封閉地包入在一密封體積內、諸如孔腔110，其已被蝕刻進入該等晶圓102、104、106之一或多個。以適當用於晶圓級3D-IC整合的格式，該等技術允許裝置晶粒型式之合併，其不能被傳統處理所供應。該晶粒108典型係由半導體材料、諸如矽所形成，雖然其他材料能被使用係可預知的。經過DBH接合或在凸塊112及墊片114藉由使用凸塊接合，該晶粒108之機械及電氣整合至底部晶圓102及選擇性至蓋體晶圓106能被施行。於其他實施例中，該晶粒108可藉由電線或類似互連件及/或藉由氧化物或超音波接合被機械地及電連接。
圖2B係晶圓組件100的前端處理中所使用之未組裝底部晶圓102及中間晶圓104的概要截面圖解(其對應於方法10之步驟12)。中間晶圓104可為由矽或另一可蝕刻材料所組成，而該底部晶圓102及頂部晶圓106可為由矽或不同材料、諸如碳化矽、熔融石英、玻璃、藍寶石、砷化鎵、磷化銦、絕緣層上覆矽(SOI)、金屬、陶瓷及其他電介體、傳導性、或半導體材料所組成。於此實施例中，該等晶圓102、104可由半導體晶圓、諸如矽半導體晶圓所組成，然而其他型式的材料可被使用。該等晶圓102、104大致上係平坦的。底部晶圓102包括底部表面116及面朝孔腔之頂部表面118，且中間晶圓104包括面朝孔腔的底部表面120及頂部表面122。底部晶圓102可包括設置在面朝孔腔之表面118上或剛好在面朝孔腔的表面118下方之IC 124。中間晶圓104亦可具有被放置在面朝孔腔的底部表面120及頂部表面122之任一或兩者上、或於面朝孔腔的底部表面120及頂部表面122之任一或兩者下方的ICs 126、128。
複數個TSVs 130a、130b等(大致上130)可被形成於晶圓102、104之每一者中，並以導電材料(銅、鋁、鎢、摻雜多晶矽等)充填。TSVs 130被選擇性配置，以提供複數個電互連件，其允許該等晶圓102、104將電信號傳輸例如至在給與的晶圓內及/或於(圖2A的)裝置晶粒圖108之間的電零組件。TSVs 130能使用各種半導體處理方法被形成。譬如，在一些實施例中，一系列光微影及化學製程被施行，以由該等晶圓102、104移去材料，以產生該等通孔130。於一些實施例中， 添加製程被使用於將額外材料加至該等晶圓102、104，以產生該TSVs 130。
參考圖2C(其對應於方法10之步驟14)，底部晶圓102及中間晶圓104的鄰接表面118、120被處理，以製備用於接合之晶圓，以建立一中介晶圓堆疊132(圖2D中所顯示)。在此實施例中，該等表面118、120被處理，以加入一或多個凸塊墊片134，用於未來與該裝置晶粒102互連(在圖1中所顯示)。氧化物層136、138可接著被形成在該等晶圓102、104的相反表面118、120上。當矽被暴露至氧(或包括氧之流體、例如空氣)時，二氧化矽被形成在矽晶圓表面上。當矽在周遭條件之下被暴露至空氣時，氧化物的薄層(例如10Å)能被形成在該等表面118、120上。各種半導體加工技術被使用於在矽表面上建立二氧化矽。這些技術典型涉及處理使用較高之溫度及不同的環境(例如流體)之矽晶圓，以在矽上可控制地生長二氧化矽層。譬如，超過600℃的溫度通常被使用於O2或H2O環境。然而，350℃通常係用於有效矽晶圓之限制，以便避免該晶圓的遞降性能。每一表面118、120上之被形成的氧化物層可接著被拋光，以產生與該等凸塊墊片134共平面的平滑氧化物層表面136、138。各種技術能被使用於建立該等平滑之表面。譬如，晶圓表面118、120的化學或機械式平坦化能被完成，以藉由拋光、蝕刻、或該二者之結合產生平滑的表面。在一些實施例中，該等晶圓102、104之表面118、120可藉由將該等晶圓暴露至研磨及/或腐蝕化學品而被平滑化，並會同與該等晶圓表面118、120接觸及係相對該等晶圓運動的拋光墊片。於一些實施例中，該等表面118、120被平滑化至少於10Å之表面粗糙度。
該等晶圓102、104可接著被接合在一起，以形成如在圖2D中所顯示的晶圓堆疊132(對應於方法10之步驟16)，其描述晶圓堆疊132的截面視圖。該等晶圓102、104可為藉由DBH所氧化物接合在一起及藉由將其平坦化之氧化物表面118、120帶入彼此接觸來退火，以建立該等晶圓112、114間之共價接合線139。該共價接合線139係大致上較薄，且具有比目前在傳統晶圓組件中被使用於將晶圓接合在一起的有機黏結接合較少之熱阻抗。因為該共價接合線139係相當薄(例如比軟 焊劑凸塊及底層填料較薄)，互連件能被以遠較高的間距密度放置在該等晶圓102、104上。
參考圖2E(其對應於方法10之步驟18)，底部晶圓102的被暴露底部表面116及晶圓堆疊132之頂部晶圓104的頂部表面122可接著被薄化及平坦化，以顯露TSVs 130之端部140，且互連墊片142可在該等被顯露的TSVs端部140被氧化物接合至表面116、122上。氧化物層(未示出)可接著被選擇性加入及平坦化，且硬遮罩144形成在晶圓表面122的各區域之上，以被保護免於遭受隨後的蝕刻製程。
參考圖2F(其對應於方法10之步驟20)，經過未被該硬保護遮罩144所保護的中間晶圓104之頂部表面122的區域146之蝕刻，孔腔110可接著被形成在該晶圓堆疊132中(每一者被顯示於圖2E中)。硬保護遮罩144(例如由TiW合金所組成)的使用允許遠較寬廣之處理溫度範圍，能夠使用寬廣範圍的技術讓該裝置晶粒(未示出)被安裝在該孔腔110中。孔腔110可在氧化物接合線139被蝕刻進入該中間晶圓104直至埋藏之氧化物(BOX)層148，該氧化物接合線139先前形成在(步驟16)底部晶圓102及中間晶圓104之間。該BOX層148用作用於該孔腔蝕刻製程的蝕刻停止層，顯露用於連接至裝置晶粒108之凸塊墊片134(被顯示於圖2G中)，其先前被形成(步驟14)在該等晶圓102、104的表面上。該孔腔110之外周邊可被該大體上平面式BOX層148與該孔腔110的大體上直立側壁150、152(及進一步藉由待加入蓋體晶圓106的底部表面154所界定)之相交處所界定。孔腔110可基於被封裝的晶粒之數目及尺寸且基於熱管理設計需求而被以各種尺寸蝕刻，並利用矽蝕刻法、較佳地係深反應離子蝕刻(DRIE)、產生正交於該BOX層148的幾乎直立之側壁。另一選擇係，孔腔110可使用反應離子蝕刻(RIE)或異向性化學品蝕刻(其可導致傾斜或斜面側壁)被蝕刻。孔腔110的功能包括提供裝置晶粒108環境保護、高密度電路互連、物理封裝及熱介面、以及使裝置功能性模糊不清、及提供來自逆向工程之裝置安全性。蓋體晶圓106的底部表面154(其可包括面朝下之IC 156)可經過氧化物層形成及平坦化同時發生地被製備用於氧化物接合。
參考圖2G(其對應於方法10的步驟22)，一或多個同種或 異種裝置晶粒108可接著經由凸塊158被機械地及電連接至孔腔110中所暴露之凸塊墊片134。該晶粒安裝製程可包括各種技術，包括超音波接合、軟焊凸起(例如經由凸塊接合部134)、或氧化物接合、打線接合、環氧基樹脂，並可在該晶粒及晶圓102、104間之任何表面上的多數個組構中包括電、機械、或熱介面，該晶粒被接合至該等表面。表一呈現示範之瞬態液相軟焊凸塊技術，其可被利用於安裝裝置晶粒108。
Figure 106143303-A0202-12-0010-1
參考圖2H(其對應於方法10的步驟24)，在該晶粒108被安裝至該孔腔110中的凸塊墊片134之後，該硬遮罩層144(圖2G中所顯示)可被移去，允許該蓋體晶圓106被安裝至該晶圓堆疊132。於所顯示的實施例中，孔腔110藉此在中間晶圓104的頂部表面118之剩餘部份及蓋體晶圓106的底部表面154間之晶圓介面160、162正以非常堅固之氧化物接合部包圍。選擇性地，熱材料層164可被形成在該晶粒108上，提供晶粒108及蓋體晶圓106間之熱介面。另外，或另一選擇地，類似熱介面(未示出)可被形成於該晶粒108及一或多個其他晶圓102、104及/或另一晶粒之間，以便輔助熱管理該3D-IC晶圓組件100。蓋體晶圓106可為在介面160、162氧化物接合，以形成完整的半導體晶圓組件100。於一些實施例中，該蓋體晶圓106可包含源自獨立之半導體製造製程中的晶圓上下堆疊之外部層。在底部晶圓102的底部表面116中之TSVs 130的所顯露之端部166、及底部晶圓102的底部表面116上所形成之互連墊片142可提供電路徑，用於該晶粒108及晶圓102、104、106間之連接部至外部裝置及晶圓(未示出)。在其他實施例中，使用軟焊或熱 壓縮接合，中間晶圓104的頂部表面118之剩餘部份及蓋體晶圓106的底部表面154可在該等介面162、164被接合。如所注意者，該接合製程可在該等介面160、162密封孔腔110，以便形成封裝該裝置晶粒108之密閉式密封。
該頂部表面118及底部表面154能在該等介面160、162無任何外部壓力地被接合。然而，於諸如熱壓縮接合的一些實施例中，額外之壓力被施加至，以強迫該等表面118、154進入彼此接觸。該晶粒108可經過暴露在該孔腔110內的金屬部件(例如凸塊墊片、通孔等)或電路被互連至該3D晶圓組件100中之任何或所有該等晶圓102、104、106，其每一者可含有一或多個導電ICs 124、126、166，包括主動或被動ICs，其在任何表面上可為平坦的、或直立地配置經過該晶圓。
參考圖2A(其對應於處理步驟26之一些特色)，孔洞或管道168可譬如經過任何或所有該等晶圓102、104、106被蝕刻，以便允許熱或結構材料的進入，以與該被封裝晶粒108造成接觸。另一選擇係，此管道168可被使用於以想要之氣體或液體淨化或回填該孔腔110，以增強所嵌入ICs的某些性質。導熱材料170(例如非傳導性冷卻流體、或被使用於熱、電、化學、保護功能、或機械目的之任何數目材料)可充填一部份或所有該孔腔110，且接著該管道168可被插入(例如以軟焊劑等)或以該導熱材料170充填。另一選擇係，該管道168可具有至孔腔110及來自孔腔110的熱通氣孔之作用。該3D-IC晶圓組件100的被完成之第一實施例可接著藉由傳統機構被切成方塊形。
那些熟習該技術領域者將了解所揭示的技術提供之優點，包括管理與W2W製程獨立的D2W出產損失之能力，該W2W製程形成晶圓堆疊，其可被接合至諸如上述的3D-IC晶圓組件100。源自在此中所揭示之製程的裝置之產出係藉由僅只將“已知良好的晶粒”合併進入該等裝置及藉此避免堆疊產出損失所改善，其減少該整個成本。再者，接合薄晶粒之能力允許用於多數個裝置層的堆疊，包括那些來自不同技術者，利用TSVs被直立地連接，同時維持低輪廓封裝及短電路徑長度。不同裝置晶粒通常具有不同之厚度(例如100微米-700微米)。為了容納於多數個晶粒封裝晶圓組件實施例中的不同晶粒厚 度，中間晶圓104能被製造具有大於該最厚之互連晶粒108的厚度(及如此，孔腔深度)，以便消除緊密地匹配III-V裝置厚度之需要，且亦提供熱隔離。此外，封閉的前側通孔製程可被採用於連接至該D2W組件100之晶圓，以便控制成本，且允許用於錫凸塊處理的脫扣位置，用於晶粒安裝及外部晶圓連接。在個別晶片/晶粒已被由一陣列切除之後，被使用於個別晶粒之底部充填附接的傳統有機接合一起被施行；反之，在此中所敘述的技術允許該接合在該晶圓級被施行。於一些實施例中，該等共價接合線可為比有機接合線較薄10倍。
圖3A-3D係遭受根據第二方法實施例的處理之晶圓堆疊200(對應於方法10的步驟30-36)之分解及整合視圖的概要截面圖解，以製造氧化物接合晶圓組件之替代實施例，其將裝置晶粒202封裝在藉由底部晶圓206、中間晶圓208及蓋體晶圓210所形成的孔腔204中。製造此替代晶圓組件中所採用之前端半導體製程可為與該第一方法實施例的圖2A-2D有關所敘述之那些者完全相同。在圖3A-3D中所描述的晶圓處理結果具有某些類似性(例如該晶圓之一般半導體處理技術、定向及組份等)，但在數個態樣中與圖2E-2H中所顯示的那些者不同。圖3A說明由底部晶圓206及中間晶圓208所組成之晶圓堆疊200，一或多個孔腔204已被蝕刻進入該中間晶圓。如在圖3B-3D中所顯示，不同的後端製程可被利用在此第二實施例中，以在蓋體晶圓210之底部表面216上形成凸塊墊片212及凸塊214。該蓋體晶圓210係凸塊接合至被安裝晶粒202的背後218及在接點220接合至中間晶圓208。凸塊接合該蓋體晶圓210至該中間晶圓208(如與該第一方法實施例之氧化物接合相反)導致3D-IC半導體晶圓組件222，諸如在圖3D中所描述，其中該中間晶圓208及該蓋體晶圓210界定氣隙224，而非將該裝置晶粒202封裝於全封閉密封的孔腔中。蓋體晶圓210可經過焊球接合224被電及機械地耦接至中間晶圓208，其譬如能夠在該晶圓組件222的晶圓206、208、210及202晶粒之中使電信號通過。一旦該蓋體晶圓210被接合，該已完成、電連接部226可被加至該晶圓組件222，用於連接至外部裝置、晶圓等，且該晶圓組件可被進一步處理及/或切成方塊形。
圖4A-4D係遭受根據第三方法實施例的處理之晶圓堆 疊400(對應於方法10的步驟40-46)之分解及整合視圖的概要截面圖解，以製造氧化物接合晶圓組件之替代實施例，其將裝置晶粒402封裝在藉由底部晶圓406、中間晶圓408及蓋體晶圓410所界定的圍繞孔腔404中。製造此替代晶圓組件中所採用之前端半導體製程可為與該第一方法實施例的圖2A-2D有關所敘述之那些者完全相同。在圖4A-4D中所描述的晶圓處理結果具有某些類似性(例如該晶圓之一般半導體處理技術、定向及組份等)，但在數個態樣中與圖2E-2H中所顯示的那些者不同。來自該第一實施例之一變動被顯示在圖4B中，其中熱介面層412(或諸如上述的另一功能層)可於該孔腔404中附接該晶粒402之前或之後被形成在該裝置晶粒402上。該熱介面層412可接著以類似於該上述的方式被平坦化、清潔及氧化物接合，如可同時期地為蓋體晶圓410之相反底部表面418。用於至另一晶圓(未示出)的外部連接之電凸塊420可被加至底部晶圓406的表面422，如於圖4D中所顯示。蓋體晶圓410可在頂部表面區域414、416被電及機械地耦接至中間晶圓408及至熱層412。中間層406及蓋層408間之接合導致合成的3D-IC晶圓組件424，具有全封閉地密封孔腔404，而封裝裝置晶粒402。該等表面414、416、418可被製備來於將該等晶圓接合在一起之前平坦化氧化物表面(類似地如相對於譬如圖2A-2H所敘述)。
因可對該等示範實施例作成各種修改，如上面參考該等對應說明所敘述，而未由該揭示內容的範圍脫離，其係意欲使該前面敘述中所含有及於所附圖面中所顯示之所有事物將被解釋為說明性而非限制性。如此，本揭示內容的寬度及範圍將不被該等上述示範實施例之任一者所限制，但應只按照至此為止所附上的以下申請專利範圍及其同等項所界定。
10、12、14、16、18、20、22、24、26、30、32、34、36、40、42、44、46‧‧‧步驟

Claims (22)

  1. 一種半導體晶圓組件，包含：一第一晶圓，包括一第一表面及一積體電路；一第二晶圓，具有一第一表面及一第二表面，該第一表面接合至該第一晶圓，其中該第一晶圓及該第二晶圓界定一孔腔；一半導體晶粒，在該孔腔內機械地及電連接至該第一晶圓；及一第三晶圓，包括一積體電路，且具有被接合至該第二晶圓的該第二表面之一第一表面，藉此將該半導體晶粒封裝在該孔腔內；其中該晶圓組件被建構成產生一或多個堆疊的積體電路，當該晶圓組件被切割時，每一積體電路包括一或多個被封裝之半導體晶粒，且該第二晶圓包括互連至該第一晶圓及第三晶圓的該等積體電路之一主動積體電路。
  2. 如申請專利範圍第1項之半導體晶圓組件，其中該半導體晶粒係藉由一凸塊接合、一引線互連、一超音波接合及一氧化物接合其中至少一者所機械地及電連接至該第一晶圓。
  3. 如申請專利範圍第1項之半導體晶圓組件，其中該孔腔被全封閉地密封，以封裝該半導體晶粒。
  4. 如申請專利範圍第1項之半導體晶圓組件，其中該第三晶圓的積體電路係鄰近該第三晶圓之該第一表面且電連接至該第一及第二晶圓。
  5. 如申請專利範圍第1項之半導體晶圓組件，其中該第一晶圓的積體電路係鄰近該第一晶圓之該第一表面，其被電連接至該第二及第三晶圓。
  6. 如申請專利範圍第1項之半導體晶圓組件，另包含至該半導體晶粒的至少一個電路徑，其經過該第一、第二及第三晶圓之至少一個至該晶圓組件的一外部表面。
  7. 如申請專利範圍第1項之半導體晶圓組件，另包含在該半導體晶粒及該第一、第二及第三晶圓的一或多個之間的一或多個熱介面。
  8. 如申請專利範圍第1項之半導體晶圓組件，其中該第二晶圓及該第三晶圓被凸塊接合，以便界定一提供與該孔腔熱隔離的氣隙。
  9. 如申請專利範圍第1項之半導體晶圓組件，其中該第一晶圓的積體電路係鄰近該第一表面，且該第一晶圓包括經過該第一晶圓至該積體電路之電路徑。
  10. 如申請專利範圍第1項之半導體晶圓組件，其中：該第二晶圓的該第二表面及該第三晶圓之該第一表面的每一者包括一氧化物層；及該第二晶圓及該第三晶圓係在其個別之氧化物層被氧化物接合在一起。
  11. 如申請專利範圍第1項之半導體晶圓組件，其中該第一、第二及第三晶圓其中一或多個界定由該晶圓組件之外部至該孔腔的一管道。
  12. 如申請專利範圍第11項之半導體晶圓組件，其中該管道及該孔腔係以一導熱材料至少局部地充填。
  13. 如申請專利範圍第11項之半導體晶圓組件，其中該管道及該孔腔被排空及密封，而提供一真空包裝。
  14. 如申請專利範圍第11項之半導體晶圓組件，其中該管道及該孔腔被排空及在密封之前以一液體或氣體回填。
  15. 如申請專利範圍第1項之半導體晶圓組件，其中該半導體晶粒另包含氧化物接合至該第一晶圓及該第三晶圓的至少一者之至少一氧化物層。
  16. 一種半導體晶圓組件，包含：一第一晶圓，包括一積體電路及一第一表面；一第二晶圓，具有一第一表面及一第二表面，該第一表面接合至該第一晶圓，其中該第一晶圓及該第二晶圓界定一孔腔；一半導體晶粒，在該孔腔內機械地及電連接至該第一晶圓；及一第三晶圓，包括一積體電路，且具有被接合至該第二晶圓的該第二表面之一第一表面，藉此將該半導體晶粒封裝在該孔腔內。 其中該第三晶圓的積體電路係鄰近該第三晶圓之該第一表面且電連接至該第一及第二晶圓。
  17. 一種半導體晶圓組件，包含： 一第一晶圓，包括一積體電路及一第一表面；一第二晶圓，接合至該第一晶圓，藉此以該第一晶圓及該第二晶圓界定一孔腔；一半導體晶粒，在該孔腔內機械地及電連接至該第一晶圓；及一第三晶圓，包括一積體電路，且被接合至該第二晶圓，藉此將該半導體晶粒封裝在該孔腔內；其中該第一晶圓的該積體電路係鄰近該第一晶圓之該第一表面且電連接至該第二及第三晶圓。
  18. 一種半導體晶圓組件，包含：一第一晶圓；一第二晶圓，被接合至該第一晶圓，藉此以該第一晶圓及該第二晶圓界定一孔腔；一半導體晶粒，在該孔腔內機械地及電連接至該第一晶圓；一第三晶圓，被接合至該第二晶圓，藉此將該半導體晶粒封裝在該孔腔內；及在該半導體晶粒及該第一、第二及第三晶圓的一或多個之間的一或多個熱介面。
  19. 一種半導體晶圓組件，包含：一第一晶圓；一第二晶圓，接合至該第一晶圓，藉此以該第一晶圓及該第二晶圓界定一孔腔；一半導體晶粒，在該孔腔內機械地及電連接至該第一晶圓；及一第三晶圓，接合至該第二晶圓，藉此將該半導體晶粒封裝在該孔腔內；其中該第二晶圓及該第三晶圓被凸塊接合，以便界定一提供與該孔腔熱隔離的氣隙。
  20. 一種半導體晶圓組件，包含：一第一晶圓；一第二晶圓，接合至該第一晶圓，其中該第一晶圓及該第二晶圓界定一孔腔； 一半導體晶粒，在該孔腔內機械地及電連接至該第一晶圓；及一第三晶圓，被接合至該第二晶圓，藉此將該半導體晶粒封裝在該孔腔內；其中該第一、第二及第三晶圓其中一或多個界定由該晶圓組件之外部至該孔腔的一管道。
  21. 一種半導體晶圓組件，包含：一第一晶圓，包括一積體電路；一第二晶圓，接合至該第一晶圓，其中該第一晶圓及該第二晶圓界定一孔腔；一半導體晶粒，在該孔腔內機械地及電連接至該第一晶圓；及一第三晶圓，包括一積體電路，且接合至該第二晶圓，藉此將該半導體晶粒封裝在該孔腔內；其中該第二晶圓包括互連至該第一晶圓及該第三晶圓的該等積體電路之一主動積體電路。
  22. 一種半導體晶圓組件，包含：一第一晶圓，包括一積體電路，且具有包括一氧化物層之一第一表面；一第二晶圓，具有一第一表面及一第二表面，該第一表面包括被接合至該第一晶圓的該氧化物層之一氧化物層，其中該第一晶圓及該第二晶圓界定一孔腔；一半導體晶粒，在該孔腔內機械地及電連接至該第一晶圓；及一第三晶圓，包括一積體電路，且具有被接合至該第二晶圓的該第二表面之一第一表面，藉此將該半導體晶粒封裝在該孔腔內；其中該半導體晶粒另包含氧化物接合至該第一晶圓及該第三晶圓的至少一者之至少一氧化物層。
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