TWI711062B - Capacitor array and composite electronic component - Google Patents

Abstract

The present invention provides a capacitor array having a high degree of freedom in layout, in which a plurality of solid electrolytic capacitor elements are aggregated into a single array. The capacitor array according to the present invention includes a plurality of solid electrolytic capacitor elements provided by partitioning a single solid electrolytic capacitor sheet, a sheet-shaped first sealing layer, and a sheet-shaped second sealing layer. The solid electrolytic capacitor sheet includes an anode plate, a porous layer, a dielectric layer, and a cathode layer. The solid electrolytic capacitor sheet has a first main surface and a second main surface. The first main surface side of each of the solid electrolytic capacitor elements is disposed on the first sealing layer. The second sealing layer is disposed covering the solid electrolytic capacitor elements on the first sealing layer from the second main surface side. The solid electrolytic capacitor elements are partitioned from each other by a slit-shaped sheet removal part.

Description

Capacitor array and composite electronic parts

The invention relates to a capacitor array and composite electronic parts.

Patent Document 1 discloses a solid electrolytic capacitor array, which is characterized by comprising: a capacitor element group including a plurality of capacitor elements; one or more anode terminals and one of the capacitor elements in the capacitor element group Each of one or more anode lead wires is connected and led out; one or more cathode terminals are connected to and led out of the cathode layer of the above-mentioned capacitor element; and an external resin layer that covers the above-mentioned capacitor Element; and the anode terminal and the cathode terminal are configured as external terminals. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2004-281750

[The problem to be solved by the invention]

According to Patent Document 1, by connecting a plurality of capacitor elements to the anode terminal and the cathode terminal to form an array structure, it can be easily manufactured to realize low ESR (Equivalent Series Resistance) and low ESL (Equivalent Series Inductance, etc.) Effective series inductance) and solid electrolytic capacitor array with excellent high frequency characteristics.

However, when using the method described in Patent Document 1 to form a plurality of capacitor elements into an array, the formed capacitor elements must be connected to each other in advance. Therefore, the manufacturing process tends to become complicated and the overall volume capacity density of the capacitor array Low-level issues. Therefore, it is not the best performance for high frequency.

The present invention was made in order to solve the above-mentioned problems, and its object is to provide a capacitor array in which a plurality of solid electrolytic capacitor elements are collected into one, and the degree of freedom of layout is high. Furthermore, the object of the present invention is to provide a composite electronic component in which electronic components are mounted on the external electrodes of the capacitor array. [Technical means to solve the problem]

The capacitor array of the present invention includes a plurality of solid electrolytic capacitor elements obtained by dividing one solid electrolytic capacitor chip, a chip-shaped first sealing layer, and a chip-shaped second sealing layer. The solid electrolytic capacitor chip includes: an anode plate including a valve metal; a porous layer provided on at least one main surface of the anode plate; a dielectric layer provided on the surface of the porous layer; and a cathode layer, It includes a solid electrolyte layer disposed on the surface of the dielectric layer; and has a first main surface and a second main surface opposite in the thickness direction. The first main surface side of each of the plurality of solid electrolytic capacitor elements is arranged on the first sealing layer. The second sealing layer is arranged so as to cover the plurality of solid electrolytic capacitor elements on the first sealing layer from the second main surface side. The solid electrolytic capacitor elements are divided by slit-shaped sheet removal parts.

The composite electronic component of the present invention includes: the capacitor array of the present invention; and an external electrode provided on the outer side of the first sealing layer or the second sealing layer of the capacitor array, and is connected to the anode plate and the cathode of the capacitor array Each of the layers is connected; and the electronic parts connected to the above-mentioned external electrodes. [Effects of Invention]

According to the present invention, it is possible to provide a capacitor array in which a plurality of solid electrolytic capacitor elements are collected into one, and the layout freedom is high.

The capacitor array and composite electronic component of the present invention will be described below. However, the present invention is not limited to the following constitutions, and can be suitably changed and applied within a range that does not change the gist of the present invention. Furthermore, a combination of two or more of the ideal constitutions of the present invention described below is also the present invention.

[Capacitor Array] The capacitor array of the present invention includes a plurality of solid electrolytic capacitor elements, a chip-shaped first sealing layer, and a chip-shaped second sealing layer. The first main surface side of each of the plurality of solid electrolytic capacitor elements is arranged on the first sealing layer, and the second sealing layer is arranged so as to cover the plurality of solid electrolytic capacitor elements on the first sealing layer from the second main surface side.

The capacitor array of the present invention is characterized in that a plurality of solid electrolytic capacitor elements are originally one piece of solid electrolytic capacitor chip, and the solid electrolytic capacitor elements are divided by slit-shaped sheet removal parts.

By uniformly forming a plurality of solid electrolytic capacitor elements from one sheet, a capacitor array with a high degree of freedom in layout can be manufactured inexpensively. Therefore, for individual applications such as a central processing unit (CPU) or a power management IC (PMIC (Power Management Integrated Circuit, power management integrated circuit)), different wiring paths can be flexibly dealt with.

In addition, by changing the size when the solid electrolytic capacitor elements are divided, solid electrolytic capacitor elements with different characteristics can be arranged in the capacitor array. Thereby, the characteristic impedance of the broadband can be matched when connected in parallel.

In the capacitor array of the present invention, the first sealing layer and the second sealing layer are layers containing sealing resins such as epoxy resin or phenol resin. In order to prevent the sealing layers from exerting stress on the device during the formation of the capacitor array and thermal stress load, the glass transition temperature Tg or elastic modulus of the sealing layer must be controlled. Specifically, it is preferably one highly filled with inorganic fillers such as alumina and silica.

Fig. 1 is a cross-sectional view schematically showing an example of the capacitor array of the present invention. The capacitor array 1 shown in FIG. 1 includes a plurality of solid electrolytic capacitor elements 10A, 10B, and 10C, a sheet-shaped first sealing layer 11 and a sheet-shaped second sealing layer 12. The solid electrolytic capacitor element 10A has a first main surface S1 and a second main surface S2 opposed to each other in the thickness direction (the vertical direction in FIG. 1 ), and the first main surface S1 side is arranged on the first sealing layer 11. The same applies to the solid electrolytic capacitor elements 10B and 10C. The second sealing layer 12 is arranged so as to cover the plurality of solid electrolytic capacitor elements 10A, 10B, and 10C on the first sealing layer 11 from the second main surface S2 side. Therefore, the capacitor array 1 shown in FIG. 1 has a chip-like shape as a whole.

In the capacitor array 1 shown in FIG. 1, the solid electrolytic capacitor element 10A includes an anode plate 21; a porous layer 22 provided on at least one main surface of the anode plate 21; and a dielectric layer 23 provided on the porous layer 22; and the cathode layer 24, which is disposed on the surface of the dielectric layer 23. In FIG. 1, the cathode layer 24 includes a solid electrolyte layer 24a disposed on the surface of the dielectric layer 23, a carbon layer 24b disposed on the surface of the solid electrolyte layer 24a, and a copper layer 24c disposed on the surface of the carbon layer 24b. In FIG. 1, both main surfaces of the anode plate 21 are provided with a porous layer 22 and a dielectric layer 23, and only the second main surface S2 side is provided with a cathode layer 24, or only the first main surface S1 side is provided with a cathode In the layer 24, the cathode layer 24 may be provided on both the first main surface S1 side and the second main surface S2 side. In addition, the porous layer 22 may be provided on both main surfaces of the anode plate 21, or may be provided on either main surface. The same applies to the solid electrolytic capacitor elements 10B and 10C.

The solid electrolytic capacitor elements 10A, 10B, and 10C are originally a single solid electrolytic capacitor chip 100 (see FIGS. 8A and 8B, etc.). The space between the solid electrolytic capacitor element 10A and the solid electrolytic capacitor element 10B, and the space between the solid electrolytic capacitor element 10B and the solid electrolytic capacitor element 10C are divided by a slit-shaped sheet removal part 25. Therefore, the configurations of the solid electrolytic capacitor elements 10A, 10B, and 10C are the same. In addition, the distance from the bottom surface of the second sealing layer 12 to the anode plate 21 of each solid electrolytic capacitor element 10A, 10B, and 10C is constant.

As shown in FIG. 1, it is preferable that the second sealing layer 12 enters between the anode plates 21 of adjacent solid electrolytic capacitor elements on the first sealing layer 11 toward the first sealing layer 11 side, and then enters the first sealing layer 11 Part. If the second sealing layer 12 enters a part of the first sealing layer 11, the adhesion between the first sealing layer 11 and the second sealing layer 12 is improved, so the reliability of the capacitor array 1 is improved.

In the capacitor array 1 shown in FIG. 1, the second sealing layer 12 enters the first sealing layer 11 toward the side of the first sealing layer 11 between the anode plates 21 of all adjacent solid electrolytic capacitor elements, and then enters the first sealing layer 11 A part of the layer 11, but there may be a part where the second sealing layer 12 does not enter a part of the first sealing layer 11. In addition, the second sealing layer 12 does not need to enter the first sealing layer 11.

As shown in FIG. 1, it is preferable to provide an insulating layer 30 for insulating the anode plate 21 and the cathode layer 24 on the surface of the dielectric layer 23 on the second main surface S2 side where the cathode layer 24 is not provided. In FIG. 1, the insulating layer 30 is provided on the surface of the dielectric layer 23 on the first main surface S1 side, and the insulating layer 30 may not be provided on the surface of the dielectric layer 23 on the first main surface S1 side.

Although not shown in FIG. 1, as described later, external electrodes connected to each of the anode plate 21 and the cathode layer 24 are provided on the outer side of the first sealing layer 11 or the second sealing layer 12.

The form of connecting the anode plate or the cathode layer to the external electrode is not particularly limited, but it is preferable to provide a through electrode. The anode plate or the cathode layer is connected to the external electrode via the through electrode, and the through electrode penetrates the first sealing layer in the thickness direction Or the second sealing layer. Through the through electrode, the lead-out distance from the anode plate or the cathode layer to the external electrode can be shortened.

In the capacitor array 1 shown in FIG. 1, the side surfaces of the solid electrolytic capacitor elements 10A and 10C are exposed. For example, they can be covered with a first sealing layer or a second sealing layer, or with an insulating layer. In addition, a stress relaxation layer, a moisture-proof film, etc. may be provided between the solid electrolytic capacitor element and the first sealing layer or the second sealing layer.

In the capacitor array of the present invention, the interval between the anode plates of the solid electrolytic capacitor elements adjacent to the first sealing layer (the length shown by D ₁₀ in FIG. 1) is not particularly limited, and is preferably 15 μm or more, It is more preferably 30 μm or more, and still more preferably 50 μm or more. On the other hand, the interval between the anode plates of the adjacent solid electrolytic capacitor elements on the first sealing layer is preferably 500 μm or less, more preferably 200 μm or less, and still more preferably 150 μm or less.

In the capacitor array of the present invention, the number of solid electrolytic capacitor elements arranged on the first sealing layer is not particularly limited as long as it is two or more. The solid electrolytic capacitor element may be linearly arranged on the first sealing layer, or may be planarly arranged. In addition, the solid electrolytic capacitor elements may be arranged regularly on the first sealing layer, or may be arranged irregularly. The size and shape of the solid electrolytic capacitor components may be the same, or may be partially or completely different.

Fig. 2 is an enlarged cross-sectional view schematically showing another example of the sheet removal part. The sheet removal part 25A shown in FIG. 2 has a wedge shape whose width decreases from the second main surface S2 of the solid electrolytic capacitor elements 10A and 10B toward the first main surface S1. The wedge shape of the sheet removal part 25A does not reach the porous layer 22 on the first main surface S1 side of the solid electrolytic capacitor elements 10A and 10B, nor does it reach the anode plate 21.

In the capacitor array of the present invention, the sheet removal portion preferably has a wedge shape whose width decreases from one main surface of the solid electrolytic capacitor element to the other main surface. The sheet removal part may have a wedge shape whose width decreases from the second main surface of the solid electrolytic capacitor element to the first main surface, or it may have a width decreasing from the first main surface of the solid electrolytic capacitor element to the second main surface The wedge shape.

The above-mentioned wedge shape preferably does not reach the anode plate of the solid electrolytic capacitor element. Especially when porous layers are provided on both main surfaces of the anode plate, the wedge shape is preferably a porous layer that does not reach the other main surface of the solid electrolytic capacitor element. When it has a wedge shape whose width decreases from the second main surface of the solid electrolytic capacitor element to the first main surface, the wedge shape is preferably a porous layer that does not reach the first main surface of the solid electrolytic capacitor element. On the other hand, when there is a wedge shape whose width decreases from the first main surface of the solid electrolytic capacitor element to the second main surface, the wedge shape is preferably a porous shape that does not reach the second main surface side of the solid electrolytic capacitor element. Quality layer.

In the capacitor array of the present invention, the insulating layer preferably contains resin. As the resin constituting the insulating layer, for example, polystyrene resin, polyether resin, cyanate ester resin, fluororesin (tetrafluoroethylene, tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer, etc.), polystyrene Insulating resins such as imine resins, polyimide imine resins, epoxy resins and derivatives or precursors thereof. Furthermore, the insulating layer may include the same resin as the first sealing layer and the second sealing layer. Unlike the first sealing layer and the second sealing layer, if the insulating layer contains an inorganic filler, it may adversely affect the effective part of the solid electrolytic capacitor element. Therefore, the insulating layer is preferably composed of a resin alone system.

In the capacitor array of the present invention, the first sealing layer and the second sealing layer preferably contain resin. Examples of resins constituting the first sealing layer and the second sealing layer include epoxy resins and phenol resins. The first sealing layer and the second sealing layer further preferably contain a filler. Examples of the filler contained in the first sealing layer and the second sealing layer include inorganic fillers such as silica particles, alumina particles, and metal particles. The resin constituting the first sealing layer may be the same as or different from the resin constituting the second sealing layer.

The first sealing layer and the second sealing layer may each consist of only one layer, or may include two or more layers. The number of layers constituting the first sealing layer may be the same as or different from the number of layers constituting the second sealing layer. When the first sealing layer or the second sealing layer contains two or more layers, a through electrode can be provided, and an internal electrode can be provided between each sealing layer, and the anode plate or the cathode layer and the external electrode can be connected through the through electrode and the internal electrode , The through electrode penetrates each sealing layer existing between the anode plate or the cathode layer and the external electrode in the thickness direction.

In the capacitor array of the present invention, the anode plate of the solid electrolytic capacitor element contains a valve action metal that exhibits a so-called valve action. Examples of the valve metal include simple metals such as aluminum, tantalum, niobium, titanium, and zirconium, or alloys containing these metals. Among them, aluminum or aluminum alloy is preferred.

The shape of the anode plate is preferably a flat plate shape, and more preferably a foil shape. The anode plate only needs to have a porous layer on at least one main surface. You may have a porous layer on both main surfaces. The porous layer is preferably an etching layer formed on the surface of the anode plate.

The thickness of the anode plate before etching is preferably 60 μm or more and 200 μm or less. After the etching treatment, the thickness of the unetched core is preferably 15 μm or more and 70 μm or less. The thickness of the porous layer is designed to meet the required withstand voltage and electrostatic capacitance, and it is preferable that the total porous layer on both sides of the core is 10 μm or more and 180 μm or less.

In the capacitor array of the present invention, the dielectric layer of the solid electrolytic capacitor element is disposed on the surface of the porous layer. The dielectric layer is formed along the surface of the porous layer to form pores (recesses). The dielectric layer is preferably an oxide film containing the aforementioned valve metal. For example, when aluminum foil is used as the anode plate, the surface of the aluminum foil is anodized (also referred to as chemical treatment) in an aqueous solution containing ammonium adipate, etc., to form a dielectric layer including an oxide film.

The thickness of the dielectric layer is designed in a way that meets the required withstand voltage and electrostatic capacitance, preferably 10 nm or more and 100 nm or less.

In the capacitor array of the present invention, the cathode layer of the solid electrolytic capacitor element is disposed on the surface of the dielectric layer. The cathode layer includes a solid electrolyte layer disposed on the surface of the dielectric layer. The cathode layer further preferably includes a conductor layer provided on the surface of the solid electrolyte layer.

Examples of the material constituting the solid electrolyte layer include conductive polymers such as polypyrroles, polythiophenes, and polyanilines. Among them, polythiophenes are preferred, and poly(3,4-ethylenedioxythiophene) called PEDOT is particularly preferred. In addition, the conductive polymer may contain a dopant such as polystyrene sulfonic acid (PSS).

The solid electrolyte layer is formed by, for example, the following method: using a treatment solution containing monomers such as 3,4-ethylenedioxythiophene to form poly(3,4-ethylenedioxythiophene) on the surface of the dielectric layer. Polymeric film; or coating a dispersion liquid of polymer such as poly(3,4-ethylenedioxythiophene) on the surface of the dielectric layer and let it dry. Furthermore, it is preferable to form the outer layer of the covering dielectric layer after forming the inner layer filling the pores (recesses) of the dielectric layer, thereby forming the solid electrolyte layer.

The solid electrolyte layer can be formed in a specific area by applying the above-mentioned treatment liquid or dispersion liquid on the dielectric layer by sponge transfer, screen printing, dispenser, inkjet printing, etc. The thickness of the solid electrolyte layer is preferably 2 μm or more and 20 μm or less.

The conductor layer includes at least one of a conductive resin layer and a metal layer. The conductor layer may only be a conductive resin layer, or only a metal layer. The conductor layer preferably covers the entire surface of the solid electrolyte layer.

Examples of the conductive resin layer include a conductive adhesive layer containing at least one conductive filler selected from the group consisting of a silver filler, a copper filler, a nickel filler, and a carbon filler.

As a metal layer, a metal plating film, a metal foil, etc. are mentioned, for example. The metal layer preferably includes at least one metal selected from the group consisting of nickel, copper, silver, and alloys mainly composed of these metals. Furthermore, the so-called "principal component" refers to the element component with the largest existence ratio (weight%) of the element.

The conductor layer includes, for example, a carbon layer provided on the surface of the solid electrolyte layer and a cathode extraction layer provided on the surface of the carbon layer.

The carbon layer is configured to electrically and mechanically connect the solid electrolyte layer and the cathode lead-out layer.

The carbon layer can be formed in a specific area by applying carbon paste on the solid electrolyte layer by using sponge transfer, screen printing, dispenser, inkjet printing, etc. Furthermore, the carbon layer is preferably a cathode lead-out layer in the next step in a state of being viscous before drying. The thickness of the carbon layer is preferably 2 μm or more and 20 μm or less.

The cathode lead-out layer is, for example, a printed electrode layer. The printed electrode layer can be formed by printing electrode paste on the carbon layer using sponge transfer, screen printing, spray coating, dispenser, inkjet printing, or the like. As the electrode paste, it is preferable to use an electrode paste mainly composed of silver, copper or nickel. In the case of screen printing, the thickness of the cathode lead-out layer can also be set to 2 μm or more and 20 μm or less.

The capacitor array of the present invention is preferably manufactured in the following manner.

The manufacturing method of the capacitor array of the present invention includes the following steps: preparing a solid electrolytic capacitor chip having a first main surface and a second main surface opposed to each other in the thickness direction; and arranging a sheet-like shape on the first main surface side of the solid electrolytic capacitor chip The first sealing layer; by cutting the solid electrolytic capacitor chip from the second main surface side in the thickness direction, it is divided into a plurality of solid electrolytic capacitor elements arranged on the first sealing layer; and from the second main surface A sheet-shaped second sealing layer is arranged to cover a plurality of solid electrolytic capacitor elements on the first sealing layer.

When a plurality of solid electrolytic capacitor elements are individually arranged on the first sealing layer, a gap must be provided between adjacent solid electrolytic capacitor elements. Therefore, the larger the number of solid electrolytic capacitor elements, the larger the ratio of the gaps. On the other hand, the smaller the ratio of the effective parts of the solid electrolytic capacitor elements. In response to this, in the state where the first sealing layer is arranged on the first main surface side of the solid electrolytic capacitor chip, the solid electrolytic capacitor chip is cut from the second main surface side and divided into a plurality of solid electrolytic capacitor elements, thereby, Capacitor arrays with a large percentage of the effective portion of solid electrolytic capacitor elements can be manufactured.

An example of each step is described below.

First, as shown in FIGS. 3A, 3B, 4A, 4B, 5, 6A, 6B, 7A, 7B, 8A, and 8B, solid electrolytic capacitor chips are prepared.

Fig. 3A is a perspective view schematically showing an example of a step of preparing a formed foil, and Fig. 3B is a cross-sectional view thereof. A chemical conversion foil 20 such as aluminum is prepared as the anode plate 21. The anode plate 21 is provided with a porous layer 22 on at least one main surface, and a dielectric layer 23 is provided on the surface of the porous layer 22. For example, aluminum foil can be prepared as an anode plate instead of the chemical conversion foil 20. After the porous layer is formed by etching the surface of the aluminum foil, anodizing is performed in an aqueous solution containing ammonium adipate, etc., thereby forming a The dielectric layer of the oxide film.

Fig. 4A is a perspective view schematically showing an example of a step of forming an insulating layer, and Fig. 4B is a cross-sectional view thereof. In order to distinguish the effective part of the solid electrolytic capacitor element, an insulating resin is coated on the dielectric layer 23 to form the insulating layer 30. The method of applying the insulating resin is not particularly limited, and examples thereof include a dispenser, screen printing, and the like. In Fig. 4A, 3 vertical x 2 horizontal total 6 areas for mounting solid electrolytic capacitor elements are one capacitor array unit.

Fig. 5 is a perspective view schematically showing an example of a step of forming a through hole. A through hole 31 is formed at a specific position around the capacitor array unit, and the through hole 31 penetrates the chemical conversion foil 20 on which the insulating layer 30 is formed in the thickness direction.

As described later, a through electrode is formed in the through hole 31. The through electrode is used for the connection between the anode plate and the external electrode or the connection between the cathode layer and the external electrode. The through electrode can be used to connect the cathode layers formed by interposing the anode plate. In addition, the through electrode can be used for connections other than the above. As explained in [Composite Electronic Components], the capacitor array of the present invention is a composite electronic component due to the mounting of electronic components. In composite electronic components, the external electrodes of the capacitor array and the electronic components are connected in the thickness direction through the through electrodes formed in the through holes 31, or the electronic components other than the capacitor array are connected in the thickness direction.

Furthermore, as shown in FIG. 5, a through hole 32 may be formed for arranging a capacitor element of a different type from the solid electrolytic capacitor element.

FIG. 6A is a perspective view schematically showing an example of a step of forming a solid electrolyte layer, and FIG. 6B is a cross-sectional view thereof. A solid electrolyte layer 24 a is formed on the dielectric layer 23. For example, the solid electrolyte layer can be formed by the following method: using a treatment solution containing monomers such as 3,4-ethylenedioxythiophene to form poly(3,4-ethylenedioxythiophene) on the surface of the dielectric layer. Polymeric film; or coating a dispersion liquid of polymer such as poly(3,4-ethylenedioxythiophene) on the surface of the dielectric layer and let it dry. Furthermore, it is preferable to form the outer layer of the covering dielectric layer after forming the inner layer filling the pores of the dielectric layer, thereby forming the solid electrolyte layer.

Fig. 7A is a perspective view schematically showing an example of a step of forming a carbon layer, and Fig. 7B is a cross-sectional view thereof. A carbon layer 24b is formed on the solid electrolyte layer 24a. For example, the carbon layer can be formed by coating and drying a conductive adhesive paste containing carbon filler.

FIG. 8A is a perspective view schematically showing an example of a step of forming a copper layer, and FIG. 8B is a cross-sectional view thereof. A copper layer 24c is formed on the carbon layer 24b. As a result, a cathode layer 24 including a solid electrolyte layer 24a, a carbon layer 24b, and a copper layer 24c is formed on the dielectric layer 23. For example, a conductive adhesive paste containing a copper filler can be used to form the copper layer, or the copper layer can be formed by copper plating.

Through the above steps, the following solid electrolytic capacitor chip 100 can be obtained, which has an anode plate 21, a porous layer 22 disposed on at least one main surface of the anode plate 21, a dielectric layer 23 disposed on the surface of the porous layer 22, And the cathode layer 24 disposed on the surface of the dielectric layer 23. As shown in FIG. 8B, the solid electrolytic capacitor chip 100 has a first main surface S1 and a second main surface S2 opposed to each other in the thickness direction.

Next, as shown in FIGS. 9A and 9B, a sheet-shaped first sealing layer is arranged on the first main surface side of the solid electrolytic capacitor chip.

Fig. 9A is a perspective view schematically showing an example of a step of disposing the first sealing layer, and Fig. 9B is a cross-sectional view thereof. The first sealing layer 11 is arranged on the first main surface S1 side of the solid electrolytic capacitor chip 100. For example, a sheet containing insulating resin is bonded to a solid electrolytic capacitor chip. The first sealing layer 11 can enter a part of the through holes 31 and 32.

Then, as shown in FIGS. 10A and 10B, the solid electrolytic capacitor chip is cut in the thickness direction from the second main surface side, and divided into a plurality of solid electrolytic capacitor elements arranged on the first sealing layer. Examples of the cutting method include laser processing, cutting processing, and the like.

FIG. 10A is a perspective view schematically showing an example of a step of cutting a solid electrolytic capacitor chip, and FIG. 10B is a cross-sectional view thereof. Using the first sealing layer 11 on the first main surface S1 side as a support, the solid electrolytic capacitor chip 100 is cut in the thickness direction from the second main surface S2 side. At this time, it is preferable that a part of the first sealing layer 11 is also cut. Thereby, the solid electrolytic capacitor chip 100 is divided into the solid electrolytic capacitor elements 10A, 10B, 10C, 10D, 10E, and 10F by the slit-shaped sheet removal part 25 in the state of being disposed on the first sealing layer 11. Strictly speaking, as shown in FIG. 10A, although the adjacent part of the capacitor array unit is not divided into solid electrolytic capacitor elements, it can be considered that one capacitor array unit is divided into solid electrolytic capacitor elements 10A, 10B, 10C, 10D, 10E And 10F.

The width of the sheet removal portion is not particularly limited, but is preferably 15 μm or more, more preferably 30 μm or more, and still more preferably 50 μm or more. On the other hand, the interval between the anode plates of the adjacent solid electrolytic capacitor elements on the first sealing layer is preferably 500 μm or less, more preferably 200 μm or less, and still more preferably 150 μm or less.

The ratio of the length/width of the sheet removal part, that is, the aspect ratio, is preferably 10 or more, more preferably 100 or more. On the other hand, the aspect ratio of the sheet removal part is preferably 1000 or less.

Fig. 11 is a perspective view schematically showing an example of a procedure for arranging capacitor elements of a different type from the solid electrolytic capacitor element. As shown in FIG. 11, a capacitor element 110 of a different type from the solid electrolytic capacitor element can be arranged in the space where the through hole 32 is formed. Examples of capacitor elements different from solid electrolytic capacitor elements include multilayer ceramic capacitors and silicon capacitors.

In addition, as shown in FIGS. 12A and 12B, a sheet-shaped second sealing layer is arranged so as to cover a plurality of solid electrolytic capacitor elements on the first sealing layer from the second main surface side.

Fig. 12A is a perspective view schematically showing an example of a step of disposing the second sealing layer, and Fig. 12B is a cross-sectional view thereof. The second sealing layer 12 is arranged to cover a plurality of solid electrolytic capacitor elements 10A, 10B, 10C, 10D, 10E, and 10F from the second main surface S2 side. For example, a sheet containing insulating resin is bonded to a solid electrolytic capacitor element. At this time, the second sealing layer 12 enters between the anode plates 21 of adjacent solid electrolytic capacitor elements on the first sealing layer 11 toward the first main surface S1 side, and then enters a part of the first sealing layer 11.

FIG. 13A is a perspective view schematically showing an example of a step of dividing into a plurality of capacitor arrays, and FIG. 13B is a cross-sectional view thereof. As shown in FIGS. 13A and 13B, by cutting each capacitor array unit, a capacitor array 1 in which a plurality of solid electrolytic capacitor elements 10A, 10B, 10C, 10D, 10E, and 10F are mounted in one array is obtained.

In the above method, although a large sheet of formed foil is used to divide into a plurality of capacitor arrays, it is also possible to use a formed foil equivalent to the size of one capacitor array without performing the step of dividing into capacitor arrays.

In the manufacturing method of the capacitor array of the present invention, it is preferable to arrange the second sealing layer after cutting the solid electrolytic capacitor chip as in the above method. However, after arranging a part of the second sealing layer, after cutting the solid electrolytic capacitor chip together with the second sealing layer, the remaining second sealing layer may be arranged on the second main surface side.

Based on the above, the capacitor array of the present invention can be manufactured.

Preferably, after the capacitor array is fabricated in the above manner, external electrodes connected to each of the anode plate and the cathode layer of the capacitor array are formed on the outer side of the first sealing layer or the second sealing layer of the capacitor array. For example, it is possible to form an external electrode having a desired pattern by performing an etching process after attaching a copper foil. Hereinafter, the external electrode connected to the anode plate is also referred to as an anode external electrode, and the external electrode connected to the cathode layer is also referred to as a cathode external electrode.

Fig. 14 is a perspective view schematically showing an example of a step of forming an anode external electrode. In FIG. 14, on the outer side of the second sealing layer 12, the anode external electrodes 41A, 41B, 41C, 41D, 41E, and 41F are formed for each anode plate 21. As shown in FIG. 14, the anode outer electrode 41B can be formed by connecting the solid electrolytic capacitor element 10B and the capacitor element 110 in parallel.

Fig. 15 is a perspective view schematically showing an example of a step of forming a cathode external electrode. In FIG. 15, cathode external electrodes 42A, 42B, 42C, and 42D are formed on the outer side of the second sealing layer 12. The cathode outer electrode 42A is commonly connected to the cathode layer 24 of the solid electrolytic capacitor elements 10A and 10B, and the cathode outer electrode 42C is commonly connected to the cathode layer 24 of the solid electrolytic capacitor elements 10D and 10E. Furthermore, a cathode external electrode may be formed for each cathode layer.

Fig. 16 is a perspective view schematically showing another example of the step of forming the external electrode of the cathode. In FIG. 16, cathode external electrodes 42A and 42B are formed on the outer side of the second sealing layer 12. The cathode outer electrode 42A is commonly connected to the cathode layer 24 of the solid electrolytic capacitor elements 10A, 10B, 10D, and 10E, and the cathode outer electrode 42B is commonly connected to the cathode layer 24 of the solid electrolytic capacitor elements 10C and 10F.

Although not shown, it is preferable to form a through electrode, connect the anode plate to the anode external electrode through the through electrode, and connect the cathode layer to the cathode external electrode, and the through electrode penetrates the second sealing layer (or the second sealing layer) in the thickness direction. 1 Sealing layer). The method of forming the through-electrode is not particularly limited. For example, a method of performing laser hole burning after forming the anode external electrode and the cathode external electrode can be cited. In addition, the through electrode may be formed before the first sealing layer or the second sealing layer is arranged, or the through electrode may be formed after the first sealing layer or the second sealing layer is arranged and before the anode external electrode and the cathode external electrode are formed.

Fig. 17 is a perspective view of Fig. 15 for explaining the function of the through hole. Fig. 18 is a perspective view of Fig. 16 for explaining the function of the through hole. In FIGS. 17 and 18, the through hole 31X is used for the connection between the anode plate and the external electrode, and the through hole 31Y is used for the connection between the cathode layer and the external electrode. In addition, the through hole 31Z is used for connection other than the capacitor.

Furthermore, the anode external electrode and the cathode external electrode may be formed simultaneously or separately.

Hereinafter, a modification example of the structure of the anode and the cathode will be described with reference to the drawings. In the following drawings, only characteristic configurations are shown, and configurations such as a dielectric layer, a solid electrolyte layer, and an insulating layer are omitted.

Fig. 19A is a projected plan view of the first modification of the structure of the anode and the cathode viewed from the side of the second sealing layer, and Fig. 19B is a projected sectional view taken along the line b-b of Fig. 19A.

The capacitor array 1A shown in FIGS. 19A and 19B includes: a wire conductor 50; an anode through-electrode 51 that penetrates the first sealing layer 11 and the second sealing layer 12 in the thickness direction; and an anode through-hole conductor 52 that is in the thickness direction The upper part penetrates the second sealing layer 12; the anode wiring pattern 53 is provided on the outer side of the second sealing layer 12; and the anode wiring pattern 54 is provided on the outer side of the first sealing layer 11. In the capacitor array 1A shown in FIGS. 19A and 19B, a part of the porous layer 22 is removed in a linear shape, and a wire conductor 50 is provided in the removed portion. In addition, an anode through-hole conductor 52 is provided directly above the wire conductor 50, and an anode wiring pattern 53 is provided directly above the anode through-hole conductor 52. The anode plate 21 is electrically connected to the anode through electrode 51 via the wire conductor 50, the anode via hole conductor 52 and the anode wiring pattern 53.

The capacitor array 1A shown in FIGS. 19A and 19B further includes: a cathode through electrode 61 which penetrates the first sealing layer 11 and the second sealing layer 12 in the thickness direction; and a cathode through hole conductor 62 which penetrates the first sealing layer in the thickness direction. 2 sealing layer 12; cathode wiring pattern 63, which is provided on the outer side of the second sealing layer 12; and cathode wiring pattern 64, which is provided on the outer side of the first sealing layer 11. A cathode through hole conductor 62 is provided directly above the cathode layer 24, and a cathode wiring pattern 63 is provided directly above the cathode through hole conductor 62. The cathode layer 24 is electrically connected to the cathode through electrode 61 via the cathode via conductor 62 and the cathode wiring pattern 63.

As shown in FIG. 19A, the anode X and the cathode Y are preferably arranged in a staggered line.

Fig. 20A is a projected plan view of the second modification of the structure of the anode and the cathode viewed from the side of the second sealing layer, and Fig. 20B is a projected cross-sectional view taken along the line b-b of Fig. 20A.

The capacitor array 1B shown in FIGS. 20A and 20B has the same configuration as the capacitor array 1A shown in FIGS. 19A and 19B except that the wire conductor 50 is located on the same line as the anode through electrode 51. In FIG. 20A, the anode wiring pattern 53 is omitted, and in FIG. 20B, the anode via hole conductor 52 is omitted.

As shown in FIG. 20A, the anode X and the cathode Y are preferably arranged alternately in a line.

Fig. 21A is a projected plan view of the third modification of the structure of the anode and the cathode viewed from the side of the second sealing layer, and Fig. 21B is a projected cross-sectional view taken along the line b-b of Fig. 21A.

The capacitor array 1C shown in FIGS. 21A and 21B has the same configuration as the capacitor array 1A shown in FIGS. 19A and 19B, except that it includes via-hole conductors 50A instead of the line conductors 50. In the capacitor array 1C shown in FIGS. 21A and 21B, an opening is formed in a part of the porous layer 22, and a through-hole conductor 50A is provided in the opening. Compared with the capacitor array 1A shown in FIGS. 19A and 19B, the capacitor array 1C shown in FIGS. 21A and 21B can achieve space saving.

As shown in FIG. 21A, the anode X and the cathode Y are preferably arranged alternately in a line.

Fig. 22A is a projected plan view of the fourth modification of the anode and cathode structure viewed from the side of the second sealing layer, and Fig. 22B is a projected cross-sectional view taken along line b-b of Fig. 22A.

In the capacitor array 1D shown in FIGS. 22A and 22B, the anode plate 21 is directly connected to the wall surface of the anode through electrode 51. Therefore, the capacitor array 1D shown in FIGS. 22A and 22B can be space-saving.

As shown in FIG. 22A, the anode X and the cathode Y are preferably arranged in a staggered grid pattern.

As described above, the capacitor array of the present invention can be arranged such that when viewed from the side of the first sealing layer or the side of the second sealing layer, the anodes and cathodes are arranged in a linear staggered arrangement, or arranged in a staggered grid pattern.

In addition, in the capacitor array of the present invention, the lead-out of the anode can be connected to the anode through electrode in either the main surface direction or the end surface direction.

As described above, as a method of cutting the solid electrolytic capacitor chip when manufacturing the capacitor array of the present invention, laser processing, cutting processing, etc. can be cited. Among them, by cutting the solid electrolytic capacitor chip by laser processing, the solid electrolytic capacitor element can be formed into a free shape. Therefore, the following effects can be achieved, namely, arranging two or more solid electrolytic capacitor elements with different areas of the capacitor portion in a single capacitor array; arranging the sheet removal portion so as not to spread over the entire capacitor array; and arranging the capacitor portion Solid electrolytic capacitor elements whose planar shape is not rectangular.

Fig. 23 is a perspective view schematically showing another example of the step of cutting the solid electrolytic capacitor chip. In FIG. 23, the shape of the divided solid electrolytic capacitor element is different from that of FIG. 10A. In the example shown in FIG. 23, the sheet-removing portion 25 is divided into three types of solid electrolytic capacitor elements 10A, 10B, and 10C having different capacitance portions. In FIG. 23, the solid electrolytic capacitor element 10C is arranged on the extension of the sheet material removal portion 25 that divides the solid electrolytic capacitor elements 10A and 10B.

In this way, in the capacitor array of the present invention, at least a part of the sheet-removed portion may be arranged so as not to spread over the entire capacitor array.

In the capacitor array of the present invention, at least one solid electrolytic capacitor element can be arranged on the extension line of the sheet removal part.

In the capacitor array of the present invention, two or more types of solid electrolytic capacitor elements with different areas of the capacitor portion may be included.

In the capacitor array of the present invention, a solid electrolytic capacitor element whose planar shape of the capacitor portion is not rectangular may be included. In this manual, "rectangle" means square or rectangle. Therefore, in the capacitor array of the present invention, for example, the planar shape that may include the capacitor portion is a polygon other than a rectangle such as a quadrangle, a triangle, a pentagon, a hexagon, etc., or a shape including a curved portion, a circle, an ellipse, etc. Solid electrolytic capacitor components. In this case, it may include two or more solid electrolytic capacitor elements with different planar shapes of the capacitor portion. In addition, in addition to solid electrolytic capacitor elements whose planar shape of the capacitor portion is not rectangular, solid electrolytic capacitor elements whose planar shape is rectangular with or without the capacitor portion may be included.

Fig. 24 is a plan view schematically showing an example of a capacitor part whose planar shape is not rectangular. The outer shape of the capacitor part 70 shown in FIG. 24 is not rectangular, and a through hole 71 is formed inside. The above-mentioned through electrode can be formed inside the through hole 71. In FIG. 24, the outer wall surface and the inner wall surface of the capacitor portion 70 are provided with insulating portions 72.

As described above, the capacitor array of the present invention can further include a stress relaxation layer between the solid electrolytic capacitor element and the first sealing layer or the second sealing layer. In this case, the stress relaxation layer may be provided between at least one of the solid electrolytic capacitor element and the first sealing layer and between the solid electrolytic capacitor element and the second sealing layer.

When the capacitor array of the present invention is provided with a stress relaxation layer, the stress relaxation layer may also be provided in the sheet removal part. In other words, the stress relaxation layer can also be provided between adjacent solid electrolytic capacitor elements.

By providing the stress relaxation layer in the above-mentioned parts, it is possible not to impair the necessary capabilities (resistance, barrier performance, etc.) or the necessary capabilities of the sealing layer (easy) for the conductor part and the insulating part arranged on the outermost part of the solid electrolytic capacitor element. When it is in close contact with wiring and is easy to form smoothly, etc.), it relieves the stress generated between the inside and outside of the capacitor array. Especially when the layout in the plane is different (for example, the shape of the solid electrolytic capacitor element is asymmetrical in the main plane or asymmetrical with the other main plane), etc., the stress relaxation is provided in a way that only part of the thermal characteristics is different Layer, can relax the stress in the surface direction.

Fig. 25 is a cross-sectional view schematically showing an example of a capacitor array provided with a stress relaxation layer. FIG. 26 is a perspective view schematically showing an example of a solid electrolytic capacitor chip used for manufacturing the capacitor array shown in FIG. 25. In FIG. 26, for convenience, only one capacitor array is provided with a stress relaxation layer. In addition, FIG. 25 corresponds to the cross section of the solid electrolytic capacitor chip shown in FIG. 26 along the arrow.

The capacitor array 1E shown in FIG. 25 is provided with a stress relaxation layer 13 between the solid electrolytic capacitor elements 10A, 10B, and 10C and the first sealing layer 11, and between the solid electrolytic capacitor elements 10A, 10B, and 10C and the second sealing layer 12. . In the capacitor array 1E shown in FIG. 25, the stress relaxation layer 13 is provided so as to cover the entire insulating layer 30. Furthermore, the stress relaxation layer 13 is filled in the sheet removal part 25.

Although not shown in FIG. 26, the stress relaxation layer 13 is also provided between the solid electrolytic capacitor elements 10D, 10E, and 10F and the first sealing layer 11. Furthermore, since the second sealing layer 12 is arranged in the state shown in FIG. 26, the stress relaxation layer 13 is also provided between the solid electrolytic capacitor elements 10D, 10E, 10F and the second sealing layer 12. The through hole 31 shown in FIG. 26 may be filled with the stress relaxation layer 13 or not.

Fig. 27 is a cross-sectional view schematically showing another example of a capacitor array provided with a stress relaxation layer. FIG. 28 is a perspective view schematically showing an example of a solid electrolytic capacitor chip used for manufacturing the capacitor array shown in FIG. 27. In FIG. 28, for convenience, only one capacitor array is provided with a stress relaxation layer. In addition, FIG. 27 corresponds to the cross section of the solid electrolytic capacitor chip shown in FIG. 28 along the arrow.

The capacitor array 1F shown in FIG. 27 is provided with a stress relaxation layer 13 between the solid electrolytic capacitor elements 10A, 10B, and 10C and the first sealing layer 11, and between the solid electrolytic capacitor elements 10A, 10B, and 10C and the second sealing layer 12. . In the capacitor array 1F shown in FIG. 27, the stress relaxation layer 13 is provided so as to cover not only the entire insulating layer 30 but also the entire solid electrolytic capacitor elements 10A, 10B, and 10C. Furthermore, the stress relaxation layer 13 is filled in the sheet removal part 25.

Although not shown in FIG. 28, the stress relaxation layer 13 is also provided between the solid electrolytic capacitor elements 10D, 10E, and 10F and the first sealing layer 11. In addition, since the second sealing layer 12 is arranged in the state shown in FIG. 28, the stress relaxation layer 13 is also provided between the solid electrolytic capacitor elements 10D, 10E, 10F and the second sealing layer 12. The through hole 31 shown in FIG. 28 may be filled with the stress relaxation layer 13 or not.

Fig. 29 is a cross-sectional view schematically showing another example of a capacitor array provided with a stress relaxation layer. FIG. 30 is a perspective view schematically showing an example of a solid electrolytic capacitor chip used for manufacturing the capacitor array shown in FIG. 29. In FIG. 30, for convenience, only one capacitor array is provided with a stress relaxation layer. In addition, FIG. 29 corresponds to the cross section of the solid electrolytic capacitor chip shown in FIG. 30 along the arrow.

In FIG. 29, the stress relaxation layer 13 is provided only in a part of the capacitor array 1G. The capacitor array 1G shown in FIG. 29 includes a stress relaxation layer 13 between the solid electrolytic capacitor elements 10B and 10C and the first sealing layer 11 and between the solid electrolytic capacitor elements 10A and 10C and the second sealing layer 12. Furthermore, the stress relaxation layer 13 is filled in the sheet removal part 25.

Although not shown in FIG. 30, the stress relaxation layer 13 may be provided between at least one of the solid electrolytic capacitor elements 10D, 10E, and 10F and the first sealing layer 11, or may not be provided. In addition, the stress relaxation layer 13 may be provided between at least one of the solid electrolytic capacitor elements 10D, 10E, and 10F and the second sealing layer 12, or may not be provided. The through hole 31 shown in FIG. 30 may be filled with the stress relaxation layer 13 or not.

For example, when the shape of the solid electrolytic capacitor element is asymmetrical in the main surface or asymmetrical with the other main surface, the capacitor array 1G shown in FIG. 29, by providing the stress relaxation layer 13 only on a part of the capacitor array, The thermal stress balance of the entire capacitor array can be obtained.

In the capacitor array of the present invention, the stress relaxation layer preferably includes an insulating resin. Examples of insulating resins constituting the stress relaxation layer include epoxy resins, phenol resins, and silicone resins. The stress relaxation layer further preferably contains a filler. Examples of the filler contained in the stress relaxation layer include inorganic fillers such as silica particles, alumina particles, and metal particles. The insulating resin constituting the stress relaxation layer is preferably different from the resin constituting the first sealing layer and the second sealing layer.

The first sealing layer and the second sealing layer are required to have characteristics such as adhesion to the external electrodes as the exterior body, so it is difficult to make the linear expansion coefficient uniformly consistent with the solid electrolytic capacitor element, or it is difficult to select a resin with any elastic modulus. In response to this, by providing the stress relaxation layer, the thermal stress design can be adjusted without losing the functions of the solid electrolytic capacitor element, the first sealing layer, and the second sealing layer.

It is preferable that the moisture permeability of the stress relaxation layer is lower than the moisture permeability of at least one of the first sealing layer and the second sealing layer. In this case, in addition to adjusting the stress, the penetration of water into the solid electrolytic capacitor element can also be reduced. The moisture permeability of the stress relaxation layer can be adjusted according to the type of insulating resin constituting the stress relaxation layer, the amount of filler contained in the stress relaxation layer, and the like.

In the capacitor array of the present invention, when a stress relaxation layer is provided between the solid electrolytic capacitor element and the first sealing layer, as long as the stress relaxation layer is provided between at least one solid electrolytic capacitor element and the first sealing layer can. The stress relaxation layer may not be provided in the whole between the solid electrolytic capacitor element and the first sealing layer, and there may be a portion where the stress relaxation layer is not provided between the solid electrolytic capacitor element and the first sealing layer.

In the capacitor array of the present invention, when a stress relaxation layer is provided between the solid electrolytic capacitor element and the second sealing layer, as long as the stress relaxation layer is provided between at least one solid electrolytic capacitor element and the second sealing layer can. The stress relaxation layer may not be provided in the whole between the solid electrolytic capacitor element and the second sealing layer, and there may be a portion where the stress relaxation layer is not provided between the solid electrolytic capacitor element and the second sealing layer.

In the capacitor array of the present invention, when the stress relaxation layer is provided between the solid electrolytic capacitor element and the first sealing layer, and between the solid electrolytic capacitor element and the second sealing layer, at least one solid electrolytic capacitor element is required A stress relaxation layer may be provided between the first sealing layer and between at least one solid electrolytic capacitor element and the second sealing layer. There may be a solid electrolytic capacitor element with a stress relaxation layer provided only on the first sealing layer side, a solid electrolytic capacitor element with a stress relaxation layer provided only on the second sealing layer side, and a first sealing layer side and a second Both the sealing layer side are provided with a solid electrolytic capacitor element with a stress relaxation layer. The stress relaxation layer may not be provided on the whole between the solid electrolytic capacitor element and the first sealing layer or the second sealing layer, and there may be no stress relaxation layer between the solid electrolytic capacitor element and the first sealing layer or the second sealing layer The location.

In the capacitor array of the present invention, when the stress relaxation layer is provided in the sheet removal portion, it is only necessary to provide the stress relaxation layer in at least one sheet removal portion. The stress relaxation layer is preferably filled in the sheet removal part. The stress relaxation layer further preferably enters a part of the first sealing layer.

[Composite Electronic Parts] The composite electronic component of the present invention includes: the capacitor array of the present invention; external electrodes are provided on the outer side of the first sealing layer or the second sealing layer of the capacitor array and connected to each of the anode plate and the cathode layer of the capacitor array ; And electronic parts, which are connected to the above-mentioned external electrodes.

In the composite electronic component of the present invention, as the electronic component connected to the external electrode, it can be a passive component or an active component. Both the passive element and the active element can be connected to the external electrode, or either the passive element and the active element can be connected to the external electrode. In addition, it can also be a composite of passive components and active components connected to external electrodes.

Examples of passive components include inductors and the like. Active components include memory, GPU (Graphical Processing Unit, graphics processing unit), CPU (Central Processing Unit), MPU (Micro Processing Unit, microprocessor), and PMIC (Power Manegement IC).

As explained above, the capacitor array of the present invention has a chip shape as a whole. Therefore, in the composite electronic component of the present invention, the capacitor array can be used as a mounting substrate, and electronic components can be mounted on the capacitor array. Furthermore, by making the shape of the electronic components mounted on the capacitor array into a sheet shape, the capacitor array and the electronic components can be connected in the thickness direction through the through electrodes penetrating each electronic component in the thickness direction. As a result, the active component and the passive component can be formed into a unified module.

For example, the capacitor array of the present invention can be electrically connected between a voltage regulator including a semiconductor active device and a load supplied with a converted DC voltage to form a switching regulator.

In the composite electronic component of the present invention, a circuit layer can be formed on any one surface of the capacitor matrix sheet obtained by further arranging a plurality of capacitor arrays of the present invention, and then connected to a passive element or an active element.

In addition, the capacitor array of the present invention can be arranged in a cavity part previously provided on a substrate, and after embedding with resin, a circuit layer is formed on the resin. Other passive components or active components can also be mounted on other cavities of the same substrate.

Alternatively, the capacitor array of the present invention can be mounted on a smooth carrier such as a wafer or glass, and after forming the outer layer with resin, the circuit layer is formed, and then connected to the passive component or the active component.

1, 1A, 1B, 1C, 1D, 1E, 1F, 1G: capacitor array 10A, 10B, 10C, 10D, 10E, 10F: solid electrolytic capacitor element 11: first sealing layer 12: second sealing layer 13: stress relaxation Layer 20: formed foil 21: anode plate 22: porous layer 23: dielectric layer 24: cathode layer 24a: solid electrolyte layer 24b: carbon layer 24c: copper layer 25, 25A: sheet removal part 30: insulating layer 31, 31X, 31Y, 31Z, 32: Through hole 41A, 41B, 41C, 41D, 41E, 41F: Anode external electrode 42A, 42B, 42C, 42D: Cathode external electrode 50: Wire conductor 50A: Through hole conductor 51: Anode through electrode 52: Anode through-hole conductor 53, 54: Anode wiring pattern 61: Cathode through-electrode 62: Cathode through-hole conductor 63, 64: Cathode wiring pattern 70: Capacitor 71: Through hole 72: Insulating part 100: Solid electrolytic capacitor chip 110 : Capacitor element D ₁₀ that is different from the solid electrolytic capacitor element: Space between anode plates S1: First main surface S2: Second main surface X: Anode Y: Cathode

Fig. 1 is a cross-sectional view schematically showing an example of the capacitor array of the present invention. Fig. 2 is an enlarged cross-sectional view schematically showing another example of the sheet removal part. Fig. 3A is a perspective view schematically showing an example of a step of preparing a formed foil, and Fig. 3B is a cross-sectional view thereof. Fig. 4A is a perspective view schematically showing an example of a step of forming an insulating layer, and Fig. 4B is a cross-sectional view thereof. Fig. 5 is a perspective view schematically showing an example of a step of forming a through hole. FIG. 6A is a perspective view schematically showing an example of a step of forming a solid electrolyte layer, and FIG. 6B is a cross-sectional view thereof. Fig. 7A is a perspective view schematically showing an example of a step of forming a carbon layer, and Fig. 7B is a cross-sectional view thereof. FIG. 8A is a perspective view schematically showing an example of a step of forming a copper layer, and FIG. 8B is a cross-sectional view thereof. Fig. 9A is a perspective view schematically showing an example of a step of disposing the first sealing layer, and Fig. 9B is a cross-sectional view thereof. FIG. 10A is a perspective view schematically showing an example of a step of cutting a solid electrolytic capacitor chip, and FIG. 10B is a cross-sectional view thereof. Fig. 11 is a perspective view schematically showing an example of a procedure for arranging capacitor elements of a different type from the solid electrolytic capacitor element. Fig. 12A is a perspective view schematically showing an example of a step of disposing the second sealing layer, and Fig. 12B is a cross-sectional view thereof. FIG. 13A is a perspective view schematically showing an example of a step of dividing into a plurality of capacitor arrays, and FIG. 13B is a cross-sectional view thereof. Fig. 14 is a perspective view schematically showing an example of a step of forming an anode external electrode. Fig. 15 is a perspective view schematically showing an example of a step of forming a cathode external electrode. Fig. 16 is a perspective view schematically showing another example of the step of forming the external electrode of the cathode. Fig. 17 is a perspective view of Fig. 15 for explaining the function of the through hole. Fig. 18 is a perspective view of Fig. 16 for explaining the function of the through hole. Fig. 19A is a projected plan view of the first modification of the structure of the anode and the cathode viewed from the side of the second sealing layer, and Fig. 19B is a projected cross-sectional view taken along the line b-b of Fig. 19A. Fig. 20A is a projected plan view of the second modification of the structure of the anode and the cathode viewed from the side of the second sealing layer, and Fig. 20B is a projected cross-sectional view taken along the line b-b of Fig. 20A. FIG. 21A is a projected plan view of the third modification of the structure of the anode and the cathode viewed from the second sealing layer side, and FIG. 21B is a projected cross-sectional view taken along the line b-b of FIG. 21A. Fig. 22A is a projected plan view of the fourth modification of the structure of the anode and the cathode viewed from the second sealing layer side, and Fig. 22B is a projected cross-sectional view taken along the line b-b of Fig. 22A. Fig. 23 is a perspective view schematically showing another example of the step of cutting the solid electrolytic capacitor chip. Fig. 24 is a plan view schematically showing an example of a capacitor part whose planar shape is not rectangular. Fig. 25 is a cross-sectional view schematically showing an example of a capacitor array provided with a stress relaxation layer. FIG. 26 is a perspective view schematically showing an example of a solid electrolytic capacitor chip used for manufacturing the capacitor array shown in FIG. 25. Fig. 27 is a cross-sectional view schematically showing another example of a capacitor array provided with a stress relaxation layer. FIG. 28 is a perspective view schematically showing an example of a solid electrolytic capacitor chip used for manufacturing the capacitor array shown in FIG. 27. Fig. 29 is a cross-sectional view schematically showing another example of a capacitor array provided with a stress relaxation layer. FIG. 30 is a perspective view schematically showing an example of a solid electrolytic capacitor chip used for manufacturing the capacitor array shown in FIG. 29.

1: Capacitor array 10A, 10B, 10C: solid electrolytic capacitor element 11: first sealing layer 12: second sealing layer 21: anode plate 22: porous layer 23: dielectric layer 24: cathode layer 24a: solid electrolyte layer 24b : Carbon layer 24c: Copper layer 25: Sheet removal part 30: Insulating layer D ₁₀ : Space between anode plates S1: First main surface S2: Second main surface

Claims (16)

A capacitor array comprising: a plurality of solid electrolytic capacitor elements divided into a solid electrolytic capacitor chip, Sheet-like first sealing layer, and The second sealing layer in sheet form, The solid electrolytic capacitor chip includes: an anode plate including a valve metal; a porous layer provided on at least one main surface of the anode plate; a dielectric layer provided on the surface of the porous layer; and a cathode layer, It includes a solid electrolyte layer provided on the surface of the dielectric layer; and the solid electrolytic capacitor chip has a first main surface and a second main surface opposite in the thickness direction, The first main surface side of each of the plurality of solid electrolytic capacitor elements is arranged on the first sealing layer, The second sealing layer is arranged so as to cover the plurality of solid electrolytic capacitor elements on the first sealing layer from the second main surface side, and The solid electrolytic capacitor elements are divided by slit-shaped sheet removal parts. The capacitor array according to claim 1, wherein the distance from the bottom surface of the second sealing layer to the anode plate of each solid electrolytic capacitor element is fixed. The capacitor array according to claim 1 or 2, wherein at least one solid electrolytic capacitor element is arranged on the extension line of the sheet removal part. The capacitor array of claim 1 or 2, wherein the width of the above-mentioned sheet removal portion is 15 μm or more and 500 μm or less. The capacitor array of claim 4, wherein the width of the sheet removal portion is 200 μm or less. The capacitor array of claim 1 or 2, wherein the ratio of the length/width of the sheet removal portion, that is, the aspect ratio, is 10 or more. The capacitor array according to claim 1 or 2, wherein at least a part of the above-mentioned sheet removal portion is arranged in a manner not to spread over the entire capacitor array. The capacitor array of claim 1 or 2, wherein the sheet removal portion has a wedge shape whose width decreases from one main surface of the solid electrolytic capacitor element toward the other main surface. The capacitor array of claim 8, wherein the porous layer is provided on both main surfaces of the anode plate, The wedge shape does not reach the porous layer on the other main surface side of the solid electrolytic capacitor element. The capacitor array according to claim 1 or 2, wherein the plurality of solid electrolytic capacitor elements include two or more types of solid electrolytic capacitor elements with different areas of capacitor portions. The capacitor array according to claim 1 or 2, wherein the plurality of solid electrolytic capacitor elements include solid electrolytic capacitor elements in which the planar shape of the capacitor portion is not rectangular. The capacitor array of claim 1 or 2, wherein a stress relaxation layer is further provided between the solid electrolytic capacitor element and the first sealing layer or the second sealing layer. The capacitor array of claim 12, wherein the stress relaxation layer is also provided in the sheet removal part. The capacitor array according to claim 12, wherein the stress relaxation layer includes an insulating resin. The capacitor array according to claim 12, wherein the moisture permeability of the stress relaxation layer is lower than the moisture permeability of at least one of the first sealing layer and the second sealing layer. A composite electronic component, comprising: the capacitor array of any one of claims 1 to 15; An external electrode is provided on the outer side of the first sealing layer or the second sealing layer of the capacitor array and connected to each of the anode plate and the cathode layer of the capacitor array; and The electronic component is connected to the above-mentioned external electrode.

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