TWI711032B - Auto timing switching apparatus and method applied to display panel - Google Patents

Abstract

An auto timing switching apparatus applied to a display panel is disclosed. The auto timing switching apparatus includes a mode detection unit and a timing control unit. The mode detection unit is coupled to the display panel and used to automatically detect a specific driving mode that a gate driving circuit uses on the display panel. The timing control unit is coupled to the mode detection unit and the gate driving circuit respectively and used to select a corresponding specific timing control setting from a plurality of timing control settings according to the specific driving mode and output the specific timing control setting to the gate driving circuit. The plurality of timing control settings corresponds to different charging times respectively.

Description

Automatic time sequence switching device and method applied to display panel

The present invention relates to displays, and in particular relates to an automatic timing switching device and method applied to a display panel.

Generally speaking, the current gate driving mode of the display panel mostly adopts a bilateral driving mode in which the left and right sides of the display panel are simultaneously driven. Regardless of whether the display panel uses a gate drive integrated circuit or a gate drive circuit array substrate (Gate on Array, GOA), due to its complicated wiring, once the manufacturing process has defects, the circuit board can be modified to only start from the display panel. Left-side drive or unilateral drive mode that only drives from the right side of the display panel.

If the unilateral drive mode is only driven from the left side of the display panel, in order to avoid wrong charging on the non-driving side (that is, the right side of the display panel), the display screen of the display panel will appear white, usually shorten the driving side (that is, the display panel). The charging time on the left), but it will cause insufficient charging on the drive side, resulting in a difference in brightness and darkness on the display screen of the display panel. In the same way, if the unilateral driving mode is used that only drives from the right side of the display panel, shortening the charging time on the driving side (that is, the right side of the display panel) will cause insufficient charging on the driving side (that is, the right side of the display panel), resulting in the display of the display panel. The picture appears to be dark and bright.

In the above example, no matter it is the bilateral drive mode or the unilateral drive mode, the same control circuit board (Control board) is used for control. If a different control circuit board is used to distinguish the two-sided drive mode and the left/right one-sided drive mode, it is difficult to predict that process defects will appear on the left or right side of the display panel, and it is impossible to know in advance that the two-sided drive mode will be changed to the left side. The unilateral drive mode or the right unilateral drive mode will cause problems such as difficult material preparation and difficult control of shipments, which need to be overcome.

Therefore, the present invention provides an automatic timing switching device and method applied to a display panel to solve the above-mentioned problems encountered in the prior art.

A specific embodiment according to the present invention is an automatic timing switching device applied to a display panel. In this embodiment, the automatic timing switching device includes a mode detection unit and a timing control unit. The mode detection unit is coupled to the display panel for automatically detecting a specific driving mode adopted by the gate driving circuit on the display panel. The timing control unit is coupled to the mode detection unit for selecting a corresponding specific timing control setting from a plurality of timing control settings according to a specific driving mode and outputting the specific timing control setting. The plurality of timing control settings respectively correspond to different charging times.

In one embodiment, the specific driving mode is a bilateral driving mode, a left unilateral driving mode, or a right unilateral driving mode.

In one embodiment, the mode detection unit receives the first feedback signal from the first side of the display panel and the second feedback signal from the second side of the display panel respectively, and according to the first feedback signal and the second feedback signal The level of the feedback signal determines the specific driving mode.

In one embodiment, when the first feedback signal and the second feedback signal are both at the first level, the specific driving mode is the bilateral driving mode; when the first feedback signal is at the first level and the second feedback signal When it is the second level, the specific driving mode is the left unilateral driving mode; when the first feedback signal is the second level and the second feedback signal is the first level, the specific driving mode is the right unilateral driving mode.

In one embodiment, the timing control unit is coupled to the gate driving circuit. The display panel includes a plurality of gate lines and a plurality of data lines. The gate drive circuit is coupled to the plurality of gate lines. The plurality of gate lines respectively transmit a plurality of scan line signals and the plurality of data lines respectively transmit a plurality of A data line signal, if the first scan line signal transmitted by the first gate line of the plurality of gate lines starts at the first time and ends at the second time, and the first of the plurality of data lines The first data line signal transmitted by one data line has a pixel voltage corresponding to the first gate line, and the first time interval between the first time and the second time is the charging time.

In one embodiment, if the first data line signal transmitted by the first data line starts to switch to the second pixel voltage corresponding to the second gate line of the plurality of gate lines at the third time, The second time interval between the second time and the third time is related to the first time interval, and the plurality of timing control settings also correspond to different second time intervals.

In one embodiment, when the second time interval becomes longer, the first time interval is relatively shorter.

Another specific embodiment according to the present invention is an automatic timing switching method applied to a display panel. In this embodiment, the automatic timing switching method includes the following steps: (a) automatically detecting the specific driving mode adopted by the gate driving circuit for the display panel; (b) selecting the corresponding from a plurality of timing control settings according to the specific driving mode (C) output a specific timing control setting; wherein the plurality of timing control settings correspond to different charging times.

Compared with the prior art, the automatic timing switching device and method of the present invention automatically detects the driving mode adopted by the gate driving circuit for the display panel according to the level of the feedback signal on the left and right sides of the display panel, and according to the detection The timing control setting corresponding to the measured drive mode output is used to adjust the timing relationship between the scan line signal transmitted by the gate line and the data line signal transmitted by the data line, thereby effectively avoiding the non-driving side in the conventional technology Wrong charging causes the screen to appear white and insufficient charging on the drive side causes the screen to appear bright and dark.

In addition, because the automatic timing switching device and method of the present invention still use the same control circuit board no matter which gate drive mode is used, it will not cause difficulty in preparing materials and difficult to control shipments encountered by the prior art. And other issues.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.

In the drawings, some areas are enlarged for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a region or a substrate is referred to as being "on" or "connected (or referred to as coupled)" or "electrically connected" to another element, it may be directly connected to another element. It is connected to another element (or referred to as being coupled) or electrically connected, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected (or referred to as coupled)" can refer to physical and/or electrical connections.

A specific embodiment according to the present invention is an automatic timing switching device for different gate drive modes applied to a display panel. In this embodiment, the automatic timing switching device receives feedback signals from the left and right sides of the display panel, and automatically determines according to the level of the feedback signal that the current gate drive mode used by the gate drive circuit for the display panel is Double-side drive mode, left-side single-side drive mode or right-side single-side drive mode, and then output corresponding timing control settings according to different gate drive modes.

Therefore, regardless of whether the gate drive circuit currently adopts the bilateral drive mode, the left unilateral drive mode or the right unilateral drive mode for the display panel, the automatic timing switching device can automatically switch to provide a suitable charging time, so it can effectively avoid the conventional technology. Encountered problems such as incorrect charging on the non-drive side causing the screen to appear white and insufficient charging on the drive side to cause the screen to appear bright and dark.

Please refer to FIG. 1. FIG. 1 is a schematic diagram showing the automatic timing switching device 1 applied to the display DP.

As shown in FIG. 1, the display DP includes an automatic timing switching device 1, a control circuit board 2, a display panel 3, and gate drive circuits 4A-4B. The automatic sequence switching device 1 and the gate drive circuits 4A-4B are arranged on the control circuit board 2. The automatic timing switching device 1 is respectively coupled to the display panel 3 and the gate driving circuits 4A-4B. The gate driving circuits 4A-4B are respectively coupled to the automatic timing switching device 1 and the display panel 3. The automatic timing switching device 1 respectively receives the first feedback signal FB1 from the first side (for example, the left side) LS of the display panel 3 and the second feedback signal FB2 from the second side (for example, the right side) RS of the display panel 3, and Corresponding to the output specific timing control setting TS to the gate drive circuit 4A~4B.

Please refer to FIG. 2. FIG. 2 is a functional block diagram of the automatic timing switching device 1.

As shown in FIG. 2, the automatic timing switching device 1 includes a mode detection unit 10 and a timing control unit 12. The mode detection unit 10 is coupled to the display panel 3 to automatically detect the specific driving mode DM adopted by the gate driving circuits 4A~4B on the display panel 3, for example, from the first side (left side) LS and the first side of the display panel 3 Bilateral drive mode in which RS is driven at the same time on both sides (right side), unilateral drive mode in which LS drives only from the first side (left side) of display panel 3, or only from the second side Side) Single-side drive mode of RS drive.

In practical applications, the mode detection unit 10 can respectively receive the first feedback signal FB1 from the first side (left side) LS of the display panel 3 and the second feedback signal from the second side (right side) RS of the display panel 3 Signal FB2, and according to the level of the first feedback signal FB1 and the second feedback signal FB2 to determine the specific driving mode DM adopted by the gate driving circuits 4A-4B for the display panel 3.

For example, as shown in Table 1, when the first feedback signal FB1 and the second feedback signal FB2 are both at the first level (for example, high level), the mode detection unit 10 may determine that the specific driving mode DM is a slave A bilateral drive mode in which the first side (left side) LS and the second side (right side) RS of the display panel 3 are simultaneously driven; when the first feedback signal FB1 is at the first level (for example, high level) and the second feedback signal FB2 When it is the second level (for example, the low level), the mode detection unit 10 can determine that the specific driving mode DM is a unilateral driving mode driven only from the first side (left side) LS of the display panel 3; when the first feedback signal When FB1 is at the second level (for example, low level) and the second feedback signal FB2 is at the first level (for example, high level), the mode detection unit 10 can determine that the specific driving mode DM is only from the second level of the display panel 3. Side (right) RS-driven right-side single-side drive mode.

After the mode detection unit 10 has automatically determined the specific driving mode DM adopted by the gate driving circuits 4A-4B for the display panel 3 according to the levels of the first feedback signal FB1 and the second feedback signal FB2, the mode detection unit 10 transmits the specific drive mode DM to the timing control unit 12, and the timing control unit 12 selects a specific timing control setting TS corresponding to the specific drive mode DM from a plurality of timing control settings according to the specific drive mode DM and outputs it.

In practical applications, the plurality of timing control settings respectively correspond to different charging times.

For example, when the mode detection unit 10 determines that the specific drive mode DM is the double-sided drive mode, the timing control unit 12 will select the first timing control setting corresponding to the double-sided drive mode from a plurality of timing control settings, and the first The timing control setting will correspond to the first charging time.

Similarly, when the mode detection unit 10 determines that the specific drive mode DM is the left unilateral drive mode, the timing control unit 12 will select the second timing control setting corresponding to the left unilateral drive mode from a plurality of timing control settings, and The second timing control setting will correspond to the second charging time. When the mode detection unit 10 determines that the specific drive mode DM is the right unilateral drive mode, the timing control unit 12 will select the third timing control setting corresponding to the right unilateral drive mode from a plurality of timing control settings, and the third timing The control setting will correspond to the third charging time.

Thereby, even if the driving mode of the display panel by the gate driving circuit is changed, for example, from the original double-side driving mode to the current left-side single-side driving mode, the automatic timing switching device 1 of the present invention can automatically detect the current driving mode. Mode, and automatically select the timing control settings corresponding to the current drive mode, so as to provide timing control settings and charging time suitable for the current drive mode to the gate drive circuit to avoid mischarging on the non-drive side and insufficient charging on the drive side, etc. problem.

Next, it will be explained through an embodiment. If the gate drive circuit array substrate (GOA) is taken as an example, it is assumed that the gate drive circuit array substrate originally used the bilateral drive mode, but due to the failure of the drive circuit on one side of the display panel (for example, the right side), it was modified to only A unilateral drive mode that drives the other side of the display panel (for example, the left side). At this time, the signal connection method of the gate drive circuit array substrate is shown in FIG. 3. Among them, the signal VGHD, which was originally a positive voltage, becomes a signal VSSQ with a negative voltage after modification. The mode detection unit 10 can determine that it is the left unilateral drive mode based on this signal, and output the corresponding timing control setting according to Table 2 (for example, the second time interval ΔT2 shown in FIG. 5, but not limited to this) .

Table 2 The first feedback signal FB1 on the first side (left side) The second feedback signal FB2 on the second side (right side) Specific drive mode DM Timing control setting (second time interval ΔT2) First level (high level) First level (high level) Bilateral drive mode 6us First level (high level) Second level (lower level) Single side drive mode on the left 5us->6.65us Second level (lower level) First level (high level) Right side single drive mode 6.15us>-4.5us

Next, the definition of the second time interval ΔT2 in FIG. 5 and its relationship with the first time interval (ie, the charging time) ΔT1 will be described.

Referring to FIG. 4, it is assumed that the display panel 3 includes a plurality of pixels R/G/B, a plurality of horizontal gate lines GL1~GL3, and a plurality of vertical data lines DL1~DL6. The gate lines GL1 to GL3 and the data lines DL1 to DL6 are respectively coupled to a plurality of R/G/B transistor switches TR. The gate lines GL1 to GL3 are coupled to the gate driving circuit for respectively transmitting a plurality of scan line signals G1 to G3 issued by the gate driving circuit. The data lines DL1 to DL6 are coupled to the source driving circuit for respectively transmitting a plurality of data line signals D1 to D6 issued by the gate driving circuit.

If the display panel 3 includes three horizontal gate lines GL1~GL3 as an example, the conduction time of the transistor switch TR of the pixel R/G/B of each horizontal column only accounts for at most one-third of the update time of the entire screen. One. Once the image update frequency is faster and the number of horizontal gate lines increases, the conduction time of the transistor switch TR will be shorter. For example, assuming that the image update frequency is 60 Hz and the display panel includes 1024 horizontal gate lines, the conduction time of the transistor switch TR in each horizontal column is approximately (1/60)/1024=16.3us .

However, the actual effective charging time (Charge time) also needs to consider the difference between the scan line signals G1~G3 transmitted by the gate lines GL1~GL3 and the data line signals D1~D6 transmitted by the data lines DL1~DL6. Synchronize. Therefore, the automatic timing switching device 1 of the present invention can automatically switch to the corresponding timing control setting according to the detection result of the current gate driving mode of the display panel 3 to adjust the scan line signal G1 transmitted by the gate lines GL1~GL3 The timing relationship between ~G3 and the data line signals D1~D6 transmitted by the data lines DL1~DL6 achieves the effect of timing control. In this way, no matter whether the gate driving circuit adopts the double-sided driving mode, the left-side single-side driving mode or the right-side single-side driving mode, the pixels in each horizontal column of the display panel 3 can get a suitable charging time without Incorrect charging or insufficient charging occurs.

It should be noted that the scan line signals G1 to G3 transmitted by the gate lines GL1 to GL3 and the data line signals D1 to D6 transmitted by the data lines DL1 to DL6 will be delayed and distorted with the propagation distance. Therefore, in order to ensure all pixels of the display panel 3, before the data line signal is switched, the scan line signal has turned off the transistor switch TR of the pixel to avoid writing an incorrect voltage. Therefore, the signal must be adjusted in timing. Delay to compensate.

For example, in order to control the charging time allocated to each pixel, to ensure that even if the scan line signal is delayed, the data line signal must be switched off before the pixel voltage corresponding to the next gate line. The transistor switch TR, therefore, the present invention defines the time interval between the end time of the scan line signal and the start time of the next data line signal as "GD space", such as the second time interval ΔT2 in FIG. 5.

As shown in FIG. 5, if the scan line signal G1 transmitted by the gate line GL1 starts at the first time t1 and ends at the second time t2, and the data line signal D1 transmitted by the data line DL1 corresponds to the gate line GL1 Then, the first time interval ΔT1 between the first time t1 and the second time t2 is the “charging time” of the pixel R coupled to the gate line GL1 and the data line DL1. If the data line signal D1 transmitted by the data line DL1 starts to switch to the second pixel voltage V2 corresponding to the gate line GL2 at the third time t3, the second time interval between the second time t2 and the third time t3 ΔT2 is the "GD space" defined earlier.

In practical applications, the second time interval ΔT2 is related to the first time interval (that is, the charging time) ΔT1. When the second time interval ΔT2 becomes longer, the first time interval ΔT1 will be relatively short, so that the actual chargeable time of the pixel R becomes shorter. Therefore, the present invention needs to consider the combined effect of charging time and signal delay at the same time when performing timing control, so as to effectively avoid the problems of insufficient charging and incorrect charging.

For example, as shown in Table 2, different timing control settings in various gate driving modes can correspond to different second time intervals ΔT2, respectively. It should be noted that in the bilateral drive mode, since the left LS and the right RS of the display panel 3 both receive the scan line signal at the same time, that is, the left LS and the right RS of the display panel 3 have no obvious signal delay effect. The entire display panel 3 may use the same timing control setting, for example, the second time interval ΔT2 is 6 us.

However, in the unilateral driving mode, since only the driving side of the display panel 3 receives the scan line signal, the non-driving side of the display panel 3 will have a significant signal delay effect. Therefore, different positions on the display panel 3 It is necessary to use different timing control settings, such as a different second time interval ΔT2, to eliminate the signal delay effect.

Furthermore, due to the manufacturing process, the optimal timing control settings (such as the second time interval ΔT2) corresponding to the left unilateral drive mode and the right unilateral drive mode are actually asymmetrical, so the left unilateral drive mode and the right unilateral drive mode are actually asymmetrical. There are different timing control settings for the side drive modes, so the same control circuit board can be used to avoid problems such as whitening of the screen due to incorrect charging on the non-drive side and insufficient charging on the drive side to cause the screen to appear bright and dark. Encountered problems such as difficulty in preparing materials and difficulty in controlling shipments.

For example, referring to Table 2 and Figure 6, in the left unilateral driving mode, that is, the scan line signal is transmitted from the left LS of the display panel 3 to the right RS, then from the left LS of the display panel 3 to the right RS. The second time interval ΔT2 used by the pixels of different panel areas XL2, XL1, XR1, XR2 increases from 5.0us, 6.0us, 6.5us to 6.65us, that is, the difference from the left LS of the display panel 3 to the right RS The first time interval (ie, the charging time) ΔT1 used by the pixels of XL2, XL1, XR1, and XR2 in the panel area will correspondingly decrease.

Similarly, in the right unilateral driving mode, that is, the scan line signal is transmitted from the right RS of the display panel 3 to the left LS, and then from the right RS of the display panel 3 to the different panel areas XR2, XR1, XL1 of the left LS The second time interval ΔT2 used by XL2 is increased from 4.5us, 5.5us, 6.0us to 6.15us, that is, the different panel areas XR2, XR1, XL1, and XL2 from the right RS of the display panel 3 to the left LS The first time interval (ie, the charging time) ΔT1 will decrease accordingly.

Another specific embodiment according to the present invention is an automatic timing switching method applied to a display panel. Please refer to FIG. 7. FIG. 7 is a flowchart of the automatic time sequence switching method in this embodiment.

As shown in Fig. 7, the automatic time sequence switching method in this embodiment includes the following steps:

Step S10: automatically detect the specific driving mode adopted by the gate driving circuit for the display panel;

Step S12: Select a corresponding specific timing control setting from a plurality of timing control settings according to the specific driving mode; and

Step S14: output specific timing control settings.

In practical applications, the plurality of timing control settings can respectively correspond to different charging times, but not limited to this. Step S10 may include: receiving the first feedback signal from the first side of the display panel and the second feedback signal from the second side of the display panel respectively; and according to the position of the first feedback signal and the second feedback signal The quasi level determines the specific drive mode.

For example, when the first feedback signal and the second feedback signal are both at the first level, step S10 may determine that the specific driving mode is the bilateral driving mode; when the first feedback signal is at the first level and the second level When the grant signal is at the second level, step S10 can determine that the specific drive mode is the left unilateral drive mode; when the first feedback signal is at the second level and the second feedback signal is at the first level, step S10 can determine the specific drive mode The driving mode is the right-side unilateral driving mode, but not limited to this.

Compared with the prior art, the automatic timing switching device and method of the present invention automatically detects the driving mode adopted by the gate driving circuit for the display panel according to the level of the feedback signal on the left and right sides of the display panel, and according to the detection The timing control setting corresponding to the measured drive mode output is used to adjust the timing relationship between the scan line signal transmitted by the gate line and the data line signal transmitted by the data line, thereby effectively avoiding the non-driving side in the conventional technology Wrong charging causes the screen to appear white and insufficient charging on the drive side causes the screen to appear bright and dark.

In addition, because the automatic timing switching device and method of the present invention still use the same control circuit board no matter which gate drive mode is used, it will not cause difficulty in preparing materials and difficult to control shipments encountered by the prior art. And other issues.

Through the detailed description of the preferred embodiments above, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, its purpose is to cover various changes and equivalent arrangements within the scope of the patent application for the present invention.

1: Automatic timing switching device 2: Control circuit board 3: display panel 4A~4B: Gate drive circuit DP: display TS: Specific timing control setting FB1~FB2: The first feedback signal ~ the second feedback signal LS: First side RS: second side R, G, B: pixel 10: Pattern detection unit 12: Timing control unit DM: specific drive mode ST, HCs, LCs, VGHD, Type C, VSSQ: signal G1~G3: scan line signal D1~D6: data line signal GL1~GL3: gate line DL1~DL6: data line TR: Transistor switch t1~t3: first time to third time HAVDD: Half working voltage V1~V2: the first pixel voltage ~ the second pixel voltage ΔT1: the first time interval ΔT2: second time interval XR1~XR2, XL1~XL2: Panel area S10~S14: steps

FIG. 1 is a schematic diagram of an automatic timing switching device according to a specific embodiment of the present invention applied to a display.

Figure 2 shows a functional block diagram of the automatic sequence switching device.

FIG. 3 is a schematic diagram showing the signal connection when the gate drive circuit array substrate (GOA) is changed from the double-sided drive mode to the single-sided drive mode.

4 is a schematic diagram showing a display panel including a plurality of horizontal gate lines and a plurality of vertical data lines respectively coupled to a plurality of pixels of transistor switches.

5 is a schematic diagram showing the waveforms of the scan line signal transmitted by the gate line and the data line signal transmitted by the data line.

FIG. 6 is a schematic diagram showing the left side single-side driving mode and the right side single-side driving mode respectively corresponding to different timing control settings.

FIG. 7 is a flowchart of an automatic time sequence switching method according to another specific embodiment of the present invention.

S10~S14: steps

Claims (14)

An automatic timing switching device applied to a display panel, the automatic timing switching device includes: A mode detection unit, coupled to the display panel, for automatically detecting a specific driving mode adopted by a gate driving circuit for the display panel; and A timing control unit, respectively coupled to the mode detection unit and the gate drive circuit, for selecting a corresponding specific timing control setting from a plurality of timing control settings according to the specific driving mode and setting the specific timing control setting Output to the gate drive circuit; Among them, the plurality of timing control settings respectively correspond to different charging times. According to the automatic timing switching device described in item 1 of the scope of patent application, the specific driving mode is a bilateral driving mode, a left unilateral driving mode, or a right unilateral driving mode. According to the automatic timing switching device described in claim 1, wherein the mode detection unit receives a first feedback signal from a first side of the display panel and a second side of the display panel. A second feedback signal, and the specific driving mode is determined according to the level of the first feedback signal and the second feedback signal. For example, the automatic timing switching device described in item 3 of the scope of patent application, wherein when the first feedback signal and the second feedback signal are both at the first level, the specific driving mode is the bilateral driving mode; when the first When the feedback signal is at the first level and the second feedback signal is at the second level, the specific driving mode is the left-side unilateral driving mode; when the first feedback signal is at the second level and the second feedback When the signal is in the first position, the specific driving mode is the right side single-side driving mode. The automatic timing switching device described in item 1 of the scope of patent application, wherein the display panel includes a plurality of gate lines arranged horizontally and a plurality of data lines arranged vertically, and the gate drive circuit Is coupled to the plurality of gate lines, the plurality of gate lines respectively transmit a plurality of scan line signals and the plurality of data lines respectively transmit a plurality of data line signals, if one of the plurality of gate lines is the first A first scan line signal transmitted by the gate line starts at a first time and ends at a second time, and a first data line signal transmitted by the first data line of one of the plurality of data lines has Corresponding to a first pixel voltage of the first gate line, a first time interval between the first time and the second time is the charging time. The automatic timing switching device described in item 5 of the scope of patent application, wherein if the first data line signal transmitted by the first data line starts to switch to the one corresponding to the plurality of gate lines at a third time A second pixel voltage of a second gate line, a second time interval between the second time and the third time is related to the first time interval, and the plurality of timing control settings are also They respectively correspond to different second time intervals. According to the automatic time sequence switching device described in item 6 of the scope of patent application, when the second time interval becomes longer, the first time interval is relatively shorter. An automatic time sequence switching method applied to a display panel. The automatic time sequence switching method includes the following steps: (a) Automatically detect a specific driving mode adopted by a gate driving circuit for the display panel; (b) Select a corresponding specific timing control setting from a plurality of timing control settings according to the specific driving mode; and (c) Output the specific timing control setting to the gate drive circuit; Among them, the plurality of timing control settings respectively correspond to different charging times. The automatic timing switching method described in item 8 of the scope of patent application, wherein the specific driving mode is a bilateral driving mode, a left unilateral driving mode or a right unilateral driving mode. The automatic time sequence switching method as described in item 8 of the scope of patent application, wherein step (a) includes: Receiving a first feedback signal from a first side of the display panel and a second feedback signal from a second side of the display panel respectively; and The specific driving mode is determined according to the level of the first feedback signal and the second feedback signal. For example, the automatic timing switching method described in item 10 of the scope of patent application, wherein when the first feedback signal and the second feedback signal are both at the first level, the specific driving mode is the bilateral driving mode; When the feedback signal is at the first level and the second feedback signal is at the second level, the specific driving mode is the left-side unilateral driving mode; when the first feedback signal is at the second level and the second feedback When the signal is in the first position, the specific driving mode is the right side single-side driving mode. The automatic timing switching method described in item 8 of the scope of patent application, wherein the display panel includes a plurality of gate lines and a plurality of data lines, the gate driving circuit is coupled to the plurality of gate lines, and the plurality of gates The pole lines respectively transmit a plurality of scan line signals and the plurality of data lines respectively transmit a plurality of data line signals, if a first scan line signal transmitted by the first gate line of one of the plurality of gate lines starts at A first time and ends at a second time, and a first data line signal transmitted by a first data line of the plurality of data lines has a first picture corresponding to the first gate line If the voltage is equal to the element voltage, a first time interval between the first time and the second time is the charging time. The automatic timing switching method described in item 12 of the scope of patent application, wherein if the first data line signal transmitted by the first data line starts to switch to the one corresponding to the plurality of gate lines at a third time A second pixel voltage of a second gate line, a second time interval between the second time and the third time is related to the first time interval, and the plurality of timing control settings are also They respectively correspond to different second time intervals. The automatic time sequence switching method as described in item 13 of the scope of patent application, wherein when the second time interval becomes longer, the first time interval is relatively shorter.

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