TWI709886B - Touch and display device - Google Patents

Abstract

A touch and display device includes a touch electrode array, a driving circuit, a control signal generation circuit and a touch multiplexed circuit. The touch electrode array includes multiple touch electrodes. The driving circuit is configured to output multiple first control signals. The control signal generation circuit is electrically coupled to the driving circuit, and configured to generate multiple second control signals according to the first control signals. The touch multiplexed circuit is electrically coupled to the touch electrodes and the control signal generation circuit, and configured to output multiple detecting signals according to the second control signals to detect touch. The number of the second control signals is larger than the number of the first control signals.

Description

Touch display device

The present disclosure relates to a touch display device, and particularly a touch display device with a touch multiplex circuit.

With the development of technology, the demand for touch display devices has become more and more extensive. Since moving the circuits in the chip to the glass (Glass) process can reduce the cost of the chip, it will be helpful for applications that require a multi-chip architecture. However, due to the limited number of pins of chip circuits moved into the glass process, it is unable to support the operation of multiplexed circuits that require multiple control signals.

Therefore, how to output the control signal required by the multiplexer circuit with a limited number of pins is a design consideration and challenge at present.

An implementation aspect of the present disclosure relates to a touch display device including a touch electrode array, a driving circuit, a control signal generating circuit, and a touch multiplexing circuit. The touch electrode array includes a plurality of touch electrodes. The driving circuit is used for outputting a plurality of first control signals. The control signal generating circuit is electrically coupled to the driving circuit for generating a plurality of second control signals according to the first control signal. The touch multiplex circuit is electrically coupled to the contact control electrode and the control signal generating circuit for Second, the control signal outputs a plurality of detection signals to the touch electrode for touch detection. The number of second control signals is greater than the number of first control signals.

100‧‧‧Touch display device

110‧‧‧Drive circuit

120‧‧‧Touch electrode array

130‧‧‧Control signal generating circuit

132‧‧‧Starting circuit

134‧‧‧End circuit

136‧‧‧Pull-up circuit

138‧‧‧Pull-down circuit

140‧‧‧Touch Multiplex Circuit

140a~140n‧‧‧Touch Multiple Unit

150‧‧‧Pixel array

160‧‧‧Gate drive circuit

170‧‧‧Switching circuit

P[1], P[2]~P[n], P[n+1], P[n+2]~P[2n]…P[6n]‧‧‧Touch electrode

C1~Cn‧‧‧Touch electrode array

L1, L2, L3, L4, L5‧‧‧Connecting line

PX‧‧‧Pixel

A1~A6‧‧‧area

Rx1~Rx6‧‧‧Output

S[1]~S[6], S[1]G~S[6]G, S[k], S[k]G‧‧‧Second control signal

Sgd‧‧‧Reset signal

M1~M6、M1’~M6’‧‧‧Transistor

Tf, Td, Tr, Tt, t1~t6‧‧‧period

Vcom‧‧‧Common voltage level

Vgd‧‧‧Reset voltage level

Sen‧‧‧Detection voltage

TPSR[1]~TPSR[6], TPSR[k]‧‧‧Shift temporary storage unit

SRc‧‧‧shift register circuit

Inv‧‧‧Reverse circuit

T1~T18‧‧‧Transistor

R1, R2‧‧‧Resistor

Q‧‧‧node

TP_CK, TP_XCK‧‧‧clock signal

TP_STV, S[k-1]‧‧‧Start signal

TP_END, S[k+1]‧‧‧End signal

TPSW‧‧‧Select signal

VGH‧‧‧High reference voltage level

VSS‧‧‧Low reference voltage level

GOFF‧‧‧Gate drive end signal

FIG. 1A is a schematic diagram of a touch display device according to some embodiments of the present disclosure.

FIG. 1B is a schematic diagram showing another touch display device according to some embodiments of the present disclosure.

FIG. 2 is a schematic diagram of a touch electrode array according to some embodiments of the present disclosure.

FIG. 3 is a schematic diagram of a touch multiplexing circuit according to some embodiments of the present disclosure.

FIG. 4 is a schematic diagram of a touch multiplex unit according to some embodiments of the present disclosure.

FIG. 5 is a timing diagram of a control signal and touch electrode operation according to some embodiments of the present disclosure.

FIG. 6 is a schematic diagram of a control signal generating circuit according to some embodiments of the present disclosure.

FIG. 7 is a schematic diagram of a shift register unit according to some embodiments of the present disclosure.

FIG. 8 is a schematic diagram of signal timing of a control signal generating circuit according to some embodiments of the present disclosure.

Figure 9 illustrates another shift according to other embodiments of the present disclosure Schematic diagram of the bit temporary storage unit.

FIG. 10 is a schematic diagram showing another shift register unit according to other embodiments of the present disclosure.

FIG. 11 is a schematic diagram showing the signal timing of another shift register unit according to other embodiments of the present disclosure.

FIG. 12 is a schematic diagram of another shift register unit according to other embodiments of the present disclosure.

FIG. 13 is a schematic diagram of another shift register unit according to other embodiments of the present disclosure.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the specific embodiments described are only used to explain the case, not to limit the case, and the description of the structural operation is not used to limit the order of its execution. The recombined structures and the devices with equal effects are all within the scope of this disclosure. In addition, according to industry standards and common practices, the drawings are only for the purpose of supplementary explanation, and are not drawn according to the original dimensions. In fact, the dimensions of various features can be arbitrarily increased or decreased for ease of explanation. In the following description, the same elements will be described with the same symbols to facilitate understanding.

Unless otherwise specified, the terms used in the entire specification and the scope of the patent application usually have the usual meaning of each term used in the field, in the content disclosed here, and in the special content. Some terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance on the description of the present disclosure.

The terms "include", "have" and so on used in this article are all open terms, meaning "including but not limited to". In addition, the "and/or" used in this article includes any one of one or more of the related listed items and all combinations thereof.

In this text, when a component is referred to as "connection" or "coupling", it can refer to "electrical connection" or "electrical coupling". "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless clearly indicated by the context, the terms do not specifically refer to or imply order or sequence, nor are they used to limit the present invention.

For ease of description, the circuits and components of the touch display device 100 of the present disclosure are respectively shown in FIG. 1A and FIG. 1B. Please refer to Figure 1A. FIG. 1A is a schematic diagram of a touch display device 100 according to some embodiments of the present disclosure. As shown in FIG. 1A, the touch display device 100 includes a driving circuit 110, a touch electrode array 120, a control signal generating circuit 130, and a touch multiplexing circuit 140. The touch electrode array 120 includes a plurality of touch electrodes arranged in an array. In the embodiment in FIG. 1A, the touch electrode array 120 includes n touch electrode columns C1 to Cn, and each touch electrode column includes 6n touch electrodes. For example, the first touch electrode column C1 includes touch electrodes P[1]~P[6n]. Among them, n is a positive integer greater than 1.

Structurally, the driving circuit 110 is electrically coupled to the control signal generating circuit 130. The control signal generating circuit 130 is electrically coupled to the contact control multiplexing circuit 140. The touch multiplex circuit 140 is electrically coupled to a plurality of touch circuits in the contact control electrode array 120 pole. Specifically, the driving circuit 110 is electrically coupled to the control signal generating circuit 130 through the connecting line L1. The control signal generating circuit 130 is electrically coupled to the control multiplex circuit 140 through the connection line L2. The touch multiplex circuit 140 is electrically coupled to a plurality of touch electrodes in the control electrode array 120 through the connection line L3.

In some embodiments, the number of connecting lines L1 is less than the number of connecting lines L2. For example, there may be 4 connecting lines L1 and 12 connecting lines L2, but it is not limited thereto. In addition, in some embodiments, each touch electrode in the touch electrode array 120 is electrically connected to the touch multiplex circuit 140 through a single wire in the connection line L3. In other words, as shown in FIG. 1A, the touch electrode array 120 includes a total of 6n by n touch electrodes, and the connecting line L3 includes 6n by n independent wires.

In operation, the driving circuit 110 is used to output a plurality of first control signals to the control signal generating circuit 130. The control signal generating circuit 130 is used to generate a plurality of second control signals according to the first control signal, and output the second control signals to the touch multiplexing circuit 140. The touch multiplexing circuit 140 is used for outputting a plurality of detection signals to corresponding touch electrodes for touch detection according to the second control signal. Wherein, the number of second control signals is greater than the number of first control signals.

Next, please refer to Figure 1B. FIG. 1B is a schematic diagram showing another touch display device according to some embodiments of the present disclosure. As shown in FIG. 1B, the touch display device 100 further includes a pixel array 150, a gate driving circuit 160, and a switching circuit 170. The pixel array 150 includes a plurality of pixels arranged in an array (as shown by PX in the figure). The gate driving circuit 160 includes a plurality of shift registers (not shown in the figure) connected in series. The switching circuit 170 includes a plurality of switches (not shown in the figure). Structurally, the driving circuit 110 is electrically coupled through the connecting line L4 Gate drive circuit 160. The gate driving circuit 160 is electrically coupled to the pixel array 150. The driving circuit 110 is electrically coupled to the switching circuit 170 through the connecting line L5. The switching circuit 170 is electrically coupled to the contact control electrode array 120. In some embodiments, the touch electrode array 120 and the pixel array 150 may overlap. For example, the touch electrode array 120 can be implemented by common electrodes in the pixel array 150.

In operation, the driving circuit 110 is used to output a plurality of gate control signals to the gate driving circuit 160, and the shift register in the gate driving circuit 160 is used to generate corresponding gate driving signals according to the gate control signals The polar drive signal is output to the pixel array 150 for display. In addition, the driving circuit 110 is used for outputting a selection signal to the switching circuit 170, and the switching circuit 170 is used for selectively turning on or turning off the internal switch according to the selection signal. Specifically, when the touch display device 100 performs display, the selection signal is at the on level so that the switching circuit 170 turns on the internal switch to output the common voltage level to the touch electrode array 120. When the touch display device 100 performs touch detection, the selection signal is at the off level so that the switching circuit 170 turns off the internal switch.

In some embodiments, the gate drive circuit 160 can be implemented by gate on array (GOA) technology. It is worth noting that, in some embodiments, the touch display device 100 further includes a source driving circuit, a data multiplexing circuit, and/or other control circuits. Figures 1A and 1B are only examples for convenience of explanation, and are not intended to limit the case.

In some embodiments, some pins included in the driving circuit 110 are shown in Table 1 below.

For example, the sixth pin is connected to the connecting line L5 in FIG. 1B to provide a selection signal to the switching circuit 170. The 7th to 16th pins are connected to the connecting line L4 in FIG. 1B for providing signals to the gate driving circuit 160. The 19th to 24th pins are used to provide signals to the data multiplex circuit or source drive circuit. Among them, the remaining pins 1 to 5 can provide signals required by the touch multiplex circuit 140. In this embodiment, the second to fifth pins are connected to the connecting line L1 in Figure 1A to provide the first control signal to the control signal generating circuit 130, and the control signal generating circuit 130 is based on the first control signal The second control signal whose quantity is greater than the quantity of the first control signal is generated to output to the touch multiplex circuit 140. In this way, the control signal generation circuit 130 can output the control signal required by the touch multiplex circuit 140 with a limited number of pins.

How the control signal generating circuit 130 generates the second control signal will be described in the following paragraphs. First, how the touch multiplexing circuit 140 outputs the detection signal to the corresponding touch electrode according to the second control signal for touch detection. Measurement. Please refer to Figure 2 and Figure 3 together. FIG. 2 is a schematic diagram showing a touch electrode array 120 according to some embodiments of the present disclosure. As shown in FIG. 2, the touch electrode array 120 includes six areas A1 to A6. Specifically, the first to n touch electrodes in the touch electrode columns C1 to Cn are located in the area A1. The n+1 to 2nth touch electrodes in the touch electrode rows C1 to Cn are located in the area A2. By analogy, the 5n+1 to 6nth touch electrodes in the touch electrode rows C1 to Cn are located in the area A6.

FIG. 3 is a schematic diagram of a touch multiplex circuit 140 according to some embodiments of the present disclosure. As shown in FIG. 3, the touch multiplexing circuit 140 includes a plurality of touch multiplexing units 140a-140n. Structurally, the touch multiplexing units 140a~140n are respectively connected to the output terminals Rx1~Rxn in the driving circuit 110. The touch multiplex units 140a to 140n are connected to the control signal generating circuit 130 through 12 wires (such as the connecting line L2 in Figure 1A). And, the touch multiplexing units 140a to 140n are respectively connected to the touch electrodes P[1] to P[6n] of the first touch electrode column C1 in the touch electrode array 120.

For example, in this embodiment, the touch multiplexer units 140a to 140n use a one-to-six multiplexer as an illustrative example. Therefore, each touch multiplexing unit is connected to 6 touch electrodes. For example, the touch multiplexing unit 140a is connected to the touch electrodes P[1], P[n+1], P[2n+1], P[3n+1], P[ respectively located in the areas A1 to A6. 4n+1], P[5n+1]. The touch multiplexing unit 140b is connected to the touch electrodes P[2], P[n+2], P[2n+2], P[3n+2], P[4n+ located in the areas A1~A6, respectively. 2], P[5n+2]. By analogy, the touch multiplex unit 140n is connected to the touch electrodes P[n], P[2n], P[3n], P[4n], P[5n], P located in the areas A1~A6. [6n].

It is worth noting that, in order to simplify the drawing, the touch electrodes connected to the touch multiplex units 140a to 140n are only marked with symbols in Figure 3. And, although the touch electrode array 120 shown in FIG. 2 is arranged in a grid matrix, it is not intended to limit the case, and those skilled in the art can design and adjust according to actual needs. In addition, for simplicity of drawing, only the touch multiplexing units 140a to 140n connected to the first touch electrode column C1 are shown in FIG. 3. The touch multiplexing units connected to the other touch electrode rows C2 to Cn in Figure 2 are similar to the touch multiplexing units 140a to 140n in Figure 3, and will not be repeated here.

In operation, the touch multiplexer units 140a~140n are used to receive the second control signals S[1]~S[6] and S[1]G~S[6]G output by the control signal generating circuit 130, and used to The second control signals S[1]~S[6] and S[1]G~S[6]G selectively output the signals transmitted by the output terminals Rx1~Rxn of the driving circuit 110 to the corresponding touch electrodes.

Specifically, please refer to Figures 4 and 5 together. FIG. 4 is a schematic diagram of a touch multiplexing unit 140a according to some embodiments of the present disclosure. Fig. 5 is a schematic diagram showing the waveforms of a second control signal S[1]~S[6], S[1]G~S[6]G and the touch electrode P[1 according to some embodiments of the present disclosure ]~P[6n] The operation sequence diagram. As shown in Fig. 4, the one-to-six touch multiplex unit 140a includes transistors M1~M6, M1'~M6'. Transistors M1~M6, M1'~M6' respectively receive corresponding second control signals S[1]~S[6], S[1]G~S[6]G from the control signal generating circuit 130, and according to The corresponding second control signals S[1]~S[6], S[1]G~S[6]G are selectively turned on or off. Among them, the second control signals S[1]~S[6] and S[1]G~S[6]G are the corresponding reverse signals. When the second control signal S[1]~S[6] is at the conduction level (The second control signal S[1]G~S[6]G is at the off level), the transistors M1~M6 are turned on to output the signal transmitted by the output terminal Rx1 of the driving circuit 110 to the corresponding touch electrode . When the second control signal S[1]G~S[6]G is at the turn-on level (the second control signal S[1]~S[6] is at the turn-off level), the transistors M1'~M6' are turned on In order to provide the reset signal Sgd to the corresponding touch electrode.

In further detail, as shown in FIG. 5, a period Tf includes a display period Td and a touch detection period Tt. The touch detection period Tt includes the reset period Tr. During the display period Td, the second control signal S[1]~S[6] is at the turn-on level (such as high voltage level), and the second control signal S[1]G~S[6]G is at the turn-off level Bit (such as low voltage level), the transistors M1~M6 are turned on and the transistors M1'~M6' are turned off. Therefore, the driving circuit 110 will provide the common voltage level Vcom to the touch electrodes P[1]~P[6n] via the touch multiplexing unit 140a through the output terminal Rx1. As shown in Figure 5, during the Td period, the touch electrodes P[1]~P[n], P[n+1]~P[2n]...P[5n+1]~P[6n] are at the common voltage Level Vcom.

During the reset period Tr, the second control signal S[1]~S[6] is at the turn-off level (such as low voltage level), and the second control signal S[1]G~S[6]G is at the on-state The level (such as high voltage level) makes the transistors M1~M6 turn off and the transistors M1'~M6' turn on. Therefore, the touch multiplexing unit 140a outputs the reset signal Sgd to the corresponding touch electrode. As shown in Figure 5, during the Td period, the touch electrodes P[1]~P[n], P[n+1]~P[2n]...P[5n+1]~P[6n] are in reset The voltage level is Vgd.

During the touch detection period Tt, the second control signal S[1]~S[6] are in turn-on level (such as high voltage level) in sequence, and the second control signal S[1]G~S[6]G They are located at the turn-off level (for example, low voltage level) in order, so that the transistors M1~M6 are turned on in sequence and the transistors M1'~M6' are turned off in sequence. Therefore, the driving circuit 110 can sequentially provide detection signals to the touch electrodes for touch detection through the touch multiplexing unit 140a through the output terminal Rx1. As shown in Fig. 5, during t1, the touch electrodes P[1]~P[n] are used to receive the detection voltage Sen. Then, the touch electrodes P[n+1]~P[2n] are used to receive the detection voltage Sen. And so on, until the touch electrodes P[5n+1]~P[6n] are used to receive the detection voltage Sen.

In this way, through the second control signals S[1]~S[6], S[1]G~S[6]G as shown in Figure 5, the touch multiplex unit 140a can be The detected signals output sequentially to the corresponding touch electrodes P[1]~P[6n] for touch detection. In addition, the operation of the touch multiplexing unit 140b~140n in Figure 3 is similar to that of the touch multiplexing unit 140a, and will not be repeated here.

For how to generate the second control signal S[1]~S[6], S[1]G~S[6]G, please refer to Figure 6. FIG. 6 is a schematic diagram of a control signal generating circuit 130 according to some embodiments of the present disclosure. As shown in FIG. 6, the control signal generating circuit 130 includes a plurality of shift register units TPSR[1]~TPSR[6]. Structurally, the shift temporary storage units TPSR[11~TPSR[6] are connected in series with each other. Operationally, the shift register units TPSR[1]~TPSR[6] are used to output the corresponding second control signals S[1]~S[6], S[1]G~S[6]G.

Specifically, the shift register unit TPSR[1] is used for outputting corresponding second control signals S[1] and S[1]G according to the start signal TP_STV and the clock signal TP_CK. The shift register unit TPSR[2] is used as the start signal according to the second control signal S[1] output by the previous stage shift register unit TPSR[1], and output according to the start signal and the clock signal TP_XCK Corresponding second control signal S[2] and S[2]G. By analogy, the shift register unit TPSR[6] is used as the start signal according to the second control signal S[5] output by the previous stage shift register unit TPSR[5], and according to the start signal and time The pulse signal TP_XCK outputs the corresponding second control signals S[6] and S[6]G. In other words, the shift register unit uses the second control signal output by itself as the start signal of the subsequent stage shift register unit.

In addition, the shift register units TPSR[1]~TPSR[6] are used to reset the corresponding second control signal according to the end signal. Specifically, the shift register unit TPSR[6] is used to reset the second control signals S[6] and S[6]G according to the end signal TP_END transmitted by the driving circuit 110. The shift register unit TPSR[1] is used as the end signal according to the second control signal S[2] output by the shift register unit TPSR[2] of the subsequent stage. By analogy, the shift register unit TPSR[5] is used as the end signal according to the second control signal S[6] output by the shift register unit TPSR[6] of the subsequent stage. In other words, the shift register unit uses the second control signal output by itself as the end signal of the previous stage shift register unit.

In this way, by the shift register units TPSR[1]~TPSR[6] connected in series in the control signal generating circuit 130, the first control signal (such as TP_STV, TP_CK, TP_XCK, TP_END) generates a large number of second control signals (such as: S[1]~S[6], S[1]G~S[6]G).

For further details, please refer to Figure 7. FIG. 7 is a schematic diagram of a shift register unit TPSR[k] according to some embodiments of the present disclosure. In some embodiments, the shift register units TPSR[1] to TPSR[6] in Fig. 6 can be implemented by the shift register units TPSR[k] in Fig. 7. It’s worth noting that the lowercase English request in the component number or signal number used here The quote k refers to any unspecified component or signal in the component group or signal group. In other words, the object referred to by the component number TPSR[k] is an unspecified arbitrary shift temporary storage unit TPSR[1]~TPSR[6], and the object referred to by the signal number S[k] is the second Among the control signals S[1]~S[6], the second control signal corresponding to the shift register unit TPSR[k].

As shown in Fig. 7, the shift register unit TPSR[k] includes a shift register circuit SRc and an inverter circuit Inv. The shift register circuit SRc is coupled to the driving circuit 110 for receiving the start signal TP_STV, the end signal TP_END, the clock signal TP_CK or TP_XCK from the driving circuit 110, and is used for outputting the corresponding second control signal S[k]. The reverse circuit Inv is coupled to the shift register circuit SRc, and is used for receiving the second control signal S[k] from the shift register circuit SRc, and is used for outputting a corresponding reverse control signal according to the second control signal S[k] S[k]G.

Specifically, the shift register circuit SRc includes a start circuit 132, an end circuit 134, a pull-up circuit 136, a pull-down circuit 138, and a node Q. In operation, the start circuit 132 is used to output a high voltage level to the node Q according to the start signal TP_STV. The end circuit 134 is used for pulling the node Q to a low voltage level according to the end signal TP_END. The pull-up circuit 136 is used for outputting the second control signal S[k] of the conduction level according to the voltage level of the node Q and the clock signal TP_CK or TP_XCK. The pull-down circuit 138 is used to reset the second control signal S[k] to the off level.

The shift register circuit SRc includes transistors T1 to T10 and resistor R1. Wherein, the start circuit 132 includes a transistor T1. The termination circuit 134 includes a transistor T2. The pull-up circuit 136 includes transistors T8 and T9. The pull-down circuit 138 includes transistors T4, T5, T6, and T10.

The first terminal of the transistor T1 is coupled to the high reference voltage level VGH. Electricity The second end of the crystal T1 is coupled to the node Q. The control terminal of the transistor T1 is used to receive the start signal TP_STV, and is used to turn on the start signal TP_STV to output a high voltage level to the node Q.

The first end of the transistor T2 is coupled to the second end of the transistor T1 and the node Q. The second end of the transistor T2 is used to receive the selection signal TPSW (as shown in Table 1 in the above paragraph). The control terminal of the transistor T2 is used to receive the end signal TP_END, and is used to pull the node Q to a low voltage level according to the end signal TP_END.

The first terminal and the control terminal of the transistor T3 are coupled to the high reference voltage level VGH. The second end of the transistor T3 is coupled to the first end of the resistor R1. The first end of the transistor T4 is coupled to the second end of the resistor R1. The second end of the transistor T4 is used for receiving the selection signal TPSW. The control terminal of the transistor T4 is coupled to the node Q for selectively turning on or off according to the voltage level of the node Q.

The first end of the transistor T5 is coupled to the node Q. The control terminal of the transistor T5 is coupled to the second terminal of the resistor R1. The first end of the transistor T6 is coupled to the second end of the transistor T5. The control terminal of the transistor T6 is coupled to the second terminal of the resistor R1. The second end of the transistor T6 is used to receive the selection signal TPSW.

The first end of the transistor T7 is coupled to the node Q. The control terminal of the transistor T7 is coupled to the high reference voltage level VGH for outputting the voltage level of the node Q. The first end of the transistor T8 is used to receive the clock signal TP_CK or TP_XCK. The control terminal of the transistor T8 is coupled to the second terminal of the transistor T7 for receiving the voltage level of the node Q. The first end of the transistor T9 is coupled to the second end of the transistor T8. The control terminal of the transistor T9 is coupled to the second terminal of the transistor T7 for receiving the voltage level of the node Q, and is used for selectively turning on the voltage level of the node Q to pass the transistor The second terminal of T9 outputs the second control signal S[k].

The first end of the transistor T10 is coupled to the second end of the transistor T9. The second end of the transistor T10 is used to receive the selection signal TPSW. The control terminal of the transistor T10 is coupled to the second terminal of the resistor R1. The transistor T10 is used to reset the second control signal S[k] to the off level.

In addition, in the embodiment of FIG. 7, the inverter circuit Inv is used to output the inverse control signal S[k]G according to the voltage level of the second terminal of the resistor R2. The inverter circuit Inv includes transistors T11, T12 and resistor R2. The first terminal and the control terminal of the transistor T11 are coupled to the high reference voltage level VGH. The second end of the transistor T11 is coupled to the first end of the resistor R2. The first end of the transistor T12 is coupled to the second end of the resistor R2. The second end of the transistor T12 is used to receive the selection signal TPSW. The control terminal of the transistor T12 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc.

Next, please refer to Figure 7 and Figure 8 together. FIG. 8 is a schematic diagram of a signal timing diagram of a control signal generating circuit 130 according to some embodiments of the present disclosure. As shown in Figure 8, during the display period Td, the selection signal TPSW, the start signal TP_STV, the end signal TP_END, the clock signals TP_CK and TP_XCK are at high voltage levels, so that the transistors T1, T2, T3, T4, T7, T8, T9, T11, and T12 are turned on and transistors T5, T6, and T10 are turned off. Therefore, the node Q is pulled up to a high voltage level, the second control signal S[k] outputs a high voltage level, and the second control signal S[k]G outputs a low voltage level. As a result, as shown in Figures 4 and 5, when the second control signals S[1]~S[6] are all high voltage levels and the second control signals S[1]G~S[6] When G is the low voltage level, the transistors M1~M6 are all turned on and the transistors M1'~M6' are all turned off, so that the driving circuit 110 can provide the common voltage level Vcom through the output terminal (such as Rx1) Touch electrodes.

Please continue to refer to Figures 7 and 8. During the reset period Tr in the touch detection period Tt, the selection signal TPSW turns to a low voltage level, the start signal TP_STV is at a high voltage level and the end signal TP_END is at a low level. The voltage level makes the transistors T1, T3, T4, and T7 turn on and the transistors T2, T5, T6, T10 turn off. Therefore, the node Q is pulled up to a high voltage level, so that the transistors T8 and T9 are turned on. Then, during the period t1 in the touch detection period Tt, since the clock signal TP_CK is converted to the high voltage level, the transistors T8 and T9 output the second high voltage level according to the high voltage level clock signal TP_CK. Control signal S[1]. In addition, since the second control signal S[1] is at a high voltage level and the transistors T11 and T12 are turned on, the second control signal S[1]G is output at a low voltage level.

At the same time, during the period t1 of the touch detection period Tt, the second control signal S[1] at the high voltage level will be used as the start signal of the next stage shift register unit TPSR[2], so that the shift is temporarily The node Q of the memory cell TPSR[2] is pulled up to a high voltage level. Similarly, in the period t2 of the touch detection period Tt, since the clock signal TP_XCK is converted to a high voltage level, the shift register unit TPSR[2] outputs a high voltage according to the clock signal TP_XCK of the high voltage level The second control signal S[2] of the level.

In addition, during the period t2 of the touch detection period Tt, the second control signal S[2] at the high voltage level will be used as the end signal of the previous shift register unit TPSR[1] to turn on the transistor T2 . At this time, since the transistors T2, T3, T5, T6, T7, and T10 are turned on and the transistors T1, T4 are turned off, the voltage level of the node Q will be pulled down to a low voltage level. When the voltage level of the node Q is at the low voltage level, the transistors T8 and T9 are turned off, making the second control signal The number S[1] is reset to the low voltage level. In addition, since the second control signal S[1] is at a low voltage level, the transistor T12 is turned off and the transistor T11 is turned on, so the second control signal S[1]G is output at a high voltage level.

In other words, each stage of the shift register unit TPSR[k] receives the second control signal S[k-1] of the previous stage of shift register unit TPSR[k-1] as the start signal, so that the shift register unit The node Q of TPSR[k] is charged. In the corresponding period tk, the second control signal S[k] output by the shift register unit TPSR[k] turns to a high voltage level. Until the shift register unit TPSR[k] receives the second control signal S[k+1] of the next stage shift register unit TPSR[k+1] as the end signal, the shift register unit TPSR[k ] The node Q is pulled down to reset the second control signal S[k] to the low voltage level.

In this way, by controlling the multiple shift register units TPSR[1]~TPSR[6] connected in series in the signal generating circuit 130, the second control signal S[1] required by the touch multiplex circuit 140 can be generated. ]~S[6], S[1]G~S[6]G.

In some other embodiments, the reverse circuit Inv in the shift register unit TPSR[k] includes different circuits. Please refer to Figure 9. FIG. 9 is a schematic diagram of another shift register unit TPSR[k] according to other embodiments of the present disclosure. In the embodiment shown in Fig. 9, elements similar to those in Fig. 7 are represented by the same element symbols, and their operations have been described in the previous paragraphs, so they will not be repeated here. Compared with FIG. 7, in the embodiment of FIG. 9, the control terminal of the transistor T11 in the inverter circuit Inv is coupled to the second terminal of the resistor R1. In this way, the transistor T11 is turned on only when the node Q is at a low voltage level, instead of being in a constant-on state, which can slow down the speed of component degradation. In addition, in this embodiment, since the transistor T11 The control terminal of is to receive the voltage level of the second terminal of the resistor R1. Therefore, when the reverse control signal S[k]G output by the inverter circuit Inv is at a high voltage level, it will be close to the high reference voltage level VGH. Will not produce a critical voltage drop. For example, if the high reference voltage level VGH is about 8.5V, the high-level reverse control signal S[k]G in the embodiment in Figure 7 is about 8.5V minus the threshold voltage of the transistor T11, and Figure 9 In this embodiment, the high-level reverse control signal S[k]G is about 8.5V.

Please refer to Figure 10. FIG. 10 is a schematic diagram of another shift register unit TPSR[k] according to other embodiments of the present disclosure. In the embodiment shown in FIG. 10, elements similar to those in FIG. 7 are represented by the same element symbols, and their operations have been described in the previous paragraphs, so they will not be repeated here. Compared with Figure 7, in the embodiment of Figure 10, the control terminal of the transistor T11 in the inverter circuit Inv is coupled to the signal GOFF provided by the 12th pin in Table 1, and the second terminal of the transistor T12 It is coupled to the low reference voltage level VSS. Among them, the signal GOFF is the final stage end signal among the gate control signals provided by the driving circuit 110 to the gate driving circuit 160. The voltage level of the signal GOFF is as shown in FIG. 11. During the display period Td is the low voltage level, and during the touch detection period Tt is the high voltage level. In addition, similar to the embodiment in Figure 9, since the control terminal of the transistor T11 receives the voltage level of the signal GOFF, the inverse control signal S[k]G output by the inverter circuit Inv is at the high voltage level. At this time, it will be close to the high reference voltage level VGH without generating a critical voltage drop.

Please refer to Figure 12. FIG. 12 is a schematic diagram of another shift register unit TPSR[k] according to other embodiments of the present disclosure. In the embodiment of Fig. 12, the elements similar to those in Fig. 7 are given the same symbol table As shown, its operation has been explained in the previous paragraph, so I will not repeat it here. Compared with FIG. 7, in the embodiment of FIG. 12, the inverter circuit Inv includes transistors T13, T14, T15, and T16. The first terminal and the control terminal of the transistor T13 are coupled to the high reference voltage level VGH. The first end of the transistor T14 is coupled to the second end of the transistor T13. The control terminal of the transistor T14 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc. The second end of the transistor T14 is used for receiving the selection signal TPSW. The first terminal of the transistor T15 is coupled to the high reference voltage level VGH. The control terminal of the transistor T15 is coupled to the second terminal of the transistor T13. The first end of the transistor T16 is coupled to the second end of the transistor T15. The control terminal of the transistor T16 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc. The second end of the transistor T16 is used to receive the selection signal TPSW. In this embodiment, the inverter circuit Inv is used to output the inverse control signal S[k]G according to the voltage level of the second terminal of the transistor T15.

As a result, in the embodiment in Figure 12, the reverse signal is generated by the transistor T13, T14, and T16 being turned on and the transistor T15 being turned off. Therefore, the reverse control signal S[ k] When G is at a low voltage level, it will be close to the low voltage level of the selection signal TPSW without being pulled up by the voltage divider value. For example, if the low-voltage level of the selection signal TPSW is about -8.0V, the low-level reverse control signal S[k]G in the embodiment in Figure 7 is about -8.0V plus a voltage division value, and The low-level reverse control signal S[k]G in the embodiment in Figure 12 is about -8.0V.

Please refer to Figure 13. FIG. 13 is a schematic diagram of another shift register unit TPSR[k] according to other embodiments of the present disclosure. In the embodiment in FIG. 13, elements similar to those in FIG. 7 are denoted by the same element symbols, and their operations have been described in the previous paragraphs, and will not be repeated here. And picture 7 By comparison, in the embodiment shown in Figure 13, the inverter circuit Inv includes transistors T17 and T18. The first terminal of the transistor T17 is coupled to the high reference voltage level VGH. The control terminal of the transistor T17 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc. The first end of the transistor T18 is coupled to the second end of the transistor T17. The control terminal of the transistor T18 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc. The second terminal of the transistor T18 is coupled to the low reference voltage level VSS. In this embodiment, the inverter circuit Inv is used to output the inverse control signal S[k]G according to the voltage level of the second terminal of the transistor T17.

In this way, in the embodiment in Figure 13, the transistor T17 is only turned on when the shift register circuit SRc outputs the high-level second control signal S[k], instead of being in a constant-on state, which can slow down component degradation speed. In addition, similar to the embodiment in Figure 12, since the transistors T17 and T18 do not generate the pull-down voltage level through the resistor R2, the inverse control signal S[k]G output by the inverter circuit Inv is at a low voltage level. At this time, it will be close to the low reference voltage level VSS without being pulled up by the voltage divider value.

It is worth noting that although in the embodiments of the present disclosure, only one-to-six touch multiplexer units are used as an example, those skilled in the art have different signal numbers and types of multiplexers according to actual needs. The design adjustment is not used to limit the case.

In addition, it should be noted that, in the case of no conflict, the features and circuits in the various drawings, embodiments, and embodiments of the present disclosure can be combined with each other. The circuit shown in the figure is only an example, and is simplified to make the description concise and easy to understand, and is not intended to limit the case. In addition, the various devices, units, and components in the foregoing embodiments can be implemented by various types of digital or analog circuits. Now, it can also be realized by different integrated circuit chips, or integrated into a single chip. The foregoing is only an example, and the present disclosure is not limited thereto.

To sum up, in this case, by applying the above-mentioned various embodiments, the display function and the touch detection function in the same area can be realized by sharing the common electrode through the division in time sequence, without adding additional components. In addition, by dividing the electrode array into different regions, different regions can simultaneously perform display or touch detection respectively during the same period. It achieves the addition of touch function without taking up the original pixel charging time and will not affect the charging efficiency.

Although the content of this disclosure has been disclosed in the above embodiments, it is not intended to limit the content of this disclosure. Those with ordinary knowledge in the technical field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this The scope of protection of the disclosed content shall be subject to the scope of the attached patent application.

100‧‧‧Touch display device

110‧‧‧Drive circuit

120‧‧‧Touch electrode array

130‧‧‧Control signal generating circuit

140‧‧‧Touch Multiplex Circuit

P[1]~P[6n]‧‧‧Touch electrode

C1~Cn‧‧‧Touch electrode array

L1, L2, L3‧‧‧Connecting line

Claims (9)

A touch display device includes: a touch electrode array including a plurality of touch electrodes; a driving circuit for outputting a plurality of first control signals; a control signal generating circuit electrically coupled to the driving circuit, and To generate a plurality of second control signals according to the first control signals; and a touch multiplex circuit electrically coupled to the touch electrodes and the control signal generating circuit for outputting according to the second control signals A plurality of detection signals are sent to the touch electrodes for touch detection, wherein the number of the second control signals is greater than the number of the first control signals, and the control signal generating circuit includes a plurality of shift register units , The shift register units are connected in series with each other, the shift register units are used to output the corresponding second control signals, and each of the shift register units includes: a shift register circuit, It is used to output a corresponding one of the second control signals according to a start signal and a clock signal; and a reverse circuit is used to output a reverse control signal according to the corresponding one of the second control signals. The touch display device according to claim 1, wherein one of the shift register circuits outputs the corresponding second control signal as the start signal of the shift register circuit of the subsequent stage, and outputs The corresponding second control signal is used as an end signal of the shift register circuit of the previous stage. The touch display device according to claim 1, wherein the shift The bit temporary storage circuit includes: a start circuit for outputting a high voltage level to a node according to the start signal; an end circuit for pulling the node to a low voltage level according to an end signal; A pull-down circuit for outputting the second control signal at a turn-on level according to the voltage level of the node and the clock signal; and a pull-down circuit for resetting the second control signal to a turn-off level . The touch display device according to claim 1, wherein the reverse circuit includes: a resistor; a first transistor, a first end of the first transistor is coupled to a high reference voltage level, the first A second end of the transistor is coupled to a first end of the resistor; and a second transistor, a first end of the second transistor is coupled to a second end of the resistor, and a second end of the second transistor A control terminal is coupled to the shift register circuit and used for receiving the second control signal output from the shift register circuit, and the reverse circuit is used for outputting the reverse direction according to the voltage level of the second terminal of the resistor Control signal. The touch display device according to claim 4, wherein a control terminal of the first transistor is coupled to the first terminal of the first transistor, and the second transistor A second end of the transistor is coupled to a selection signal. The touch display device according to claim 4, wherein a control terminal of the first transistor is coupled to the shift register circuit, and a second terminal of the second transistor is coupled to a selection signal. The touch display device according to claim 4, wherein a control terminal of the first transistor is coupled to a gate drive end signal, and a second terminal of the second transistor is coupled to a low reference voltage level. The touch display device according to claim 1, wherein the reverse circuit includes: a third transistor, a first terminal and a control terminal of the third transistor are coupled to a high reference voltage level; Four transistors, a first end of the fourth transistor is coupled to a second end of the third transistor, and a control end of the fourth transistor is coupled to the shift register circuit and used for receiving from the shift register For the second control signal output by the bit register circuit, a second end of the fourth transistor is coupled to a selection signal; a fifth transistor, a first end of the fifth transistor is coupled to the high reference voltage Level, a control end of the fifth transistor is coupled to the second end of the third transistor; and a sixth transistor, a first end of the sixth transistor is coupled to the fifth transistor A second terminal, a control terminal of the sixth transistor is coupled to the shift register circuit and used for receiving the second control signal output from the shift register circuit, A second end of the sixth transistor is coupled to the selection signal, and the reverse circuit is used for outputting the reverse control signal according to the voltage level of the second end of the fifth transistor. The touch display device according to claim 1, wherein the reverse circuit includes: a seventh transistor, a first end of the seventh transistor is coupled to a high reference voltage level; and an eighth transistor , A first end of the eighth transistor is coupled to a second end of the seventh transistor, a control end of the eighth transistor and a control end of the seventh transistor are coupled to the shift temporary The storage circuit is used for receiving the second control signal output from the shift register circuit, a second end of the eighth transistor is coupled to a low reference voltage level, and the inverter circuit is used for receiving the second control signal output from the shift register circuit. The voltage level of the second terminal of the crystal outputs the reverse control signal.

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