CN110989868A

CN110989868A - Touch control display device

Info

Publication number: CN110989868A
Application number: CN201911258812.5A
Authority: CN
Inventors: 张哲嘉; 李家圻; 庄铭宏; 钟俊甫; 陈政德; 刘贵文; 杜宗谚
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-05-02
Filing date: 2019-12-10
Publication date: 2020-04-10
Anticipated expiration: 2039-12-10
Also published as: TWI709886B; CN110989868B; TW202042025A

Abstract

The invention discloses a touch display device which comprises a touch electrode array, a driving circuit, a control signal generating circuit and a touch multiplex circuit. The touch electrode array comprises a plurality of touch electrodes. The driving circuit is used for outputting a plurality of first control signals. The control signal generating circuit is electrically coupled to the driving circuit and used for generating a plurality of second control signals according to the first control signal. The touch multiplex circuit is electrically coupled to the touch electrode and the control signal generating circuit and is used for outputting a plurality of detection signals to the touch electrode according to the second control signal to perform touch detection. Wherein the number of second control signals is greater than the number of first control signals.

Description

Touch control display device

Technical Field

The present invention relates to a touch display device, and more particularly, to a touch display device with a touch multiplexing circuit.

Background

With the development of technology, the demand of touch display devices is becoming more and more extensive. This is useful for applications requiring multi-chip architectures, since moving the circuitry in the wafer to Glass (Glass) processing can reduce wafer cost. However, since the number of pins (pins) of the chip circuit moved into the glass process is limited, it is impossible to support the operation of the multiplexing circuit requiring a plurality of control signals.

Therefore, it is a design consideration and challenge to output the control signals required by the multiplexing circuit under the condition of limited pin number.

Disclosure of Invention

An embodiment of the invention relates to a touch display device, which includes a touch electrode array, a driving circuit, a control signal generating circuit and a touch multiplexing circuit. The touch electrode array comprises a plurality of touch electrodes. The driving circuit is used for outputting a plurality of first control signals. The control signal generating circuit is electrically coupled to the driving circuit and used for generating a plurality of second control signals according to the first control signal. The touch multiplex circuit is electrically coupled to the touch electrode and the control signal generating circuit and is used for outputting a plurality of detection signals to the touch electrode according to the second control signal to perform touch detection. Wherein the number of second control signals is greater than the number of first control signals.

Drawings

Fig. 1A is a schematic diagram illustrating a touch display device according to some embodiments of the invention.

Fig. 1B is a schematic diagram illustrating another touch display device according to some embodiments of the invention.

Fig. 2 is a schematic diagram illustrating a touch electrode array according to some embodiments of the invention.

Fig. 3 is a schematic diagram of a touch multiplexing circuit according to some embodiments of the invention.

Fig. 4 is a schematic diagram illustrating a touch multiplexing unit according to some embodiments of the invention.

FIG. 5 is a timing diagram illustrating operations of control signals and touch electrodes according to some embodiments of the invention.

FIG. 6 is a schematic diagram of a control signal generating circuit according to some embodiments of the invention.

FIG. 7 is a diagram illustrating a shift register unit according to some embodiments of the present invention.

FIG. 8 is a signal timing diagram illustrating a control signal generating circuit according to some embodiments of the present invention.

FIG. 9 is a diagram illustrating another shift register unit according to some other embodiments of the present invention.

FIG. 10 is a diagram illustrating another shift register unit according to some other embodiments of the present invention.

FIG. 11 is a signal timing diagram illustrating another shift register unit according to some other embodiments of the present invention.

FIG. 12 is a diagram illustrating another shift register unit according to some other embodiments of the present invention.

FIG. 13 is a diagram illustrating another shift register unit according to some other embodiments of the present invention.

Wherein, the reference numbers:

100: touch control display device

110: driving circuit

120: touch electrode array

130: control signal generating circuit

132: start circuit

134: termination circuit

136: pull-up circuit

138: pull-down circuit

140: touch control multiplex circuit

140a to 140 n: touch multiplex unit

150: pixel array

160: gate drive circuit

170: switching circuit

P [1], P [2] to P [ n ], P [ n +1], P [ n +2] to P [2n ] … P [6n ]: touch electrode

C1-Cn: touch electrode array

L1, L2, L3, L4, L5: connecting wire

PX: pixel

A1-A6: region(s)

Rx 1-Rx 6: output end

S1-S6, S1G-S6G, S k, Sk G: the second control signal

Sgd: reset signal

M1-M6, M1 '-M6': transistor with a metal gate electrode

Tf, Td, Tr, Tt, t 1-t 6: period of time

Vcom: common voltage level

Vgd: reset voltage level

Sen: detecting voltage

TPSR [1] to TPSR [6], TPSR [ k ]: shift temporary storage unit

SRc: shift register circuit

Inv: inverting circuit

T1-T18: transistor with a metal gate electrode

R1, R2: resistance (RC)

Q: node point

TP _ CK, TP _ XCK: clock signal

TP _ STV, S [ k-1 ]: initial signal

TP _ END, S [ k +1 ]: end signal

TPSW: selection signal

VGH: high reference voltage level

VSS: low reference voltage level

GOFF: end of gate drive signal

Detailed Description

The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are only for explaining the present invention and not for limiting the present invention, and the description of the structural operation is not for limiting the execution sequence thereof, and any structure obtained by recombining the elements and having equivalent functions is included in the scope of the present invention. Moreover, the drawings are for illustrative purposes only and are not drawn to scale in accordance with established standards and practice in the industry, and the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. In the following description, the same elements will be described with the same reference numerals for ease of understanding.

The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in the art, in the disclosure herein and in the claims, unless otherwise indicated. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the present disclosure.

As used herein, the terms "comprising," having, "and the like are open-ended terms that mean" including, but not limited to. Further, as used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

When an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "connected" or "coupled" may also be used to indicate that two or more elements are in mutual engagement or interaction. Moreover, although terms such as "first," "second," …, etc., may be used herein to describe various elements, these terms are used merely to distinguish one element or operation from another element or operation described in similar technical terms. Unless the context clearly dictates otherwise, the terms do not specifically refer or imply an order or sequence nor are they intended to limit the invention.

For convenience of illustration, the circuits and elements of the touch display device 100 of the invention are respectively shown in fig. 1A and fig. 1B. Please refer to fig. 1A. Fig. 1A is a schematic diagram illustrating a touch display device 100 according to some embodiments of the invention. As shown in fig. 1A, the touch display device 100 includes a driving circuit 110, a touch electrode array 120, a control signal generating circuit 130, and a touch multiplexing circuit 140. The touch electrode array 120 includes a plurality of touch electrodes arranged in an array. In the embodiment of FIG. 1A, touch electrode array 120 includes n touch electrode columns C1-Cn, each including 6n touch electrodes. For example, the first touch electrode row C1 includes touch electrodes P [1] P [6n ]. Wherein n is a positive integer greater than 1.

Structurally, the driving circuit 110 is electrically coupled to the control signal generating circuit 130. The control signal generating circuit 130 is electrically coupled to the touch multiplexing circuit 140. The touch multiplexing circuit 140 is electrically coupled to the touch electrodes in the touch electrode array 120. Specifically, the driving circuit 110 is electrically coupled to the control signal generating circuit 130 through the connection line L1. The control signal generating circuit 130 is electrically coupled to the touch multiplexing circuit 140 through a connection line L2. The touch multiplexing circuit 140 is electrically coupled to the touch electrodes of the touch electrode array 120 through a connection line L3.

In some embodiments, the number of connecting lines L1 is less than the number of connecting lines L2. For example, the connecting lines L1 may be 4 connecting lines L2 may be 12 connecting lines, but not limited thereto. In some embodiments, each touch electrode in the touch electrode array 120 is electrically connected to the touch multiplexing circuit 140 through a single wire of the connection line L3. In other words, as shown in fig. 1A, the touch electrode array 120 includes a total of 6n times n touch electrodes, and the connection line L3 includes 6n times n independent conductive lines.

In operation, the driving circuit 110 is configured to output a plurality of first control signals to the control signal generating circuit 130. The control signal generating circuit 130 is configured to generate a plurality of second control signals according to the first control signal, and output the second control signals to the touch multiplexing circuit 140. The touch multiplexing circuit 140 is configured to output a plurality of detection signals to corresponding touch electrodes according to the second control signal for touch detection. The number of the second control signals is larger than that of the first control signals.

Please refer to fig. 1B. Fig. 1B is a schematic diagram illustrating another touch display device according to some embodiments of the invention. As shown in fig. 1B, the touch display device 100 further includes a pixel array 150, a gate driving circuit 160 and a switching circuit 170. The pixel array 150 includes a plurality of pixels (shown as PX in the figure) arranged in an array. The gate driving circuit 160 includes a plurality of shift registers (not shown) connected in series. The switching circuit 170 includes a plurality of switches (not shown). Structurally, the driving circuit 110 is electrically coupled to the gate driving circuit 160 through the connection line L4. The gate driving circuit 160 is electrically coupled to the pixel array 150. The driving circuit 110 is electrically coupled to the switching circuit 170 through a connection line L5. The switching circuit 170 is electrically coupled to the touch electrode array 120. In some embodiments, the touch electrode array 120 and the pixel array 150 may overlap. For example, the touch electrode array 120 may be implemented by a common electrode in the pixel array 150.

In operation, the driving circuit 110 is configured to output a plurality of gate control signals to the gate driving circuit 160, and the shift register in the gate driving circuit 160 is configured to generate corresponding gate driving signals according to the gate control signals and output the gate driving signals to the pixel array 150 for displaying. In addition, the driving circuit 110 is configured to output a selection signal to the switching circuit 170, and the switching circuit 170 is configured to selectively turn on or off the internal switch according to the selection signal. Specifically, when the touch display device 100 displays, the selection signal is at the on level, so that the switching circuit 170 turns on the internal switch to output the common voltage level to the touch electrode array 120. When the touch display device 100 performs touch detection, the selection signal is at the off level to turn off the internal switch by the switching circuit 170.

In some embodiments, the gate driving circuit 160 may be implemented by Gate On Array (GOA) technology. It is noted that, in some embodiments, the touch display device 100 further includes a source driving circuit, a data multiplexing circuit and/or other control circuits. Fig. 1A and 1B are merely examples for convenience of explanation, and are not intended to limit the present disclosure.

In some embodiments, the driving circuit 110 includes some pins as shown in the following table.

Watch 1

For example, the 6 th pin is connected to the connection line L5 in fig. 1B for providing the selection signal to the switching circuit 170. The 7 th to 16 th pins are connected to the connection line L4 in fig. 1B for providing signals to the gate driving circuit 160. The 19 th to 24 th pins are used for providing signals to the data multiplexing circuit or the source driving circuit. Wherein, the remaining 1 st to 5 th pins can provide signals required by the touch multiplexing circuit 140. In the present embodiment, the connection lines L1 in fig. 1A are connected by the 2 nd to 5 th pins to provide the first control signals to the control signal generating circuit 130, and the control signal generating circuit 130 generates the second control signals with the number greater than that of the first control signals according to the first control signals to output to the touch multiplexing circuit 140. In this way, the control signal generating circuit 130 can output the control signal required by the touch multiplexing circuit 140 under the condition of limited number of pins.

How the control signal generating circuit 130 generates the second control signal will be described in the following paragraphs, and how the touch multiplexing circuit 140 outputs the detection signal to the corresponding touch electrode for touch detection according to the second control signal will be described first. Please refer to fig. 2 and fig. 3 together. Fig. 2 is a schematic diagram of a touch electrode array 120 according to some embodiments of the invention. As shown in FIG. 2, the touch electrode array 120 includes 6 areas A1-A6. Specifically, the 1 st to n-th touch electrodes in the touch electrode rows C1 to Cn are located in the area a 1. The (n + 1) th to (2 n) th touch electrodes in the touch electrode rows C1-Cn are located in the area A2. By analogy, the 5n +1 to 6n touch electrodes in the touch electrode rows C1 to Cn are located in the area a 6.

Fig. 3 is a schematic diagram of a touch multiplexing circuit 140 according to some embodiments of the invention. As shown in fig. 3, the touch multiplexing circuit 140 includes a plurality of touch multiplexing units 140a to 140 n. Structurally, the touch multiplexing units 140a to 140n are respectively connected to the output terminals Rx1 to Rxn of the driving circuit 110. The touch multiplexing units 140a to 140n are connected to the control signal generating circuit 130 through 12 wires (e.g., the connection line L2 in fig. 1A). And the touch multiplexing units 140 a-140 n are respectively connected to the touch electrodes P1-P6 n of the first touch electrode row C1 in the touch electrode array 120.

For example, in the present embodiment, the touch multiplexing units 140a to 140n are illustrated as a pair of six multiplexers. Therefore, each touch multiplexing unit is respectively connected to 6 touch electrodes. For example, the touch multiplexing units 140a are connected to the touch electrodes P [1], P [ n +1], P [2n +1], P [3n +1], P [4n +1], and P [5n +1] respectively located in the regions a 1-a 6. The touch multiplexing units 140b are connected to the touch electrodes P2, P n +2, P2 n +2, P3 n +2, P4 n +2, and P5 n +2 in the regions A1-A6, respectively. In this way, the touch multiplexing units 140n are connected to the touch electrodes P [ n ], P [2n ], P [3n ], P [4n ], P [5n ], and P [6n ] in the regions a 1-a 6, respectively.

It should be noted that, for simplicity of drawing, the touch electrodes connected to the touch multiplexing units 140a to 140n are only marked with symbols in fig. 3. Also, although the touch electrode array 120 shown in fig. 2 is arranged in a grid matrix, it is not limited to this case, and one skilled in the art can design and adjust the touch electrode array according to actual requirements. In addition, for simplicity of drawing, only the touch multiplexing units 140a to 140n connected to the first touch electrode row C1 are shown in fig. 3. The touch multiplexing units connected to the other touch electrode rows C2-Cn in fig. 2 are similar to the touch multiplexing units 140 a-140 n in fig. 3, and are not repeated here.

In operation, the touch multiplexing units 140a to 140n are used to receive the second control signals S1 to S6 and S1G to S6G output by the control signal generating circuit 130, and selectively output the signals transmitted from the output terminals Rx1 to Rxn of the driving circuit 110 to the corresponding touch electrodes according to the second control signals S1 to S6 and S1G to S6G.

Specifically, please refer to fig. 4 and 5 together. Fig. 4 is a schematic diagram illustrating a touch multiplexing unit 140a according to some embodiments of the invention. FIG. 5 is a waveform diagram of second control signals S [1] S [6], S [1] G S [6] G and a timing diagram of operations of touch electrodes P [1] P [6n ] according to some embodiments of the present invention. As shown in fig. 4, the pair of six touch multiplexing units 140a includes transistors M1-M6, M1 '-M6'. The transistors M1-M6, M1 '-M6' receive respective second control signals S [1] -S [6], S [1] G-S [6] G from the control signal generation circuit 130, respectively, and are selectively turned on or off according to the respective second control signals S [1] -S [6], S [1] G-S [6] G, respectively. Wherein the second control signals S1-S6 and S1G-S6G are respective inverted signals. When the second control signals S1-S6 are at the ON level (the second control signals S1G-S6G are at the OFF level), the transistors M1-M6 are turned on to output the signal transmitted from the output terminal Rx1 of the driving circuit 110 to the corresponding touch electrode. When the second control signals S [1] G-S [6] G are at the ON level (the second control signals S [1] S [6] are at the OFF level), the transistors M1 'M6' are turned on to provide the reset signal Sgd to the corresponding touch electrodes.

To explain in detail, as shown in fig. 5, the one period Tf includes a display period Td and a touch detection period Tt. The touch detection period Tt includes a reset period Tr. During the display period Td, the second control signals S1-S6 are at an ON level (e.g., a high voltage level) and the second control signals S1G-S6G are at an OFF level (e.g., a low voltage level), such that the transistors M1-M6 are turned on and the transistors M1 '-M6' are turned off. Therefore, the driving circuit 110 provides the common voltage level Vcom to the touch electrodes P [1] P [6n ] through the output terminal Rx1 via the touch multiplexing unit 140 a. As shown in FIG. 5, during Td, touch electrodes P [1] -P [ n ], P [ n +1] -P [2n ] … P [5n +1] -P [6n ] are at a common voltage level Vcom.

During the reset period Tr, the second control signals S [1] -S [6] are at an OFF level (e.g., a low voltage level) and the second control signals S [1] -S [6] G are at an ON level (e.g., a high voltage level), such that the transistors M1-M6 are turned off and the transistors M1 '-M6' are turned on. Therefore, the touch multiplexing unit 140a outputs the reset signal Sgd to the corresponding touch electrode. As shown in FIG. 5, during Td, the touch electrodes P [1] -P [ n ], P [ n +1] -P [2n ] … P [5n +1] -P [6n ] are at the reset voltage level Vgd.

During the touch detection period Tt, the second control signals S1-S6 are sequentially at an ON level (e.g., a high voltage level), and the second control signals S1G-S6G are sequentially at an OFF level (e.g., a low voltage level), such that the transistors M1-M6 are sequentially turned on and the transistors M1 '-M6' are sequentially turned off. Therefore, the driving circuit 110 can sequentially provide the detection signals to the touch electrodes for touch detection through the output terminal Rx1 via the touch multiplexing unit 140 a. As shown in FIG. 5, during t1, the touch electrodes P [1] P [ n ] are used for receiving the detecting voltage Sen. Then, the touch electrodes P [ n +1] to P [2n ] are used for receiving the detection voltage Sen. And so on until the touch electrodes P [5n +1] -P [6n ] are used for receiving the detection voltage Sen.

Thus, the second control signals S1-S6, S1G-S6G shown in FIG. 5 enable the detection signals sequentially outputted by the touch multiplexing unit 140a to the corresponding touch electrodes P1-P6 n for touch detection. In addition, the touch multiplexing units 140b to 140n in fig. 3 operate similarly to the touch multiplexing unit 140a, and are not described herein again.

Refer to FIG. 6 for how the second control signals S [1] S [6] and S [1] G S [6] G are generated. Fig. 6 is a schematic diagram of a control signal generating circuit 130 according to some embodiments of the invention. As shown in FIG. 6, the control signal generating circuit 130 includes a plurality of shift register units TPSR [1] TPSR [6 ]. Structurally, the shift register units TPSR [1] -TPSR [6] are connected in series. In operation, the shift register units TPSR [1] TPSR [6] are used to output corresponding second control signals S [1] S [6] and S [1] G S [6] G.

Specifically, the shift register unit TPSR [1] is used for outputting the corresponding second control signals S [1] and S [1] G according to the start signal TP _ STV and the clock signal TP _ CK. The shift register unit TPSR [2] is used for outputting a second control signal S [1] as a start signal according to the second control signal S [1] outputted from the previous stage of shift register unit TPSR [1], and outputting corresponding second control signals S [2] and S [2] G according to the start signal and the clock signal TP _ XCK. In this way, the shift register unit TPSR [6] is configured to output the second control signal S [5] outputted from the previous stage of shift register unit TPSR [5] as the start signal, and output the corresponding second control signals S [6] and S [6] G according to the start signal and the clock signal TP _ XCK. In other words, the shift register unit uses the second control signal outputted by itself as the start signal of the next stage of shift register unit.

In addition, the shift register units TPSR [1] TPSR [6] are used for resetting the corresponding second control signals according to the end signal. Specifically, the shift register unit TPSR [6] is used for resetting the second control signals S [6] and S [6] G according to the END signal TP _ END transmitted by the driving circuit 110. The shift register unit TPSR [1] is used for outputting a second control signal S [2] as an end signal according to a next stage shift register unit TPSR [2 ]. In this way, the shift register unit TPSR [5] uses the second control signal S [6] outputted from the next stage of shift register unit TPSR [6] as the end signal. In other words, the shift register unit uses the second control signal outputted by itself as the end signal of the previous stage of shift register unit.

Thus, by using the shift register units TPSR [1] TPSR [6] connected in series in the control signal generating circuit 130, a larger number of second control signals (e.g., S [1] S [6], S [1] G S [6] G) can be generated according to a smaller number of first control signals (e.g., TP _ STV, TP _ CK, TP _ XCK, TP _ END).

For further details, please refer to fig. 7. FIG. 7 is a diagram of a shift register unit TPSR [ k ] according to some embodiments of the present invention. In some embodiments, the shift register units TPSR [1] -TPSR [6] in FIG. 6 can be implemented by the shift register units TPSR [ k ] in FIG. 7. It should be noted that the lower case letter index k in the component numbers or signal numbers used herein refers to any component or signal that is not specific in the component group or signal group. In other words, the element number TPSR [ k ] refers to any of the shift register units TPSR [1] TPSR [6] that is not specified, and the signal number S [ k ] refers to the second control signal corresponding to the shift register unit TPSR [ k ] among the second control signals S [1] S [6 ].

As shown in fig. 7, the shift register unit TPSR [ k ] includes a shift register circuit SRc and an inverter circuit Inv. The shift register circuit SRc is coupled to the driving circuit 110, and is configured to receive the start signal TP _ STV, the END signal TP _ END, the clock signal TP _ CK or TP _ XCK from the driving circuit 110, and output a corresponding second control signal S [ k ]. The inverting circuit Inv is coupled to the shift register circuit SRc, receives the second control signal sk from the shift register circuit SRc, and outputs a corresponding inverting control signal sk G according to the second control signal sk.

Specifically, the shift register circuit SRc includes a start circuit 132, an end circuit 134, a pull-up circuit 136, a pull-down circuit 138, and a node Q. In operation, the start circuit 132 is configured to output a high voltage level to the node Q according to the start signal TP _ STV. The termination circuit 134 is used for pulling the node Q to a low voltage level according to the termination signal TP _ END. The pull-up circuit 136 is used for outputting the second control signal S [ k ] at the conducting level according to the voltage level of the node Q and the clock signal TP _ CK or TP _ XCK. The pull-down circuit 138 is used to reset the second control signal S [ k ] to an OFF level.

The shift register circuit SRc includes transistors T1 to T10 and a resistor R1. The start circuit 132 includes a transistor T1. The termination circuit 134 includes a transistor T2. The pull-up circuit 136 includes transistors T8, T9. The pull-down circuit 138 includes transistors T4, T5, T6, T10.

A first terminal of the transistor T1 is coupled to the high reference voltage level VGH. A second terminal of the transistor T1 is coupled to the node Q. The control terminal of the transistor T1 is configured to receive the start signal TP _ STV and is turned on according to the start signal TP _ STV to output a high voltage level to the node Q.

The first terminal of the transistor T2 is coupled to the second terminal of the transistor T1 and the node Q. The second terminal of the transistor T2 is used for receiving the selection signal TPSW (as shown in table one of the above paragraphs). The control terminal of the transistor T2 is for receiving the END signal TP _ END and pulling the node Q to a low voltage level according to the END signal TP _ END.

The first terminal and the control terminal of the transistor T3 are coupled to the high reference voltage level VGH. The second terminal of the transistor T3 is coupled to the first terminal of the resistor R1. The first terminal of the transistor T4 is coupled to the second terminal of the resistor R1. The second terminal of the transistor T4 is for receiving the selection signal TPSW. The control terminal of the transistor T4 is coupled to the node Q for selectively turning on or off according to the voltage level of the node Q.

A first terminal of the transistor T5 is coupled to the node Q. The control terminal of the transistor T5 is coupled to the second terminal of the resistor R1. The first terminal of the transistor T6 is coupled to the second terminal of the transistor T5. The control terminal of the transistor T6 is coupled to the second terminal of the resistor R1. The second terminal of the transistor T6 is for receiving the selection signal TPSW.

A first terminal of the transistor T7 is coupled to the node Q. The control terminal of the transistor T7 is coupled to the high reference voltage level VGH for outputting the voltage level of the node Q. The first terminal of the transistor T8 is used for receiving the clock signal TP _ CK or TP _ XCK. The control terminal of the transistor T8 is coupled to the second terminal of the transistor T7 for receiving the voltage level of the node Q. The first terminal of the transistor T9 is coupled to the second terminal of the transistor T8. The transistor T9 has a control terminal coupled to the second terminal of the transistor T7 for receiving the voltage level of the node Q and selectively turning on according to the voltage level of the node Q to output the second control signal S [ k ] through the second terminal of the transistor T9.

The first terminal of the transistor T10 is coupled to the second terminal of the transistor T9. The second terminal of the transistor T10 is for receiving the selection signal TPSW. The control terminal of the transistor T10 is coupled to the second terminal of the resistor R1. The transistor T10 is used to reset the second control signal S k to an off level.

In addition, in the embodiment of fig. 7, the inverting circuit Inv is configured to output the inverted control signal S [ k ] G according to the voltage level of the second terminal of the resistor R2. The inverter circuit Inv includes transistors T11, T12, and a resistor R2. The first terminal and the control terminal of the transistor T11 are coupled to the high reference voltage level VGH. The second terminal of the transistor T11 is coupled to the first terminal of the resistor R2. The first terminal of the transistor T12 is coupled to the second terminal of the resistor R2. The second terminal of the transistor T12 is for receiving the selection signal TPSW. The control terminal of the transistor T12 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc.

Next, please refer to fig. 7 and fig. 8 together. Fig. 8 is a schematic diagram illustrating a signal timing diagram of the control signal generating circuit 130 according to some embodiments of the present invention. As shown in fig. 8, during the display period Td, the selection signal TPSW, the start signal TP _ STV, the END signal TP _ END, the clock signals TP _ CK and TP _ XCK are at a high voltage level, such that the transistors T1, T2, T3, T4, T7, T8, T9, T11, T12 are turned on and the transistors T5, T6, T10 are turned off. Thus, node Q is pulled up to a high voltage level, the second control signal S [ k ] outputs a high voltage level and the second control signal S [ k ] G outputs a low voltage level. Thus, as shown in FIG. 4 and FIG. 5, when the second control signals S [1] S [6] are all at the high voltage level and the second control signals S [1] G S [6] G are all at the low voltage level, the transistors M1M 6 are all turned on and the transistors M1 'M6' are all turned off, so that the driving circuit 110 can provide the common voltage level Vcom to the touch electrodes through the output terminal (e.g., Rx 1).

Referring to fig. 7 and 8, in the reset period Tr of the touch detection period Tt, the selection signal TPSW changes to the low voltage level, the start signal TP _ STV is at the high voltage level, and the END signal TP _ END is at the low voltage level, so that the transistors T1, T3, T4, and T7 are turned on, and the transistors T2, T5, T6, and T10 are turned off. Therefore, the node Q is pulled up to the high voltage level, so that the transistors T8, T9 are turned on. Then, in a period T1 of the touch detection period Tt, the clock signal TP _ CK changes to a high voltage level, so the transistors T8 and T9 output the second control signal S [1] of the high voltage level according to the clock signal TP _ CK of the high voltage level. In addition, since the second control signal S [1] is at a high voltage level and the transistors T11, T12 are turned on, the second control signal S [1] G is output at a low voltage level.

Meanwhile, in the period t1 of the touch detection period Tt, the second control signal S [1] at the high voltage level is used as the start signal of the next stage of the shift register unit TPSR [2], so that the node Q of the shift register unit TPSR [2] is pulled up to the high voltage level. Similarly, in the period t2 of the touch detection period Tt, since the clock signal TP _ XCK is changed to a high voltage level, the shift register unit TPSR [2] outputs the second control signal S [2] of the high voltage level according to the clock signal TP _ XCK of the high voltage level.

In addition, during a period T2 of the touch detection period Tt, the second control signal S [2] at the high voltage level is used as an end signal of the previous stage of the shift register unit TPSR [1], such that the transistor T2 is turned on. At this time, since the transistors T2, T3, T5, T6, T7, T10 are turned on and the transistors T1, T4 are turned off, the voltage level of the node Q will be pulled down to a low voltage level. When the voltage level of the node Q is at a low voltage level, the transistors T8, T9 are turned off, so that the second control signal S [1] is reset to a low voltage level. In addition, since the second control signal S [1] is at a low voltage level, the transistor T12 is turned off and the transistor T11 is turned on, the second control signal S [1] G is output at a high voltage level.

In other words, each stage of the shift register unit TPSR [ k ] receives the second control signal S [ k-1] of the previous stage of the shift register unit TPSR [ k-1] as a start signal to charge the node Q of the shift register unit TPSR [ k ]. During the corresponding time period tk, the second control signal S [ k ] outputted by the shift register unit TPSR [ k ] is changed to a high voltage level. Until the shift register unit TPSR [ k ] receives the second control signal S [ k +1] of the next stage of shift register unit TPSR [ k +1] as an end signal, the node Q of the shift register unit TPSR [ k ] is pulled down so that the second control signal S [ k ] is reset to a low voltage level.

Thus, the plurality of shift register units TPSR [1] TPSR [6] connected in series in the control signal generating circuit 130 can generate the second control signals S [1] S [6] S [1] G S [6] G required by the touch multiplexing circuit 140.

In some other embodiments, the inversion circuit Inv in the shift register unit TPSR [ k ] includes different circuits. Please refer to fig. 9. FIG. 9 is a diagram of another embodiment of a shift register unit TPSR [ k ]. In the embodiment of fig. 9, similar components to those of fig. 7 are denoted by the same reference numerals, and the operations thereof are already described in the previous paragraphs, and are not repeated herein. In contrast to fig. 7, in the embodiment of fig. 9, the control terminal of the transistor T11 in the inverter circuit Inv is coupled to the second terminal of the resistor R1. In this way, the transistor T11 is turned on only when the node Q is at a low voltage level, rather than in a constant on state, so that the device degradation speed can be reduced. In addition, in the embodiment, since the control terminal of the transistor T11 receives the voltage level of the second terminal of the resistor R1, the inverted control signal S k G outputted by the inverting circuit Inv is close to the high reference voltage VGH without generating a voltage drop of the threshold voltage at the high voltage level. For example, if the high reference voltage level VGH is about 8.5V, the high level inversion control signal S [ k ] G is about 8.5V minus the threshold voltage of the transistor T11 in the embodiment of FIG. 7, and the high level inversion control signal S [ k ] G is about 8.5V in the embodiment of FIG. 9.

Please refer to fig. 10. FIG. 10 is a diagram of another embodiment of a shift register unit TPSR [ k ]. In the embodiment of fig. 10, similar components to those of fig. 7 are denoted by the same reference numerals, and the operations thereof are already described in the previous paragraphs, and are not repeated herein. In contrast to fig. 7, in the embodiment of fig. 10, the control terminal of the transistor T11 in the inverter circuit Inv is coupled to the signal GOFF provided by the 12 th pin in table one, and the second terminal of the transistor T12 is coupled to the low reference voltage level VSS. The signal GOFF is an end signal of the last stage in the gate control signal provided by the driving circuit 110 to the gate driving circuit 160. As shown in fig. 11, the voltage level of the signal GOFF is a low voltage level during the display period Td and a high voltage level during the touch detection period Tt. In addition, similar to the embodiment of fig. 9, since the control terminal of the transistor T11 receives the voltage level of the signal GOFF, the inversion control signal S k G outputted by the inversion circuit Inv will be close to the high reference voltage VGH without generating a threshold voltage drop at the high voltage level.

Please refer to fig. 12. FIG. 12 is a diagram of another embodiment of a shift register unit TPSR [ k ]. In the embodiment of fig. 12, similar components to those of fig. 7 are denoted by the same reference numerals, and the operations thereof are already described in the previous paragraphs, and are not repeated herein. In contrast to fig. 7, in the embodiment of fig. 12, the inverter circuit Inv includes transistors T13, T14, T15, and T16. The first terminal and the control terminal of the transistor T13 are coupled to the high reference voltage level VGH. The first terminal of the transistor T14 is coupled to the second terminal of the transistor T13. The control terminal of the transistor T14 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc. The second terminal of the transistor T14 is for receiving the selection signal TPSW. A first terminal of the transistor T15 is coupled to the high reference voltage level VGH. The control terminal of the transistor T15 is coupled to the second terminal of the transistor T13. The first terminal of the transistor T16 is coupled to the second terminal of the transistor T15. The control terminal of the transistor T16 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc. The second terminal of the transistor T16 is for receiving the selection signal TPSW. In the present embodiment, the inverter circuit Inv is configured to output the inversion control signal S [ k ] G according to the voltage level of the second terminal of the transistor T15.

In this way, since the transistors T13, T14 and T16 are turned on and the transistor T15 is turned off to generate the inversion signal in the embodiment of fig. 12, the inversion control signal S [ k ] G outputted by the inversion circuit Inv is close to the low voltage level of the selection signal TPSW and is not pulled high by the divided voltage value when the inversion control signal S [ k ] G is at the low voltage level. For example, if the low voltage level of the selection signal TPSW is about-8.0V, the low level inversion control signal Sk G of the embodiment of FIG. 7 is about-8.0V plus a divided voltage value, while the low level inversion control signal Sk G of the embodiment of FIG. 12 is about-8.0V.

Please refer to fig. 13. FIG. 13 is a diagram of another embodiment of a shift register unit TPSR [ k ]. In the embodiment of fig. 13, similar components to those of fig. 7 are denoted by the same reference numerals, and the operations thereof are already described in the previous paragraphs, and are not repeated herein. In contrast to fig. 7, in the embodiment of fig. 13, the inverter circuit Inv comprises transistors T17 and T18. A first terminal of the transistor T17 is coupled to the high reference voltage level VGH. The control terminal of the transistor T17 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc. The first terminal of the transistor T18 is coupled to the second terminal of the transistor T17. The control terminal of the transistor T18 is coupled to the second terminal of the transistor T9 in the shift register circuit SRc. The second terminal of the transistor T18 is coupled to the low reference voltage level VSS. In the present embodiment, the inverter circuit Inv is configured to output the inversion control signal S [ k ] G according to the voltage level of the second terminal of the transistor T17.

In this way, in the embodiment of fig. 13, the transistor T17 is turned on only when the shift register circuit SRc outputs the second control signal S [ k ] at a high level, rather than being in a constant on state, so as to slow down the device degradation. In addition, similar to the embodiment of fig. 12, since the transistors T17 and T18 do not generate the pull-down voltage level through the resistor R2, the inversion control signal S [ k ] G outputted by the inversion circuit Inv will be close to the low reference voltage level VSS and will not be pulled high by the divided voltage value at the low voltage level.

It should be noted that, although only a pair of six touch multiplexing units is taken as an example in the embodiments of the disclosure, a person skilled in the art can design and adjust multiplexers with different signal numbers and types according to actual requirements, and the design is not limited to this case.

In addition, it should be noted that the features and circuits in the respective drawings, embodiments and embodiments of the present invention may be combined with each other without conflict. The circuits shown in the drawings are for illustrative purposes only, are simplified to simplify the explanation and facilitate understanding, and are not intended to limit the present disclosure. In addition, each device, unit and element in the above embodiments may be implemented by various types of digital or analog circuits, may be implemented by different integrated circuit chips, or may be integrated into a single chip. The foregoing is merely exemplary and the invention is not limited thereto.

In summary, by applying the above embodiments, the display function and the touch detection function in the same area can be realized by sharing the common electrode through the time division, and no additional element is required. In addition, the electrode array is divided into different areas, so that the different areas can simultaneously and respectively carry out display or touch detection in the same period. The touch control function is added, the original pixel charging time is not occupied, and the charging efficiency is not influenced.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A touch display device, comprising:

a touch electrode array including a plurality of touch electrodes;

a driving circuit for outputting a plurality of first control signals;

a control signal generating circuit, electrically coupled to the driving circuit, for generating a plurality of second control signals according to the first control signals; and

and the touch control multiplexing circuit is electrically coupled with the touch control electrodes and the control signal generating circuit and used for outputting a plurality of detection signals to the touch control electrodes according to the second control signals for touch control detection, wherein the quantity of the second control signals is greater than that of the first control signals.

2. The touch display device of claim 1, wherein the control signal generating circuit comprises a plurality of shift register units, the shift register units are connected in series, the shift register units are configured to output the second control signals, and each of the shift register units comprises:

a shift register circuit for outputting a corresponding one of the second control signals according to a start signal and a clock signal; and

an inverting circuit for outputting an inverted control signal according to the corresponding one of the second control signals.

3. The touch display device as recited in claim 2, wherein one of the shift register circuits outputs the corresponding second control signal as the start signal of the next shift register circuit and outputs the corresponding second control signal as an end signal of the previous shift register circuit.

4. The touch display device of claim 2, wherein the shift register circuit comprises:

a start circuit for outputting a high voltage level to a node according to the start signal;

a termination circuit for pulling the node to a low voltage level according to a termination signal;

a pull-up circuit for outputting the second control signal of a conducting level according to the voltage level of the node and the clock pulse signal; and

a pull-down circuit for resetting the second control signal to an off level.

5. The touch display device of claim 2, wherein the inverting circuit comprises:

a resistor;

a first transistor, a first terminal of which is coupled to a high reference voltage level, and a second terminal of which is coupled to a first terminal of the resistor; and

a second transistor, a first end of the second transistor is coupled to a second end of the resistor, a control end of the second transistor is coupled to the shift register circuit and is used for receiving the second control signal output from the shift register circuit,

the inverting circuit is used for outputting the inverting control signal according to the voltage level of the second end of the resistor.

6. The touch display device of claim 5, wherein a control terminal of the first transistor is coupled to the first terminal of the first transistor, and a second terminal of the second transistor is coupled to a selection signal.

7. The touch display device of claim 5, wherein a control terminal of the first transistor is coupled to the shift register circuit, and a second terminal of the second transistor is coupled to a selection signal.

8. The touch display device of claim 5, wherein a control terminal of the first transistor is coupled to a gate-driven termination signal, and a second terminal of the second transistor is coupled to a low reference voltage level.

9. The touch display device of claim 2, wherein the inverting circuit comprises:

a third transistor, a first terminal and a control terminal of which are coupled to a high reference voltage level;

a fourth transistor, a first terminal of which is coupled to a second terminal of the third transistor, a control terminal of which is coupled to the shift register circuit and is configured to receive the second control signal output from the shift register circuit, and a second terminal of which is coupled to a selection signal;

a fifth transistor, a first terminal of which is coupled to the high reference voltage level, and a control terminal of which is coupled to the second terminal of the third transistor; and

a sixth transistor, a first terminal of which is coupled to a second terminal of the fifth transistor, a control terminal of which is coupled to the shift register circuit and is configured to receive the second control signal output from the shift register circuit, a second terminal of which is coupled to the selection signal,

the inverting circuit is used for outputting the inverting control signal according to the voltage level of the second end of the fifth transistor.

10. The touch display device of claim 2, wherein the inverting circuit comprises:

a seventh transistor, a first terminal of which is coupled to a high reference voltage level; and

an eighth transistor, a first terminal of the eighth transistor being coupled to a second terminal of the seventh transistor, a control terminal of the eighth transistor and a control terminal of the seventh transistor being coupled to the shift register circuit and receiving the second control signal outputted from the shift register circuit, a second terminal of the eighth transistor being coupled to a low reference voltage level,

the inverting circuit is configured to output the inverted control signal according to a voltage level of the second terminal of the seventh transistor.