TW201716944A - Shift register - Google Patents

Abstract

A shift register adapted to be embedded in a touch control screen. The shift register includes a shift logic circuit, a first inverter, a first switch, a second inverter and a reset circuit. The first inverter is coupled to the shift logic register. The first switch is coupled to the first inverter. The second inverter is coupled to the first inverter. The reset circuit is coupled to the second inverter. The shift logic circuit produces shift signal according to a clock signal, an input signal and a clamping signal. The first inverter produces the clamping signal according to the shift signal. The first switch adjusts the voltage level of the clamping signal to a first reference voltage according to a touch enablement signal. The second inverter is used to produce an output signal corresponding to the clamping signal when is enabled. The reset circuit adjusts the voltage level of the output signal to the first reference voltage according to the touch enablement signal.

Description

Shift register

The present invention relates to a shift register, and more particularly to a shift register for an in-cell touch panel.

Based on the consideration of reducing manufacturing cost and narrow frame effect, today's panel manufacturers are gradually adopting the gate driver on array (GOA) technology. The GOA technology uses a semiconductor process to directly fabricate the shift register circuit on the glass substrate of the panel, and sequentially outputs a plurality of gate drive signals by using a plurality of serially connected shift registers to drive the pixel array of the panel. .

For an in-cell touch panel, the in-cell touch panel is provided with a gate driving circuit and a touch circuit on the same substrate. Obviously, the gate driving circuit and the touch circuit will be Cause some degree of interference with each other. Due to the strong intensity of the gate drive signal, the gate drive signal often forms noise and interferes with the touch detection signal via the capacitive coupling effect of the structure. In a worse case, the touch detection signal is also interfered by the gate drive signal and misjudges.

In order to avoid such a situation, generally, when the touch circuit is enabled, several specific signals in the shift register are pulled down to a low level to avoid the gate driving circuit and the touch circuit from each other. interference. At the same time, however, how to enable the gate drive circuit to resume normal operation after the touch circuit is enabled can become a major issue for engineers in designing the shift register.

The present invention provides a shift register capable of maintaining a desired voltage of a specific node in a shift register while pulling down a plurality of signals of the shift register, thereby allowing the shift register to be After this period of time when the touch circuit is enabled, it can quickly resume normal operation.

A shift register disclosed in the present invention is suitable for being embedded in a touch screen. The shift register includes a shift logic circuit, a first inverter, a first switch, a second inverter, and a reset circuit. The first inverter is coupled to the shift logic circuit. The first switch is coupled to the first inverter. The second inverter is coupled to the first inverter. A reset circuit is coupled to the second inverter. The shift logic circuit generates a shift signal according to the clock signal, the input signal, and the clamp signal. The first inverter generates a clamp signal in accordance with the shift signal. The first switch adjusts the potential of the clamp signal to the first reference voltage according to the touch enable signal. The second inverter is configured to generate an output signal corresponding to the clamp signal when enabled. The reset circuit adjusts the potential of the output signal to the first reference voltage according to the touch enable signal. .

In summary, the present invention discloses a shift register for charging and discharging an output node or an input node of at least one inverter in a shift register in a timely manner to lower the shift temporarily. The plurality of input signals or output signals of the memory can also maintain the desired voltage of the output or input node of the inverter, so that the shift register is after the touch circuit is enabled. Can quickly resume normal operation

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a functional block diagram of a gate driving circuit according to an embodiment of the invention. The gate driving circuit 1 has shift registers 10_1~10_4, and the shift registers 10_1~10_4 are sequentially connected in series. Taking the shift registers 10_1, 10_2 as an example, the shift register 10_1 generates a gate drive signal SR(1) according to the clock signal CK(1). The shift registers 10_1, 10_2 generate the gate drive signal SR(1) according to the clock signal CK(2) and the gate drive signal SR(1). The related actions of the shift registers 10_3, 10_4 can be deduced from the above, and the details are not repeated here. For the sake of simplicity of description, only the shift registers 10_1~10_4 are illustrated in FIG. 1, but the number of shift registers that the gate drive circuit 1 can have is not limited here. The following is a description of the structure of the shift register 10_3, and the structure of the shift registers 10_1~10_2, 10_4 is similar to that of the shift register 10_3, and thus will not be described herein.

Referring to FIG. 2, FIG. 2 is a schematic circuit diagram of a shift register according to an embodiment of the invention. The shift register 10_3 is adapted to be embedded in a touch screen. The shift register 10_3 includes a shift logic circuit 102, a first inverter 104, a first switch 106, a second inverter 108, and a reset circuit 110. The first inverter 104 is electrically connected to the shift logic circuit 102. The first switch 106 is electrically connected to the first inverter 104. The second inverter 108 is electrically coupled to the first inverter 104 . The reset circuit 110 is electrically connected to the second inverter 108. In this embodiment, the reset circuit 110 is a transistor T21. The first inverter 104 includes a pull-up switch T11 and a pull-down switch T12. In fact, the shift register 10_3 shown in FIG. 2 is merely an example, and each module or unit is not limited to the embodiment shown in FIG. 2, and all of them have similar functions in similar timings. It belongs to the scope of this case.

The shift logic circuit 102 generates a shift signal G(3) according to the clock signal CK(3), the input signal, and the clamp signal K(3). In this embodiment, the input signal is the gate drive signal SR(2), but is not limited thereto. The first inverter 104 generates the clamp signal K(3) in accordance with the shift signal G(3). The first switch 106 adjusts the potential of the clamp signal K(3) to the first reference voltage XDONB according to the touch enable signal TP_EN. The second inverter 108 is configured to generate an output signal corresponding to the clamp signal K(3) when enabled. The reset circuit 110 adjusts the potential of the gate drive signal SR(3) to the first reference voltage XDONB according to the touch enable signal TP_EN.

In more detail, when the gate driving circuit 1 operates normally, the voltage levels of the gate driving signals SR(1) to SR(4) are sequentially pulled high to a high potential. In the case of the shift register 10_2, 10_3, the shift register 10_2 first raises the voltage level of the gate drive signal SR(2) to a transient potential, and the transistors T1 and T2 are turned on, and the control is performed. The voltage level of the signal Q(3) is thus pulled high, and then the transistor T8 is turned on because of the control signal Q(3) after the potential rises.

Next, the gate drive signal SR(2) is pulled low to a low potential, and the transistors T1, T2 are not turned on. At this time, the clock signal CK(3) is turned to a high potential, and the transistor T8 is maintained in an on state. The shift signal G(3) is pulled high to a high potential with the clock signal CK(3) via the conduction path of the transistor T8 and the short-circuit path of the transistor T9. Due to the circuit wiring mode, the transistor T9 can also be used as a capacitor. Therefore, when the shift signal G(3) is pulled high with the clock signal CK(3), the control signal is due to the capacitive coupling effect of the transistor T9. Q(3) is pushed higher in conjunction, and the shift signal G(3) is pulled high again to the potential shown in FIG. Then, the shift signal G(3) is inverted to the clamp signal K(3) via the first inverter 104, and the clamp signal K(3) is further inverted by the second inverter 108 into the gate drive signal SR ( 3) and output. When the pulse signal CK(3) is pulled low to a low level, the gate drive signal SR(3) is also pulled down to a low potential. The on-resistance of the first switch 106 controlled by the touch enable signal TP_EN is lower than the on-resistance of the pull-up switch T11 controlled by the shift signal G(3).

As shown in FIG. 2, the shift register 10_3 also has an enable switch 112. The enable switch 112 is electrically coupled to the second inverter 108 and selectively enables the second inverter 108 in accordance with the gate drive signal SR(2). In this embodiment, the enable switch 112 is a P-type metal oxide semiconductor field effect transistor, and its control terminal receives the gate drive signal SR(2). When the gate drive signal SR(2) is at a low voltage level, the enable switch 112 is turned on to enable the second inverter 108.

When the touch circuit of the in-cell touch panel is to perform touch scanning, the clock signal CK(3), the first reference voltage XDONB and the second reference voltage VGH are pulled down to a low level to drive the gate. The circuit 1 is paused for a period of time, and the touch circuit performs touch scanning during this period of time. Please refer to FIG. 3 to illustrate the operation mode of the shift register 10_3 when the touch display panel performs touch scanning, and FIG. 3 is a timing diagram of the shift register according to FIG. 2 of the present invention. .

As shown in FIG. 3, before the time point t1, the gate driving circuit 1 operates normally, so the control signal Q(2) is pulled high to the high potential, and the shift signal G(2) is associated with the control signal Q(2). ) is pulled high to high, and at this time the control signal Q(3) is pulled high to the transient potential. Since the touch circuit starts to perform touch detection at time t1, the clock signal CK(3) is pulled low to a low level, and the touch enable signal TP_EN is pulled high to a high level. At this time, since the clock signal CK(3) is at a low potential, the shift signal G(3) cannot be pulled up by the clock signal CK(3) via the transistors T8 and T9, so the control signal Q(3) cannot be The aforementioned capacitive coupling effect is adjusted to a high potential, so that the shift signal G(3) cannot be adjusted to a high potential.

At this time, the first switch 106 is turned on because of the high-potential touch enable signal TP_EN, and the clamp signal K(3) is pulled low to a low potential without conducting the transistors T5, T6, T7 via the transistor T3. Moreover, the reset circuit 110 also adjusts the potential of the gate touch signal SR(3) to the first reference voltage XDONB according to the high potential touch enable signal TP_EN. Therefore, by the above operation, between the time point t1 and the time point t2, the gate drive signal SR(3) and the other gate drive signals generated by the shift register are adjusted to a low potential without It will interfere with the touch circuit for touch detection.

In addition to the embodiment as described in FIG. 2, the shift register 10_3 can have several embodiments as described below.

Please refer to FIG. 4. FIG. 4 is a schematic circuit diagram of a shift register according to another embodiment of the present invention. In the embodiment corresponding to Figure 4, the reset circuit 110' is a multiplexer. The first input of the reset circuit 110' is electrically coupled to the second reference voltage VGH. The second input of reset circuit 110' is electrically coupled to the output of first inverter 104. The selection signal terminal of the reset circuit 110' is configured to receive the touch enable signal TP_EN. The output of reset circuit 110' is electrically coupled to the input of second inverter 108. The reset circuit 110' selectively outputs the second reference potential VGH or the clamp signal output from the first inverter 104 according to the potential level of the touch enable signal TP_EN. In an embodiment, when the touch enable signal TP_EN is at a low level, the reset circuit 110' outputs a gate drive signal according to the second reference voltage VGH, and when the touch enable signal TP_EN is at a high level, The reset circuit 110' outputs a gate drive signal in accordance with the clamp signal K(3) output from the first inverter 104. That is, in another embodiment, the reset circuit 110' selectively outputs the second reference voltage VGH or the clamp signal output by the first inverter 104 according to the potential of the inverted touch enable signal TP_EN. .

Please refer to FIG. 5. FIG. 5 is a schematic circuit diagram of a shift register according to a further embodiment of the present invention. In the embodiment corresponding to FIG. 5, the shift register 10_3 further has a third inverter 114 and a fourth inverter 116. The third inverter 114 is electrically connected to the output of the second inverter 108. The fourth inverter 116 is electrically connected to the output of the third inverter 114. Also.

In the embodiment corresponding to FIG. 5, the shift register 10_3 may further include a third switch 118. The third switch 118 is, for example, a transistor T22. The first end of the third switch 118 is electrically connected to the output end of the third inverter 114, the second end of the third switch 118 is electrically connected to the second reference voltage VGH, and the third switch 118 is according to the third switch 118. The touch enable reverse signal ~TP_EN of the control terminal selectively establishes a current path between the first end of the third switch 118 and the second end of the third switch 118. The transistor T22 of the third switch 118 is, for example, a P-type metal oxide semiconductor field effect transistor (MOSFET) or an N-type metal oxide semiconductor field effect transistor. As the type of the transistor T22 is different, the transistor T22 is turned on according to the touch enable signal TP_EN or the touch enable inverted signal ~TP_EN. This is a general knowledge of those skilled in the art, and can be freely designed after reading this specification, and is not limited herein.

Please refer to FIG. 6. FIG. 6 is a schematic circuit diagram of a shift register according to still another embodiment of the present invention. Compared to FIG. 5, as shown in FIG. 6, in fact, the shift register 10_3 may not have the transistor T21.

In summary, the present invention discloses a shift register for charging and discharging an output node or an input node of at least one inverter in a shift register in a timely manner by a switch circuit. Interfering with the in-cell touch panel for touch scanning and pulling down multiple input signals or output signals of the shift register can also maintain the desired voltage of the output or input node of the at least one inverter . In this way, in addition to letting the shift register not perform a malfunction during the touch scan of the in-cell touch panel, the shift register can be terminated by the touch panel in the in-cell touch panel. After that, it can quickly resume normal operation.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1‧‧ ‧ gate drive circuit
10_1~10_4‧‧‧Shift register
102‧‧‧Shift logic circuit
104‧‧‧First Inverter
106‧‧‧First switch
108‧‧‧Second inverter
110, 110'‧‧‧Reset circuit
112‧‧‧Enable switch
114‧‧‧ Third Inverter
116‧‧‧fourth inverter
118‧‧‧third switch
CK(1)~CK(4)‧‧‧ clock signal
G(2), G(3)‧‧‧ shift signals
K(3)‧‧‧ clamp signal
Q(2), Q(3)‧‧‧ control signals
TP_EN‧‧‧Touch enable signal
~TP_EN‧‧‧Touch enabled reverse signal
T1~T21‧‧‧O crystal
T11‧‧‧ Pull-up switch
T12‧‧‧ pull-down switch
T1, t2‧‧‧ time point
SR(1)~SR(4)‧‧‧ gate drive signal
VGH‧‧‧second reference voltage
XDONB‧‧‧ first reference voltage

FIG. 1 is a functional block diagram of a gate driving circuit according to an embodiment of the invention. FIG. 2 is a schematic circuit diagram of a shift register according to an embodiment of the invention. FIG. 3 is a timing diagram of the shift register shown in FIG. 2 according to the present invention. 4 is a circuit diagram of a shift register according to another embodiment of the present invention. FIG. 5 is a schematic circuit diagram of a shift register according to a further embodiment of the present invention. FIG. 6 is a schematic circuit diagram of a shift register according to still another embodiment of the present invention.

102‧‧‧Shift logic circuit

104‧‧‧First Inverter

106‧‧‧First switch

108‧‧‧Second inverter

110‧‧‧Reset circuit

112‧‧‧Enable switch

CK(3)‧‧‧ clock signal

G(3)‧‧‧ shift signal

K(3)‧‧‧ clamp signal

Q(3)‧‧‧ control signal

SR(2), SR(3)‧‧‧ gate drive signal

TP_EN‧‧‧Touch enable signal

T1~T21‧‧‧O crystal

VGH‧‧‧ first reference voltage

XDONB‧‧‧second reference voltage

Claims (7)

A shift register adapted to be embedded in a touch screen, the shift register comprising: a shift logic circuit for generating a shift signal according to a clock signal, an input signal and a clamp signal a first inverter electrically connected to the shift logic circuit to generate the clamp signal according to the shift signal; a first switch electrically connected to the first inverter, according to a touch enable signal The potential of the clamp signal is adjusted to a first reference voltage; a second inverter is electrically coupled to the first inverter for generating an output signal corresponding to the clamp signal when enabled; And a reset circuit electrically connected to the second inverter, and adjusting the potential of the output signal to the first reference voltage according to the touch enable signal. The shift register of claim 1, wherein the reset circuit is a second switch, the second switch has a first end, a second end and a control end, the second switch One end is electrically connected to the output end of the second inverter, the second end of the second switch is electrically connected to the first reference voltage, and the second switch is in accordance with the touch of the control end of the second switch The control enable signal selectively establishes a current path between the first end of the second switch and the second end of the second switch. The shift register of claim 1, wherein the reset circuit is a multiplexer, the multiplexer comprising: a first input terminal electrically connected to a second reference voltage; a second input The terminal is electrically connected to the output end of the first inverter; a selection signal end is configured to receive a touch enable inverted signal; and an output end is electrically connected to the input end of the second inverter . The shift register according to Item 1 or 2, further comprising: a third inverter electrically connected to the output end of the second inverter; and a fourth inverter, the electric The connection is made to the output of the third inverter. The shift register according to the fourth aspect, further comprising a third switch, the third switch having a first end, a second end and a control end, the first end of the third switch being electrically Connected to the output end of the third inverter, the second end of the third switch is electrically connected to a second reference voltage, and the third switch is configured according to the touch enable signal of the control end of the third switch And establishing a current path between the first end of the third switch and the second end of the third switch. The shift register of any one of the items 1 to 3, wherein the first inverter comprises a pull-up switch and a pull-down switch, and the first switch is controlled by the shift signal The on-resistance of the conduction is smaller than the on-resistance of the pull-up switch controlled by the touch enable signal. The shift register according to any one of the items 1 to 3, further comprising a uniform energy switch electrically connected to the second inverter, and selectively enabling the second reverse according to the input signal Phase device.