TWI699580B - Array substrate - Google Patents

Abstract

An array substrate is provided. The array substrate includes a substrate, a first alignment mark, a pair of first auxiliary pattern, a plurality of signal lines and a plurality of pixel units. The substrate has a display area and a peripheral area located at a side of the display area. The first alignment mark is disposed within the peripheral area of the substrate. The pair of first auxiliary pattern are disposed within the peripheral area of the substrate, and are located at two sides of the first alignment mark. The signal lines are disposed within the peripheral area of the substrate, wherein at least one of the signal lines overlaps at least one of the first alignment mark and the pair of first auxiliary pattern along the normal direction of the first substrate. The pixel units are disposed within the display area of the substrate.

Description

Array substrate

The present invention relates to an array substrate, and particularly relates to an array substrate that can meet the design requirements of a narrow frame.

The border around the display area is regarded as one of the important factors affecting the aesthetic appearance of the display device. Therefore, display device related industries have invested in slim border designs to make display devices with the same display quality more lightweight, thin and short, to meet consumer needs. Generally speaking, in the process of manufacturing an array substrate for a display device, alignment marks should be provided in the peripheral area of the display area to avoid patterning processes, alignment or any process that requires alignment marks. deviation. However, the necessity of setting the alignment mark limits the development of array substrates that conform to the narrow frame design.

An embodiment of the present invention provides an array substrate, which meets the requirements of narrow frame design.

An array substrate according to an embodiment of the present invention includes a substrate, a first alignment mark, a pair of first auxiliary patterns, a plurality of signal lines, and a plurality of pixel units. The substrate has a display area and a peripheral area, and the peripheral area is located on one side of the display area. The first alignment mark is disposed in the peripheral area of the substrate. A pair of first auxiliary patterns are arranged in the peripheral area of the substrate and located on both sides of the first alignment mark. The plurality of signal lines are arranged in the peripheral area of the substrate, wherein at least one of the plurality of signal lines overlaps with at least one of the first alignment mark and the pair of first auxiliary patterns in the normal direction of the substrate. A plurality of pixel units are arranged in the display area of the substrate.

Based on the above, in the array substrate of the present invention, a plurality of pixel units are arranged in the display area of the substrate, and the first alignment mark, a pair of first auxiliary patterns and a plurality of signal lines are arranged in the peripheral area of the substrate. A pair of first auxiliary patterns are located on both sides of the first alignment mark, and at least one of the plurality of signal lines and at least one of the first alignment mark and a pair of first auxiliary patterns are on the substrate. The line directions are overlapped, so that the array substrate can meet the requirements of narrow frame design.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

As used herein, "approximately", "approximately", "essentially", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account all The measurement in question and the specific number of errors associated with the measurement (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, the "approximate", "approximate", "essential", or "substantially" used herein can be based on measurement properties, cutting properties, or other properties to select a more acceptable range of deviation or standard deviation, and Not one standard deviation applies to all properties.

It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on", "connected to" or "contacting" another element, it can be directly on or with another element. Elements are connected/contacted, or intermediate elements may also be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly in contact with” another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" can mean that there are other components between the two components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those with ordinary knowledge in any technical field. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meaning in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

In order to comply with the narrow frame design, at least one embodiment of the present invention provides an array substrate, which can achieve the above advantages. Hereinafter, various embodiments are specifically described to describe the array substrate of the present invention in detail, as an example on which the present invention can be implemented.

FIG. 1 is a schematic top view of an array substrate according to an embodiment of the present invention. Please refer to FIG. 1, the array substrate 10 may include a substrate 100. In this embodiment, the substrate 100 may have a display area A and a peripheral area B surrounding the display area A, wherein the peripheral area B may include a driving circuit area C and a marking area M located on one side of the driving circuit area C. Although FIG. 1 reveals that the peripheral area B surrounds the display area A, the present invention is not limited to this. In other embodiments, the peripheral area B may be located on one side of the display area A.

In this embodiment, the display area A may include multiple scan lines SL, multiple data lines DL, and multiple pixel units U. In this embodiment, the scan lines SL are not parallel to the data lines DL, that is, the scan lines SL and the data lines DL are arranged to cross each other. In addition, the plurality of scan lines SL and the plurality of data lines DL may be located in different layers, and a gate insulating layer GI may be sandwiched between the plurality of scan lines SL and the plurality of data lines DL (described in detail later) . In this embodiment, each pixel unit U can be electrically connected to one of the scan lines SL and one of the data lines DL. In this embodiment, each pixel unit U may include an active element T (described in detail later) and a pixel electrode PE/PE2 (described in detail later).

In this embodiment, the driving circuit area C may include any driving circuit for an array substrate, such as a gate driving circuit, a source driving circuit, etc., which are well known to those with ordinary knowledge in the art. In addition, in the present embodiment, the mark area M may include alignment marks (described in detail later) that are required to be used in the process of manufacturing the array substrate 10.

In order to describe the technical content of the array substrate 10 of this embodiment in more detail, the manufacturing method of the array substrate 10 will be described below in conjunction with FIGS. 2A to 2C and FIGS. 3A to 3C. It is worth mentioning that, as shown in FIG. 1, the array substrate 10 includes a plurality of pixel units U. However, in order to clearly illustrate the present invention, FIGS. 2A to 2C and 3A to 3C only show one of the pixel units. U.

2A to 2C are flow cross-sectional views of a manufacturing method of an array substrate according to an embodiment of the present invention. 3A to 3C are top views of a process of a manufacturing method of an array substrate according to an embodiment of the present invention. The cross-sectional positions of FIGS. 2A to 2C correspond to the positions of the cross-sectional lines I-I' and II-II' of FIGS. 3A to 3C.

2A and 3A at the same time, the scan line SL, the data line DL and the active device T are formed in the display area A of the substrate 100, and the first alignment mark 102 is formed in the marking area M of the peripheral area B of the substrate 100. And a plurality of first signal line segments L1 and a plurality of third signal line segments L3 are formed in the peripheral area B of the substrate 100. In addition, for convenience of description, FIG. 2A omits the related elements in the driving circuit area C of the peripheral area B. As mentioned above, anyone with ordinary knowledge in the art should understand that the driving circuit area C may include driving Circuits, such as gate drive circuits, source drive circuits, etc.

In this embodiment, the substrate 100 may be a rigid substrate, such as a glass substrate, a quartz substrate, or a silicon substrate, or may be a flexible substrate, such as a polymer substrate or a plastic substrate.

In this embodiment, the method for forming the active device T may include the following steps: sequentially forming an active layer SC, a gate insulating layer GI, a gate electrode G, an interlayer insulating layer IL1, a source electrode S, and a drain electrode D on the substrate 100, The active layer SC includes a source region SR, a drain region DR, and a channel region CR formed by an ion doping process with a gate G as a mask. The gate G and the channel region CR are in the normal direction n of the substrate 100 Overlapping, the source S is electrically connected to the source region SR through the opening H1 formed in the gate insulating layer GI and the interlayer insulating layer IL1, and the drain D is electrically connected to the source region SR through the opening H2 formed in the gate insulating layer GI and the interlayer insulating layer IL1. The drain region DR is electrically connected, but the invention is not limited to this. In this embodiment, the active layer SC, the gate insulating layer GI, the gate G, the interlayer insulating layer IL1, the source S, and the drain D can be implemented by any method known to those with ordinary knowledge in the art. To form, so I won’t repeat it here. In this embodiment, the active device T is a top gate type thin film transistor, but the invention is not limited to this. In other embodiments, the active device T may also be a bottom gate type thin film transistor, a three-dimensional type thin film transistor, or other suitable types of thin film transistors.

In this embodiment, the gate G is realized by a part extending from the scan line SL. That is, in this embodiment, the gate electrode G and the scan line SL can belong to the same film layer, have substantially the same material, and can be formed in the same photomask manufacturing process. However, the present invention is not limited to this. In other embodiments, a part of the scan line SL itself can be used as the gate G. In addition, in this embodiment, a part of the data line DL itself can be used as the source S. That is to say, in this embodiment, the source electrode S and the data line DL can belong to the same film layer, have substantially the same material, and can be formed in the same mask manufacturing process. However, the present invention is not limited to this. In other embodiments, the gate G can be realized by a part extending from the data line DL. In addition, in this embodiment, the drain electrode D and the source electrode S can belong to the same film layer, have substantially the same material, and can be formed in the same photomask manufacturing process. In this embodiment, the materials of the scan line SL, the gate G, the data line DL, the source S and the drain D may include (but are not limited to): metals, alloys, nitrides of the foregoing materials, and oxidation of the foregoing materials. Materials, oxynitride of the aforementioned materials, other non-metallic materials with conductive properties, or other suitable materials.

In this embodiment, the material of the active layer SC may include polysilicon, that is, the active device T may be a Low Temperature Poly-Silicon Thin Film Transistor (LTPS TFT). However, the present invention does not limit the type of the active device. In other embodiments, the material of the active layer SC may include amorphous silicon, microcrystalline silicon, nanocrystalline silicon, single crystal silicon, organic semiconductor materials, metal oxide semiconductor materials, carbon nanotubes/rods, perovskite Or other suitable materials.

In this embodiment, the gate insulating layer GI and the interlayer insulating layer IL1 are formed on the substrate 100 in an all-round way. That is, in this embodiment, the gate insulating layer GI and the interlayer insulating layer IL1 are located in the display area A and the peripheral area B. In this embodiment, the gate insulating layer GI covers the active layer SC, and the interlayer insulating layer IL1 is disposed on the gate insulating layer GI and covers the gate G. In this embodiment, the gate insulating layer GI and the interlayer insulating layer IL1 may have a single-layer or multi-layer structure, respectively. In this embodiment, the materials of the gate insulating layer GI and the interlayer insulating layer IL1 may respectively include inorganic materials, organic materials, or other suitable materials, where the inorganic materials include (but not limited to) silicon oxide, silicon nitride, or Silicon oxynitride; organic materials include, but are not limited to, polyimide resins, epoxy resins, or acrylic resins.

In this embodiment, the first alignment mark 102 is formed on the interlayer insulating layer IL1. In this embodiment, the first alignment mark 102 and the data line DL, the source S and the drain D can belong to the same film layer, have substantially the same material, and can be formed in the same mask manufacturing process. In this embodiment, the material of the first alignment mark 102 may include (but is not limited to): metals, alloys, nitrides of the foregoing materials, oxides of the foregoing materials, oxynitrides of the foregoing materials, and other non-metallic materials. Materials with conductive properties, or other suitable materials.

In this embodiment, the first signal line segment L1 and the third signal line segment L3 are formed on the interlayer insulating layer IL1. In this embodiment, the first signal line segment L1 is located on one side of the first alignment mark 102, and the third signal line segment L3 is located on the other side of the first alignment mark 102. In this embodiment, the first signal line segment L1 and the third signal line segment L3 are arranged correspondingly. In this embodiment, the first signal line segment L1 and the third signal line segment L3, the data line DL, the source S, the drain D, and the first alignment mark 102 may belong to the same film layer and have substantially the same material, and Can be formed in the same mask manufacturing process.

Next, referring to FIG. 2B, an insulating layer PL covering the active device T, the first alignment mark 102, the first signal line segment L1 and the third signal line segment L3 is fully formed on the substrate 100 to protect the active device T and Flattening function. In other words, in this embodiment, the insulating layer PL is located in the display area A and the peripheral area B. In this embodiment, the insulating layer PL may have a single-layer or multi-layer structure. In this embodiment, the material of the insulating layer PL may include inorganic materials, organic materials, or other suitable materials. Inorganic materials include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride; organic materials such as Including (but not limited to): polyimide (PI), polyamic acid (PAA), polyamide (PA), polyvinyl alcohol (PVA), polyvinyl alcohol Cinnamate (polyvinyl cinnamate, PVCi), or suitable photoresist material. In addition, in this embodiment, the method for forming the insulating layer PL may include a physical vapor deposition method, a chemical vapor deposition method, or a photoresist coating method.

2B and 3B at the same time, using the photomask 200 as a mask to perform a patterning process on the insulating layer PL to form a pair of first auxiliary patterns 104 in the peripheral area B of the substrate 100, and expose the drain The pole D opening O1, the opening O2 exposing the first alignment mark 102, the opening O3 exposing the first signal line segment L1, and the opening O4 exposing the third signal line segment L3. In this embodiment, a part of the insulating layer PL serves as a pair of first auxiliary patterns 104. In this embodiment, the patterning process may include exposure and development steps. However, the present invention is not limited to this. In other embodiments, the patterning process may include exposure, development, and etching steps.

In this embodiment, the photomask 200 includes a substrate 202, a mask pattern 204, and a pair of marking patterns 206. The material of the substrate 202 may include (but is not limited to): glass, quartz or other applicable transparent materials. The mask pattern 204 is disposed on the substrate 202 and defines openings O5 to O8. When the photomask 200 is used as a mask to perform a patterning process on the insulating layer PL, openings O1 to O4 can be defined in the insulating layer PL through the openings O5 to O8, respectively. From another point of view, in this embodiment, in the normal direction n of the substrate 100, the openings O5 to O8 overlap with the openings O1 to O4, respectively. In this embodiment, the material of the mask pattern 204 may include a light blocking material, such as chromium, titanium, or molybdenum.

A pair of marking patterns 206 are disposed on the substrate 202. When the photomask 200 is used as a mask to perform a patterning process on the insulating layer PL, a pair of first auxiliary patterns 104 can be defined by a pair of marking patterns 206. From another point of view, in this embodiment, in the normal direction n of the substrate 100, a pair of marking patterns 206 and a pair of first auxiliary patterns 104 overlap. In this embodiment, the material of the pair of marking patterns 206 may include a light blocking material, such as chromium, titanium, or molybdenum.

In this embodiment, when the mask 200 is used as the mask to perform the patterning process on the insulating layer PL, from the above view angle (as shown by the dotted area in FIG. 2B), a pair of marking patterns 206 are located on the first A pair of marks 102 on both sides. As mentioned above, the pair of marking patterns 206 correspond to the pair of first auxiliary patterns 104, so the pair of first auxiliary patterns 104 are also located on both sides of the first alignment mark 102.

In addition, in this embodiment, from the above perspective (as shown by the dotted area in FIG. 2B), the orthographic projection of the side E3 of the marking pattern 206 on the substrate 100 is the same as the side E1 of the first alignment mark 102. There is the shortest distance d1 between the orthographic projections on the substrate 100, and the orthographic projection of the side E4 of the mark pattern 206 on the substrate 100 and the side E2 of the first alignment mark 102 on the orthographic projection of the substrate 100 have The shortest distance d2. When the photomask 200 is disposed on the substrate 100 in a correct and precise orientation for the patterning process, the shortest distance d1 and the shortest distance d2 are substantially equal. That is to say, when the patterning process is to be performed with the photomask 200 as a mask, the alignment can be performed by adjusting the position of the photomask 200 so that the shortest distance d1 and the shortest distance d2 are substantially equal to avoid affecting the patterning process. The precision. From another point of view, in this embodiment, the first alignment mark 102 and the pair of mark patterns 206 can be used as positioning marks of the photomask 200 used to perform the patterning process on the insulating layer PL.

Next, referring to FIGS. 2C and 3C at the same time, a pixel electrode PE is formed in the display area A of the substrate 100, and a plurality of second signal line segments L2 are formed in the peripheral area B of the substrate 100. In this embodiment, the pixel electrode PE and the second signal line segment L2 can belong to the same film layer, have substantially the same material, and can be formed in the same mask manufacturing process. In this embodiment, the material of the pixel electrode PE may include (but is not limited to): transparent metal oxide conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium Zinc oxide, other suitable oxides, or a stacked layer of at least two of the above.

In this embodiment, the pixel electrode PE is electrically connected to the drain D of the active device T through the opening O1. In detail, in this embodiment, the pixel electrode PE directly contacts the drain D of the active device T through the opening O1, as shown in FIG. 2C. In addition, in this embodiment, the pixel electrode PE and the active element T constitute the pixel unit U together.

In this embodiment, the second signal line segment L2 connects the first signal line segment L1 and the third signal line segment L3. In detail, in this embodiment, the second signal line segment L2 directly contacts the first signal line segment L1 through the opening O3, and the second signal line segment L2 directly contacts the third signal line segment L3 through the opening O4, as shown in FIG. 2C Shown. From another point of view, in this embodiment, the first signal line segment L1, the second signal line segment L2, and the third signal line segment L3 connected to each other together form the signal line L. Although FIG. 3C only shows two signal lines L, the present invention does not limit the number of signal lines L. According to the actual structure and requirements of the array substrate 10, the array substrate 10 may have more than three signal lines L. In addition, in this embodiment, the signal line L can be any peripheral signal line well known to those skilled in the art, such as a gate drive circuit, a source drive circuit, a power supply, or a timing controller circuit. Peripheral signal line for sexual connection.

In this embodiment, in the normal direction n of the substrate 100, the second signal line segment L2 of the signal line L overlaps the first auxiliary pattern 104. In other words, in this embodiment, a part of the signal line L is located in the marking area M and filled in the opening O2. From another point of view, in this embodiment, a part of the signal line L extends through the marking area M. Although FIG. 3C reveals that two signal lines L and a pair of first auxiliary patterns 104 overlap in the normal direction n of the substrate 100, the present invention is not limited to this. In one embodiment, in the normal direction n of the substrate 100, one signal line L overlaps with one of the pair of first auxiliary patterns 104. In another embodiment, in the normal direction n of the substrate 100, one signal line L overlaps with one of the pair of first auxiliary patterns 104, and the other signal line L overlaps with the first alignment mark 102 overlapping. In another embodiment, in the normal direction n of the substrate 100, a signal line L overlaps the first alignment mark 102. In still another embodiment, in the normal direction n of the substrate 100, the two signal lines L overlap with the first alignment mark 102. In still another embodiment, in the normal direction n of the substrate 100, a signal line L overlaps with one of the first alignment mark 102 and the pair of first auxiliary patterns 104. That is, in the array substrate 10, in the normal direction n of the substrate 100, as long as at least one of the signal lines L is in phase with at least one of the first alignment mark 102 and the pair of first auxiliary patterns 104 Overlap falls within the scope of the present invention.

After the foregoing process steps, the fabrication of the array substrate 10 can be roughly completed. It is worth noting that, in the array substrate 10, the first alignment mark 102, a pair of first auxiliary patterns 104, and a plurality of signal lines L are disposed in the peripheral area B of the substrate 100, and the pair of first auxiliary patterns 104 are located Both sides of the first alignment mark 102, and at least one of the signal line L overlaps with at least one of the first alignment mark 102 and a pair of first auxiliary patterns 104 in the normal direction n of the substrate 100 Therefore, the array substrate 10 can meet the requirements of narrow frame design. In other words, the array substrate 10 can simultaneously achieve the effect of having good accuracy due to the first alignment mark 102 in the patterning process using the photomask 200 as the mask, and the effect of increasing the space utilization of the peripheral area B.

In this embodiment, the array substrate 10 does not include a common electrode layer, but the invention is not limited to this. In other embodiments, the array substrate 10 may include a common electrode layer. Hereinafter, other implementation types will be described with reference to FIGS. 4A to 4E and FIGS. 5A to 5E. It must be noted here that the following embodiments follow the component symbols and part of the content of the foregoing embodiments, wherein the same or similar symbols are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

4A to 4E are flow cross-sectional views of a manufacturing method of an array substrate according to another embodiment of the present invention. 5A to 5E are top views of the process of a manufacturing method of an array substrate according to another embodiment of the present invention. The positions of the cross-sections in FIGS. 4A to 4E correspond to the positions of the cross-section lines I-I' and II-II' in FIGS. 5A to 5E. Fig. 4A and Fig. 5A are steps performed after Fig. 2B and Fig. 3B are continued. In addition, by performing all the steps shown in FIGS. 4A to 4E and FIGS. 5A to 5E, the fabrication of the array substrate 20 will be roughly completed, and the top view of the array substrate 20 can be referred to FIG. 1. The detailed description of manufacturing the array substrate 20 is as follows.

Referring to FIGS. 4A and 5A at the same time, a common electrode layer CM is formed in the display area A of the substrate 100, and a plurality of second signal line segments L2 are formed in the peripheral area B of the substrate 100. In this embodiment, the common electrode layer CM and the second signal line segment L2 can belong to the same film layer, have substantially the same material, and can be formed in the same photomask manufacturing process. In this embodiment, the material of the common electrode layer CM may include (but is not limited to): transparent metal oxide conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium Zinc oxide, other suitable oxides, or a stacked layer of at least two of the above.

In this embodiment, the common electrode layer CM has an opening O9, and the opening O9 exposes a part of the insulating layer PL, the opening O1, and the drain electrode D exposed by the opening O1. In other words, in this embodiment, in the normal direction n of the substrate 100, the opening O9 overlaps the opening O1. In addition, in this embodiment, the common electrode layer CM can be electrically connected to a common voltage, for example, about 0 volts.

In this embodiment, the second signal line segment L2 connects the first signal line segment L1 and the third signal line segment L3. In detail, in this embodiment, the second signal line segment L2 directly contacts the first signal line segment L1 through the opening O3, and the second signal line segment L2 directly contacts the third signal line segment L3 through the opening O4, as shown in FIG. 4A Shown. From another point of view, in this embodiment, the first signal line segment L1, the second signal line segment L2, and the third signal line segment L3 connected to each other together form the signal line L. Although FIG. 5A only shows two signal lines L, the present invention does not limit the number of signal lines L. According to the actual structure and requirements of the array substrate 20, the array substrate 20 may have more than three signal lines L. In addition, in this embodiment, the signal line L can be any peripheral signal line well known to those skilled in the art, such as a gate drive circuit, a source drive circuit, a power supply, or a timing controller circuit. Peripheral signal line for sexual connection.

In this embodiment, in the normal direction n of the substrate 100, the second signal line segment L2 of the signal line L overlaps the first auxiliary pattern 104. In other words, in this embodiment, a part of the signal line L is located in the marking area M and filled in the opening O2. From another point of view, in this embodiment, a part of the signal line L extends through the marking area M. Although FIG. 5A discloses that two signal lines L and a pair of first auxiliary patterns 104 overlap in the normal direction n of the substrate 100, the present invention is not limited to this. In one embodiment, in the normal direction n of the substrate 100, one signal line L overlaps with one of the pair of first auxiliary patterns 104. In another embodiment, in the normal direction n of the substrate 100, one signal line L overlaps with one of the pair of first auxiliary patterns 104, and the other signal line L overlaps with the first alignment mark 102 overlapping. In another embodiment, in the normal direction n of the substrate 100, a signal line L overlaps the first alignment mark 102. In still another embodiment, in the normal direction n of the substrate 100, the two signal lines L overlap with the first alignment mark 102. In still another embodiment, in the normal direction n of the substrate 100, a signal line L overlaps with one of the first alignment mark 102 and the pair of first auxiliary patterns 104. That is, in the array substrate 20, in the normal direction n of the substrate 100, as long as at least one of the signal lines L is in phase with at least one of the first alignment mark 102 and the pair of first auxiliary patterns 104 Overlap falls within the scope of the present invention.

Next, referring to FIG. 4B and FIG. 5B at the same time, an interlayer insulating layer IL2 is formed on the substrate 100 comprehensively. In other words, in this embodiment, the interlayer insulating layer IL2 is located in the display area A and the peripheral area B. In detail, in this embodiment, the interlayer insulating layer IL2 covers the common electrode layer CM, the second signal line segment L2 and the first alignment mark 102 and has an opening O10, wherein the opening O10 exposes part of the insulating layer PL, The opening O1 and the drain electrode D exposed by the opening O1. In other words, in this embodiment, the interlayer insulating layer IL2 is used to expose the drain electrode D. In addition, in this embodiment, the opening O10 overlaps the opening O1 in the normal direction n of the substrate 100. In this embodiment, the interlayer insulating layer IL2 may have a single-layer or multilayer structure. In this embodiment, the material of the interlayer insulating layer IL2 may include inorganic materials, organic materials, or other suitable materials. Inorganic materials include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride, for example; organic materials Examples include (but are not limited to): polyimide resin, epoxy resin or acrylic resin. In addition, in this embodiment, the method for forming the interlayer insulating layer IL2 may include: performing a patterning process after performing a physical vapor deposition process, a chemical vapor deposition process, or a coating process.

After forming the interlayer insulating layer IL2, a shielding layer 110 is formed in the peripheral area B of the substrate 100, and a signal line CL is formed in the display area A of the substrate 100. In this embodiment, the shielding layer 110 and the signal line CL can belong to the same film layer, have substantially the same material, and can be formed in the same photomask manufacturing process. In this embodiment, the material of the shielding layer 110 may include (but is not limited to): metals, alloys, nitrides of the foregoing materials, oxides of the foregoing materials, oxynitrides of the foregoing materials, and other non-metallic materials with conductive properties. Materials, or other suitable materials. From another point of view, in this embodiment, the shielding layer 110 does not belong to the same film layer as the scan line SL, the gate G, the data line DL, the source S and the drain D. As mentioned above, in the embodiments of FIGS. 4B and 5B, the shielding layer 110 and the signal line CL belong to the same film layer and have substantially the same conductive material, but the present invention is not limited to this. In other embodiments, the shielding layer 110 and the signal line CL may belong to different film layers and have different materials. For example, in one embodiment, the material of the shielding layer 110 is a non-conductive shielding material, and the material of the signal line CL is a conductive material, and the interlayer insulating layer IL2 may not be formed on the substrate 100 at this time.

Referring to FIG. 4B, in this embodiment, the shielding layer 110 is located on the second signal line segment L2. In other words, in this embodiment, the shielding layer 110 is disposed on the signal line L. On the other hand, in this embodiment, in the normal direction n of the substrate 100, the shielding layer 110 overlaps the first alignment mark 102 and the pair of first auxiliary patterns 104. In this way, in this embodiment, the shielding layer 110 can shield the first alignment mark 102 and the pair of first auxiliary patterns 104 to avoid the first alignment mark 102 and the pair of first auxiliary patterns that can be used as positioning marks 104 interferes with the subsequent patterning process.

In this embodiment, the signal line CL can be a common signal line. In this embodiment, the signal line CL can be electrically connected to a common voltage, for example, about 0 volts.

Next, referring to FIGS. 4C and 5C at the same time, an insulating layer BP is formed on the substrate 100. The insulating layer BP has an opening O10 and an opening O11. The opening O10 exposes a portion of the insulating layer PL, the opening O1 and the opening O1. Drain electrode D, opening O11 exposes part of shielding layer 110. In other words, in this embodiment, the insulating layer BP is located in the display area A and the peripheral area B and is disposed on the shielding layer 110. On the other hand, in this embodiment, in the normal direction n of the substrate 100, the opening O10 overlaps with the opening O1, and the opening O11 overlaps with the shielding layer 110. In this embodiment, the insulating layer BP may have a single-layer or multi-layer structure. In this embodiment, the material of the insulating layer BP may include inorganic materials, organic materials, or other suitable materials. Inorganic materials include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride; and organic materials such as Including (but not limited to): polyimide (PI), polyamic acid (PAA), polyamide (PA), polyvinyl alcohol (PVA), polyvinyl alcohol Cinnamate (polyvinyl cinnamate, PVCi), or suitable photoresist material. In addition, in this embodiment, the method for forming the insulating layer BP may include: performing a patterning process after performing a physical vapor deposition process, a chemical vapor deposition process, or a photoresist coating process.

Next, referring to FIG. 4D and FIG. 5D at the same time, the conductive material layer 120 is formed on the substrate 100 in an all-round way. In other words, in this embodiment, the conductive material layer 120 is located in the display area A and the peripheral area B. As shown in FIG. 4D, in the present embodiment, the conductive material layer 120 fills the opening O1, the opening O10, and the opening O11 to directly contact the drain D of the active device T, and fills the opening O12 to directly contact the shielding layer 110 . In this embodiment, the material of the conductive material layer 120 may include (but is not limited to): transparent metal oxide conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium Zinc oxide, other suitable oxides, or a stacked layer of at least two of the above. In addition, in this embodiment, the method for forming the conductive material layer 120 may include a chemical vapor deposition method or a physical vapor deposition method.

Next, a patterned photoresist layer 130 is formed on the conductive material layer 120. In this embodiment, the method for forming the patterned photoresist layer 130 may include the following steps: after a photoresist material layer (not shown) is formed on the conductive material layer 120, the photomask 300 is used as a mask, and the photoresist material The layer (not shown) undergoes a patterning process to form a patterned photoresist pattern 132 located in the display area A of the substrate 100, and a pair of patterned photoresist patterns 134 located in the peripheral area B of the substrate 100, wherein The patterning process may include exposure and development steps.

In this embodiment, the photomask 300 includes a substrate 302, a mask pattern 304, and a pair of marking patterns 306. The material of the substrate 302 may include (but is not limited to): glass, quartz or other applicable transparent materials. The mask pattern 304 is disposed on the substrate 302. When the photomask 300 is used as a mask and the photoresist material layer (not shown) is patterned, the patterned photoresist pattern 132 can be defined by the mask pattern 304. From another point of view, in this embodiment, the mask pattern 304 and the patterned photoresist pattern 132 overlap in the normal direction n of the substrate 100. In this embodiment, the material of the mask pattern 304 may include a light blocking material, such as chromium, titanium, or molybdenum.

A pair of marking patterns 306 are disposed on the substrate 302. When the photomask 300 is used as a mask and the photoresist material layer (not shown) is patterned, a pair of patterned photoresist patterns 134 can be defined by a pair of marking patterns 306. From another point of view, in this embodiment, in the normal direction n of the substrate 100, a pair of marking patterns 306 and a pair of patterned photoresist patterns 134 overlap. In this embodiment, the material of the pair of marking patterns 306 may include a light blocking material, such as chromium, titanium, or molybdenum.

In this embodiment, when the photomask 300 is used as the mask to perform the patterning process on the photoresist material layer (not shown), the above viewing angle (as shown in the dotted area in Figure 4D), a pair The marking pattern 306 is located on both sides of the opening O12. As mentioned above, a pair of marking patterns 306 corresponds to a pair of patterned photoresist patterns 134, so a pair of patterned photoresist patterns 134 are also located on both sides of the opening O12.

In addition, in this embodiment, from the above perspective (as shown by the dotted area in FIG. 4D), the orthographic projection of the side E7 of the marking pattern 306 on the substrate 100 and the side E5 of the opening O12 on the substrate 100 There is the shortest distance d3 between the orthographic projections of, and the shortest distance d4 between the orthographic projection of the side E8 of the marking pattern 306 on the substrate 100 and the orthographic projection of the side E6 of the opening O12 on the substrate 100. When the photomask 300 is disposed on the substrate 100 in a correct and precise orientation for the patterning process, the shortest distance d3 and the shortest distance d4 are substantially equal. In other words, when the photomask 300 is used as the mask for the patterning process, the position of the photomask 300 can be adjusted so that the shortest distance d3 and the shortest distance d4 are substantially equal to avoid affecting the patterning process. The precision. In view of this, in the present embodiment, in the patterning process performed by using the photomask 300 as a mask, the opening O12 serves as the second alignment mark 140. That is to say, in this embodiment, the second alignment mark 140 and the pair of mark patterns 306 can be used as positioning marks of the photomask 300 for patterning the photoresist material layer (not shown). In addition, although FIG. 4D reveals that the second alignment mark 140 (ie, the opening O12) completely overlaps the first alignment mark 102, the present invention is not limited to this. In one embodiment, the second alignment mark 140 (ie, the opening O12) may partially overlap the first alignment mark 102. In another embodiment, the second alignment mark 140 (ie, the opening O12) may not overlap the first alignment mark 102.

Next, referring to FIGS. 4D, 4E, 5D, and 5E at the same time, the patterned photoresist layer 130 including the patterned photoresist pattern 132 and a pair of patterned photoresist patterns 134 is used as a mask, and the conductive material layer 120 The etching process is performed to form the pixel electrode PE2 in the display area A of the substrate 100 and to form a pair of second auxiliary patterns 142 in the peripheral area B of the substrate 100. In other words, in this embodiment, the pixel electrode PE2 and the pair of second auxiliary patterns 142 may belong to the same film layer and have substantially the same material. In this embodiment, the material of the pixel electrode PE2 may include (but is not limited to): transparent metal oxide conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium Zinc oxide, other suitable oxides, or a stacked layer of at least two of the above.

In this embodiment, the pixel electrode PE2 is electrically connected to the drain D of the active device T through the opening O11, the opening O10, and the opening O1. In detail, in this embodiment, the pixel electrode PE2 directly contacts the drain electrode D of the active device T through the opening O11, the opening O10, and the opening O1, as shown in FIG. 4E. In addition, in this embodiment, the pixel electrode PE2 is structurally separated from the common electrode layer CM. In other words, in this embodiment, the pixel electrode PE2 and the common electrode layer CM can receive signals of different levels. In addition, in this embodiment, the pixel electrode PE2 has a plurality of slits J. When the array substrate 20 is applied to a display panel, a fringe electric field that can be used to drive the display medium is generated between the edge of the slit J and the common electrode layer CM. In addition, in this embodiment, the pixel electrode PE2 and the active element T constitute a pixel unit U.

In addition, in this embodiment, the pixel electrode PE2 is provided above the insulating layer BP, and the common electrode layer CM is provided below the insulating layer BP, but the present invention is not limited to this. In other embodiments, the pixel electrode PE2 may be disposed under the insulating layer BP, and the common electrode layer CM is disposed above the insulating layer BP and has a plurality of slits. At this time, the pixel electrode PE2 and the second signal line segment L2 can belong to the same film layer, have substantially the same material, and can be formed in the same photomask manufacturing process; while the common electrode layer CM and the pair of second auxiliary patterns 142 can belong to the same film layer and have substantially the same material. And can be formed in the same mask manufacturing process.

In this embodiment, a pair of second auxiliary patterns 142 are disposed on the insulating layer BP. As mentioned above, since the pair of patterned photoresist patterns 134 are located on both sides of the second alignment mark 140 (ie opening O12), the pair of second auxiliary patterns 142 are also located on the second alignment mark 140 (ie opening O12) on both sides.

After the aforementioned process steps, the fabrication of the array substrate 20 can be substantially completed. It is worth noting that in the array substrate 20, in the normal direction n of the substrate 100, the shielding layer 110 overlaps the first alignment mark 102 and the pair of first auxiliary patterns 104, and the second alignment mark 140 ( That is, the opening O12) overlaps the shielding layer 110, and a pair of second auxiliary patterns 142 are located on both sides of the second alignment mark 140 (ie, the opening O12), so that the array substrate 20 can meet the design requirements of a narrow frame. In other words, the array substrate 20 can simultaneously achieve the effect of having good accuracy due to the second alignment mark 140 (ie the opening O12) in the patterning process using the photomask 300 as the mask, and increasing the space utilization rate of the peripheral area B The effect of. For the rest, please refer to the foregoing implementation manners, and will not be repeated here.

To sum up, in the array substrate of the foregoing embodiments, a plurality of pixel units are arranged in the display area of the substrate, and the first alignment mark, a pair of first auxiliary patterns and a plurality of signal lines are arranged on the substrate In the peripheral area, a pair of first auxiliary patterns are located on both sides of the first alignment mark, and at least one of a plurality of signal lines and at least one of the first alignment mark and a pair of first auxiliary patterns They overlap in the normal direction of the substrate, so that the array substrate can meet the design requirements of a narrow frame.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

10, 20: Array substrate 100: substrate 102: First alignment mark 104: The first auxiliary pattern 110: Masking layer 120: Conductor material layer 130: patterned photoresist layer 132, 134: Patterned photoresist pattern 140: second alignment mark 142: Second auxiliary pattern 200, 300: mask 202, 302: base 204, 304: mask pattern 206, 306: marking pattern A: Display area B: Surrounding area BP, PL: insulating layer C: Drive circuit area CL, L: signal line CM: Common electrode layer CR: Channel area d1, d2, d3, d4: shortest distance D: Dip pole DL: Data line DR: Drain region E1, E2, E3, E4, E5, E6, E7, E8: side G: Gate GI: Gate insulation layer H1, H2, O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12: opening IL1, IL2: Interlayer insulation layer J: slit L1: The first signal line segment L2: second signal line segment L3: The third signal line segment M: Marked area n: normal direction PE, PE2: pixel electrode S: source SC: active layer SL: scan line SR: Source region T: Active component U: pixel unit

FIG. 1 is a schematic top view of an array substrate according to an embodiment of the present invention. 2A to 2C are flow cross-sectional views of a manufacturing method of an array substrate according to an embodiment of the present invention. 3A to 3C are top views of a process of a manufacturing method of an array substrate according to an embodiment of the present invention. 4A to 4E are flow cross-sectional views of a manufacturing method of an array substrate according to another embodiment of the present invention. 5A to 5E are top views of the process of a manufacturing method of an array substrate according to another embodiment of the present invention.

10: Array substrate

100: substrate

102: First alignment mark

104: The first auxiliary pattern

A: Display area

B: Surrounding area

CR: Channel area

D: Dip pole

DL: Data line

DR: Drain region

G: Gate

GI: Gate insulation layer

H1, H2, O1, O2, O3, O4: opening

IL1: Interlayer insulating layer

L: signal line

L1: The first signal line segment

L2: second signal line segment

L3: The third signal line segment

M: Marked area

n: normal direction

PE: pixel electrode

PL: insulating layer

S: source

SC: active layer

SL: scan line

SR: Source region

T: Active component

U: pixel unit

Claims (12)

An array substrate, including: A substrate having a display area and a peripheral area, the peripheral area is located on one side of the display area; A first alignment mark arranged in the peripheral area of the substrate; A pair of first auxiliary patterns are arranged in the peripheral area of the substrate, wherein the pair of first auxiliary patterns are located on both sides of the first alignment mark; A plurality of signal lines are arranged in the peripheral area of the substrate, wherein at least one of the signal lines and at least one of the first alignment mark and the pair of first auxiliary patterns are in a method of the substrate Overlap in the line direction; and A plurality of pixel units are arranged in the display area of the substrate. The array substrate described in item 1 of the scope of patent application further includes: a first insulating layer disposed on the display area and the peripheral area of the substrate, and each pixel unit includes: An active device including a gate, an active layer, a source and a drain; and a pixel electrode electrically connected to the drain of the active device, The first insulating layer covers the active element in each pixel unit. The array substrate described in item 2 of the scope of patent application, wherein: The material of the first alignment mark is the same as the material of the source electrode and the drain electrode, and A part of the first insulating layer serves as the pair of first auxiliary patterns. For the array substrate described in item 2 of the scope of patent application, each signal line includes a first signal line segment, a second signal line segment and a third signal line segment, and the second signal line segment connects the first signal line segment with the The third signal line segment, wherein the second signal line segment of at least one of the signal lines overlaps with at least one of the first alignment mark and the pair of first auxiliary patterns in the normal direction. The array substrate described in item 4 of the scope of patent application, wherein: The material of the first signal line segment is the same as the material of the source electrode and the drain electrode, The material of the third signal line segment is the same as the material of the source and the drain, and The material of the second signal line segment is the same as the material of the pixel electrode in each pixel unit. As described in the second item of the scope of patent application, the array substrate further includes a common electrode layer separated from the pixel electrode structure in each pixel unit. The array substrate described in item 6 of the scope of patent application further includes a shielding layer disposed on the signal lines, wherein the shielding layer, the first alignment mark and the pair of first auxiliary patterns are in the normal direction Overlap. The array substrate described in item 7 of the scope of patent application further includes: A second insulating layer disposed on the shielding layer, wherein the second insulating layer has an opening as a second alignment mark, and the second alignment mark overlaps the shielding layer in the normal direction; as well as A pair of second auxiliary patterns are disposed on the second insulating layer, wherein the pair of second auxiliary patterns are located on both sides of the second alignment mark. The array substrate described in item 8 of the scope of patent application, wherein: The pair of second auxiliary patterns have the same material as the common electrode layer and one of the pixel electrodes in each pixel unit, and A part of the first insulating layer serves as the pair of first auxiliary patterns. For the array substrate described in item 9 of the scope of patent application, each signal line includes a first signal line segment, a second signal line segment and a third signal line segment, and the second signal line segment connects the first signal line segment and the The third signal line segment, wherein the second signal line segment of at least one of the signal lines overlaps with at least one of the first alignment mark and the pair of first auxiliary patterns in the normal direction. The array substrate described in item 10 of the scope of patent application, wherein: The material of the first signal line segment is the same as the material of the source electrode and the drain electrode, The material of the third signal line segment is the same as the material of the source and the drain, and The second signal line segment has the same material as the other of the common electrode layer and the pixel electrode in each pixel unit. In the array substrate described in item 8 of the scope of patent application, the shielding layer, the source electrode and the drain electrode do not belong to the same film layer.

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