TWI693496B - Low dropout regulator and system thereof - Google Patents

Abstract

A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output of the low dropout regulator and a reference signal to produce a comparison result; a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result; an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.

Description

Low dropout voltage regulator and its system

The present invention relates to the field of circuit technology, and particularly to a differential pressure regulator and its system.

Low dropout voltage regulators are used in integrated circuits as a way to regulate the output voltage. Even when the output voltage is close to the supply voltage, low dropout regulators are often designed to produce a stable output voltage.

The invention provides a low-dropout voltage regulator and a system including the low-dropout voltage regulator, which can quickly adjust the output of the low-dropout voltage regulator according to the change of the output of the low-dropout voltage regulator.

A low-dropout voltage regulator that generates an output provided by an embodiment of the present invention may include: a comparison circuit configured to compare a signal representing the output of the low-dropout voltage regulator with a reference signal to generate a comparison result; a loop controller, coupled To the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result; and the output circuit, including two or more switching circuits, configured to adjust based on the output circuit control signal The number of switch circuits that are turned on among the two or more switch circuits.

A system provided by an embodiment of the present invention may include: a load circuit including a plurality of sub-circuits; a first low dropout voltage regulator, coupled to the first end of the load circuit, configured as Providing the first output of the first low dropout voltage regulator to the first end of the load circuit; and the second low dropout voltage regulator, coupled to the second end of the load circuit, configured to A second output of the second low dropout voltage regulator is provided to the second end of the load circuit; wherein the first low dropout voltage regulator is configured to send an indication to the second low dropout voltage regulator The first indication of the level change of the first output; wherein, the first low dropout voltage regulator is the low dropout voltage regulator described in each embodiment of the present invention.

As mentioned above, the low dropout voltage regulator and system provided by the embodiments of the present invention can compare the signal representing the output of the low dropout voltage regulator and the reference signal through a comparison circuit to generate a comparison result, and based on the The comparison result generates an output circuit control signal to adjust the number of switching circuits turned on in the output circuit of the low-dropout voltage regulator. Therefore, the low-dropout voltage regulator and system of the embodiments of the present invention can quickly respond to the output of the low-dropout voltage regulator. The change immediately adjusts the output of the low-dropout regulator. Further, when the low-dropout regulator is connected to the load circuit, the embodiment of the present invention can quickly adapt to the change in the impedance of the load circuit to adjust the output of the low-dropout regulator.

100: circuit board

140: encapsulated external parts

110: packaged parts

120, 300, 400, 620, 630: ILDO regulator

130, 610: load circuit

200: DAC system

260: Control circuit

210, 310: comparator

220, 320: pulse generator

230: loop controller

240: buffer circuit

250: switch circuit

330: First branch

340: The first branch

410, 510: timer check circuit

700: System

710, 720, 730: sub-circuit

FIG. 1 describes the circuit board 100 including the package component 110 and the package outer component 140.

FIG. 2A depicts an embodiment of ILDO regulator 200.

FIG. 2B shows an embodiment of the buffer circuit 240 and the switching circuit 250.

FIG. 3 depicts another embodiment of the ILDO regulator 300 including the first branch 330 and the second branch 340.

FIG. 4 depicts a single-branch ILDO regulator 400 including a timer check circuit 410.

Figure 5 depicts the dual-branch ILDO regulator 500.

FIG. 6 depicts a system 600 including a first ILDO regulator 620 and a second ILDO regulator 630 coupled across the load circuit 610.

FIG. 7 depicts a system 700 having a first ILDO 620 and a second ILDO 630 coupled across the load circuit 610.

Integrated low dropout (Integrated Low Dropout, ILDO) regulators may be an important part of many integrated circuit solutions. Ideally, the ILDO regulator can provide a controllable output voltage level that can approach the power supply voltage level while maintaining low ripple and low noise. The ILDO regulator can adjust its output according to the change in the impedance of the load circuit coupled to its output, so that it provides constant or near-constant power, voltage or current at the output. However, a typical ILDO regulator needs to be notified of changes in load conditions in advance, indicating that the load impedance will change at specific points in time to provide appropriate output regulation. When the load circuit needs to quickly adjust the current, voltage or power provided by the ILDO regulator, the ILDO regulator with the advance notification system may not provide sufficient control. In addition, if the notification signal is lost or delayed in advance, the ILDO regulator may not be able to provide the correct output voltage, current, or power level, and the voltage, current, or power level that the load circuit may receive is insufficient or too high. Typical ILDO regulators are usually synchronized to one clock cycle, which may introduce unnecessary delays when changing the output voltage or current provided because the ILDO regulator is adjusting its output voltage, current or power level You may have to wait for the clock edge. The present invention describes an ILDO regulator with an asynchronous control system, which can quickly adjust the output of the low dropout regulator according to changes in the output of the low dropout regulator (for example, changes in the impedance of the load circuit).

Before discussing the control system of the present invention, the existence of parasitics in the circuit associated with the ILDO regulator will be discussed. FIG. 1 describes the circuit board 100 including the package component 110 and the package outer component 140. The package component 110 may include an integrated low dropout (ILDO) regulator 120 coupled to the load circuit 130. The ILDO regulator 120 can provide its output to the load circuit 130. The package outer part 140 may have parasitic inductance, parasitic capacitance and/or parasitic resistance and an external power management integrated circuit (Power Management Integrated Circuit, PMIC). For example, an inductor outside the package may have parasitic capacitance between the winding turns of the inductor. In another example, the external capacitor may have parasitic resistance at various frequencies. In addition, the package component 110 and the coupling between the package and the non-package component may have a parasitic inductance, a parasitic capacitance, and/or a parasitic resistance through a similar mechanism. Any or all of the parasitic effects described herein may change over time. In addition, the impedance of the load circuit 130 may change with time. For example, if the load circuit 130 is coupled to another circuit, the reflected impedance from the coupling may change over time, thereby changing the impedance of the load circuit 130 seen by the ILDO regulator 120. In another example, the impedance 130 of the load circuit may vary due to time-varying parasitics within the load circuit 130. In some embodiments, the ILDO regulator 120 may be designed to provide load circuit 130 with power, voltage or current output, and changes in load impedance in a manner that mitigates parasitic effects. It should be understood that the external package component 140 shown in FIG. 1 is merely an example, and in some embodiments, the external package component may not be used. In some embodiments, no on-chip packaging components are used except for the ILDO regulator 120 and the load circuit 130.

The load circuit 130 may be any circuit that receives power, current, or voltage from the ILDO regulator 120. The impedance of the load circuit 130 may change with time due to many factors, such as changes in the size of the load or changes in parasitics. Therefore, as will be described in further detail below, in some embodiments, the ILDO regulator 120 can adapt to the impedance variations of the load circuit and the parasitic effects of the package component 110 and the external components 140.

FIG. 2A depicts an embodiment of ILDO regulator 200. The ILDO regulator 200 may include a control circuit 260 and a switching circuit 250. The control circuit 260 may receive the feedback signal VFB and the reference signal VREF1 at the comparator 210. VFB may be a signal indicating the voltage level at the output of the ILDO regulator 200 (that is, VFB may reflect changes in the impedance of the load circuit). For example, in some embodiments, VFB may be the output voltage of the ILDO regulator 200. In other embodiments, VFB may be a proportional representation of the output voltage of the ILDO regulator 200. In other embodiments, the feedback signal provided to the comparator 210 may represent the current or power provided to the load circuit. VREF1 can be a reference voltage, which can be pre- First set in the system's memory, set by the user of the system, or established by any suitable method. In other embodiments, the reference signal may be a reference current or power. The comparator 210 may compare the feedback signal and the reference signal and output a COMP signal indicating a state change between the two signals. For example, if VFB is initially lower than VREF1 and then becomes higher than VREF1, the comparator 210 may generate a first COMP signal indicating that the VFB state has changed. Alternatively, if VFB is initially higher than VREF1 and then becomes lower than VREF1, the comparator 210 may generate a second COMP signal that indicates a change in the VFB state that is different from the first COMP signal. For example, the first COMP signal may be a pulse with a first shape, first duration and/or first amplitude, and the second COMP signal may be a pulse with a second shape, second duration and/or second amplitude . In some embodiments, the first COMP signal and the second COMP signal may be different and may change in different states of VFB relative to VREF1 (eg, VFB falls below VREF1 or VFB rises above VREF1). Although voltage comparison is used as an example here, it should be understood that the comparison object may be current or power in a specific implementation. A change in the level of VFB relative to VREF1 (eg, VFB falling below VREF1 or VFB rising above VREF1) can be used to determine the change in the level of the output voltage provided by the ILDO regulator 200 to the load circuit. Therefore, the ILDO regulator 200 can adjust its output voltage to compensate for the level change of VFB relative to VREF1.

The output COMP of the comparator 210 may be sent to the pulse generator 220. The output COMP can cause the pulse generator 220 to generate pulses that can be sent to the loop controller 230. The pulse generator 220 may be suitable for generating a signal representing a state change detected by the comparator 210. In some embodiments, if the output COMP of the comparator 210 indicates that VFB has changed state higher than VREF1, the pulse generator 220 may generate a first type of pulse if the output COMP of the comparator 210 indicates that VFB has changed state low For VREF1, the pulse generator 220 can generate a second type of pulse. In some embodiments, the pulse generator 220 may generate the same pulse for any state change detected by the comparator 210. In such an embodiment, the comparator 210 may be connected to both the loop controller 230 and the pulse generator 220 so that when the loop controller 230 receives pulses from the pulse generator 220, it can be connected to The COMP signal generated by the comparator 210 is received to indicate a change in the level of VFB relative to VREF1 (that is, VFB becomes higher than VREF1, or VFB becomes lower than VREF1). It should be understood that in some embodiments, the pulse generator 220 may not be used, and the output of the comparator 210 may be passed to the loop controller 230. In such an embodiment, as will be described in further detail below, the level of the COMP signal can indicate the level of VFB relative to VREF1, and the loop controller 230 changes the state of the COMP signal by using the COMP signal Determines the number of enabled or disabled switches in the switch circuit 250.

The loop controller 230 may receive the signal PULSE from the pulse generator 220 and/or the signal COMP from the comparator 210 and determine the number of enabled or disabled switches in the switch circuit 250. In some embodiments where the loop controller 230 only receives the signal PULSE from the pulse generator 220, the signal PULSE may correspond to the state of the COMP output by the comparator 210. When COMP is at the first level, PULSE may correspond to the first pulse shape, first amplitude and/or first duration, when COMP is at the second level, PULSE may correspond to the second pulse shape, second amplitude and/or Or the second duration. In some embodiments where the loop controller receives both signals PULSE and COMP, regardless of the level of COMP, PULSE may be the same pulse shape, and loop controller 230 may be based on the level of COMP when the signal PULSE is received The number of enable switches in the switch circuit 250 is adjusted. In some embodiments where the loop controller 230 receives COMP instead of PULSE, when the signal COMP changes level, the loop controller 230 may adjust the number of enabled switches in the switch circuit 250. The number of enable switches in the switch circuit 250 may correspond to the level of the output voltage VOUT of the ILDO regulator 200. For example, if the loop controller 230 receives an indication that the feedback voltage VFB is lower than VREF1, the loop controller 230 may generate a signal to increase the number of switches enabled in the switching circuit 250 in order to increase the output of the ILDO regulator 200 Voltage. In such an example, if 5 switches are currently enabled in the switching circuit 250 and the loop controller 230 receives and indicates that VFB is low relative to VREF1, the loop controller 230 may generate a signal to enable the switching circuit 250 The sixth switch. Alternatively, the loop controller 230 may receive instructions regarding VFB and VREF1 An indication of the magnitude of the difference between them, and a proportional number of switches can be enabled in the switching circuit 250. In another example, if the loop controller 230 receives an indication that the feedback voltage VFB is higher than VREF1, the loop controller 230 may generate a signal to disable additional switches in the switching circuit 250 in order to reduce the ILDO regulator 200's The output voltage. In FIG. 2A, N switches are described in the switch circuit 250, where N is any positive integer greater than 1. The loop controller 230 may be any controller suitable for determining the number of switches in the switch circuit 250 and generating signals to enable these switches, such as a field programmable gate array (FPGA), a microprocessor, or a hardware logic circuit.

The signal from the loop controller 230 may pass through the optional buffer circuit 240 before reaching the switch circuit 250. The buffer circuit 240 may include N buffer amplifiers, and each buffer amplifier is connected from the loop controller 230 to a corresponding switch of the switch circuit 250. Therefore, each buffer amplifier of the buffer circuit 240 may provide a separate signal path between the loop controller 230 and each switch of the switch circuit 250. The buffer circuit 240 may adjust the impedance level seen by the output of the loop controller 230 and the input of the switch circuit 250 to drive the switch of the switch circuit 250.

The switching circuit 250 may include N switches controlled by the loop controller 230 for providing a conduction path between the high reference voltage VIN and the output VOUT of the ILDO regulator 200. The high reference voltage VIN can be provided by any known voltage source, such as a power supply or a battery. As shown in FIG. 1, the output VOUT of the ILDO regulator 200 can be connected to the load circuit.

FIG. 2B shows an embodiment of the buffer circuit 240 and the switching circuit 250. In this example, N is equal to 3, but N can use any positive integer greater than or equal to 2. The loop controller 230 provides three output signals, one for each switch in the switching circuit 250. The output signal from the loop controller 230 may pass through the buffer amplifier in the buffer circuit 240 before being connected to the control terminal (eg, gate) of the switch of the switch circuit 250. The switches in the switching circuit 250 may be connected in parallel so that more switches are turned on to produce a higher output voltage or current at VOUT, and more switches are turned off to produce a lower voltage at VOUT Output voltage, or current. It should be understood that the buffer magnification shown The configuration of the switch and the switch connection is just an example, and any suitable embodiment that allows the use of the loop controller 230 to control the switch in the switch circuit 250 can be implemented in the present invention.

In some embodiments, it may be necessary to provide multiple reference voltages so that the loop controller can adjust the output voltage related to the multiple reference voltages. Such an embodiment may allow the output voltage to remain within a range or ranges determined by multiple reference voltage levels. FIG. 3 depicts another embodiment of the ILDO regulator 300 including the first branch 330 and the second branch 340. The second branch 340 of the ILDO regulator 300 may include a second comparator 310 and a second pulse generator 320. The second comparator 310 may receive the feedback voltage VFB as the input signal and the second reference voltage VREF2. VREF2 and VREF1 are the same or different reference voltages. The comparator 310 may compare VFB and VREF2, and indicate the state change between the two signals through the signal COMP2. For example, if VFB is initially lower than VREF2 and then becomes higher than VREF2, the comparator 310 may generate a signal COMP2 indicating a state change. Alternatively, if VFB is initially higher than VREF2 and then becomes lower than VREF2, the comparator 310 may generate a signal COMP2 indicating that the state changes (VFB changes from lower than VREF2 to higher than VREF2. COMP2 and VFB generated from higher than VREF2 change COMP2 generated for VREF2 may have different duration, amplitude, etc.). The output COMP2 of the comparator 310 may reach the pulse generator 320 or the loop controller 230.

The state change detected and output by the comparator 310 may cause the pulse generator 320 to generate the pulse PULSE2, which may be sent to the loop controller 230. The pulse generator 320 may be any circuit suitable for generating a signal representing a change in state detected by the comparator 310. In some embodiments, if the comparator 310 detects that VFB has changed state above VREF2, the pulse generator 320 may generate a first type of pulse, and if the comparator 310 detects that VFB changes state below VREF2, then The pulse generator 320 may generate a second type of pulse. In some embodiments, the pulse generator 320 may periodically generate the pulse or signal PULSE2 unless the comparator 310 detects a change in the state of VFB relative to VREF2. In some embodiments, the pulse generator 320 may be Any change in the measured state produces the same pulse. It should be understood that in some embodiments, the pulse generator 320 may not be used, and the output COMP2 of the comparator 310 may be passed to the loop controller 230. In some embodiments, a pulse generator 320 may be used, and the output COMP2 of the comparator 310 may also be passed to the loop controller 230. In such an embodiment, if two state changes are detected, the loop controller 230 may use the outputs of the comparators 210 and 310 in combination with the outputs of the pulse generators 220 and 320 to determine the priority order of the controller. For example, if VFB starts below VREF1 and VREF2, but then rises rapidly to exceed VREF1 and VREF2, in this example, VREF2>VREF1, the loop controller 230 can determine that it should handle the event generated by the second branch 340, that is, the first The events on the second comparator 310 and the second pulse generator 320, because based on the relationship between the two reference voltages, processing the events on the second branch 340 will inherently satisfy the events on the first branch 330.

Although two branches 330 and 340 are depicted in FIG. 3, each branch serves as a signal chain that receives a signal indicating an output voltage or a reference voltage, and is used to generate an event detection signal and transmit it to the loop controller 230. It can be understood that the present invention Any number of branches can be used. The signal indicative of the output voltage may be a voltage or current signal with or without scaling to the output voltage. For example, three branches with three reference voltages may be used, or four branches with four reference voltages may be used. In addition, if a suitable comparator is used, a single branch can use multiple reference voltages. It should be understood that, in some embodiments, a single comparator may be used with two reference voltages VREF1 and VREF2 without using two comparators. The output of the comparator may be a tristate signal indicating the level of VFB compared to two reference voltages, or the comparator may have two outputs, each output indicating that VFB is compared to one of the two references Level.

The ILDO regulator 300 with two branches can be used to monitor the output voltage VOUT and keep it within predetermined limits. For example, VREF1 may be set to the lower limit voltage, and VREF2 may be set to the upper limit voltage. If it is specified that VOUT, which should be between VREF1 and VREF2 during system operation, increases due to various parasitic effects or load effects such that VFB exceeds the upper limit voltage VREF2, then compare The generator 310 will trigger an event and send a change indicating the state to the loop controller 230 and/or the pulse generator 320. If the comparator 310 sends a signal to the pulse generator 320, the pulse generator 320 will then generate and send a pulse corresponding to the change in the state of the comparator to the loop controller 230. The loop controller 230 will then reduce the number of switches turned on in the switching circuit 250 to reduce the output voltage VOUT. The number of disabled switches can be a fixed amount (for example, the loop controller disables an additional switch for each event), or it can be a proportional amount (for example, the loop controller disables VOUT compared to the reference The difference in voltage (ie, the number of switches where VOUT is greater than the reference voltage) is proportional to the number of switches). If VOUT drops due to various parasitic effects or load effects, causing VFB to fall below the lower limit voltage VREF1, the comparator 210 will trigger an event and send a signal indicating a state change to the loop controller 230 and/or the pulse generator 220. If the comparator 210 sends a signal to the pulse generator 220, the pulse generator 220 will then generate a pulse corresponding to the state change of the comparator 210 and send it to the loop controller 230. The loop controller 230 will then increase the number of turned-on switches in the switch circuit 250 to increase the output voltage VOUT. The number of switches that are turned on can be a fixed amount (for example, the loop controller enables an additional switch for each event), or it can be a proportional amount (for example, the loop controller disables VOUT compared to the reference The difference in voltage (ie, the number of switches where VOUT is smaller than the reference voltage) is proportional.

In some embodiments, it may be necessary to control the output voltage relative to a time reference. If the output voltage remains at a fixed level longer than the reference time, you may need to adjust the output voltage level to provide precise control of the output voltage level. For example, if the desired output voltage level is 0.70V, and the output voltage level remains at 0.69V for longer than a predetermined amount of time, it may be desirable to increase the output voltage level even if the resulting level is higher than 0.70V. The average output voltage over a period of time is close to 0.70V.

FIG. 4 depicts a single-branch ILDO regulator 400 including a timer check circuit 410. The timer check circuit 410 may include a time comparison circuit and an operation timer. In some embodiments, the operation timer may be separate from the timer check circuit 410, and the timer check circuit 410 may be The timer receives the timing signal. When the comparator 210 detects an event based on the relative value of the feedback voltage VFB and the reference voltage VREF1 (that is, the relative value of the feedback voltage VFB and the reference voltage VREF1 changes, for example, VFB changes from below VREF1 to above VREF1, or VFB When changing from above VREF1 to below VREF1), the comparator 210 may send an instruction to the timer check circuit 410 and the pulse generator 220 and the loop controller 230 (wherein at least one of the pulse generator 220 and the loop controller 230 is selected) The signal of the event. The timer check circuit 410 can compare the value of the operation timer when the event from the comparator 210 is received with the threshold time T1, and if the value of the operation timer is greater than the threshold time T1, it means that the output voltage VOUT remains at a single undesirable If the level is too long, the timer check circuit 410 can trigger the loop controller 230 to adjust the number of conducting switches in the switch circuit 250 accordingly (for example, when the comparator 210 detects that the feedback voltage VFB is less than the reference voltage VREF1 Low becomes higher than the reference voltage VREF1, and the value of the running timer is greater than the threshold time T1, then the timer check circuit 410 can trigger the loop controller 230 to reduce the number of conducting switches in the switching circuit 250 accordingly; on the contrary, when comparing The detector 210 detects that the feedback voltage VFB changes from being higher than the reference voltage VREF1 to being lower than the reference voltage VREF1, and the value of the running timer is greater than the threshold time T1, the timer checking circuit 410 can trigger the loop controller 230 to increase the switching circuit accordingly Number of conducting switches in 250;). In this embodiment, whenever the switch circuit 250 adjusts the number of its internally turned on switches according to the comparison result of the operation timer value and the threshold time T1, or whenever the timer check circuit 410 compares the operation timer value and the threshold value After time T1, the operation timer in the timer check circuit 410 may be reset, or the operation timer in the timer check circuit 410 may be reset when the comparison result of the comparator changes. The running timer may be any suitable timing circuit, such as an oscillator, clock input or counter. The threshold time may be a preset time to adjust the action of the loop controller 230. In addition, the timer check circuit 410 may also or alternatively receive the feedback voltage VFB from the comparator 210 or directly from the input of the ILDO regulator 400. Therefore, if the timer check circuit 410 detects that VFB is at a constant undesired level for a time exceeding the threshold T1, the timer check circuit 410 may trigger the loop controller 230 to adjust the number of turned-on switches in the switch circuit 250 accordingly , Even if the comparator did not cause something (For example, if the timer check circuit 410 detects that VFB is at a constant, too low voltage level for more than T1, it can trigger the loop controller 230 to increase the number of conducting switches in the switching circuit 250 accordingly; instead, If the timer check circuit 410 detects that VFB is at a constant excessively high voltage level for more than T1, the loop controller 230 may be triggered to reduce the number of conducting switches in the switching circuit 250 accordingly;). Time-based control allows finer control of the output voltage VOUT of the allowed system. The specific approach is to first change the output voltage VOUT by using a voltage level based on a comparison relationship, and then readjust with time based on timer control The voltage level of the output voltage VOUT. Therefore, in an embodiment of the present invention, a timer check circuit can be used to prevent the output voltage VOUT from remaining at a single undesirable level longer than a certain period of time. For example, it is acceptable for the output voltage to be slightly higher or lower than the desired output voltage in a short period of time, but it is undesirable for the output voltage to remain at this voltage level that is higher or lower than the desired level.

Figure 5 depicts a dual-branch ILDO regulator 500, where each branch has a timer check circuit. The working principle of the first branch including the comparator 210, the timer check circuit 410, the pulse generating circuit 220, and the loop controller 230 is the same as that in FIG. 4 and will not be repeated here. This embodiment only discusses the working principle of the second branch including the comparator 310, the timer check circuit 510, the pulse generation circuit 320, and the loop controller 230. Specifically, when the comparator 310 is based on the feedback voltage VFB and the reference voltage VREF2 The relative value detects an event (that is, the relative value of the feedback voltage VFB and the reference voltage VREF2 changes, for example, VFB changes from below VREF2 to above VREF2, or VFB changes from above VREF2 to below VREF2). The generator may send a signal indicating the event to the timer check circuit 510 and the pulse generator 320 and the loop controller 230 (wherein at least one of the pulse generator 320 and the loop controller 230 may be selected for transmission). The timer check circuit 510 can compare the value of the operation timer when the event from the comparator 310 is received with the threshold time T2, if the value of the operation timer is greater than the threshold time T2, it means that the output voltage VOUT remains at a single undesirable Is too long, the timer check circuit 510 can trigger the loop controller 230 to adjust the number of conducting switches in the switch circuit 250 accordingly (For example, when the comparator 310 detects that the feedback voltage VFB changes from being lower than the reference voltage VREF2 to being higher than the reference voltage VREF2, and the value of the running timer is greater than the threshold time T2, the timer check circuit 510 can trigger the loop controller 230 accordingly reduces the number of turned-on switches in the switching circuit 250; on the contrary, when the comparator 310 detects that the feedback voltage VFB changes from higher than the reference voltage VREF2 to lower than the reference voltage VREF2, and the value of the running timer is greater than the threshold time T2, then the timer check circuit 510 can trigger the loop controller 230 to increase the number of conducting switches in the switch circuit 250 accordingly;). In this embodiment, whenever the switch circuit 250 adjusts the number of its internally turned on switches according to the comparison result of the operation timer value and the threshold time T2, or whenever the timer check circuit 510 compares the operation timer value and the threshold value After time T2, the operation timer in the timer check circuit 510 may be reset. The running timer can be any suitable timing mechanism, such as an oscillator, clock input, or counter. As described above, the threshold time may be a preset time to adjust the action taken by the loop controller 230. In addition, the timer check circuit 510 may alternatively receive the feedback voltage VFB from the comparator 310 or directly receive the feedback voltage VFB from the input of the ILDO regulator 500. Therefore, if the timer check circuit 510 detects that VFB is at a constant undesired level for a time exceeding the threshold T2, the timer check circuit 510 may trigger the loop controller 230 to adjust the number of turned-on switches in the switch circuit 250 accordingly Even if the comparator does not cause an event (for example, if the timer check circuit 510 detects that VFB is at a constant too low voltage level for more than T2, the loop controller 230 may be triggered to increase the conduction in the switch circuit 250 accordingly The number of switches; on the contrary, if the timer check circuit 510 detects that VFB is at a constant excessively high voltage level for more than T2, the loop controller 230 can be triggered to reduce the number of conducting switches in the switch circuit 250 accordingly; However, in a plurality of timer check circuits, the interval of the plurality of timer check circuits may be set to adjust the action taken by the loop controller 230. For example, if T1 is less than T2, in the case where the running timer reaches T1 and VOUT is at an undesirable level, the loop controller 230 may set the number of turned-on switches to the first configuration. If the operation timer reaches the time between T1 and T2 and VOUT is at an undesirable level, the loop controller 230 may set the number of turned-on switches to the second configuration. Although in Figure 5 two separate timer check circuits 410 and 510 are described. It should be understood that the two timer check circuits can be implemented as a single timer check circuit with multiple inputs and thresholds. In addition, it should be understood that although two branches are described in FIG. 5. Any number of branches and timer check circuits can be used to provide finer control of the output voltage VOUT.

Furthermore, in another embodiment, an ILDO regulator 500 with two branches can be used to monitor the output voltage VOUT and keep it within predetermined limits. For example, VREF1 may be set to the lower limit voltage, and VREF2 may be set to the upper limit voltage. If it is specified that VOUT, which should be between VREF1 and VREF2 during system operation, increases due to various parasitic effects or load effects, such that VFB is lower than the lower limit voltage VREF1, the comparator 210 will trigger an event and send a change indicating the state to the timer The inspection circuit 410 and the loop controller 230 and the pulse generator 220 (wherein at least one of the pulse generator 220 and the loop controller 230 is selected). The timer check circuit 410 can compare the value of the operation timer when the event from the comparator 210 is received with the threshold time T1, if the value of the operation timer is greater than the threshold time T1, it means that the output voltage VOUT remains below VREF1 If the time of a certain undesired level is too long, the timer check circuit 410 can trigger the loop controller 230 to increase the number of conducting switches in the switching circuit 250 accordingly. In this embodiment, whenever the switch circuit 250 adjusts the number of its internally turned on switches according to the comparison result of the operation timer value and the threshold time T1, or whenever the timer check circuit 410 compares the operation timer value and the threshold value After time T1, the operation timer in the timer check circuit 410 may be reset. If it is specified that VOUT, which should be between VREF1 and VREF2 during system operation, increases due to various parasitic effects or load effects so that VFB exceeds the upper limit voltage VREF2, the comparator 310 will trigger an event and send a state change indication to the timer check The circuit 510 and the loop controller 230 and the pulse generator 320 (wherein at least one of the pulse generator 320 and the loop controller 230 is selected). The timer check circuit 510 can compare the value of the operation timer when the event from the comparator 310 is received with the threshold time T2. If the value of the operation timer is greater than the threshold time T2, it means that the output voltage VOUT remains greater than VREF2. If the time of an undesired level is too long, the timer check circuit 510 can trigger The road controller 230 accordingly reduces the number of conducting switches in the switching circuit 250. In this embodiment, whenever the switch circuit 250 adjusts the number of its internally turned on switches according to the comparison result of the operation timer value and the threshold time T2, or whenever the timer check circuit 510 compares the operation timer value and the threshold value After time T2, the operation timer in the timer check circuit 510 may be reset. In a specific implementation, the threshold times T1 and T2 may be the same or different.

In some embodiments, the load circuit at the output of the ILDO regulator may include a mesh circuit. In this case, supplying the output of the ILDO regulator to one end of the mesh circuit may cause uneven power, voltage, or current distribution across the load circuit. Described here is a system with multiple ILDO regulators to provide power, voltage or current at multiple points in the load circuit, where the ILDO regulators can communicate to maintain system stability or otherwise Improve control of the system.

FIG. 6 depicts a system 600 including a first ILDO regulator 620 and a second ILDO regulator 630 coupled across the load circuit 610. In an embodiment where the load circuit 610 is equivalent to a resistance grid, if a single ILDO regulator is used and connected to one side of the load circuit 610, the grid may cause the voltage from the ILDO regulator to be on the load circuit 610 Dissipated unevenly, leading to inefficient operation and high power loss. Therefore, the system 600 uses a first ILDO regulator 620 on the first side of the load circuit 610 and a second ILDO regulator 630 on the second side of the load circuit 610. By providing equal voltages on separate sides of the load circuit 610, the voltage dissipation across the grid can be reduced, and more uniform power consumption can be achieved. However, if the first ILDO regulator 620 and the second ILDO regulator 630 independently supply voltage to the grid, if the output voltage is not adjusted in a synchronized manner, the output voltages may suppress each other.

FIG. 7 depicts a system 700 having a first ILDO 620 and a second ILDO 630 coupled across the load circuit 610. The load circuit 610 includes N sub-circuits arranged in the mesh network (regardless of the number of switches in the ILDO switching circuit), where N is a positive integer greater than or equal to 1. Each sub-circuit 710, 720 and 730 may serve as a sub-circuit within the load circuit 610 coupled to the first ILDO 620 and the second ILDO 630, but if the first ILDO regulator 620 and the second ILDO regulator 630 operate independently, Each The resistance value between the sub-circuits 710, 720 and 730 may cause uneven power consumption across these sub-circuits. Therefore, the first ILDO regulator 620 and the second ILDO regulator 630 may exchange control signals through the communication channel. For example, in a unidirectional embodiment, the loop controller of the first ILDO regulator 620 may receive signals from the comparator, pulse generator, and/or timer check circuit of the second ILDO regulator 630. Therefore, if the second ILDO regulator 630 detects that the event on the second side of the load circuit 610 does not occur on the first side of the load circuit 610, the first ILDO regulator 620 may be notified and the first ILDO is stable The loop controller of the voltage regulator 620 may change the number of turned-on switches to adjust the output voltage of the first ILDO regulator 620 and prevent the damping effect from occurring through the uneven voltage applied to the load circuit 610. In another bidirectional embodiment, both ILDOs 620 and 630 can check circuits based on their timers, pulse generators and/or comparators transmit event information to each other to maintain a synchronized voltage output to the load circuit 610. Although two ILDOs are described in Figures 6 and 7, it should be recognized that any number of ILDOs can be applied to the load circuit and synchronized.

For this reason, the data structure and the mentioned code disclosed in the present invention can be stored in whole or in part in a computer-readable storage medium, hardware module or hardware device. The computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic or optical storage devices (eg, hard disks, magnetic tapes, optical drives, digital optical drives), or other current Media that is known or will be developed in the future and has the ability to store code and/or materials. The hardware modules or hardware devices disclosed in the present invention include, but are not limited to, dedicated integrated circuits (Applications-Specific Integrated Circuits, ASICs), field-programmable gate arrays (FPGAs), dedicated Or shared processors, and other hardware modules or devices that are currently known or will be developed in the future.

Although the embodiments of the present invention are described through a part of the embodiments, the present invention is not limited to the specific forms described herein. To be precise, the scope of the present invention is limited only by the corresponding patent application. In addition, although one feature may only be described in one specific embodiment, those skilled in the art may know that, with reference to the present invention, multiple features in the described embodiments may be grouped Together. In the scope of the patent application, the term "comprising" does not exclude the presence of other elements or steps.

Further, although individual features may be included in different patent applications, these features may be combined as advantageously as possible, and inclusion in different patent applications does not mean that a combination of features is not feasible and/or Adverse. In addition, the features included in the scope of one type of patent application do not mean to be limited to that category. On the contrary, it means that according to the actual situation, these features can also be applied to the scope of other types of patent application.

The use of ordinal numbers such as "first", "second", and "third" in the scope of the patent application to modify an element does not imply any priority, priority order, sequence between elements, or execution The chronological order of the methods, but only used as an identifier to distinguish different elements with the same name (with different ordinal numbers).

Certain terms are used in the specification and patent application scope to refer to specific elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and the scope of patent application do not use the difference in names as the way to distinguish the components, but the differences in the functions of the components as the criteria for distinguishing. The "include" and "include" mentioned in the entire specification and the scope of patent application are open terms, so they should be interpreted as "including but not limited to". "Generally" means that within the acceptable error range, those skilled in the art can solve the technical problem within a certain error range and basically achieve the technical effect. In addition, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if it is described that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting means Device. The following is a preferred mode for implementing the present invention, the purpose of which is to illustrate the spirit of the present invention and not to limit the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art in this field can act as a person without departing from the spirit and scope of the present invention. There are some changes and modifications, so the scope of protection of the present invention shall be subject to the scope defined by the patent application. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

200: DAC system

260: Control circuit

210: comparator

220: pulse generator

230: loop controller

240: buffer circuit

250: switch circuit

Claims (18)

An output low-dropout voltage regulator includes: a comparison circuit configured to compare a signal representing the output of the low-dropout voltage regulator with a reference signal to produce a comparison result; a loop controller coupled to the comparison circuit, Is configured to generate an output circuit control signal based at least in part on the comparison result; a switch circuit is configured to adjust the number of turned-on switches in the switch circuit based on the output circuit control signal; and coupled in the A buffer circuit between the loop controller and the switch circuit, wherein the buffer circuit is configured to turn on/off the switch in the switch circuit based on the output circuit control signal. The low-dropout voltage regulator according to patent scope 1, wherein the comparison circuit is coupled to the loop controller through a pulse generator configured to generate pulses according to changes in the comparison result, Wherein the loop controller is configured to generate the output circuit control signal based on the pulse. The low-dropout voltage regulator according to patent application scope 2, wherein the pulse generator is configured to generate a first type of pulse when the output is greater than the reference signal, and when the output is less than the reference signal A second type of pulse is generated. The low dropout voltage regulator according to patent scope 1, wherein the loop controller is configured to generate an output circuit control signal that enables at least one of the switch circuits when the output is less than the reference signal ;or The loop controller is configured to generate an output circuit control signal that disables at least one of the switch circuits when the output is greater than the reference signal. The low-dropout voltage regulator according to patent scope 1 further includes: a timer check circuit configured to, when the comparison result of the comparison circuit changes, run the execution time of the timer when the comparison result changes The first reference time is compared to generate a time check signal. The low dropout voltage regulator according to patent scope 5, wherein the loop controller is further configured to generate the output circuit control signal based on the time check signal, wherein when the time check signal indicates the execution time When the first reference time is exceeded, the output circuit control signal is generated. The low-dropout voltage regulator according to patent application scope 5 or 6, wherein: the execution time is reset after the output circuit adjusts the number of turned-on switches; or the execution time is reset by the timer check circuit The execution time is reset after comparing with the first reference time; or the execution time is reset when the comparison result of the comparator changes. The low-dropout voltage regulator according to patent scope 1, wherein the comparison circuit is a first comparison circuit, the reference signal is a first reference signal, and the comparison result generated by the comparison circuit is a first comparison result , The low dropout voltage regulator further includes: a second comparison circuit configured to compare the signal representing the output of the low dropout voltage regulator with a second reference signal to produce a second comparison result, wherein the loop control Further coupled To the second comparison circuit and configured to generate the output circuit control signal based at least in part on the first comparison result and the second comparison result. The low-dropout voltage regulator according to patent application scope 8, further comprising: a second pulse generator coupled between the second comparison circuit and the pulse generator, the second pulse generator being configured as The second pulse is generated according to the change of the second comparison result. The low-dropout voltage regulator according to patent scope 8 further includes: a first timer check circuit configured to change the first comparison result when the comparison result of the first comparison circuit changes A first execution time of an operation timer is compared with a first reference time to generate a first time check signal; and a second timer check circuit is configured to, when the comparison result of the second comparison circuit changes, When the second comparison result changes, the second execution time of the second operation timer is compared with the second reference time to generate a second time check signal. The low-dropout voltage regulator according to patent scope 8, wherein the loop controller is further configured to generate the output circuit control signal based on the first time check signal and/or the second time check signal; When the first time check signal indicates that the first execution time exceeds the first reference time, an output circuit control signal is generated based on the first comparison result; wherein when the second time check signal indicates When the second execution time exceeds the second reference time, an output circuit control signal is generated based on the second comparison result. The low-dropout voltage regulator according to patent application scope 10 or 11, wherein the first execution time and the second execution time are reset after the output circuit adjusts the number of turned-on switches. The low dropout voltage regulator according to patent application scope 10 or 11, wherein the first execution time is reset after the first timer check circuit compares the first execution time with a first reference time; The second execution time is reset after the second timer check circuit compares the second execution time with a second reference time. The low-dropout voltage regulator according to patent application scope 8, wherein the loop controller is configured to generate a signal that enables at least one switch in the switch circuit when the output signal is less than the first reference signal An output circuit control signal, and an output circuit control signal that disables at least one of the switch circuits when the output signal is greater than the second reference signal. A system with a low-dropout voltage regulator includes: a load circuit including a plurality of sub-circuits; a first low-dropout voltage regulator coupled to a first end of the load circuit and configured to reduce the first low voltage The first output of the differential regulator is provided to the first end of the load circuit; and the second low-dropout regulator, coupled to the second end of the load circuit, is configured to apply the second low voltage The second output of the differential voltage regulator is provided to the second end of the load circuit; wherein the first low-dropout voltage regulator is configured to send to the second low-dropout voltage regulator an indication of the first output The first indication of the level change; wherein, the first low dropout voltage regulator is the low voltage as described in any one of patent applications 1-14 Poor voltage regulator. The system according to patent scope 15, wherein the second low dropout voltage regulator is configured to provide the second output based on the first indication to synchronize the second output with the first output . The system according to patent application scope 15, wherein the second low dropout voltage regulator is configured to send a second indication indicating a change in the level of the second output voltage to the first low dropout voltage regulator, The second low-dropout voltage regulator is the low-dropout voltage regulator according to any one of patent applications 1-14. The system according to patent scope 17, wherein the first low dropout voltage regulator is configured to provide the first output based on the second indication to synchronize the first output with the second output .

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