JP5928867B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply apparatus that converts an input DC voltage into another DC voltage and outputs the converted DC voltage.

FIG. 6 is a diagram showing a general configuration of a conventional switching power supply device including a flyback DC / DC converter. In FIG. 6, one end of the primary winding P1 of the transformer T is connected to the DC input terminal DCIN, and the other end is connected to the drain of the switching element Q1 made of a MOSFET. The source of the switching element Q1 is grounded via a switching current detection resistor Rs, and the gate is connected to the output terminal Q of the flip-flop FF.
The flip-flop FF turns on and off the switching element Q1. A snubber circuit including a diode Dd, a capacitor Cd, and a resistor Rd for absorbing surge energy is connected between the drain and the DC input terminal of the switching element Q1.

  A rectifying / smoothing circuit including a diode D and an output capacitor Co is connected to the secondary winding S1 of the transformer T. The anode of the diode D is connected to one end of the secondary winding S1, and the other end of the secondary winding S1 is grounded. The cathode of the diode D is grounded via the output capacitor Co and is connected to the DC output terminal DCOUT.

  The DC output terminal DCOUT is connected to the inverting input terminal (−) of the operational amplifier OP provided on the secondary side. The non-inverting input terminal (+) of the operational amplifier OP is connected to the reference voltage for setting the output voltage. The operational amplifier OP amplifies the error between the voltage at the DC output terminal DCOUT and the reference voltage for setting the output voltage, and outputs it as a feedback signal FB to the non-inverting input terminal (+) of the comparator CMP1. An inverting input terminal (−) of the comparator CMP1 is connected to a connection point between the source of the switching element Q1 and the resistor Rs, and a voltage OCP generated in the resistor Rs is input thereto. The output of the comparator CMP1 is sent to the reset terminal R of the flip-flop FF via the inverter 20 and the AND circuit 21. The flip-flop FF is set by a set signal S from the one-shot circuit 11 and is reset by a reset signal R obtained by ORing the signals from the inverter 20 or the one-shot circuit 12 by an OR circuit 21.

  The oscillator OSC generates a switching frequency and a maximum on-pulse, and inputs the switching frequency and the maximum on-pulse from the one-shot circuit 11 to the set terminal of the flip-flop FF with a rising edge pulse, and inputs them to the reset terminal through the OR circuit 21 with a falling edge pulse.

  Next, the operation of the conventional switching power supply device configured as described above will be described. FIG. 7 is a timing chart showing the operation of the conventional switching power supply device. When the flip-flop FF is set by the set signal S, the switching element Q1 is turned on. A current flows through a route of DCIN → P1 → Q1 → Rs → ground (GND), and the value of this current gradually increases. Thereby, voltage OCP also rises gradually.

  When the level of the voltage OCP becomes higher than the level of the feedback signal FB from the operational amplifier OP, the signal output from the comparator CMP1 and passing through the inverter 20 becomes H level, and the reset signal R is reset via the OR circuit 21 to the flip-flop FF. Output to terminal R. When the flip-flop FF is reset by the reset signal R, the switching element Q1 is turned off. Further, since the path of the input current is cut, the value of the input current becomes zero, and thus the voltage OCP becomes zero. Furthermore, since the voltage OCP becomes zero, the signal output from the comparator CMP1 and passing through the inverter 20 changes to L level, and the reset signal R becomes pulsed.

  While the switching element is on, energy is accumulated in the primary winding P1 of the transformer T. When the switching element is turned off, a DC output voltage is output by a rectifying and smoothing circuit including a diode D and a capacitor Co, and power is supplied to a load (not shown). Is supplied.

  When the switching element OFF time elapses and the energy of the transformer T accumulated during the switching element ON period is released, the voltage of the primary winding P1 starts free oscillation, so the voltage VDS gradually decreases. Come. Here, the next on-pulse signal is generated from the oscillator OSC, and the one-shot circuit 11 generates a set signal S having a predetermined width by using the rising edge of the signal from the oscillator OSC as a trigger and inputs it to the S terminal of the flip-flop FF. To do. Thereby, the flip-flop FF is set, and the switching element Q1 is turned on. Thereafter, the above-described operation is repeated.

As described above, the PWM flyback converter controls the on-pulse width by changing the switching on-duty according to the output power. That is, in a load state where the output power is constant (does not change), the switching on / off duty is fixed according to the constant power.
However, if the switching frequency is changed to generate jitter at the switching frequency, there is a response delay in the feedback system, so the on-pulse width cannot be changed in accordance with the switching cycle.
For example, in the case of jitter that increases the switching period T shown in FIG. 8 to twice the switching period 2T, the duty of the on-pulse becomes relatively short with respect to the switching period 2T, and 1 / per cycle. Only output power of 2 can be supplied. During the jitter period, the output voltage decreases by t2, and when the jitter period t2 returns to the predetermined period t1, the output voltage increases, and thus the ripple voltage increases.

  In response to this problem, a power supply circuit that gradually varies the switching frequency (oscillation frequency) using a variable frequency oscillator and changes the feedback voltage according to the switching frequency can reduce the response delay of the feedback control. Since the switching current corresponding to the switching frequency can be passed without any influence, an increase in the ripple voltage can be suppressed.

  As a related technique, Patent Document 1 adds a clock oscillator, a pattern generator, and an attenuator circuit component to a general-purpose circuit of a switching regulator. In accordance with the change of the oscillation frequency, the feedback control voltage changes the impedance of the attenuator circuit to stably supply the output power and suppress the ripple voltage. As a result, a switching power supply device that can greatly reduce switching noise and improve ripple voltage is disclosed.

US Pat. No. 7,184,283

However, the jitter type flyback converter circuit used in the above-described conventional switching power supply device speeds up the response by intentionally changing the impedance of the feedback control voltage. Accordingly, in order to finely adjust the variable width, n a plurality of attenuator elements synchronized with the plurality of output signals Mn of the pattern generator are required, resulting in a large-scale configuration.
In addition, when the number of output signals Mn of the pattern generator is reduced to several, it is necessary to narrow the oscillation frequency jitter range or to speed up the response of the feedback control system, thereby reducing the EMI noise reduction effect. Or the stability of the feedback control system will be lost.

  An object of the present invention is to provide a switching power supply device capable of obtaining a stable ripple voltage without reducing EMI noise and losing stability of a feedback control system.

In order to solve the above problem, a switching power supply according to the present invention includes a series circuit in which a primary winding of a transformer and a switching element are connected in series at both ends of a DC power supply,
A control circuit for turning on and off the switching element;
A rectifying / smoothing circuit for rectifying and smoothing the voltage generated in the secondary winding of the transformer;
An error amplification circuit that amplifies an error voltage between the output voltage of the rectifying and smoothing circuit and a reference voltage and outputs the amplified error voltage to the control circuit;
The control circuit includes:
A signal generator for generating a signal for turning on and off the switching element;
A counter that counts the number of times the switching element is turned on by a signal output from the signal generator;
A frequency subtractor that subtracts on / off of the switching element each time the count value by the counter reaches a predetermined value;
A delay that controls the signal generator by switching the delay time so that a signal for turning off the switching element is output after being delayed from the signal output from the signal generator immediately before being subtracted by the frequency subtractor. And a time switching circuit.

  According to the present invention, jitter can be generated in the oscillation frequency (switching period) at predetermined intervals, noise can be reduced, and a ripple voltage can be stably obtained.

It is a block diagram which shows the structure of the switching power supply device which concerns on Example 1 of this invention. It is a timing chart which shows operation | movement of the switching power supply apparatus which concerns on Example 1 of this invention. It is a circuit diagram which shows in detail an example of the delay time switching circuit of the switching power supply device concerning Example 1 of this invention. It is a block diagram which shows the structure of the switching power supply which concerns on Example 2 of this invention. It is a circuit diagram which shows in detail the example of the delay time switching circuit based on Example 2 of this invention. It is a figure for demonstrating the conventional switching power supply device. It is a timing chart which shows operation | movement of the conventional switching power supply apparatus. It is a switching current waveform at the time of performing jitter operation | movement with the conventional switching power supply device.

  Hereinafter, a switching power supply according to an embodiment of the present invention will be described in detail with reference to the drawings.

  In the present invention, the switching frequency in the switching power supply apparatus that performs feedback control based on the switching current is forcibly switched, but the on-duty is relatively prevented from changing due to switching of the switching frequency. Here, switching of the switching frequency is performed by counting the number of pulse signals generated from the oscillator, generating a pulse signal thinned out from the number of original pulse signals every predetermined number, and changing the switching frequency of the switching element. . At the same time as generating the thinned pulse signal, a predetermined delay time is added to the on-pulse of the pulse signal to correct the on-duty so as not to change.

1 is a diagram illustrating a configuration of a switching power supply apparatus according to a first embodiment of the present invention. In addition,
In Figure 1, the description is omitted the same reference numeral is applied to the conventional switching power supply device of the same portion shown in FIG. 6, illustrating the different portions from the conventional switching power supply device illustrated in FIG 6.

Switching power supply according to a first embodiment of the present invention, the conventional switching power supply shown in FIG. 6, the frequency subtracter 30 and the delay time switching circuit 22 is added.

The frequency subtractor 30 counts the number of pulse signals generated from the oscillator OSC, and generates a pulse signal that is thinned out from the number of original pulse signals every predetermined number.
As shown in FIG. 1, the frequency subtractor 30 includes a counter A, a counter B, and a switch 33. The counter A has a function of, for example, dividing by 2, and turns on and off the switch 33 by the output of the counter A. The pulse signal generated from the oscillator OSC is output to the set terminal of the flip-flop FF via the switch 33 by the operation of the counter A. For example, the counter B has a function of setting and resetting the counter A every 10 counts, and the output of the counter B switches the delay time of the delay time switching circuit 22.

  In response to the switching signal sent from the counter B of the frequency subtractor 30, the delay time switching circuit 22 sets the delay time of the signal cmp_out sent from the comparator CMP1 via the inverter 20 to, for example, zero time 0 (s ) Or at a predetermined time t (s). The delay time switching circuit 22 can be configured with a time constant circuit. In this case, the delay time is switched by switching the time constant. The signal output from the delay time switching circuit 22 is output as the reset signal R to the reset terminal R of the flip-flop FF. The delay time switching circuit 22 will be described in detail later.

  The counter B32 output of the frequency subtractor 30 sets the counter A and at the same time switches the delay time of the delay time switching circuit 22 to a predetermined time t (s). That is, the pulse signal is thinned out by the set counter A and the oscillation period is switched to double, and at the same time, the delay time of the delay time switching circuit 22 is set to the predetermined time t (s), so that the switching element Q1 The correction is made so as not to affect the on-duty of the gate pulse signal.

  Next, the operation of the switching power supply according to the first embodiment configured as described above will be described with reference to the timing chart shown in FIG. In the timing chart shown in FIG. 2, the switching signal from the counter A indicates a case where the switch signal is switched off every time the count number counts two.

In the period 2T in which the switching cycle (oscillation cycle) in the timing chart of FIG. 2 is long, the output of the counter B32 of the frequency subtractor 30 outputs an H level signal, sets the counter A31 to the set state, and switches to the delay time switching circuit 22 A signal is sent and the delay time is switched to the predetermined time t (s) side. The counter A31 subtracts the pulse signal from the oscillator OSC at a rate of once every two times and outputs it to the one-shot circuits 11 and 12. When the pulse signal (set signal S) output from the one-shot circuit 11 is input to the set terminal S of the flip-flop FF, the flip-flop FF outputs an H level signal from the output terminal. Thereby, the switching element Q1 is turned on, and a switching current flows through the resistor Rs. When the voltage drop of the resistor Rs, that is, the level of the voltage OCP becomes larger than the level of the feedback signal FB from the operational amplifier OP, cmp_out of L level is output from the comparator CMP1. The signal cmp_out is delayed by a predetermined time t (s), and the reset signal R is output to the reset terminal R of the flip-flop FF via the OR circuit 21. For this reason, the ON width of the switching element Q1 extends for a predetermined time t (s), and the switching current increases. Therefore, even if the switching period is changed to twice, the power supplied to the output can be stabilized by extending the ON width of the switching element Q1 so that the energy per unit time does not change. The energy U per cycle of the flyback switching power supply device corresponds to ½ of the product of the inductance L of the transformer T and the square of the switching current peak value, and is ½ LI2, so the cycle is doubled. In this case, the switching current peak value may be multiplied by √2.
That is, since the switching current peak value is proportional to the ON time of the switching element Q1, the predetermined time t (s) of the delay time switching circuit 22 is set to √2 times the ON width of the switching element Q1.

  Although not shown, when the output of the counter B32 is switched to the L level signal, the counter A31 is reset and a switching signal is sent to the delay time switching circuit 22 so that the delay time is on the zero time 0 (s) side. Since the switching is performed, the next of the long cycle 2T returns to the normal cycle T. In addition, it can be set to be switched to a long cycle 2T by arbitrarily selecting the number of counts until the switching signal is output from the counter B32.

  Next, details of the delay time switching circuit 22 will be described. FIG. 3A shows that when there is no delay time switching circuit 22 as in the conventional switching power supply device, the output terminal of the comparator CMP1 reaches the reset terminal R of the flip-flop FF via the inverter 20 and the OR circuit 21. FIG. 3B is a circuit diagram illustrating a path when the delay time switching circuit 22 is present. FIG. 3B shows a circuit in which the inverter 20 and the delay time switching circuit 22 are integrated.

  The delay time switching circuit 22 is composed of P-type and N-type C-MOS, and the output of the comparator CMP1 is connected to the input of the first-stage C-MOS, and a signal obtained by inverting the input signal is output. The gate of the lower P-type MOSPL of the two P-type MOSs connected in series is further connected to the input terminal of the second-stage C-MOS, and the gate of the upper P-type MOSPH is the delay time switching circuit. 22 is connected to the input terminal A of the switching signal. The source of the upper P-type MOS is connected to the power supply Vcc.

  When the switching signal from the counter B32 of the frequency subtracter 30 is L level, the operation is performed with no delay. Here, when an L level signal is input from the counter B32 to the input terminal A of the delay time switching circuit 22, the upper P-type MOSPH of the two P-type MOSs is turned on, so that the first-stage C-MOS is turned on. Input to the L level, an H level signal is output from the two P-type MOSs, and a time constant capacitor (not shown) formed by the capacitance between the gate and the source of the N-type MOS of the next stage C-MOS Ct is charged without delay. At the same time, an H level signal is output from the P-type MOS of the first-stage C-MOS, but since a signal is output via the time constant resistor Rt, the charging effect by the two P-type MOSs is high. As a result, an H level signal is output from the inverter 20 without delay.

  Next, when the signal from the counter B32 is at the H level, the operation is performed with “delay”, and the upper P-type MOSPH of the two P-type MOSs is switched off. In this state, when the output of the comparator CMP1 becomes L level, the output of the first-stage C-MOS is inverted to H level. In this case, the time constant capacitor Ct (not shown) is not charged by the two P-type MOSs, and the time constant from the second-stage C-MOS is supplied from the P-type MOS of the first-stage C-MOS via the time-constant resistor Rt. The capacitor Ct is charged. Therefore, a delay time t (s) is generated by the time constant resistor Rt and the time constant capacitor Ct, and the H level signal sent to the reset terminal R of the flip-flop FF is delayed.

  As described above, the delay time can be switched in two stages by the signal from the counter B32. Therefore, by distributing the switching period to T and 2T, a jitter effect can be obtained, the average value of EMI noise can be reduced, and the on-pulse width of the switching element Q1 can be increased to √ in synchronization with the switching period 2T. By extending the delay time t (s) by twice, the amount of energy per cycle can be maintained, so that an increase in ripple voltage can be suppressed.

In the first embodiment, the delay time t (s) is one fixed time, but a second embodiment in which a delay time that more matches the on-pulse width of the switching element Q1 will be described.
FIG. 4 is a block diagram illustrating the configuration of the switching power supply according to the second embodiment. FIG. 5 is a circuit diagram showing in detail the delay time switching circuit 22a of the second embodiment. The delay time can be switched in three stages: “no delay”, “medium delay”, and “large delay”.

In the block diagram showing the configuration of the switching power supply device of FIG. 4, the difference from the first embodiment is that a comparator CMP2 and a reference voltage Vm are added and the delay time switching circuit 22a is changed.
The positive terminal of the reference voltage Vm is connected to the inverting terminal of the comparator CMP2, and the non-inverting terminal is connected to the connection point between the source of the switching element Q1 and the resistor Rs and the inverting terminal of the comparator CMP1. The output terminal of the comparator CMP2 is connected to the B terminal of the delay time switching circuit 22a. The negative voltage of the reference voltage Vm is connected to the other end of the resistor Rs and the ground (GND). The comparator CMP2 compares the voltage drop of the resistor Rs with the reference voltage Vm, and outputs an H level signal when the switching current value flowing through the resistor Rs is larger than about ½ of the output power supplied to the secondary side. It is set to be.

The delay time switching circuit 22a differs from the circuit shown in FIG. 3 in that the time constant resistor Rt between the P-type MOS of the first stage C-MOS and the drain of the N-type MOS is changed to a time constant resistor Rt1, Two P-type MOSs (Ph, PL) are added, and the drain terminal of the added lower P-type MOSPL is connected to the output terminal of the first-stage C-MOS through a time constant resistor Rt2.

A new input terminal B is provided at the gate of the upper P-type MOSPh of the two added P-type MOSs (Ph, Pl), and a signal from the comparator CMP2 is input. Here, the signal sent from the comparator CMP2 is input to the input terminal B.
That is, when the power supplied to the secondary side is less than 1/2 of the rated power, an L level signal is input to the input terminal B, and when the power supplied to the secondary side is 1/2 or more of the rated power, an H level signal is input. Is done.

  First, when an L level signal is input to the input terminal A from the counter B32 of the frequency subtractor 30, "no delay" is set regardless of the level signal at the input terminal B. Next, when an H level signal is input from the counter B32 to the input terminal A and an L level signal is input to the input terminal B, the delay time is the resistance value of the parallel connection of the time constant resistors Rt1 and Rt2, and a time constant (not shown). The time tm (s) determined by the capacitor Ct (“delaying”). Further, when an H level signal is input from the counter B32 to both the input terminal A and the input terminal B, a time t (s) determined by the time constant resistor Rt1 and the time constant capacitor Ct (“large delay”). ), Which is the most delayed time.

As described above, the delay time can be switched in three stages by the signal from the comparator CMP2 and the signal from the counter B32. Further, since the delay time when the period is 2T can be selected according to the magnitude of the supplied power by the signal from the comparator CMP2, the fluctuation of the ripple voltage when the frequency is jittered can be suppressed more finely. .
Similarly to the first embodiment, it is possible to reduce the average value of EMI noise by jittering the frequency.

  The present invention is applicable to a switching power supply device that requires a reduction in the average value of EMI noise and stable operation.

11, 12 One-shot circuit 20 Inverter 22 Delay time switching circuit 30 Frequency subtractor T Transformer Q1 Switching element Rt, Rt1, Rt2 Time constant resistor C Capacitor Co Output capacitor D Diode CMP1, CMP2 Comparator OP Operational amplifier FF Flip-flop

Claims (2)

A series circuit in which a transformer primary winding and a switching element are connected in series at both ends of a DC power supply;
A control circuit for turning on and off the switching element;
A rectifying / smoothing circuit for rectifying and smoothing the voltage generated in the secondary winding of the transformer;
An error amplification circuit that amplifies an error voltage between the output voltage of the rectifying and smoothing circuit and a reference voltage and outputs the amplified error voltage to the control circuit;
The control circuit includes:
A signal generator for generating a signal for turning on and off the switching element;
A counter that counts the number of times the switching element is turned on by a signal output from the signal generator;
A frequency subtractor that subtracts on / off of the switching element each time the count value by the counter reaches a predetermined value;
A delay that controls the signal generator by switching the delay time so that a signal for turning off the switching element is output after being delayed from the signal output from the signal generator immediately before being subtracted by the frequency subtractor. And a time switching circuit.
The switching power supply device according to claim 1, wherein the delay time switching circuit switches the delay time in accordance with an amount of power supplied by the switching power supply device.

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