JP2009254148A - Semiconductor integrated device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated device that includes an output circuit capable of preventing a through current in accordance with characteristics of a MOS transistor. <P>SOLUTION: The semiconductor integrated device is provided with an output circuit 11 having first/second MOS transistors M1, M2, a drive circuit 12 for alternately turning ON/OFF both of the first/second MOS transistors, and a control means 13. The control means calculates elapsed time ΔT during which a gate voltage Vg2 (Vg1) of the MOS transistor M2 (M1) in the ON state of the first/second MOS transistors M1, M2 changes from a first voltage V1, set between a voltage when the gate voltage Vg2 (Vg1) starts to reverse and a threshold Vth2 (Vth1) of the MOS transistor M2 (M1) in the ON state, to a second voltage V2, set between the first voltage V1 and the threshold Vth2 (Vth1), and outputs a signal, delayed in accordance with the elapsed time ΔT, to the drive circuit 12 as a control signal Vc1 (Vc2) that turns ON the MOS transistor M1 (M2) in the OFF state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated device.

  In the DC-DC converter that outputs a voltage obtained by transforming the input voltage by alternately turning on and off the high-side MOS transistor and the low-side MOS transistor connected in series, due to a slight difference in the operation timing of the high-side and low-side MOS transistors, When inverting, both MOS transistors are turned on at the same time, and there is a problem that a through current flows from the power source to the ground, resulting in an increase in current consumption.

  Therefore, a dead time for simultaneously turning off both MOS transistors when the drive signal is inverted is provided to prevent a through current (see, for example, Patent Document 1).

  The DC-DC converter disclosed in Patent Document 1 is a sense FET that detects current conduction in a body diode of a low-side switch, and a current detection / comparison that is coupled to the sense FET and detects a change in current conduction. And a delay circuit and a clock / logic circuit coupled to the current detection / comparator circuit for predicting and adjusting a delay time when switching between the high-side switch and the low-side switch. .

  However, when at least one of the high-side MOS transistor and the low-side MOS transistor is replaced with another MOS transistor having different characteristics, the slope of the gate signal changes due to a difference in gate input capacitance, etc. There are problems such as a decrease in conversion efficiency and an increase in loss due to the occurrence of a through current.

  In particular, in an MCM (Multi Chip Module) in which a high-side MOS transistor, a low-side MOS transistor, and a driver IC are housed in one package, it is necessary to adjust dead time each time the specification of the MOS transistor is changed. There is a problem that a great deal of time and money is generated.

The DC-DC converter disclosed in Patent Document 1 does not disclose anything about this point.
JP 2005-94994 A

  The present invention provides a semiconductor integrated device having an output circuit capable of preventing a through current in accordance with the characteristics of a MOS transistor.

  A semiconductor integrated device of one embodiment of the present invention includes a first insulated gate field effect transistor and a second insulated gate field effect transistor connected in series between an input voltage and a reference potential, and transforms the input voltage. An output circuit that outputs a voltage; a drive circuit that alternately turns on and off the first insulated gate field effect transistor and the second insulated gate field effect transistor according to a drive signal; the first insulated gate field effect transistor; Among the second insulated gate field effect transistors, the gate voltage of the insulated gate field effect transistor in the on state is between the voltage when the gate voltage starts to reverse and the threshold value of the insulated gate field effect transistor in the on state. From the first voltage set to the second voltage set between the first voltage and the threshold value. And a control means for outputting to the drive circuit as a control signal for turning on the insulated gate field effect transistor in an off state, a time delay until the elapsed time is obtained. Yes.

  According to the present invention, a semiconductor integrated device having an output circuit capable of preventing a through current in accordance with the characteristics of a MOS transistor can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  A semiconductor integrated device according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a semiconductor integrated device, FIG. 1 (a) is a block diagram showing its configuration, FIG. 1 (b) is a block diagram showing essential parts, and FIG. 2 is a first and second voltage of the semiconductor integrated device. FIG. 3 is a circuit diagram showing a time calculation circuit of the semiconductor integrated device, FIG. 4 is a circuit diagram showing an arithmetic circuit of the semiconductor integrated device, and FIG. 5 is a timing chart showing the operation of the semiconductor integrated device. 6 is a diagram showing the effect of the present embodiment in comparison with the comparative example, FIG. 6A is a diagram illustrating the present embodiment, and FIG. 6B is a diagram illustrating the comparative example.

  As shown in FIG. 1A, the semiconductor integrated device 10 of this embodiment includes an N-channel first insulated gate field effect transistor (hereinafter referred to as a first MOS transistor) connected in series between an input voltage Vin and a reference potential GND. ) M1 and an N-channel second insulated gate field effect transistor (hereinafter referred to as a second MOS transistor) M2, an output circuit 11 for outputting a voltage Vout (hereinafter referred to as an output voltage) obtained by transforming the input voltage Vin, and a drive signal PWM Accordingly, a drive circuit 12 for alternately turning on and off the first MOS transistor M1 and the second MOS transistor M2 is provided.

  Further, of the first MOS transistor M1 and the second MOS transistor M2, the gate voltage Vg2 (Vg1) of the on-state MOS transistor M2 (M1) is equal to the voltage at which the gate voltage Vg2 (Vg1) starts to be inverted and the on-state MOS From the first voltage V1 set between the threshold value Vth2 (Vth1) of the transistor M2 (M1) to the second voltage V2 set between the first voltage V1 and the threshold value Vth2 (Vht1). Elapsed time ΔT is obtained, a delayed signal is generated according to the elapsed time ΔT, and the delayed signal is output to the drive circuit 12 as a control signal Vc1 (Vc2) for turning on the MOS transistor M1 (M2) in the off state. Control means 13 is provided.

In the output circuit 11, the first MOS transistor M <b> 1 (high side transistor) has a drain connected to the input voltage Vin, a source connected to the output node Nout, and a gate connected to the high side drive circuit 14 of the drive circuit 12. .
The second MOS transistor M2 (low side transistor) has a drain connected to the output node Nout, a source connected to the reference potential GND, and a gate connected to the low side drive circuit 15 of the drive circuit 12.

  A low pass filter having an inductor L and a capacitor C is connected to the output node Nout. The output voltage Vout smoothed by the low-pass filter is output to the outside as a constant output voltage Vdc.

  In the drive circuit 12, the high side drive circuit 14 generates a high level drive voltage for driving the first MOS transistor M1 in accordance with the drive signal PWM. The low side drive circuit 15 generates a low level drive voltage for driving the second MOS transistor M2 in accordance with the drive signal PWM.

  As shown in FIG. 1B, the control circuit 13 compares the gate voltage Vg2 (Vg1) with the first voltage V1, outputs the first comparison result Vo1, and the gate voltage Vg2. (Vg1) is compared with the second voltage V2, and the second voltage detection circuit 22 that outputs the second comparison result Vo2 and the first comparison result Vo1 and the second comparison result Vo2 are used to determine the gate voltage Vg2 (Vg1). Is a time calculation circuit 23 for obtaining an elapsed time ΔT from the first voltage V1 to the second voltage V2, and a second comparison result Vo2 is delayed by a time τ (ΔT) according to the elapsed time ΔT. And an arithmetic circuit 24 that outputs the comparison result Vo2 to the drive circuit 12 as a control signal Vc1 (Vc2).

As shown in FIG. 2, the first voltage detection circuit 21 is configured such that the gate voltage Vg2 (Vg1) is supplied to the negative input terminal, and the first reference voltage Vref1 equal to the first voltage V1 is supplied to the positive input terminal. A comparator 31 is provided.
Similarly, the second voltage detection circuit 22 includes a second comparator 32 in which the gate voltage Vg2 (Vg1) is supplied to the negative input terminal and the second reference voltage Vref2 equal to the second voltage V2 is supplied to the positive input terminal. is doing.
The first reference voltage Vref1 and the second reference voltage Vref2 are obtained, for example, by dividing the power supply Vcc with resistors R1, R2, and R3.

At time t1 when the gate voltage Vg2 (Vg1) drops and reaches the first voltage V1, the first comparison result Vo1 of the first comparator 31 changes from “L” level to “H” level.
Similarly, the gate voltage Vg2 (Vg1) further decreases, and the second comparison result Vo2 of the second comparator 32 changes from the “L” level to the “H” level at the time t2 when the gate voltage Vg2 (Vg1) reaches the second voltage V2.
The elapsed time ΔT until the gate voltage Vg2 (Vg1) reaches the second voltage V2 from the first voltage V1 is t2-t1.

  As shown in FIG. 3, the time calculation circuit 23 is a counter having a clock generation circuit 41 that generates a clock signal, a logic circuit 42 that includes an inverter and a NAND circuit, and JK flip-flops FF1 to FFn.

  The logic circuit 42 detects when the first comparison result Vo1 is changed from “L” level to “H” level, outputs the clock signal CLK to the JK flip-flop FF1, and the second comparison result Vo2 is “L” level. Is detected as “H” level, and the output of the clock signal CLK is stopped.

  The JK flip-flops FF1 to FFn start counting the clock signal CLK when the first comparison result Vo1 is detected, and stop counting the clock signal CLK when the second comparison result Vo2 is detected. Qn is output. The elapsed time ΔT at this time is represented by the product of the count number and the period of the clock signal CLK.

  As shown in FIG. 4A, the arithmetic circuit 24 includes a CR time constant circuit 50 in which the CR time constant is adjusted according to the elapsed time ΔT, and a series circuit of an inverter 51.

  The CR time constant circuit 50 has a source connected to the power supply Vcc, a drain connected to the node N3, a gate connected to the node N4, a drain connected to the node N5, and a source connected to the reference potential. Via an N-MOS transistor 53 connected to GND, having a gate connected to the node N4, a capacitor C1 having one end connected to the node N5 and the other end connected to the reference potential GND, and switching elements S1 to Sn. Resistors R1a to Rna are commonly connected between the node N3 and the node N5.

  The CR time constant circuit 50 changes the CR time constant according to the elapsed time ΔT by switching the switch elements S1 to Sn based on the outputs Q1 to Qn of the JK flip-flops FF1 to FFn of the time calculation circuit 23 shown in FIG. It functions as a delay circuit that can be adjusted and the delay time can be varied.

  As shown in FIG. 4B, when the second comparison result Vo2 changes from “L” level to “H” level at time t2, the N-MOS transistor 53 is turned on and the P-MOS transistor 52 is turned off. The electric charge accumulated at the node N5 is discharged through the on-resistance of the N-MOS transistor 53, and the potential VN3 of the node N3 decreases according to the CR time constant.

  When the potential VN3 of the node N3 becomes the threshold value Vth53 of the inverter 51 at time t3, the output of the inverter 51 is inverted from the “L” level to the “H” level.

  Accordingly, the control signal Vc1 (Vc2) obtained by delaying the second comparison result Vo2 by τ (ΔT) = t3−t2 according to the elapsed time ΔT is obtained.

FIG. 5 is a timing chart showing the operation of the semiconductor integrated device 10.
As shown in FIG. 5, as an initial state, when the drive signal PWM is “L” level and the output voltage Vout is “L” level, the first MOS transistor M1 is off, the second MOS transistor M2 is on, and the first MOS The gate voltage Vg1 of the transistor M1 is at “L” level, and the gate voltage Vg2 of the second MOS transistor M2 is at “H” level.

  When the drive signal PWM is inverted from the “L” level to the “H” level at time t0, the charge charged in the gate input capacitance of the second MOS transistor M2 is discharged through the internal resistance of the low side drive circuit 15, and the gate The voltage Vg2 starts to invert and drops from the “H” level toward the “L” level.

At time t1, the gate voltage Vg2 becomes smaller than the “H” level that is the voltage at which the gate voltage starts to invert, and becomes the first voltage V1 that is larger than the threshold value Vth2 of the second MOS transistor M2.
At time t2, the gate voltage Vg2 becomes a second voltage V2 that is smaller than the first voltage V1 and larger than the threshold value Vth2.
At time t3, the gate voltage Vg2 becomes equal to the threshold value Vth2, and the second MOS transistor M2 is turned off.

At this time, when the change of the gate voltage Vg2 is approximated by a straight line, the slope α is expressed by the following equation.
α = (V2−V1) / (t2−t1) = (V2−V1) / ΔT (1)
The time t3 when the gate voltage Vg2 becomes equal to the threshold value Vth2 can be predicted by the following equation.
t3 = t2 + (Vth2-V2) ΔT / (V2-V1) (2)
Therefore, after the delay time τ (ΔT) represented by the following expression has elapsed from time t2, the off-state first MOS transistor M1 may be turned on.
τ (ΔT) = t3−t2 = (Vth2−V2) ΔT / (V2−V1) (3)
This prevents the first and second MOS transistors M1 and M2 from being turned on at the same time, and starts the operation of turning on the first MOS transistor M1 after detecting that the second MOS transistor M2 is turned off. Compared to the case, the time delay is small, and it is possible to optimize the dead time in which the first and second MOS transistors M1 and M2 are simultaneously turned off.

  Originally, it is ideal to turn on the first MOS transistor M1 at the predicted time t3, but it is desirable to turn on the first MOS transistor at time t4 = t3 + δ that allows for the allowance time δ in consideration of the variation in prediction.

At time t4, the first control signal Vc1 changes from “L” level to “H” level, and the gate voltage Vg1 of the first MOS transistor M1 rises.
When the gate voltage Vg1 becomes equal to the threshold value Vth1 of the first MOS transistor M1 at time t5, the first MOS transistor M1 is turned on and the output voltage Vout is changed from the “L” level to the “H” level.
Time (t5-t3) is a dead time td in which both the first MOS transistor M1 and the second MOS transistor M2 are turned off.

6A and 6B are diagrams showing the effects of the present embodiment in comparison with the comparative example. FIG. 6A is a diagram illustrating the present embodiment, and FIG. 6B is a diagram illustrating the comparative example.
Here, in the comparative example, a threshold value Vthoff lower than the threshold value Vth2 of the second MOS transistor M2 is set, and when the gate voltage Vg2 becomes equal to the threshold value Vthoff, that is, after the second MOS transistor M2 is completely turned off, The case where the first MOS transistor in the off state is turned on is shown. First, a comparative example will be described.

As shown in FIG. 6B, in the comparative example, when the gate voltage Vg2 starts to invert and drops from the “H” level to the “L” level as indicated by the solid line 60, at time t8, the gate voltage Vg2 Becomes equal to the threshold value Vth2, the second MOS transistor M2 is turned off.
When the gate voltage Vg2 becomes equal to the threshold value Vthoff at time t8a after the second MOS transistor M2 is completely turned off, the gate voltage Vg1 rises as shown by the solid line 60a.
When the gate voltage Vg1 becomes equal to the threshold value Vth1 at time t8b, the first MOS transistor M1 is turned on. The dead time td60 is t8b-t8.

  If the first MOS transistor M1 is left as it is, and the second MOS transistor M2 is changed to a MOS transistor having a smaller gate input capacitance, the gate voltage Vg2 drops rapidly from the solid line 60 as shown by the solid line 61.

As a result, at time t7 earlier than time t8, the gate voltage Vg2 becomes equal to the threshold value Vth2, and the second MOS transistor M2 is turned off.
When the gate voltage Vg2 becomes equal to the threshold value Vthoff at a time t7a earlier than the time t8a after the second MOS transistor M2 is completely turned off, the gate voltage Vg1 rises at the time t7a as shown by a solid line 61a.

When the gate voltage Vg1 becomes equal to the threshold value Vth1 at time t7b, the first MOS transistor M1 is turned on.
Since the time (t7a-t7) is shorter than the time (t8a-t8) and the time (t7b-t7a) is equal to the time (t8b-t8a), the dead time td61 is shorter than the dead time td60.
As a result, both the first and second MOS transistors M1 and M2 are turned on, increasing the possibility that a through current flows.

  If the first MOS transistor M1 is left as it is and the second MOS transistor M2 is changed to a MOS transistor having a larger gate input capacity, the gate voltage Vg2 falls more slowly than the solid line 60 as shown by the solid line 62.

As a result, at time t9 later than time t8, the gate voltage Vg2 becomes equal to the threshold value Vth2, and the second MOS transistor M2 is turned off.
After the second MOS transistor M2 is completely turned off, when the gate voltage Vg2 becomes equal to the threshold value Vthoff at a time t9a later than the time t8a, the gate voltage Vg1 rises at the time t9a as shown by the solid line 62a.

When the gate voltage Vg1 becomes equal to the threshold value Vth1 at time t9b, the first MOS transistor M1 is turned on.
Since time (t9a-t9) is longer than time (t8a-t8) and time (t9b-t9a) is equal to time (t8b-t8a), dead time td62 is longer than dead time td60. Thereby, DC-DC conversion efficiency will fall.

  On the other hand, as shown in FIG. 6A, in this embodiment, when the gate voltage Vg2 drops as shown by the solid line 60, the elapsed time ΔT60 until the gate voltage Vg2 reaches the second voltage V2 from the first voltage V1. After a corresponding delay time τ (ΔT60), the gate voltage Vg1 of the first MOS transistor M1 rises as indicated by a solid line 60b. Here, the margin time δ = 0 shown in FIG. 5 is set.

  Next, when the gate voltage Vg2 drops abruptly from the solid line 60 as shown by the solid line 61, a delay time τ (ΔT61) corresponding to the elapsed time ΔT61 until the gate voltage Vg2 reaches the second voltage V2 from the first voltage V1. Later, the gate voltage Vg1 of the first MOS transistor M1 rises as indicated by the solid line 61b.

  When the gate voltage Vg2 gradually drops from the solid line 60 as shown by the solid line 62, after the delay time τ (ΔT62) corresponding to the elapsed time ΔT62 until the gate voltage Vg2 reaches the second voltage V2 from the first voltage V1. The gate voltage Vg1 of the 1MOS transistor M1 rises as indicated by a solid line 62b.

  As a result, the rise time of the gate voltage Vg1 of the first MOS transistor M1 shifts according to the slope of the gate voltage Vg2, so that a constant dead time can be obtained regardless of the slope of the gate voltage Vg2.

FIG. 7 is a view showing an MCM (Multi Chip Module) in which the semiconductor integrated device 10 is housed in one package.
As shown in FIG. 7, the MCM 16 includes a driver IC 18 on which a semiconductor chip, that is, a first MOS transistor M1, a second MOS transistor M2, a drive circuit 12, and a control means 13 are integrated on a substrate 17, for example, a ceramic substrate, and is bonded. The wire 19 is electrically connected and the whole is molded with resin (not shown).

  Even if the characteristics of the first MOS transistor M1 and the second MOS transistor M2 to be mounted are changed according to the specifications of the MCM 16, there is no need to readjust the dead time, so the MCM 16 can be manufactured with less time and cost. Is possible.

  Here, when the characteristics of the first and second MOS transistors M1 and M2, such as the current driving capability, change, the gate input capacitances of the first and second MOS transistors M1 and M2 change accordingly. This means that the threshold values Vth1 and Vth2 of the transistors M1 and M2 are basically unchanged.

  As described above, in the semiconductor integrated device 10 of the present embodiment, the gate voltage of the on-state MOS transistor of the first MOS transistor M1 and the second MOS transistor M2 reaches from the first voltage V1 to the second voltage V2. The control means 13 is provided for determining the elapsed time ΔT until the drive circuit 12 is generated, generating a delayed signal according to the elapsed time ΔT, and outputting the delayed signal to the drive circuit 12 as a control signal Vc2 for turning on the off-state MOS transistor. Yes.

As a result, the rise time of the gate voltage Vg1 of the first MOS transistor M1 shifts according to the slope of the gate voltage Vg2, so that a constant dead time can be obtained regardless of the slope of the gate voltage Vg2.
Therefore, the semiconductor integrated device 10 having the output circuit 11 capable of preventing the through current according to the characteristics of the output MOS transistors M1 and M2 is obtained.

  Here, the case where the first MOS transistor M1 is off and the second MOS transistor M2 is on is described as the initial state. However, even if the first MOS transistor M1 is on and the second MOS transistor M2 is off, symbols in parentheses are used. As shown in FIG.

  Although the case where the change of the gate voltage Vg2 is linearly approximated has been described, approximation other than linear approximation, such as polynomial approximation, can be used.

Although the case where the output circuit 11 has the N-channel first and second MOS transistors M1 and M2 has been described, a CMOS output circuit in which the first MOS transistor M1 is a P-channel MOS transistor may be used.
In this case, since the first gate voltage Vg1 is opposite, the first voltage V1 is set larger than the voltage at which the gate voltage Vg1 starts to be inverted and smaller than the threshold value Vth1, and the second voltage V2 is set to the first voltage V1. It is set larger and smaller than the threshold value Vth1.

A semiconductor integrated device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 8 is a circuit diagram showing first and second voltage detection circuits of the semiconductor integrated device. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.
The present embodiment is different from the first embodiment in that the first and second voltage detection circuits are composed of CMOS inverters.

That is, as shown in FIG. 8, the first voltage detection circuit of the semiconductor integrated device of the present embodiment includes a first CMOS inverter 71 having a threshold value equal to the first voltage V1.
Similarly, the second voltage detection circuit includes a second CMOS inverter 72 having a threshold value equal to the second voltage V2.

  The first CMOS inverter 71 has a P-MOS transistor 73 and an N-MOS transistor 74, and the second CMOS inverter 72 has a P-MOS transistor 75 and an N-MOS transistor 76.

  As is well known, the threshold value of the CMOS inverter is a voltage value at which the input voltage and output voltage of the input / output transfer characteristics are equal, and the gate width W and gate length L of the P-MOS transistor and N-MOS transistor are changed. Thus, a required threshold value is obtained.

  As described above, the semiconductor integrated device of the present embodiment includes the first and second CMOS inverters as the first and second voltage detection circuits. By configuring the first and second voltage detection circuits with MOS transistors, the circuit configuration can be simplified and the chip size can be reduced as compared with the case where a comparator and a dividing resistor are used.

  A semiconductor integrated device according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 9 is a circuit diagram showing a time calculation circuit of the semiconductor integrated device. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The difference between the present embodiment and the first embodiment is that the time calculation circuit is composed of inverters connected in multiple stages.

  That is, as shown in FIG. 9, the time calculation circuit 80 of the semiconductor integrated device according to the present embodiment starts the signal propagation based on the first comparison result Vo1 and stops the signal propagation based on the second comparison result Vo2. The inverter circuit 81 and a detection circuit 82 for detecting how many stages of the inverter the signal has propagated are provided.

  The inverter circuit 81 includes inverters INV1 to INVn that are connected in multiple stages via switch elements S1a to Sna, and an inverter 84 that is connected to an input terminal of an even-numbered inverter among the inverters INV1 to INVn.

  In the inverter circuit 81, since the switch element 83 is off and the switch elements S1a to S1n are on in the initial state, the input of the odd-numbered inverter among the inverters INV1 to INVn is “L” level, The input is at the “H” level.

  When the switch element 83 is turned on by the first comparison result Vo1 at time t1, the input of the inverter INV1 becomes “H” level, and after the delay time Δtd of the inverter, the output of the inverter INV1 becomes “L” level. The output of the next inverter is inverted every time the inverter delay time Δtd, and the signal propagates.

  When the switch elements S1a to S1n are turned off by the second comparison result Vo2 at time t2, signal propagation stops and the input / output levels of the inverters INV1 to INVn are held.

As a result, among the inputs of the odd-numbered inverters and the inputs of the even-numbered inverters viewed through the output of the inverter 84, all the inputs of the inverters up to the number of stages where the signal has propagated become the “H” level.
Since the signal has not yet propagated, the input of the next-stage inverter of the number of stages where the signal has propagated becomes “L” level.

  Therefore, since the signal is propagated to the inverter whose input is “H” level and the input of the next stage inverter is “L” level, the elapsed time ΔT = t2−t1 is the delay time Δtd of the inverter and the signal propagates. It is obtained by the product of the number of inverter stages.

  For example, if the signal propagates to the inverter INV3, the elapsed time ΔT = 3Δtd + Td. However, Td is the inherent delay time of the inverter circuit 81 from when the first comparison result Vo1 is output until the inverter INV1 operates.

  When the second comparison result Vo2 is output at time t2, the detection circuit 82 performs a second comparison at time t2 with the NAND circuits NA0 to NAn that perform NAND operation on the second comparison result Vo2 and the inputs of the inverters INV1 to INVn. When the result Vo2 is output, a switch unit 85 for transmitting the NAND operation result of the NAND circuits NA0 to NAn to the next and an XOR operation unit 86 for performing an XOR operation on adjacent NAND operation results are provided. .

As a result, among the outputs X0 to Xn of the XOR operation unit 86, when the adjacent NAND operation results are different, the XOR operation result becomes “H” level. Can be detected.
For example, if the signal propagates to the inverter INV3, the output X3 of the XOR operation unit 86 becomes “H” level.

As described above, the semiconductor integrated device of the present embodiment is connected in multiple stages as the time calculation circuit 80, which starts signal propagation based on the first comparison result Vo1 and stops signal propagation based on the second comparison result Vo2. An inverter circuit 81 and a detection circuit 82 for detecting how many stages of the inverter the signal has propagated are provided.
Since the inverter circuit 81 and the detection circuit 82 can be configured by a CMOS circuit or the like, there is an advantage that the circuit configuration is simplified as compared with the case where a clock generation circuit and a counter are used.

  A semiconductor integrated device according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 10 is a circuit diagram showing an arithmetic circuit of the semiconductor integrated device. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The present embodiment is different from the first embodiment in that a delay circuit having a different delay time is provided for the arithmetic circuit, and any one is selected according to the elapsed time ΔT.

  That is, as shown in FIG. 10, the arithmetic circuit 90 of the semiconductor integrated device of this embodiment includes a plurality of series circuits of CR time constant circuits 91 and inverters 92 having different CR time constants, and switching elements S1b˜ One of the series circuits is selected according to the elapsed time ΔT according to Snb.

  The CR time constant circuit 91 has the same circuit configuration and operating principle as the CR time constant circuit 50 shown in FIG. 4A, except that the CR time constant circuit 91 has different time constants due to one resistor R1b to Rnb and the capacitor C1a. The description is omitted.

By driving the switch elements S1b to Snb with the outputs X0 to Xn-1 of the time calculation circuit 80 shown in FIG. 9, a CR time constant circuit 91 having any CR time constant different from each other according to the elapsed time ΔT; A series circuit with the inverter 92 is selected.
Thereby, a signal Vc1 (Vc2) obtained by delaying the second comparison result Vo2 according to the elapsed time ΔT can be obtained.

  As described above, the arithmetic circuit 90 of the semiconductor integrated device according to the present embodiment includes a plurality of series circuits of the CR time constant circuit 91 and the inverter 92 having different CR time constants, depending on the switch elements S1b to Snb. Any one of the series circuits is selected according to the elapsed time ΔT.

  Thereby, in the series circuit of each CR time constant circuit 91 and the inverter 92, in order to obtain the delay time of the predetermined second comparison result Vo2, circuit constants such as resistors, capacitors, transistors, etc. are individually set for each series circuit. There are advantages that can be optimized.

1A and 1B are diagrams illustrating a semiconductor integrated device according to a first embodiment of the present invention, in which FIG. 1A is a block diagram illustrating the configuration, and FIG. 1 is a circuit diagram showing first and second voltage detection circuits of a semiconductor integrated device according to Embodiment 1 of the present invention; 1 is a circuit diagram showing a time calculation circuit of a semiconductor integrated device according to Embodiment 1 of the present invention. 1 is a circuit diagram showing an arithmetic circuit of a semiconductor integrated device according to Embodiment 1 of the present invention. 3 is a timing chart showing the operation of the semiconductor integrated device according to the first embodiment of the present invention. FIGS. 6A and 6B are diagrams illustrating the effects of the semiconductor integrated device according to the first embodiment of the present invention in comparison with the comparative example, in which FIG. 6A illustrates the present example and FIG. 6B illustrates the comparative example. 1 is a diagram showing an MCM using a semiconductor integrated device according to Embodiment 1 of the present invention. FIG. 6 is a circuit diagram showing first and second voltage detection circuits of a semiconductor integrated device according to Embodiment 2 of the present invention. FIG. 6 is a circuit diagram showing a time calculation circuit of a semiconductor integrated device according to Embodiment 3 of the present invention. FIG. 6 is a circuit diagram showing an arithmetic circuit of a semiconductor integrated device according to Embodiment 4 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated device 11 Output circuit 12 Drive circuit 13 Control means 14 High side drive circuit 15 Low side drive circuit 16 MCM
17 Board 18 Driver IC
19 Bonding wire 21 First voltage detection circuit 22 Second voltage detection circuit 23, 80 Time calculation circuit 24, 90 Arithmetic circuit 31 First comparator 32 Second comparator 41 Clock generation circuit 42 Logic circuit 50, 91 CR time constant circuit 51, 84, 92, INV1 to INVn Inverters 52, 73, 75, 93 P-MOS transistors 53, 74, 76, 94 N-MOS transistor 71 First CMOS inverter 72 Second CMOS inverter 81 Inverter circuit 82 Detection circuit 83, S1 to Sn, S1a to Sna, S1b to Snb switch element 85 switch unit 86 XOR operation unit M1 first MOS transistor M2 second MOS transistor Nout output node Vin input voltage Vout output voltage Vc1 first control signal Vc2 second control signal Vo1 First comparison result Vo2 Second comparison results R1, R2, R3, R1a to Rna, R1b to Rnb Resistors FF1 to FFn JK flip-flop C1, C1a to Cna Capacitors NA0 to NAn NAND circuit

Claims (5)

An output circuit having a first insulated gate field effect transistor and a second insulated gate field effect transistor connected in series between an input voltage and a reference potential, and outputting a voltage obtained by transforming the input voltage;
A drive circuit that alternately turns on and off the first insulated gate field effect transistor and the second insulated gate field effect transistor in response to a drive signal;
Of the first insulated gate field effect transistor and the second insulated gate field effect transistor, the gate voltage of the insulated gate field effect transistor in the on state is the same as the voltage when the gate voltage starts to reverse and the insulated gate in the on state. An elapsed time from a first voltage set between the threshold of the field effect transistor to a second voltage set between the first voltage and the threshold is obtained, and the elapsed time Control means for outputting to the drive circuit a control signal for turning on the insulated gate field effect transistor in an off state, a signal delayed according to
A semiconductor integrated device comprising: The control means includes
A first voltage comparison circuit that compares the gate voltage with the first voltage and outputs a first comparison result;
A second voltage comparison circuit that compares the gate voltage with the second voltage and outputs a second comparison result;
A time calculation circuit for obtaining an elapsed time from the first voltage to the second voltage using the first comparison result and the second comparison result;
An arithmetic circuit that delays the second comparison result according to the elapsed time and outputs the delayed second comparison result to the drive circuit;
The semiconductor integrated device according to claim 1, comprising:   The first voltage comparison circuit is equal to a first comparator in which the gate voltage is supplied to one input terminal and a first reference voltage equal to the first voltage is supplied to the other input terminal, or equal to the first voltage A first CMOS inverter having a threshold value, wherein the second voltage comparison circuit is supplied with the gate voltage at one input terminal and supplied with a second reference voltage equal to the second voltage at the other input terminal; 3. The semiconductor integrated device according to claim 2, further comprising a second comparator or a second CMOS inverter having a threshold value equal to the second voltage.   The time calculation circuit starts counting a clock based on the first comparison result, stops counting a clock based on the second comparison result, and outputs a signal based on the first comparison result. A multi-stage connected inverter circuit that starts and stops propagation of the signal according to the second comparison result, and a detection circuit that detects to which inverter stage the signal has propagated are provided. The semiconductor integrated device according to claim 2.   The arithmetic circuit includes a series circuit of a CR time constant circuit in which a CR time constant is adjusted according to the elapsed time and an inverter, or a series circuit of a CR time constant circuit and an inverter having different CR time constants. The semiconductor integrated device according to claim 2, wherein any one of the series circuits is selected according to the elapsed time.

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