TW201351155A - Controlled intermediate bus architecture optimization - Google Patents

Abstract

An intermediate bus architecture power system includes a bus converter that converts an input voltage into a bus voltage on an intermediate bus and a point-of-load converter that supplies an output voltage from the bus voltage on the intermediate bus. Additionally, the intermediate bus architecture power system includes a decision engine optimizing controller that controls a system variable to improve an overall system performance based on a monitored system variable or a system constraint. In another aspect, a method of operating an intermediate bus architecture power system includes converting an input voltage into a bus voltage on an intermediate bus and converting the bus voltage on the intermediate bus into an output voltage. The method also includes controlling a system variable to improve overall system performance based on a monitored system variable or a system constraint.

Description

Controlled intermediate bus architecture optimization Related application cross-reference

The present application claims priority to U.S. Provisional Application Serial No. 61/488,440, filed on Jan. The cases are collectively assigned and incorporated herein by reference.

This application claims priority to U.S. Provisional Application Serial No. 61/488,450, filed on Jan. The manner is incorporated herein.

This application is generally directed to power conversion, and more particularly to an intermediate busbar architecture power system and a method of operating an intermediate busbar architecture power system.

The intermediate bus power system typically includes a DC bus voltage that is supplied to one of a plurality of load point converters (POLs) through an intermediate bus structure. Each of the plurality of POLs provides a separate output voltage for one of the loads that can change over time. Those skilled in the art will recognize that a POL can be a modular or discrete implementation and can also provide multiple output voltages for multiple loads. Overall system efficiency is proportional to the efficiency of the bus converter For example, and in proportion to the effectiveness of the plurality of POLs used. This overall system efficiency depends on a number of factors including a DC input voltage and DC bus voltage as well as the design and operational characteristics of the busbar converter and POL. Therefore, the overall system efficiency is optimized for the load and depends on a variety of factors. Improvements in this area will demonstrate the advantages of this technology.

Embodiments of the present invention correspond to an intermediate bus architecture power system and a method of operating an intermediate bus architecture power system.

In one embodiment, the intermediate busbar architecture power system includes a busbar converter that converts an input voltage into a busbar voltage on an intermediate busbar, and a busbar voltage supply and an output from the intermediate busbar One of the voltage load point converters. Additionally, the intermediate busway architecture power system includes a decision engine optimization controller that controls a system variable based on a monitored system variable or a system constraint to improve an overall system performance.

In another aspect, a method of operating an intermediate busbar architecture power system includes converting an input voltage to a busbar voltage on an intermediate busbar and then converting the busbar voltage on the intermediate busbar to an output voltage. The method also includes controlling a system variable based on a monitored system variable or a system constraint to improve overall system performance.

The above description of the invention has been set forth in the Detailed Description of the invention. Additional features of the invention that form the subject matter of the technical solutions of the present invention are described below. Those skilled in the art will appreciate that the concept and specific embodiments disclosed may be readily utilized as a basis for designing or modifying other structures to practice the invention.

100‧‧‧Intermediate busbar architecture power system

105‧‧‧ Busbar Converter

110‧‧‧Intermediate busbar

115 ₁ ‧‧‧Load Point Converter

115 ₂ ‧‧‧Load Point Converter

115 _N ‧‧‧Load Point Converter

600‧‧‧Decision-based controller

605‧‧‧Decision Engine Optimization Controller

610‧‧‧Independent variables

615‧‧‧Dependent variables

620‧‧‧System Constraints

700‧‧‧Intermediate busbar architecture power system

705‧‧‧ Bus Bar Converter

706‧‧‧ bus bar connection

710‧‧‧Intermediate busbar

715 ₁ ‧‧‧Load point converter

715 ₂ ‧‧‧Load Point Converter

715 _N ‧‧‧Load Point Converter

720‧‧‧Decision Engine Optimization Controller

900‧‧‧Intermediate busbar architecture power system

905‧‧‧ Bus Bar Converter

906‧‧‧ bus bar connection

910‧‧‧Intermediate busbar

915 ₁ ‧‧‧Load point converter

915 ₂ ‧‧‧Load point converter

915 _N ‧‧‧Point of Load Converter

920‧‧‧Decision Engine Optimization Controller

925‧‧‧ data and control bus

930‧‧‧Power Interface Module

1000‧‧‧Intermediate busbar architecture power system

1005‧‧‧ Bus Bar Converter

1006‧‧‧ bus bar connection

1010‧‧‧Intermediate busbar

1015 ₁ ‧‧‧Load point converter

1015 ₂ ‧‧‧Load Point Converter

1015 _N ‧‧‧Load Point Converter

1020‧‧‧Decision Engine Optimization Controller

1025‧‧‧Data and control bus

1030‧‧‧Power Interface Module

1035‧‧‧Global System Controller

1100‧‧‧Intermediate busbar architecture power system

1105‧‧‧ Busbar Converter

1106‧‧‧ bus bar connection

1110‧‧‧Intermediate busbar

1115 ₁ ‧‧‧Load point converter

1115 ₂ ‧‧‧Load point converter

1115 _N ‧‧‧Load Point Converter

1120‧‧‧Decision Engine Optimization Controller

1125‧‧‧ Data and Control Busbars

1130‧‧‧Power Interface Module

1135‧‧‧Global System Controller

1145‧‧‧Parallel busbar converter

1146‧‧‧ parallel busbar connection

C _IB ‧‧‧Intermediate busbar capacitor

V _BUS ‧‧‧ busbar voltage

V _INPUT ‧‧‧ input voltage

V _O1 ‧‧‧Output voltage

V _O2 ‧‧‧ output voltage

V _ON ‧‧‧ output voltage

V _SOURCE ‧‧‧Power supply voltage

The following description is now referred to in conjunction with the accompanying drawings in which: FIG. 1 illustrates a simplified block diagram of an intermediate bus power system that can be used to check various general features of the intermediate bus bar architecture; 2 illustrates a set of efficiency curves for a typical 48 volt input, 400 watt converter at various output voltages; FIG. 3 illustrates an exemplary set of efficiency curves for a point of load (POL) converter, which generally shows The increased efficiency characteristics vary with lower intermediate bus voltages; Figure 4 illustrates one example of intermediate bus loss characteristics due to various busbar distribution losses; Figure 5 illustrates a wide power conversion efficiency (indicated as 500 overall) ), which combines the efficiency features previously discussed with respect to Figures 2, 3, and 4; Figure 6 illustrates a block diagram of one embodiment of a decision-based controller constructed in accordance with the principles of the present invention; One block diagram of one embodiment of an intermediate busbar architecture power system constructed in accordance with the principles of the present invention; FIGS. 8A, 8B, and 8C illustrate an intermediate busbar architecture implemented in accordance with the principles of the present invention. A flowchart of an embodiment of a method for optimizing the efficiency of a power system, generally designated 800, 820, 850; FIG. 9 illustrates another embodiment of an intermediate bus structure power system constructed in accordance with the principles of the present invention. a picture 10 is a block diagram showing still another embodiment of an intermediate busbar architecture power system in accordance with the principles of the present invention; and FIG. 11 is a diagram showing the construction of an intermediate busbar power system in accordance with the principles of the present invention. A block diagram of an embodiment; and FIG. 12 is a flow diagram of one embodiment of a method of operating an intermediate bus architecture power system in accordance with the principles of the present invention.

For DC power systems having a power capability of at least 50 watts, a busbar converter is commonly used to generate an intermediate busbar voltage that supplies one of a plurality of load point converters (POL), which in turn provides a plurality of output voltages to the split load. 1 illustrates a simplified block diagram of an intermediate bus power system (collectively indicated at 100) that can be used to examine various general features of the intermediate busbar architecture. The intermediate bus power system 100 includes a busbar converter 105 that uses an input voltage (e.g., 48 volts DC) to provide an intermediate busbar voltage on an intermediate busbar 110. The intermediate bus power system 100 also includes a plurality of POLs 115 ₁ through 115 _N that provide N independently regulated DC output voltages (eg, 1.0 volts, 1.2 volts, etc.), as shown.

In general, for a constant input voltage, the efficiency of a busbar converter increases as its busbar output voltage increases. For example, a 12 volt output bus voltage converter would be more efficient than a 6 volt output bus voltage converter because the 6 volt bus voltage converter supplies the 12 volt confluence for a constant power level. The output current of the voltage converter is twice the output current, which increases the resistance loss, resulting in lower overall efficiency.

Figure 2 illustrates a set of efficiency curves (indicated generally at 200) for a typical 48 volt input, 400 watt converter at various output voltages. It is apparent that in addition to very light loads, the busbar converter operates more efficiently for a given output power due to an increase in its output voltage. In addition, the higher losses incurred by lower output voltages also limit the available output power. For example, if one of the output currents from the busbar converter is absorbed by more than 33 amps, a 5 volt output busbar converter can only supply about 165 watts, while the same converter can deliver 400 watts at a 12 volt output.

3 illustrates an exemplary set of efficiency curves (shown generally as 300) of a POL converter showing that the increased efficiency characteristic varies with lower intermediate bus voltage. The efficiency characteristics of a POL converter vary with its output voltage, its load current, and the bus voltage that supplies the POL converter input. In contrast to busbar converters, the efficiency of a POL converter increases as the busbar voltage decreases. Therefore, supplying a lower bus voltage to the POL converter increases its efficiency, while the bus converter operates more efficiently by a higher bus voltage.

One of the third factors contributing to the loss is due to the distribution resistance of the busbar. Figure 4 illustrates an example of an intermediate busbar loss characteristic due to various busbar distribution losses (indicated generally as 400). As can be seen by examining the loss feature 400, the distribution loss is increased by the decrease in the busbar voltage (the decrease in the busbar voltage is due to an increase in the current that can be supplied to a desired load).

Combining the efficiency features previously discussed produces an exemplary overall efficiency feature. Figure 5 illustrates a wide power conversion efficiency (indicated generally at 500) that combines the efficiency characteristics previously discussed with respect to Figures 2, 3, and 4. In this example, the best overall efficiency is obtained by operating at the lowest busbar voltage (5 volts in this case). However, at this output voltage, only 165 watts (5V at 33A) can be obtained from the output of the busbar converter, since the busbar converter will limit its output current. In this simple example, adjusting the bus voltage from 5 volts at the light load to 14 volts at the maximum load provides one of the systems with optimized efficiency. Of course, other examples can show different sets of efficiency curves.

Since the bus voltage changes due to input voltage and load current, optimizing system efficiency when using an unregulated busbar converter is more complicated. In addition, although an unregulated bus converter can itself have an inherent efficiency that is slightly higher than the efficiency of a regulated bus converter, the supply of "uncontrolled" bus voltage can result in lower than the use of one of the most One of the efficiency of one of the regulated busbar converters, one of the efficiency of the power system, is the efficiency of the overall power system.

Embodiments of the present invention use a decision engine optimization controller that controls a system variable based on a monitored system variable or a system constraint to improve an overall system efficiency. This provides an optimization of the overall efficiency of one of the intermediate bus power systems as compared to the efficiency optimization of the various components of an intermediate bus power system. This overall efficiency optimization can be achieved even if some components of the intermediate bus power system operate at less than their maximum available efficiency. The operational power system data and operational characteristics of the components can be stored in advance or measured in time for optimization of the overall efficiency.

The control of the intermediate bus power system can be provided by a local area controller integrated with one or more of the components (e.g., a bus bar converter) or a separate controller. The local area controller can also operate in conjunction with a global system controller or some combination of the three embodiments.

Additionally, a plurality of busbar converters can be used to provide an intermediate busbar voltage and share an intermediate busbar current with a plurality of POL converters. At least one of the busbar converters is a regulated busbar converter, and the other busbar converters may be adjusted or unregulated.

6 is a block diagram (collectively designated 600) of one embodiment of a decision-based controller constructed in accordance with the principles of the present invention. The decision-based controller 600 includes a decision engine optimization controller 605 that uses independent variables 610, dependent variables 615, and system constraints 620 to provide control decisions to a corresponding system. The decision engine optimization controller 605 changes the decision engine of one of the independent variables 610 using the independent variable 615 or the system constraint 620 for determining how to respond to the monitored independent variable 615. In one embodiment, the decision engine uses a series of logical operations and mathematical calculations based on dependent variables and affecting an independent variable. In a more general embodiment, any number of dependent variables and independent variables can be considered along with system constraints.

For example, the decision engine optimization controller 605 can include portions of a digital controller for performing regulation and control of a bus converter. More specifically, for example, the decision engine optimization controller 605 can include one or several algorithms embedded in a computer code implemented on a digital controller integrated circuit (IC). The digital controller IC can include a single digital controller that implements both the decision engine optimization controller 605 algorithm and the adjustment and control of a bus converter. Alternatively, the digital controller IC can include a plurality of digital control ICs that implement the busbar converter regulation, control, and the decision engine optimization controller.

In general, the embodiment illustrated in FIG. 6 and related embodiments to be discussed have exclusive A variable that depends on or depends on one of the control architectures used. For the purposes of the present invention, a number of independent variables are defined as such variables that are directly controllable. Accordingly, for the purposes of the present invention, dependent variables are defined as such variables that are monitored to determine, for example, whether a desired result has been achieved.

In general, a plurality of variables can be used as independent variables controlled within one embodiment of the invention using a decision engine optimization controller. An independent variable instance corresponding to any member of a power solution of a related embodiment may include an output voltage (such as a bus voltage), a switching frequency or phase (of any member of the power solution), (power solution a switching sequence, a gate drive voltage (of any component of any member of the power solution), a plurality of enable switching devices (of any member of the power solution), (power solution Multiple enable switching phases or an active perturbation of any member. Those skilled in the art will recognize that other independent variables can be equally controlled in one embodiment of the invention.

A plurality of variables can also be used as dependent variables monitored by an embodiment of the invention using a decision engine optimization controller, and can be used or not available in a decision to make a change to an independent variable. An example of a dependent variable corresponding to any member of a power solution of a related embodiment may include an output current, an efficiency, a power dissipation, an electromagnetic interference (EMI), an output surge, an instantaneous response, a temperature, A current sharing signal or response to one of the actively generated disturbances. Moreover, those skilled in the art will recognize that other variables can be similarly monitored in an embodiment.

In addition, system constraints can be used in a decision to make changes to an independent variable or to limit changes in an independent variable. System constraints can also limit changes in a dependent variable. These constraints include pre-set conditions established prior to system operation, as well as constraints imposed on the user to make changes to the user's settings that affect system operation. Field constraints are such constraints inherent in system operation, where an alarm can be considered as a special example of a field system constraint. In addition, adaptation constraints occur when a system adapts its functionality during system operation. In addition, familiar with Those skilled in the art will recognize that certain constraints or other constraints within such categories may be applied to an embodiment.

In the example of one of the independent variables of a bus voltage, a corresponding dependent variable is a bus current because it depends in part on the bus voltage. For example, the bus voltage can be varied such that the bus current meets the requirements set by system constraints. Another dependent variable is one of the results that can be indirectly improved (associated with a static bus voltage) as one of the results of the new bus voltage and the bus current variable.

Additionally, an independent variable can be an actively generated disturbance, and one or more dependent variables can be responsive to the actively generated disturbance. Alternatively, the independent and dependent variables may use passive system features. In addition, a mixture of actively generated disturbances and passive system features can form independent and dependent variables.

An independent variable can also be used as a dependent variable. An example of this is to determine one of the bus voltages by a decision engine optimization controller, but can change due to other effects and therefore needs to be monitored. In this case, it is a dependent variable, and the controller can make a change to affect it as an independent variable. Dependent variables can also be monitored directly or indirectly. An example of this is a bus current as a direct dependent variable, and a system efficiency as an indirect dependent variable.

A decision engine optimization controller monitors the temperature, current, and power dissipation of a bus converter. Based on the dependent variables, the decision engine optimization controller can establish a bias voltage in the bus voltage or switching frequency and phase to minimize the merit based on the dependent variables. For example, the independent and dependent variables can use the busbar switching frequency and phase independent variables along with the busbar voltage to improve one of the heat distributions between the plurality of parallel busbar converters. The corresponding dependent variables may include busbar converter power dissipation, busbar converter temperature, and busbar converter output current.

A decision engine optimization controller can monitor changes in a system characteristic over time and respond to the change. For example, a bus distribution loss can be degraded over time (for example, Change due to environmental corrosion). In this case, a constraint, such as a maximum busbar voltage, can be varied to compensate for this degradation.

7 is a block diagram (indicated generally at 700) of one embodiment of an intermediate busbar power system constructed in accordance with the principles of the present invention. The intermediate busbar architecture power system 700 includes a busbar converter 705 having a busbar connection 706 that converts a DC input voltage _VINPUT into a DC busbar voltage _VBUS on an intermediate busbar 710. The intermediate bus bar architecture power system 700 also includes a plurality of load point converters (POL) 715 ₁ , 715 ₂ ... 715 _N connected to the intermediate bus bar 710, the intermediate bus bar 710 from the bus bar voltage V _{The BUS} supplies a plurality of corresponding output voltages V _O1 , V _O2 ... V _ON .

The intermediate busbar architecture power system 700 further includes an algorithm that is embedded in and coupled to the busbar converter 705, and controls a system variable based on a monitored system variable or system constraint to improve overall system performance. Controller 720. For example, the decision engine optimization controller 720 can include a portion of a digital controller for performing regulation and control of a bus converter. More specifically, for example, the decision engine optimization controller 720 can include one or several algorithms embedded in computer code implemented on a digital controller IC. The digital controller IC can include a single digital controller that implements both the decision engine optimization controller 720 algorithm and the adjustment and control of a bus converter. Alternatively, the digital controller IC can include a plurality of digital control ICs that implement the busbar converter regulation, control, and the decision engine optimization controller.

The present invention has the advantage that the busbar converter 705 can automatically adjust the busbar voltage _VBUS . First, no external controller is required, as in this embodiment, the decision engine optimization controller 720 (i.e., at least its functionality and intent) has been integrated into the bus converter 705. In fact, this method can be used in different types of bus converters, from the use of analog interface and analog control bus converters to a full digital bus converter (including interface and control). Second, design and development are simplified because no external controller is required. This can be expected to significantly increase the efficiency of one of the improved schemes using a bus voltage modulation with system load. Third, this solution provides a reverse footprint that is interchangeable with existing outlets, with an existing busbar converter being replaced. In particular, in existing applications, an effective efficiency boost on a fully tuned analog converter can be obtained by using a combination of analog interface and digital control. Conversion options are also supported to save energy and cost.

The busbar connection 706 provides a controllable connection between the busbar converter 705 and an intermediate busbar 710 comprised of one or a plurality of parallel switches (e.g., field effect transistors (FETs)) that are detachably controllable. This capability allows modification of the switching resistance for one of the busbar connections 706. Alternatively, the busbar connection 706 can include a simple low impedance soldering or connectorized connection to improve system efficiency.

In the illustrated embodiment, the bus converter 705 includes the decision engine optimization controller 720 and can automatically (ie, without any communication from an external controller) change the sink The voltage V _BUS is drained to optimize the efficiency of the intermediate bus architecture power system 700. The bus bar converter 705 can measure, for example, its output current and automatically set the bus bar voltage V _BUS to improve the operation of a fixed bus bar voltage to meet the level of one system power conversion efficiency. This is accomplished by meeting the need for one of the load requirements for powering up to a design maximum (ie, a constraint). When the busbar converter 705 is powered on, for example, the algorithm in the decision engine optimization controller 720 can be automatically enabled, or alternatively, when the busbar converter 705 is powered on, the decision can be deactivated. The engine optimizes the algorithm in controller 720. If the algorithm in the decision engine optimization controller 720 is deactivated, the user can enable the decision engine optimization controller by communicating with the bus converter via, for example, a digital communication bus. 720. Alternatively, one of the contacts of the busbar converter 705 can be used by the user to indicate whether the busbar voltage change algorithm is enabled.

In addition, other embodiments may pass the bus bar voltage V _BUS (ie, using the intermediate bus bar 710 as a communication bus bar) between the bus bar converter 705 and the POLs 715 ₁ , 715 ₂ ... 715 _N Communication is provided for use by the integrated decision engine optimization controller 720. For example, the intermediate bus voltage V _BUS can be modulated to carry digital or analog information between the bus converter 705 and at least one of the POL converters 715 ₁ , 715 ₂ ... 715 _N .

The busbar converter 705 can also use additional methods to improve system efficiency based on an operational characteristic (eg, including, but not limited to, an output current, an input current, an output power, an input power, an input voltage, etc.) . For example, the busbar converter 705 can adjust its switching frequency in accordance with an operational characteristic. Additionally, it may be advantageous to reduce the switching frequency at one of the lower output power levels to further improve efficiency.

Alternatively to the efficiency of an output feature, the busbar converter 705 can adaptively adjust the timing between its various power switches. In particular, timing adjustments between the primary reference power switch and the secondary reference synchronous rectifier can be used. Yet another method of improving efficiency in accordance with an output feature is that the busbar converter 705 adaptively adjusts one of the gate drive levels of one or more power switches. These examples of additional methods of efficiency improvement are intended to be illustrative and not limiting.

An exemplary idea in such efficiency improvement schemes is that the bus converter 705 always has the lowest possible bus voltage V _BUS (or an optimal switching frequency, an optimal switching timing relationship, an optimal gate driving voltage). The operation, while satisfying the conditions under which the extracted output current meets its design constraints.

8A, 8B, and 8C are flow diagrams showing an embodiment of a method for implementing efficiency optimization of an intermediate bus architecture power system in accordance with the principles of the present invention, generally designated 800, 820, 850. In general, the methods 800, 820, and 850 can be applied to control decisions provided by embodiments of a decision engine optimization controller as discussed with respect to the present invention.

In one example, the methods can be implemented as a busbar converter (eg, busbar converter 705 of FIG. 7) using an analog circuit or a digital circuit or a combination of the two. Minute. Digital implementations may be a preferred embodiment as digital implementations generally provide greater flexibility. A number of key parameters can be established as values stored in the busbar converter during the busbar converter manufacturing test, or as values that are changed or stored through a digital interface, such as a power management busbar. This can occur before or after assembly of the busbar converter, and before the busbar converter is required to operate to deliver output power.

Examples of such parameters include adjusting a bus bar voltage Vo (eg, the DC bus bar voltage V _BUS of the intermediate bus bar 710 of FIG. 7) to its vicinity to optimize efficiency for a single bus bar converter output current. Threshold Io, 1. In addition, the parameters may include a first bus converter output current threshold Io, 1 (which can reduce a bus voltage Vo to be lower than its efficiency for improvement), and a second bus converter output Current threshold Io, 2 (need to raise the bus voltage Vo higher than it to avoid exceeding the maximum rated bus converter current capability based on the minimum and maximum allowable bus converter output voltages Vo, min, Vo, max Io, max). In this case, for example, Io, 1 may be selected as Io, 70% of max, and Io, and 2 may be selected as 85% of Io, max.

Method 800 uses a single busbar converter to output current threshold Io,1 and begins at step 802. Next, in a step 804, one of the output currents Io is supplied from an intermediate bus. A decision step 806 determines if the output current Io is less than the busbar output current threshold Io,1. If the output current Io is less than the bus converter output current threshold Io,1, then in a step 808, calculate a new lower output that is greater than or equal to a minimum allowable bus converter output voltage Vo,min Voltage Vo. The new lower output voltage Vo is set in a step 810 and the method returns to step 804. If, in step 806, the output current Io is not less than the busbar converter output current threshold Io,1, then in one step 812, one of the maximum allowable busbar converter output voltages Vo,max is calculated to be less than or equal to one. New higher output voltage Vo. The new higher output voltage Vo is set in a step 814, and the method 800 returns again to step 804 where the output is continuously measured. The current Io is adjusted correspondingly to the output voltage Vo.

The method 820 uses the first busbar converter output current threshold Io,1 and the second busbar converter output current threshold Io,2, and begins in a step 822. Next, in a step 824, one of the output currents Io is supplied from an intermediate bus. A decision step 826 determines if the output current Io is less than the first bus converter output current threshold Io,1. If the output current Io is less than the first bus converter output current threshold Io, 1, a decision step 828 determines if an output voltage Vo is greater than a minimum allowable bus voltage Vo, min. If the output voltage Vo is not greater than the minimum allowable bus voltage Vo,min, then the method 820 returns to step 824 where the output current Io continues to be measured.

If the decision step 828 determines that the output voltage Vo is greater than the minimum allowable bus voltage Vo,min, then a new lower output voltage Vo is calculated in a step 830, and the new lower output is set in a step 832. Voltage Vo (wherein the new lower output voltage Vo is equal to (Vo x Io) / (Io, 1), which is greater than or equal to the minimum allowable bus bar voltage Vo, min). The method 820 again returns to step 824 where the output current Io continues to be measured.

If, in decision step 826, the output current Io is not less than the first busbar converter output current threshold Io, 1, a decision step 834 determines if the output current Io is greater than or equal to the second busbar converter. Output current threshold Io, 2. If the output current Io is not greater than or equal to the second bus converter output current threshold Io, 2, the method 820 again returns to the step 824 where the output current Io continues to be measured.

If the output current Io is greater than or equal to the second bus converter output current threshold Io, 2, a new higher output voltage Vo is calculated in a step 836, and the new one is set in a step 838. A higher output voltage Vo (wherein the new higher output voltage Vo is equal to (Vo x Io) / (Io, 2), which is less than or equal to the maximum allowable bus bar voltage Vo, max). The method 820 then returns to the step 824 where the output current Io continues to be measured and the output voltage Vo is adjusted accordingly.

Method 850 also uses the first busbar converter output current threshold Io, 1 and second sink The streamer converter outputs current thresholds Io, 2 and output voltage modifications using discrete output voltage steps. The method 850 begins at a step 852 and measures an output current Io in a step 854. Next, a decision step 856 determines if the output current Io is greater than the second bus converter output current threshold Io,2. If the output current Io is greater than the second bus converter output current threshold Io, 2, an output voltage Vo is raised to a maximum allowable bus voltage Vo, max, and the method 850 returns to step 854.

If the output current Io is not greater than the second bus converter output current threshold Io, 2, a decision step 860 determines whether the output current Io is less than the first bus converter output current threshold Io, 1 . If the output current Io is not less than the first busbar converter output current threshold Io, 1, the method 850 returns to step 854 again. If the output current Io is less than the first bus converter output current threshold Io, 1, a decision step 862 determines if the output voltage Vo is greater than a minimum allowable bus voltage Vo, min. If the output voltage Vo is not greater than a minimum allowable bus voltage Vo,min, then the method 850 returns to step 854 again. If the output voltage Vo is greater than a minimum allowable bus voltage Vo,min, then a decision step 864 determines if the number of voltage steps is greater than the one-step limit value Co. If the number of voltage steps is not greater than the step limit value Co, then the number of voltage steps is incremented by one in step 866, and the method 850 returns to step 854. If the number of voltage steps is greater than Co, the output voltage Vo is reduced in a step 868 by a correction of the fixed voltage step Vstep. In a step 870, the number of voltage steps is reset to zero, and the method 850 returns to step 854 again.

In particular, for example, the method 850 can reduce implementation complexity of an output voltage change scheme for one of the busbar converters 705. Providing a change to the bus voltage V _BUS in discrete steps may allow for the use of a lookup table to determine other combinations of new bus voltages V _BUS or system variables for a particular power level, and thereby eliminating the need for multiplication or Division calculation. Using discrete bus voltage steps also minimizes the frequency of bus bar voltage changes, thereby reducing the disturbance of the bus bar voltage level. The use decision step 864 can slow down the rate at which the bus voltage is reduced to ensure that the system is properly adjusted to a lower bus voltage (and therefore a higher bus current).

The bus voltage change can be implemented in variable steps to accommodate different parameters when optimized. For example, during the reduced bus voltage V _BUS, the bus voltage V _BUS in the smaller step size may advantageously be used for the system to load balance before reaching a final level converter output bus. Similarly, following the increase in load power level, the bus voltage V _BUS is gradually increased in a larger step to quickly adapt to the new load power level.

In addition to being aggressive in increasing the busbar voltage but by gradually reducing the busbar voltage by using smaller steps, many other variations of such exemplary methods are also possible. The use of Io, 1 and Io according to other variables (such as a bus voltage Vo, temperature, etc.), the ratio of the variable ratio of 2 to Io, max can also make the advantages stand out. Additionally, such exemplary methods can be modified by incorporating other parameters or variables. For example, a period T1 can be used which is how long it takes to optimize the current measurement efficiency of a busbar converter (eg, every T1 second). Alternatively, increasing a rate of change S1 of an output voltage when an output current Io is equal to or greater than Io, 2 or decreasing a rate of change S2 of an output voltage Vo when the output current Io is less than Io, is another example.

In addition, the change in the bus voltage V _BUS can be achieved by charging the bus bar voltage V _BUS at a lower rate than the triggering of an overcurrent condition by charging of an intermediate bus capacitor C _IB . The maximum allowable bus voltage change rate can be determined by a user or from pre-test or by stylizing the value of the capacitor used (for example, during a manufacturing test of a system).

Since the onboard power conversion system can vary from unit to unit based on small differences in specific power subsystem characteristics, the actual measurements made during the test (such as during the process of the component module or assembly system) can be used to determine a variable (such as The optimum setting of bus voltage V _BUS ). The optimal setting may vary with one or more power conversion system variables, such as output power, module temperature, and the like. Pre-tests and features allow for the use of pre-optimized settings, thereby reducing the calculations involved in actual system usage and increasing the speed of responding to new variable values.

For example, in a power conversion embodiment, such as intermediate busbar architecture power system 700, busbar voltage _VBUS may need to be changed to accommodate an increased load level. In some cases, the load level can increase rapidly to exceed the output current limit for one of the busbar converters 705. To support this short-term increase in load level without shutting down the busbar converter 705, the current limit of the busbar converter 705 can be increased to a higher current level for a predetermined period of time to support the busbar Converter 705 continues to operate in an instantaneous load condition. This capability allows for a more aggressive setting of the optimization of the bus voltage V _BUS .

It should be apparent to those skilled in the art that one of the independent busbar converters (eg, an autonomous busbar converter having an embedded decision engine optimization controller) is described above as an intermediate busbar architecture power system. Features and advantages can also be applied to another intermediate bus architecture power system in which a bus converter optimizes the controller using one of the decision engines that are separate and separate from itself.

9 is a diagram of another embodiment of an intermediate busbar architecture power system constructed in accordance with the principles of the present invention, generally designated 900. The intermediate bus bar architecture power system 900 includes a bus bar converter 905 having a bus bar connection 906 that converts an input voltage V _INPUT into an intermediate bus bar 910 having one of the intermediate bus bar capacitors C _IB as shown in the display connection. One of the bus bars voltage V _BUS . The intermediate busbar architecture power system 900 also includes a plurality of POL converters (POL) 915 ₁ , 915 ₂ ... 915 _N having a number of inputs connected to the intermediate busbar 910, the intermediate busbar 910 from the busbar The voltage V _BUS supplies a plurality of corresponding output voltages V _O1 , V _O2 ... V _ON .

The intermediate busway architecture power system 900 further includes a decision engine optimization controller 920 that controls a system variable based on a monitored system variable or system constraint to improve overall system performance. In addition, the intermediate bus bar architecture power system 900 includes a data and control bus 925 operating as a communication bus, and a power interface module 930 connected to one of the supply voltages V _SOURCE that provides an input voltage V _INPUT .

As before, the bus current 906 provides a controllable connection of the busbar converter 905 to one of the intermediate busbars 910. The bus bar connection 906 can include one or a plurality of parallel switches (eg, FETs), wherein each switch can be independently controlled to allow modification of one of the plurality of parallel switches. Alternatively, the busbar connection 906 can include a simple low impedance soldering or connectorized connection to improve system efficiency. The purpose of the power interface module 930 is to adjust the power supply voltage V _SOURCE before the power supply voltage V _{SOURCE is} fed to the bus bar converter 905 (eg, to provide electromagnetic interference filtering, dual power supply voltage feed processing or the input) The voltage V _INPUT is boosted to facilitate traversal).

In the illustrated embodiment, the data and control bus 925 is coupled between the components of the intermediate bus architecture power system 900 to permit data transfer between all or at least a portion of the components. . Additionally, the decision engine optimization controller 920 can provide system control of the components that are controlled by the data and control bus 925. Here, the data and control signals are integrated into the data and control bus 925. Alternatively, the data and control signals may use separate bus bars.

In one case, the decision engine optimization controller 920 is a separate system controller separate from the other components. Alternatively, the decision engine optimization controller 920 can be integrated into one of the other components or Many, for example, one or more of bus bar controller 905 or POL 915 ₁ , 915 ₂ ... 915 _N.

In one embodiment, the decision engine optimization controller 920 automatically operates to optimize a whole when adjusting various parameters within the components (eg, bus voltage V _BUS or a frequency or a switching timing) System efficiency. As mentioned, each of the components communicates with one or more of the other components via the data and control bus 925. For example, the data and control bus 925 can operate in accordance with an internal integrated circuit (I ² C) communication busbar specification. Alternatively, other communication bus and bus protocols can be used, including a controller area network (CAN) bus, a serial peripheral interface (SPI) bus, or any wired, wireless, or optical communication bus method. Of course, this communication can be bidirectional or one-way communication, as needed.

As before, in some embodiments, communication between at least a portion of the components can be accomplished by bus bar voltage V _BUS . This may include communication between bus bar converter 905 and PLOs 915 ₁ , 915 ₂ ... 915 _N . As an example, the bus voltage V _BUS can be modulated by a higher frequency data signal, wherein each of the active components includes a modulated and demodulated high frequency data signal to be optimal with the decision engine. The controller 920 communicates one of the capabilities regardless of its location (ie, independent or integrated). In some embodiments, communication via the intermediate bus 910 can eliminate the need for a separate data and control bus 925 (eg, one of the embodiments of FIG. 7 above).

As mentioned, the decision engine optimization controller 920 can be integrated into one of the components (eg, bus converter 905) allowing it to monitor system performance and direct other components to perform internal adjustments. In this example, the bus converter 905 includes sufficient processing and memory capabilities to perform as the decision engine optimization controller 920 when, for example, adjusting the bus voltage V _BUS , while also instructing the POL 915 _{One of the 1} , 915 ₂ ... 915 _N or more to adjust a switching frequency. Of course, these POL 915 ₁ , 915 ₂ ... 915 _N can also be adjusted in other ways.

Each of these components (eg, POL 915 ₁ , 915 ₂ ... 915 _N ) can exhibit its own unique performance characteristics. A POL model can exhibit a different efficiency curve when compared to a different POL model. Each of these models can also react differently to other adjustments, such as switching timing or switching frequency changes. These inherent differences between different POL models can optimize an overall system efficiency and can cause an overall efficiency that is less efficient than otherwise accomplished when considering such inherent differences.

The decision engine optimization controller 920 (whether independent or integrated) can be configured to read the model of individual components (eg, POL 915 ₁ , 915 ₂ ... 915 _N ) to understand the intermediate bus The specific configuration of the architecture power system 900. The decision engine optimization controller 920 can then be programmed with specific representative features for each particular model and take this information into account when calculating overall efficiency optimization. In this manner, the decision engine optimization controller 920 can adjust each of the components a little differently, thereby generally achieving better efficiency optimization than otherwise done without this information. An efficiency optimization.

For example, for different POLs, an optimal switching frequency can be different depending on the particular operating conditions. In addition, an optimal bus voltage V _BUS can also be modified to optimize the efficiency of a particular configuration. For example, the model specific information can be stored in the decision engine optimization controller 920 as a lookup table, or this information can be included as part of the control algorithm used by the decision engine optimization controller 920.

Alternatively, each of the components can have certain aspects of its particular performance characteristics determined at a test stage, and then stored in non-volatile memory of the tested component. The decision engine optimization controller 920 can then read this information along with the model number, or can read this information instead of the model number and use a particular performance feature in an optimized algorithm. In this manner, a higher efficiency can be achieved when the intermediate busway architecture power system 900 can be adjusted and optimized by considering the actual test characteristics of the components rather than their representative characteristics.

Additionally, the decision engine optimization controller 920 can change the bus voltage V _BUS to optimize the efficiency to determine the operating point of maximum efficiency by utilizing an algorithm. For example, the decision engine optimization controller 920 can perform one of the routines of incrementing the bus voltage V _BUS while monitoring one of the input currents to the intermediate bus architecture power system 900. Next, the bus voltage V _{BUS is} set at the point of the minimum input current. This algorithm can be run periodically or according to commands. The algorithm can use averaging or smoothing techniques to avoid responding to transient conditions.

Looking at the processing power of the decision engine optimization controller 920, an optimized algorithm can exceed the available processor bandwidth, especially if the processor has other tasks to perform (such as loop compensation and duty cycle determination). Time. Thus, for example, the decision can be advantageously used The engine optimizes one of the controllers 920 to separate the processor to perform an optimization task or to separate the core using one of a multi-core processor.

In the intermediate busbar architecture power system 900, the adjustment of the busbar voltage _VBUS can advantageously take precedence over the load power information provided directly by a load. This allows the bus voltage V _BUS to be adjusted to best correspond to the new load power level before actually changing to a new level of load. Information from the load can be provided directly to the decision engine optimization controller 920 regardless of its location.

It should be understood that high temperature operation reduces the life of the electronic device and reduces device reliability. The operating temperature of one of the power components is proportional to the component's power loss along with the local ambient temperature and airflow affecting it. In complex electronic systems, power devices are positioned in a number of locations specified by a particular load device that are directly powered and thus experience a highly varying local ambient temperature and airflow. In addition, many systems operate without redundant power components, and thus, failure of a single power component can cause loss of functionality of the intermediate busbar architecture power system 900 and the load system.

In order to achieve optimum system life and reliability, it is beneficial to operate each power component such that its internal device achieves the maximum possible margin between its actual operating temperature and its maximum rated temperature. The individual power losses achieved by the various power components can be balanced and minimized by adjusting the switching frequency of each power component or the bus voltage V _BUS .

In one embodiment of the intermediate busbar architecture power system 900, each power component uses (or at least a critical power component) internal temperature measurement and reporting capabilities. This capability allows the decision engine optimization controller 920 to optimize reliability and device life by balancing or maximizing the temperature margin of each power component. This can be accomplished by a change in the switching frequency of the individual power devices or a change in the bus voltage V _BUS while ensuring that the system has an appropriate operating margin to allow the transition to increase the power level.

When the bus bar voltage V _BUS is reduced for a constant total load power, the losses within the bus bar converter 905 increase, while the losses within a POL are reduced to a greater extent, and thus, the total system loss is reduced. However, the increased loss in the busbar converter 905 will cause it to manage a higher internal device temperature. Thus, a different busbar voltage _VBUS can achieve an optimal operating temperature margin for the device in the intermediate busbar architecture power system 900, depending on the local ambient temperature and airflow affecting the power component. Other operational parameters (eg, a switching frequency, an input or output current, and an input or output voltage) may also be a concern for control and optimization. For example, this includes coordinates of the switching frequencies of the plurality of POLs to eliminate the difference or subharmonics between them.

Another factor affected by the bus voltage V _{BUS is} that one of the hold times is provided by the intermediate bus capacitor C _IB for storing the energy of the intermediate bus 910. This stored energy is proportional to the square of the busbar voltage V _BUS multiplied by the value of the intermediate busbar capacitance C _IB . The stored energy is used to provide power to POLs 915 ₁ , 915 ₂ ... 915 _N during the hold time when the input voltage V _INPUT to the busbar converter 905 is interrupted. When the busbar voltage V _BUS is reduced for efficiency optimization, the stored energy is also reduced by a larger amount due to the squared voltage relationship. For example, this may cause an unacceptable hold time to traverse to the busbar converter 905 during a temporary interruption of the input voltage V _INPUT or a system function shutdown in response to an urgent system shutdown alert signal (permitted state and data retention, etc.) Insufficient time.

In a corresponding embodiment, the decision engine optimization controller 920 causes the bus voltage V _{BUS to} increase to a maximum bus voltage just prior to the interruption of the operation. The bus voltage increases to its maximum value to ensure that V _BUS, the bus converter 905 is no longer able to maintain the bus voltage V _BUS before the maximum energy stored in the capacitor C _IB of the intermediate busbar. This allows for a value that is less than the value of the intermediate busbar capacitance C _IB required to maintain the bus voltage V _BUS at a lower value just prior to interruption or shutdown.

As mentioned previously, the decision engine optimization controller 920 can use other methods to optimize an efficiency in addition to controlling the bus voltage V _BUS . Switching field effect transistors (FETs) connected in parallel are used in many power stages. The loss associated with one of the gate drives in this parallel configuration can exceed the reduced loss provided by a lower conduction or startup resistor. The decision engine optimization controller 920 can monitor POL 915 ₁ , 915 ₂ ... 915 _N , for example, by sensing its individual output currents, and issue commands to relieve the POL 915 operating at a light load. _{One of the 1} , 915 ₂ ... 915 _N corresponds to the gate drive. The decision engine optimization controller 920 can also deactivate one of the phases for the multi-phase POL.

10 is a block diagram of still another embodiment of an intermediate busbar architecture power system constructed in accordance with the principles of the present invention, generally designated 1000. The intermediate bus architecture power system 1000 comprises a bus converter 1005, which is connected using a bus 1006, an input voltage V _INPUT converted into a display as an intermediate one of the intermediate busbar connected one bus capacitor C _IB One of the busbar voltages V _BUS on 1010. The intermediate busbar architecture power system 1000 also includes a plurality of POL converters (POL) 1015 ₁ , 1015 ₂ using individual POL controllers 1, 2...N and having inputs to the intermediate busbar 1010. .1015 _N , the intermediate bus bar 1010 supplies a plurality of corresponding output voltages V _O1 , V _O2 ... V _ON from the bus bar voltage V _BUS .

The intermediate busbar architecture power system 1000 further includes a decision engine optimization controller 1020 coupled to the busbar converter 1005 and the plurality of POLs 1015 ₁ , 1015 ₂ ... 1015 _N based on a monitored System variables or system constraints control a system variable to improve overall system performance. Further, the intermediate power bus architecture system 1000 comprises a data and control bus 1025 is connected to a power voltage V input voltage V to _{the SOURCE INPUT} one power interface module 1030, coupled to and controlling the optimization decision engine One of the devices 1020 is a global system controller 1035.

As before, the busbar connection 1006 provides a controllable connection of the busbar converter 1005 to one of the intermediate busbars 1010. The busbar connection 1006 is comprised of one of a plurality of parallel switches (eg, FETs), wherein each switch is independently controllable to permit modification of one of the plurality of parallel switches. Alternatively, the busbar connection 1006 can include a simple low impedance soldering or connectorized connection to improve system efficiency.

In the illustrated embodiment, the data and control busbar 1025 is connected thereto. Between the components of the busbar architecture power system 1000, to permit the transfer of data and control signals between at least a portion of the components. Here, the data and control signals are integrated into the data and control bus 1025. Alternatively, in other embodiments, the data and control signals may use separate bus bars.

In addition, the purpose of the power interface module 1030 in the intermediate busbar architecture power system 1000 is to adjust the power supply voltage V _SOURCE (eg, to provide electromagnetic interference filtering, before feeding the power supply voltage V _SOURCE to the busbar converter 1005, The treatment of the dual supply voltage feed or the boosting of the input voltage V _INPUT to facilitate traversal).

The decision engine optimization controller 1020 provides local system control of the components that are controllable by the data and control bus 1025. Accordingly, the global system controller 1035 can be a more general or hierarchical controller that provides supervision and overload control of the intermediate bus architecture power system 1000. Each of the plurality of POL controllers 1015 ₁ , 1015 ₂ ... 1015 _N is often passed through the data and control bus 1025 under the influence of the decision engine optimization controller 1020 or the global system controller 1035. Unit control of their respective POL converters 1, 2...N is provided.

In this configuration, the decision engine optimization controller 1020 can access information about one or more of the POLs 1015 ₁ , 1015 ₂ ... 1015 _N , including static information (such as its type or model) and Operating characteristics. In addition, real-time operational information (eg, its current load, output voltage, etc.) can also be accessible. This information, or portions thereof, can then be sent to a corresponding POL controller by the decision engine optimization controller 1020 for use in determining and setting its maximum efficiency operating point.

For example, the decision engine optimization controller 1020 can signal one of the POL controllers 1, 2...N such that a multi-phase POL can deactivate one or more phase operations. If the POL controller is to operate more efficiently with the deactivated phase, the POL controller can determine from its stored data or through the data and control bus 1025. In this case, one of the POL controllers 1, 2...N can instruct its corresponding POL to deactivate one phase Bit.

Alternatively, a POL controller can inform the decision engine to optimize the controller 1020, deactivating one phase provides better efficiency, and the decision engine optimization controller 1020 can command the POL controller to disable a phase . After receiving this command, the POL controller can also use an algorithm that allows the phase to be deactivated. An operational efficiency can be determined by this action, and further improvement can be achieved by changing the bus voltage V _BUS .

If the new operational efficiency is higher than before the deactivation phase, the POL controller will cause the phase to remain deactivated as long as the decision engine optimizes the controller 1020 to allow. Of course, other POL features can also be used to deactivate one or more phases of the POL. Examples include deactivating FETs in parallel operation as mentioned above, or changing the operating frequency of the POL. It may also include adjusting the output voltage of the POL to one of an acceptable range that results in increased efficiency.

If it is determined that the output of a POL controller is no load, the POL controller can power off its corresponding POL. In addition, a POL controller can independently recognize or receive signals at the decision engine optimization controller 1020 or the global system controller 1035, wherein a "light load" or "sleep" can be initiated for the corresponding POL of the POL controller. status. Alternatively, the decision engine optimization controller 1020 or the global system controller 1035 can initiate a command to an appropriate POL controller to enter a low level when the POL controller can do so and still meet system operational requirements. Power state or shutdown mode. The decision engine optimization controller 1020 or the global system controller 1035 can signal the POL controller with sufficient advance notice that the particular POL output will be needed again and the appropriate POLs can be recovered to deliver the required power. .

The time required to recover one of the POLs may be stored in the decision engine optimization controller 1020, the global system controller 1035, or an appropriate POL controller. For example, the recovery time may be constant for all POLs or different for one or more POLs, depending on operating conditions. Use this information to ensure that adequate recovery time is applied to each POL. This general type of control can be applied to regulated or unregulated busbar converter schemes.

When the intermediate bus architecture power system 1000 is placed in a low power sleep mode, there may be certain events or system operating modes. For example, the intermediate busway architecture power system 1000 can enter a sleep mode at a particular time of day. During the sleep mode, the bus bar converter 1005 and the POLs 1015 ₁ , 1015 ₂ ... 1015 _N enter a low power state, wherein, for example, the bus bar voltage V _BUS is a minimum voltage, and Wait for POL 1015 ₁ , 1015 ₂ ... 1015 _{N to} operate in a light load state.

11 is a block diagram of still another embodiment of an intermediate busbar architecture power system constructed in accordance with the principles of the present invention, generally designated 1100. The intermediate bus architecture power converter system 1100 includes a bus 1105, which is connected using a 1106 bus, an input voltage V _INPUT converted into a display as an intermediate one of the intermediate busbar connected one bus capacitor C _IB One of the busbar voltages V _BUS on the 1110. The intermediate busbar architecture power system 1100 also includes a plurality of POL converters (POL) 1115 ₁ , 1115 ₂ ... 1115 _N having a number of inputs connected to the intermediate busbar 1110, the intermediate busbar 1110 being from the busbar The voltage V _BUS supplies a plurality of corresponding output voltages V _O1 , V _O2 ... V _ON .

The intermediate bus bar architecture power system 1100 further includes a decision engine optimization controller 1120 coupled to the bus bar converter 1105 and the plurality of POL converters 1115 ₁ , 1115 ₂ ... 1115 _N based on a Monitor system variables or system constraints to control a system variable to improve overall system performance.

In addition, the intermediate bus structure power system 1100 includes a data and control bus 1125, and a power supply voltage V _SOURCE connected to provide an input voltage V _INPUT , a power interface module 1130 coupled to the decision engine optimization controller 1120 . One global system controller 1135 and one parallel busbar switch 1145 using a parallel busbar connection 1146, which is coupled in parallel with the busbar converter 1105 to the intermediate busbar 1110.

The bus bar connection 1106 and the parallel bus bar connection 1146 provide respective controllable connections of the bus bar converter 1105 and the parallel bus bar converter 1145 to the intermediate bus Row 1110. The busbar connection 1106 and the parallel busbar connection 1146 can, for example, each consist of one or a plurality of parallel switches (eg, FETs), wherein each switch can be independently controlled to allow modification of one of the plurality of parallel switches.

The data and control bus 1125 is coupled between the components of the intermediate bus architecture power system 1100 to permit data transfer and control signaling between at least a portion of the components. Here, the data and control signals are also integrated into the data and control bus 1125. Alternatively, in other embodiments, the data and control signals may use separate bus bars. Moreover, the purpose of the power interface module 1130 is to adjust the power supply voltage V _SOURCE before feeding the power supply voltage V _SOURCE to the bus bar converter 1105 and the parallel bus bar converter 1145.

The decision engine optimization controller 1120 provides local system control of the components that are controllable by the data and control bus 1125. As before, the global system controller 1135 can be a more general controller or a hierarchical controller that provides supervision and overload control of the intermediate bus architecture power system 1100.

The decision engine optimization controller 1120 or the global system controller 1135 can provide separate or centralized control of the plurality of parallel switches (eg, FETs) when modifying the switch conductance of the busbar connection 1106 and the parallel busbar connection 1146. For example, one or more of the plurality of parallel switches can be disconnected during light load conditions. Additionally, one of the busbar converter 1105 and the parallel busbar converter 1145 can be electrically disconnected from the intermediate busbar 1110 during light load conditions. As discussed previously, this may need to be done in a manner that considers one of the intermediate bus retention times (intermediate busbar capacitance _CIB energy storage) and startup characteristics of the recovered busbar converter. In one embodiment of the intermediate busbar architecture power system 1100, the portion of the decision engine optimization controller 1120 that controls the plurality of parallel switches is modified when the switch resistance of the busbar connection 1106 and the parallel busbar connection 1146 is modified. The busbar converter 1105 and the parallel busbar converter 1145 can be resident.

The decision engine optimization controller 1120 can adjust each of the busbar converter 1105 and the parallel busbar converter 1145 such that they are supplied to the middle equally or in proportion to produce a higher overall system power efficiency. One of the busbars 1110 has a total load current while delivering a desired busbar voltage V _BUS . These load sharing features can be constrained by predetermined constraints to meet other power system requirements (such as instantaneous load capacity and step load). In an embodiment, such limiting or parallel conditions may be determined by the global system controller 1135 and provided to the decision engine optimization controller 1120, which may then provide the busbar converter 1105 and in parallel. The adjustment and control of each of the bus converters 1145 are shared.

This can be done by measuring an output current directly or indirectly. The indirect means may include measuring the current in the switching transistor and calculating the output current using stored data (such as transformer turns ratio, duty cycle, etc.). The decision engine optimization controller 1120 can have a preset limit on the allowable output voltage or duty cycle offset under a particular operating condition to limit the voltage swing in the intermediate bus 1110 during transient conditions.

The busbar converter 1105 and the parallel busbar converter 1145 can be a mixture of one of an adjusted type and an unregulated type. The decision engine optimization controller 1120 can modify one of the regulated bus bar output voltages for matching (less than or greater than the unregulated bus bar converter). This condition can achieve a higher overall efficiency of the intermediate busbar architecture power system 1100 because it utilizes the inherently higher efficiency of an unregulated busbar converter and the control capabilities of a regulated busbar converter.

In some environments, there may be an optimum efficiency point, wherein the decision engine optimization controller 1120 sets the output of the regulated busbar converter so that it is shared between the two busbar converters 1105, 1145. Equal or proportional load. The decision engine optimization controller 1120 can be disconnected if a maximum efficiency point needs to be lower than one of the busbar voltages provided by the unregulated busbar converter, and the regulated busbar converter itself can supply the current load. The busbar of the unregulated busbar converter is connected or shut down.

12 is a flow chart of one embodiment of a method of operating an intermediate busbar power system implemented in accordance with the principles of the present invention, generally designated 1200. this method 1200 begins in a step 1205, and in a step 1210, an input voltage is converted to a bus voltage on an intermediate bus. Next, in a step 1215, the busbar voltage on the intermediate busbar is converted to an output voltage by a point-of-load converter, and in a step 1220, based on a monitored system variable or a system constraint. A system variable to improve overall system performance.

In an embodiment, controlling the system variable includes adjusting the input voltage (where the adjustment includes filtering electromagnetic interference (EMI)), providing a plurality of feeds to the input voltage or increasing a value of the input voltage to facilitate a crossing condition.

In another embodiment, controlling the system variable comprises an internal control or an external control providing one of the busbar voltages, wherein the internal control is defined as a control function embedded in the busbar converter, and external control It is defined as one of the control functions outside of the bus converter. In either case, the busbar converter can be used to connect to one of the busbars of the intermediate busbar. Alternatively, controlling the system variable includes controlling a plurality of parallel busbar converters that provide the busbar voltage, wherein in one example, at least one of the plurality of parallel busbar converters is an unregulated busbar converter. Additionally, controlling the system variable includes controlling a point-of-load converter that provides an output voltage. Additionally, controlling the system variables can include controlling a plurality of load point converters.

In yet another embodiment, controlling the system variable comprises communicating with a resource other than the system, wherein the resource can be an external system controller. In addition, controlling the system variables includes using test data, model data, or serial number data, wherein the test data, model data, or serial number data may be stored data or real-time data. Alternatively, controlling the system variable includes controlling the change in the system variable in a stepwise manner, wherein the stepwise manner can use a variable step size. In addition, controlling the system variable includes controlling the rate of change of one of the changes in the system variables.

In still another embodiment, controlling the system variable includes one of a bus bar voltage on the free intermediate bus, an output voltage, a control signal switching frequency or phase, and a control signal. The system variable is selected from the group consisting of the start time or period and the number of activated control devices. In addition, controlling the system variable includes freely supplying one of the bus bars current to the intermediate bus, a load point converter output current, one of the system devices, the power dissipation, one system device efficiency, one system device temperature, Electromagnetic interference (EMI), one of the system devices, one of the voltage surges or current surges of a system device, one of the transient responses of one of the system devices, and one of the responses to one of the actively generated system disturbances is selected for monitoring. System variables.

In a further embodiment, controlling the system variable comprises a group selection system constraint consisting of a free-preset constraint, a user-defined constraint, a site constraint, and an adaptive constraint. Additionally, controlling the system variable includes controlling the system variable based on an alarm signal, wherein in an example, the alarm signal can indicate that a system shutdown is urgent.

In yet another embodiment, controlling the system variable includes using one of the system's communication capabilities. In addition, the communication capability is in accordance with a group selected from an internal integrated circuit (I ² C) bus bar specification, a controller area network (CAN) bus bar specification, and a serial peripheral interface (SPI) bus bar specification. One. In addition, the communication capability can use a wired component, a wireless component, or an optical component. In addition, an intermediate bus can be used as the communication capability. The method 1200 ends in a step 1225.

Although the methods disclosed herein have been described and illustrated with reference to the specific steps that are performed in a particular order, it is understood that the steps can be combined, sub-divided or re-ordered to form an equivalent without departing from the teachings of the present invention. method. Accordingly, the order or grouping of the steps is not a limitation of the invention unless specifically indicated herein.

Those skilled in the art to which this application pertains will be appreciated that the described embodiments may be further added, deleted, substituted, and modified.

700‧‧‧Intermediate busbar architecture power system

705‧‧‧ Bus Bar Converter

706‧‧‧ bus bar connection

710‧‧‧Intermediate busbar

715 ₁ ‧‧‧Load point converter

715 ₂ ‧‧‧Load Point Converter

715 _N ‧‧‧Load Point Converter

C _IB ‧‧‧Intermediate busbar capacitor

V _BUS ‧‧‧ busbar voltage

V _INPUT ‧‧‧ input voltage

V _O1 ‧‧‧Output voltage

V _O2 ‧‧‧ output voltage

V _ON ‧‧‧ output voltage

Claims (52)

An intermediate busbar architecture power system includes: a busbar converter that converts an input voltage into a busbar voltage on an intermediate busbar; and a point-of-load converter from the confluence of the intermediate busbar The discharge voltage supplies an output voltage; and a decision engine optimization controller that controls a system variable based on a monitored system variable or a system constraint to improve an overall system performance. The system of claim 1, wherein the decision engine optimization controller is selected from the group consisting of: a controller embedded in the busbar converter; and a controller separate from the busbar converter. The system of claim 1, wherein the decision engine optimization controller is coupled to an intermediate bus connection of the one of the bus converters. The system of claim 1, wherein the decision engine optimization controller is coupled to a plurality of load point converters to control the system variables. A system as claimed in claim 1, wherein the decision engine optimization controller communicates with another controller to control the system variables. The system of claim 1, wherein the decision engine optimization controller uses test data, model data, or serial number data when controlling the system variables. The system of claim 6, wherein the test data, model data or serial number data is stored data. A system as claimed in claim 1, wherein the decision engine optimization controller controls one of the system variables to change in a stepwise manner. The system of claim 8, wherein the stepwise manner uses a variable step size. The system of claim 1, wherein the decision engine optimization controller controls a rate of change of the change in the system variable. The system of claim 1, wherein the system variable is selected from the group consisting of: the bus voltage on the intermediate bus; the output voltage; a control signal switching frequency or phase; a control signal activation time or period; And the number of control devices that have been activated. The system of claim 1, wherein the monitored system variable is selected from the group consisting of: a bus current supplied to the intermediate bus; an output current supplied by the point of load converter; One of the power dissipation of the device; one of the efficiency of one system device; one temperature of one system device; one electromagnetic interference (EMI) of one system device; one output voltage or current surge of one system device; one instantaneous of one system device Respond; and respond to one of the actively generated system disturbances. The system of claim 1, wherein the system constraint is selected from the group consisting of: a predetermined constraint; a user-defined constraint; a site constraint; and an adaptive constraint. The system of claim 1, wherein the system constraint is based on an alert signal. The system of claim 14, wherein the alarm signal indicates that a system shutdown is urgent of. The system of claim 1, further comprising coupling the decision engine optimization controller to one of the communication elements of a system component. The system of claim 16, wherein the communication bus is connected to provide data transfer between the decision engine optimization controller and the system component. The system of claim 16, wherein the communication bus is connected to provide a control signal between the decision engine optimization controller and the system component. The system of claim 16, wherein the communication bus is in accordance with one of the group consisting of: an internal integrated circuit (I ² C) bus bar specification; a controller area network (CAN) bus bar specification; And a list of peripheral interface (SPI) busbar specifications. The system of claim 16, wherein the communication bus uses a wired component, a wireless component, or an optical component. The system of claim 16, wherein the intermediate bus is used as the communication bus. The system of claim 1, further comprising providing one of the input voltages to adjust one of the power interface modules. The system of claim 22, wherein the adjustment of the input voltage comprises one selected from the group consisting of: filtering electromagnetic interference (EMI); providing a plurality of feeds to the input voltage; and increasing a value of the input voltage To promote crossing conditions. The system of claim 1 further comprising converting an input voltage to one of the bus bar voltages on the intermediate bus bar. The system of claim 24, wherein the decision engine optimization controller is coupled to the A bus tie converter to control the system variables. The system of claim 25, wherein the decision engine optimization controller is coupled to one of the parallel busbar converters in parallel with the intermediate busbar connection. The system of claim 24, wherein the parallel busbar converter is an unregulated busbar converter. A method of operating an intermediate busbar architecture power system, comprising: converting an input voltage into a busbar voltage on an intermediate busbar; converting the busbar voltage on the intermediate busbar into an output voltage; and based on Monitored system variables or a system constraint to control a system variable to improve overall system performance. The method of claim 28, wherein controlling the system variable comprises one selected from the group consisting of: internal control supplying one of the busbar voltages; and externally controlling one of the busbar voltages converter. The method of claim 28, wherein controlling the system variable comprises: controlling a busbar converter to a busbar voltage connection of the intermediate busbar. The method of claim 28, wherein controlling the system variable comprises: controlling a plurality of parallel busbar converters that provide the busbar voltage. The method of claim 31, wherein at least one of the plurality of parallel busbar converters is an unregulated busbar converter. The method of claim 28, wherein controlling the system variable comprises: controlling a load point converter that provides the output voltage. The method of claim 28, wherein controlling the system variable comprises: controlling a plurality of load point converters. The method of claim 28, wherein controlling the system variable comprises: communicating with a resource other than the system. The method of claim 35, wherein the resource is an external system controller. The method of claim 28, wherein controlling the system variable comprises: using test data, model data, or serial number data. The method of claim 37, wherein the test data, model data or serial number data is stored data. The method of claim 28, wherein controlling the system variable comprises: controlling one of the system variables to change in a stepwise manner. The method of claim 39, wherein the stepwise manner uses a variable step size. The method of claim 28, wherein controlling the system variable comprises controlling a rate of change of the change in the system variable. The method of claim 28, wherein controlling the system variable comprises selecting a group of the following components to select the system variable: the bus bar voltage on the intermediate bus bar; the output voltage; a control signal switching frequency or phase; a control signal Start time or period; and the number of control devices that have been activated. The method of claim 28, wherein controlling the system variable comprises selecting the monitored system variable by a group of the following components: a bus current supplied to the intermediate bus; a load point converter output current; a system Power dissipation of one of the devices; efficiency of one of the system devices; temperature of one of the system devices; electromagnetic interference (EMI) of one of the system devices; voltage surge or current surge of one of the system devices; One of the system devices responds instantaneously; and responds to one of the actively generated system disturbances. The method of claim 28, wherein controlling the system variable comprises selecting the system constraint from a group of the following components: a predetermined constraint; a user defined constraint; a site constraint; and an adaptive constraint. The method of claim 28, wherein controlling the system variable comprises: controlling the system variable based on an alert signal. The method of claim 45, wherein the alert signal indicates that a system shutdown is urgent. The method of claim 28, wherein controlling the system variable comprises using a communication capability for the system. The method of claim 47, wherein the communication capability is in accordance with one of the group consisting of: an internal integrated circuit (I ² C) bus bar specification; a controller area network (CAN) bus bar specification; A series of peripheral interface (SPI) busbar specifications. The method of claim 47, wherein the communication capability uses a wired component, a wireless component, or an optical component. The method of claim 47, wherein the intermediate bus is used as the communication capability. The method of claim 28, wherein controlling the system variable comprises adjusting the one of the input voltages. The method of claim 51, wherein the adjusting of the input voltage comprises one selected from the group consisting of: Filtering electromagnetic interference (EMI); providing a plurality of feeds to the input voltage; and increasing a value of the input voltage to facilitate a crossing condition.