TWI691038B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method of forming the same, the semiconductor device includes a dielectric layer, a conductive structure and a passivation layer. The dielectric layer is disposed on the substrate, and the conductive structure is disposed in the dielectric layer and having a portion thereof protruded from the dielectric layer. The conductive structure further includes a turning portion disposed on a sidewall thereof. The protection layer is conformal formed on the dielectric layer and the conductive structure.

Description

Semiconductor device and its forming method

The invention relates to a semiconductor device and a method for forming the same, in particular to a semiconductor device with metal wires and a method for forming the same.

In the modern information society, the microprocessor system composed of integrated circuits (IC) has been widely used in all aspects of life, such as automatically controlled household appliances, mobile communication equipment, personal computers, etc. There are traces of integrated circuits. With the increasingly sophisticated technology and the various imaginations of human society for electronic products, integrated circuits have also developed in the direction of more elements, more precision and smaller size.

The so-called integrated circuit is generally formed by a die produced in a conventional semiconductor manufacturing process. The process of manufacturing the die begins with the production of a wafer: first, multiple regions are distinguished on a wafer, and on each region, through various semiconductor processes such as deposition, lithography, etching, or flattening In order to form various required circuit routes, and use miniaturized wiring vias and interlayer dielectric layers to form a multilayer interconnection wiring structure on each region of the wafer to meet the effects of high integration and high-speed operation. Afterwards, each area on the wafer is cut into various die, and various packaging techniques are used In this technique, the die is packaged into a chip to form a complete package. In order to meet the needs of various miniaturization, the industry currently has severe restrictions and requirements on the structure and process of each stage of the integrated circuit.

An object of the present invention is to provide a semiconductor device provided with a conductive structure, and a turning portion is further provided on a side wall of the semiconductor device, thereby reducing the steepness between the top surface of the conductive structure and surrounding components. Therefore, a protective layer disposed on the conductive structure can cover the conductive structure relatively flatly and have an optimized thickness.

An object of the present invention is to provide a method for forming a semiconductor device, which forms a conductive structure on a dielectric layer, and further forms a turning portion on a side wall of the conductive structure to slow down the top surface of the conductive structure to The steepness between the surrounding elements. Therefore, a protective layer formed subsequently can cover the conductive structure relatively flatly to avoid problems such as cracks in the corner region.

To achieve the above object, an embodiment of the present invention provides a semiconductor device, which includes a dielectric layer, a conductive structure, and a protective layer. The dielectric layer is disposed on a substrate, the conductive structure is disposed in the dielectric layer, and partially protrudes from the dielectric layer, wherein a side wall of the conductive structure has a turning portion. The protective layer is conformally covered on the dielectric layer and the conductive structure.

To achieve the above objective, an embodiment of the present invention provides a method for forming a semiconductor device, which includes the following steps. First, provide a substrate and form a substrate on the substrate A dielectric layer, a dielectric hole is formed in the dielectric layer. Next, a conductive structure is formed, the conductive structure fills the dielectric hole and partially protrudes above the dielectric layer, wherein a side wall of the conductive structure has a turning portion. Then, a protective layer is conformally formed on the dielectric layer and the conductive structure.

Overall, the present invention forms a conductive structure partially protruding from the surface of the dielectric layer in a dielectric layer, and further provides a turning portion on the protruding portion, such as an inclined side wall and an arc side wall , A shoulder or an additional side wall, etc. The turning part can reduce the steepness between the top surface of the conductive structure and the surrounding elements, thereby, the subsequent film layers stacked on the conductive structure, such as passivation layers and other protective layers, can be more flatly covered The conductive structure has an optimized thickness and a stable structure.

100: base

110, 150: dielectric layer

120: conductive area

130: Stop layer

140: media hole

160: barrier layer

170: metal layer

171: Conductive structure

190: Passivation layer

200, 220: patterned mask layer

210: silicon nitride layer

371, 373, 375, 377, 379: conductive structure

371a, 373a: inclined side wall

375a: Arc side wall

377a: shoulder

380: Side wall

391, 393, 395, 397, 399: passivation layer

T1, T2: thickness

P1, P2: etching process

θ: included angle

FIGS. 1 to 2 are schematic diagrams showing the steps of the method for forming a semiconductor device in the first embodiment of the present invention, wherein: FIG. 1 is a schematic cross-sectional view of a semiconductor device after forming a conductive layer; FIG. 2 is a semiconductor A schematic cross-sectional view of the device after forming a protective layer.

FIGS. 3 to 6 are schematic diagrams showing the steps of the method for forming a semiconductor device in the second embodiment of the present invention, wherein: FIG. 3 is a schematic cross-sectional view of a semiconductor device after an etching process; FIG. 4 is a semiconductor FIG. 5 is a schematic cross-sectional view of a semiconductor device after forming another conductive structure; FIG. 6 is a cross-sectional schematic view of a semiconductor device after forming another conductive structure.

FIGS. 7 to 8 are schematic diagrams showing the steps of the method for forming a semiconductor device in the third embodiment of the present invention, wherein: FIG. 7 is a schematic cross-sectional view of a semiconductor device after another etching process; FIG. 8 is a A schematic cross-sectional view of the semiconductor device after forming another conductive structure.

9 to 10 are schematic diagrams showing the steps of the semiconductor device forming method in the fourth embodiment of the present invention, wherein: FIG. 9 is a schematic cross-sectional view of a semiconductor device after forming a sidewall; FIG. 10 is a semiconductor A schematic cross-sectional view of the device after forming a protective layer.

In order to enable those of ordinary skill in the art of the present invention to further understand the present invention, the following lists several preferred embodiments of the present invention, and in conjunction with the accompanying drawings, detailed description of the composition of the present invention and the desired Effect.

FIGS. 1 to 2 illustrate a method of forming a semiconductor device in the first embodiment of the invention. First, a substrate 100 is provided, such as a semiconductor substrate, such as a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, or a silicon-on-insulator substrate (silicon) -on-insulator substrate) etc. At least one conductive region 120 is also formed on the substrate 100, which may be various conductive units or metal contacts. For example, for example, two conductive regions 120 are formed in a dielectric layer 110 as shown in FIG. 1, and each conductive region 120 may be a contact plug and a via plug. Or wire (metal line), etc.

Then, two conductive structures 171 respectively connecting the conductive regions 120 are formed on the substrate 100. Specifically, the formation of the conductive structure 171 is, for example, first forming two dielectric holes 140 that sequentially penetrate a dielectric layer 150 and a stop layer 130, respectively communicating with the conductive regions 120 below, and then forming a dielectric hole 140 The barrier layer 160 is made of materials such as titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN), and a metal layer 170 is made of low-resistance metal materials such as aluminum. The barrier layer 160 covers the surface of the dielectric hole 140 and the dielectric layer 150 integrally, and the metal layer 170 on it fills the dielectric hole 140 to cover the surface of the dielectric layer 150, such as Shown in Figure 1. In this way, by using the patterned mask layer 200 formed on the metal layer 170 to perform a patterning process, the metal layer 170 and the barrier layer 160 on the surface of the dielectric layer 150 can be partially removed, as shown in the second The conductive structure 171 shown in the figure. Then, after removing the patterned mask layer 200, a protective layer is formed on the conductive structure 171. In this embodiment, the protective layer is, for example, a double-layer structure composed of a passivation layer 190 containing phosphorosilicate glass (PSG) and a silicon nitride layer 210, but not as a limit.

The forming method of the first embodiment of the present invention is completed by the foregoing process. It should be noted that according to the method of this embodiment, after the metal layer 170 fills the dielectric hole 140, a film of a specific thickness is further deposited on the surface of the dielectric layer 150. Therefore, the subsequent patterning process forms The conductive structure 171 has a portion protruding from the dielectric hole 140 and located on the dielectric layer 150. Therefore, the conductive structure 171 in this part can be used as a bonding pad, and can be connected to wire bonds or solder bumps through the subsequent packaging process to integrate the circuit. The electronic signal is transmitted to the outside world. However, in this embodiment, there is a certain height difference between the portion of the conductive structure 171 and the top surfaces of the dielectric layers 150 on both sides, and the side wall between the top surface of the portion and the top surface of the dielectric layer 150 is relatively steep It is steep, for example, it is a vertical side wall as shown in FIG. 2, or a side wall (not shown) having an inclination of more than 80 degrees. Therefore, when the protective layer is formed later (especially when the passivation layer 190 is formed), it is easy to deposit too much material at the top corner of the part to produce a larger thickness 190a, while the bottom corner of the part is Depositing less material results in a smaller thickness 190b, as shown in Figure 2. In this case, the formed passivation layer 190 cannot have an appropriate thickness, and the overall thickness T1 is small and uneven, so that during subsequent packaging and other processes, the stress cannot be effectively dispersed, and the passivation layer 190 is likely to crack (passivation crack).

In order to improve the aforementioned problem of cracking of the passivation layer 190, the following will further describe other embodiments or variations of the method for forming a semiconductor device of the present invention. In order to simplify the description, the following description mainly focuses on the differences between the embodiments, and does not repeat the same points. In addition, the same elements in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

Please refer to FIGS. 3 to 6, which are schematic diagrams showing the steps of the method for forming a semiconductor device in the second embodiment of the present invention. The previous steps of this embodiment are substantially the same as the first preferred embodiment described above, as shown in FIG. 1, and will not be repeated here. The main difference between the process of this embodiment and the aforementioned first preferred embodiment is that after forming the conductive structure 171 and removing the patterned mask layer 200, an additional etching process P1 is performed to protrude the conductive structure 171 from the dielectric layer A turning portion is formed on the part of 150, which further reduces the steepness of the part.

In detail, the etching process P1 is, for example, a dry etching process or a wet etching process Cheng, which is to laterally etch the metal layer 170 of the conductive structure 171 to form a conductive structure 371 having an inclined sidewall 371a. Wherein, the inclined sidewall 371a is formed on the portion of the conductive structure 371 that protrudes from the dielectric layer 150, and has an angle θ of less than 80 degrees with the top surface of the dielectric layer 150, preferably between 80 degrees and 60 Between degrees, as shown in Figure 4.

Then, as described in the foregoing first embodiment, a passivation layer 391 and a silicon nitride layer 210 can be formed on the conductive structure 371. It should be noted that in this embodiment, the inclined sidewall 371a is formed on the side wall of the conductive structure 371, which can effectively buffer the steep contour between the top surface of the conductive structure 371 and the dielectric layers 150 on both sides, and avoid The subsequently formed passivation layer 391 is excessively deposited at the top corner of the portion of the conductive structure 371, or is deposited in a small amount at the bottom corner of the portion of the conductive structure 371. Therefore, the passivation layer 391 can cover the conductive structure 371 relatively flatly, and has a thickness T2 greater than the aforementioned passivation layer 190.

In addition, it should also be noted that in other embodiments, the etching parameters such as temperature, pressure, etching time, etching angle, or gas flow rate during the etching process P1 may be further adjusted to form the formation shown in FIG. 5 A conductive structure 373, which only forms an inclined side wall 373a on the upper half of the portion protruding from the dielectric layer 150, and presents two inclined side wall patterns; or forms a conductive structure as shown in FIG. 6 At 375, a circular arc side wall 375a is formed on the part. Wherein, the inclined side wall 373a of the conductive structure 373 and a horizontal plane parallel to the top surface of the dielectric layer 150 also have an included angle θ of less than 80 degrees, preferably between 80 degrees and 60 degrees, as in the fifth The picture shows.

Thus, the forming method of the second embodiment of the present invention is completed. According to the method of this embodiment, after the patterned conductive structure 171 is formed, the laterally etched conductive structure 171 protrudes In the portion of the dielectric layer 150, a turning portion is formed on the portion, such as the inclined sidewall 371a, 373a or the arc-shaped sidewall 375a. In this way, the turning portion can be used to improve the original steep profile of the conductive structure, and to slow down the slope of the side walls of the conductive structures 371, 373, and 375, thereby avoiding excessive deposition of passivation layers 391, 393, and 395 formed on the conductive structures 371 and 373 , 375 at the top corner and cause unevenness. Therefore, the passivation layers 391, 393, and 395 formed by the method of this embodiment can cover the conductive structures 371, 373, and 375 more flatly and have a thickness T2 greater than that of the aforementioned passivation layer 190.

Please refer to FIGS. 7 to 8, which are schematic diagrams illustrating the steps of the method for forming a semiconductor device in the third embodiment of the present invention. The previous steps of this embodiment are substantially the same as the first preferred embodiment described above, as shown in FIG. 1, and will not be repeated here. The main difference between the process of this embodiment and the aforementioned first preferred embodiment is that after the conductive structure 171 is formed, the patterned mask layer 200 is not removed, but the patterned mask layer 200 is etched isotropically to reduce its size Size, a patterned mask layer 220 with a smaller size is formed, as shown in FIG. 7.

Then, using the patterned mask layer 220, another etching process P2 is performed, such as a wet etching or dry etching process, and the portion of the conductive structure 171 exposed outside the patterned mask layer 220 is partially removed, thereby forming a sidewall with a The conductive structure 377 of the shoulder 377a. The shoulder 377a can also improve the steep profile between the top surface of the conductive structure 377 and the dielectric layers 150 on both sides, so that the subsequently formed passivation layer 397 can more flatly cover the conductive structure 377 and have a larger passivation layer 190 The thickness T2 is shown in Figure 8.

In addition, in another embodiment, several patterned mask layers (not shown) with progressively smaller sizes may be used for sequential etching, and the conductive structure 171 protrudes from A stepped structure (not shown) is formed on a portion of the dielectric layer 150 so that the stepped structure includes a plurality of shoulders (not shown) that are sequentially retracted from bottom to top. Therefore, the stepped structure can also be used as a turning portion to reduce the steepness of the conductive structure 171. By the foregoing steps, the forming method of the third embodiment of the present invention is completed. According to the method of this embodiment, the conductive structure 171 is etched using the patterned mask layer 220 of reduced size to form a shoulder portion 377a as a turning portion. Therefore, the use of the shoulder portion 377a can improve the steepness between the top surface of the conductive structure 377 and the elements on both sides, to avoid excessive deposition of the passivation layer 399 formed later on the top corner of the conductive structure 377, or a small amount deposited on the conductive structure 377 The bottom corner is prone to cracking.

Please refer to FIG. 9 to FIG. 10, which are schematic diagrams showing the steps of the method for forming a semiconductor device in the fourth embodiment of the present invention. The previous steps of this embodiment are substantially the same as the first preferred embodiment described above, as shown in FIG. 1, and will not be repeated here. The main difference between the manufacturing process of this embodiment and the aforementioned first preferred embodiment is that after forming the conductive structure 171 and removing the patterned mask layer 200, an additional sidewall 380 is formed on the conductive structure 171 to improve the conductive structure 171 Steep silhouette.

In detail, the sidewall sub 380 is formed by, for example, first forming a material layer (not shown), for example, including silicon oxide (silicon oxide, SiO) and other better covering dielectric materials, covering the conductive structure 171, and then After performing an etching process, the material layer is partially removed to form a sidewall sub 380 only on the portion of the conductive structure 171 protruding from the dielectric layer 150, which has an arc-shaped sidewall, as shown in FIG. The side wall 380 can also reduce the steepness between the top surface of the conductive structure 171 and the top surfaces of the dielectric layers 150 on both sides thereof, and can be used as a turning portion.

Therefore, the subsequently formed passivation layer 399 will not be excessively deposited at the top corners of the conductive structure 171 or a small amount deposited at the bottom corners of the conductive structure 171, but can cover the conductive structure 171 more flatly, and It has a thickness T2 greater than the aforementioned passivation layer 190, as shown in FIG. Thus, the forming method of the fourth embodiment of the present invention is completed.

Overall, the present invention is to form a conductive structure partially protruding from its surface in a dielectric layer, and further provided a turning portion on the protruding portion of the conductive structure, such as an inclined side wall and two sections of inclined side wall , An arc side wall, a shoulder or an additional side wall, etc. The turning part can improve the steep outline between the top surface of the conductive structure and the surrounding elements, and provide a more gentle slope or structure. In this way, when other film layers continue to be formed on the conductive structure, such as passivation layers and other protective layers, the film layers can cover the conductive structure more flatly to avoid excessive deposition on specific parts, and can be optimized The thickness and stable structure. In addition, those skilled in the art should understand that in the foregoing embodiments of the present invention, two conductive structures are formed, and the two conductive regions below are electrically connected to each other as an example of implementation. However, it should be noted that In other embodiments of the invention, the specific number and position of the conductive structure can be adjusted according to product requirements.

The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: base

110: dielectric layer

120: conductive area

130: Stop layer

150: dielectric layer

160: barrier layer

170: conductive layer

371: Conductive structure

371a: Inclined sidewall

210: silicon nitride layer

391: Passivation layer

T2: thickness

θ: included angle

Claims (16)

A semiconductor device includes: a dielectric layer disposed on a substrate; a conductive structure disposed in the dielectric layer, and a portion of the conductive structure protruding above the dielectric layer, and a sidewall of the portion has A turning portion, wherein the turning portion and the conductive structure comprise the same material; and a protective layer conformally covers the dielectric layer and the conductive structure. The semiconductor device as described in item 1 of the patent application range, wherein the turning portion includes an inclined sidewall, wherein the angle between the inclined sidewall and the substrate is less than 80 degrees. The semiconductor device as described in item 1 of the patent application range, wherein the turning portion includes two inclined side walls, wherein the upper half of the side wall is inclined and has an angle of less than 80 degrees with the substrate surface. The semiconductor device as described in item 1 of the patent application range, wherein the turning portion includes a shoulder portion. The semiconductor device as described in item 1 of the patent application range, wherein the turning portion includes a circular arc side wall. The semiconductor device as described in item 1 of the patent application range, wherein the turning portion includes a side wall sub disposed on the side wall of the part, wherein the side wall sub There is an arc side wall. The semiconductor device as described in item 6 of the patent application range, wherein the sidewall includes a dielectric material. A method for forming a semiconductor device includes: providing a substrate; forming a dielectric layer on the substrate, a dielectric hole is formed in the dielectric layer; forming a conductive structure, the conductive structure filling the dielectric hole and having protrusions A portion on the dielectric layer, wherein the portion of the conductive structure has a turning portion, wherein the turning portion and the conductive structure comprise the same material; and the dielectric layer and the conductive structure are conformal To form a protective layer. The method for forming a semiconductor device as described in item 8 of the patent application range, wherein the formation of the conductive structure includes: forming a conductive layer, filling the dielectric hole and covering the dielectric layer; and using a patterned mask The mask layer undergoes an etching process to pattern the conductive layer to form the conductive structure. The method for forming a semiconductor device as described in item 9 of the scope of the patent application further includes: after the etching process, performing a side etching process to etch the conductive structure to form the turning portion. The method for forming a semiconductor device as described in item 10 of the patent application range, wherein after the lateral etching process, the turning portion is formed with an inclined sidewall, wherein the angle between the inclined sidewall and the substrate is less than 80 degrees. The method for forming a semiconductor device as described in item 10 of the patent application range, wherein after the lateral etching process, the turning portion is formed with two inclined side walls, wherein the upper half of the side wall is inclined and is in contact with the The angle between the substrates is less than 80 degrees. The method for forming a semiconductor device as described in item 10 of the patent application scope, wherein after the lateral etching process, the turning portion is formed with an arc-shaped side wall. The method for forming a semiconductor device as described in item 9 of the patent application scope further includes: after the etching process, performing another etching process using another patterned mask layer to etch the conductive structure, wherein the other patterned The size of the mask layer is smaller than the patterned mask layer. The method for forming a semiconductor device as described in item 14 of the patent application scope, wherein after the other etching process, the turning portion is formed with a shoulder portion. The method for forming a semiconductor device as described in item 9 of the patent application scope further includes: forming a material layer over the conductive structure and the dielectric layer after the etching process; and An etch-back process is performed to partially remove the material layer and form a side wall on the conductive structure, wherein the side wall has an arc-shaped side wall.

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