TWI690169B - Method of shift-coefficient table design of qc-ldpc code for larger code block sizes in mobile communications - Google Patents

Abstract

A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Description

Shift coefficient table design of QC-LDPC codes for large code block size in mobile communication Accounting method

The present invention generally relates to mobile communication, and particularly relates to a shift coefficient table for quasi-cyclic low-density parity-check (QC-LDPC) codes used for larger code block sizes in mobile communication design.

Unless otherwise stated herein, the method described in this section is not prior art to the request items listed below and cannot be included as prior art due to inclusion in this section.

The 3rd Generation Partnership Project (3GPP) has approved a plan to accelerate the development of the 5th generation (5G) new radio (NR) specifications, so it can be expected that standards-based 5G NR wireless communication services can be launched in the near future. 3GPP also agreed that QC-LDPC will be used for the 5G NR data channel. However, no details have been defined on how QC-LDPC-based encoding (eg, encoding and decoding) can be implemented.

The following summary is only illustrative and is not intended to be limiting in any way. That is, the following overview is provided to introduce the concepts of novel and non-obvious technologies described in this article. Benefits and advantages. The selection implementation is further described in the detailed description below. Therefore, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended to determine the scope of the claimed subject matter.

In one aspect, a method of wireless communication may involve a processor of a device establishing a wireless communication link with at least one other device via a transceiver of the device. The method may also involve the processor performing wireless communication with other devices via the wireless communication link as follows: (a) selecting a first shift coefficient table from a plurality of shift coefficient tables; (b) using a basic matrix and a At least a part of a shift coefficient table generates a QC-LDPC code; (c) selects a codebook from a plurality of codebooks embedded in the QC-LDPC code; (d) stores the selected codebook to be associated with the processor The memory of (e) encodes the data using the selected codebook to generate a plurality of modulation symbols of the data; and (f) controls the transceiver to multiplex, convert, filter, amplify and pass the modulation symbols to the modulation symbols One or more antennas radiate the modulation symbol as an electromagnetic wave, so as to transmit the modulation symbol of the material to the other device via a wireless communication link. When selecting the first shift coefficient table from the plurality of shift coefficient tables, the method further involves the processor according to one or a plurality of rules related to any one or two of the code block size and the code rate of the data , Select the first shift coefficient table for a relatively large code block size.

It is worth noting that although the following provides a description of the proposed scheme and various examples in the context of 5G NR wireless communication, the other proposed agreements, standards and specifications applicable to the implementation, the proposed concepts, schemes and any Transforms/derivatives can be implemented in communications. Therefore, the scope of the proposed solution is not limited to the description provided herein.

100: basic matrix

I1: The first part of the information matrix

I2: The second part of the information matrix

I3: The third part of the information matrix

200: Process

210, 220, 230, 240, 250: block

300: Quasi-row orthogonal layer design

400: Hybrid orthogonal layer design

500: QC-LDPC

600: core matrix

700: core basic matrix

800: core basic matrix

900: shift coefficient design

1000: communication system

1005: The first device

1050: Second device

1036, 1086: antenna

1030, 1080: transceiver

1032, 1082: transmitter

1034, 1084: receiver

1010, 1060: processor

1012, 1062: encoder

1014, 1064: decoder

1016, 1066: memory

1020, 1070: memory

1022, 1072: instruction

1024, 1074: Information

1040: Communication link

1100: Process

1110, 1120, 1130, 1140: block

1200: Process

1210, 1220, 1230: block

1300: Process

1310, 1320, 1330: block

1400: Process

1410, 1420, 1430, 1412, 1414: block

1500: shift coefficient table

1600: Shift coefficient table

1700: Shift coefficient table

1800: shift coefficient table

1900: shift coefficient table

2000: shift coefficient table

2100: Shift coefficient table

2200: Shift coefficient table

2300: Process

2310, 2320, 2330, 2340: block

2400: Process

2410, 2420: block

24202, 24204, 24206, 24208, 24210, 24212: sub-blocks

The drawings are included to provide a further understanding of the application, and the drawings are incorporated and form a part of the application. The drawings illustrate the embodiments of the present application, and together with the description are used to explain the principles of the present application. It is understandable that the drawings are not necessarily drawn to scale, some parts The dimensions in the application are shown disproportionately to clearly illustrate the concept of the present application.

Figure 1 is a schematic diagram of an exemplary multi-codebook embedded LDPC code design based on an embodiment of the present application; Figure 2 is a schematic diagram of an example logic flow related to a multi-codebook embedded LDPC code based on an embodiment of the present application Figure 3 is a schematic diagram of an exemplary quasi-row orthogonal layer design based on an embodiment of the present application; Figure 4 is an exemplary hybrid orthogonal layer design based on an embodiment of the present application FIG. 5 is a schematic diagram of an exemplary QC-LDPC code supporting an extremely low bit rate based on an embodiment of the present application; FIG. 6 is an exemplary kernel matrix design based on an embodiment of the present application; 7 is a schematic diagram of an exemplary concept of a core basic matrix based on an embodiment of the present application; FIG. 8 is a schematic diagram of an exemplary concept of a core basic matrix based on another embodiment of the present application; FIG. 9 is based on the present application FIG. 10 is a block diagram of an exemplary communication system based on an embodiment of the present application; FIG. 11 is a flowchart of an exemplary process based on an embodiment of the present application; Figure 12 is a flowchart of an exemplary process based on another embodiment of the present application; Figure 13 is a flowchart of an exemplary process based on another embodiment of the present application; Figure 14 is another based on the present application A flowchart of an exemplary process of an embodiment; each of FIGS. 15A and 15B is a schematic diagram of a partial exemplary shift coefficient table based on an embodiment of the present application; each of FIGS. 16A and 16B is based on this A schematic diagram of a part of an exemplary shift coefficient table of an embodiment of the application; each of FIGS. 17A and 17B is a schematic diagram of a partial exemplary shift coefficient table based on an embodiment of the present application; each of FIGS. 18A and 18B One is a partial exemplary shift coefficient table based on the embodiment of the present application Schematic diagram of FIG. 19A and FIG. 19B are each a partial schematic diagram of an exemplary shift coefficient table based on an embodiment of the present application; each of FIG. 20A and FIG. 20B are a partial exemplary diagram based on an exemplary embodiment of the present application Schematic diagram of the shift coefficient table; each of FIGS. 21A and 21B is a schematic diagram of some exemplary shift coefficient tables based on the embodiment of the present application; each of FIGS. 22A and 22B is based on the embodiment of the present application FIG. 23 is a schematic diagram of an exemplary logic flow for selecting a shift coefficient table based on an embodiment of the application; FIG. 24 is an example of another embodiment based on the application Flow chart of sexual process.

Detailed examples and implementations of the claimed subject matter are disclosed herein. However, it should be understood that the disclosed embodiments and implementations are merely illustrative of the claimed subject matter, which may be embodied in various forms. However, the present disclosure may be implemented in many different forms, and should not be interpreted as being limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that the description of the present disclosure is thorough and complete, and will fully convey the scope of the present disclosure to those having ordinary knowledge in the art. In the following description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

Overview

The proposed concepts and solutions generally involve the following fields: multi-codebook embedded LDPC code design, hybrid orthogonal LDPC layer design, very low code rate (CR) QC-LDPC support, kernel matrix design and shift coefficients design. The field of hybrid orthogonal LDPC layer design includes quasi-row New concepts and solutions for orthogonal layer design and hybrid orthogonal layer design. The following describes the proposed concepts and solutions with reference to FIGS. 1 to 9.

Figure 1 shows an exemplary multi-codebook embedded LDPC code design according to an embodiment of the present invention. Referring to FIG. 1, the basic parity check matrix (referred to interchangeably as “basic matrix” herein) 100 of the QC-LDPC code according to the present invention may have a plurality of codebooks embedded therein.

As shown in FIG. 1, the basic matrix 100 may include a parity matrix of a plurality of parity bits and an information matrix of a plurality of information bits. In other words, the basic matrix 100 can be defined by a parity matrix and an information matrix, where the parity matrix has relatively few non-zero/non-empty bits (each represented by "1" in FIG. 1) and most of the zero/space Yuan (each represented by "0" in Figure 1). The parity matrix can also define a set of linear constraints on the code bits. Therefore, each of the plurality of codebooks embedded in the QC-LDPC code of the basic matrix 100 may include a parity matrix and a corresponding part of an information matrix of a corresponding size, so that the sizes of the plurality of codebooks are different from each other. Therefore, regardless of the size, each codebook may constitute at least a part of the basic matrix. In the example shown in Figure 1, the codebook can be expressed as follows: Codebook = (I1 or I2 or I3) + P

The label "I1" represents the first part of the information matrix, the label "I2" represents the second part of the information matrix, the label "I3" represents the third part of the information matrix, and the label "P" represents the parity matrix. Here, the size of I1 (for example, in terms of the number of bits and/or the size of the memory) is larger than the size of I2, and the size of I2 is larger than the size of I3.

The size of the resulting codebook may vary depending on the size of the partial information matrix that forms the codebook with the parity matrix. It is worth noting that although the example shown in FIG. 1 describes three codebooks of different sizes due to the combination of I1+P, I2+P and I3+P, according to various embodiments of the present invention, the different sizes The number of codebooks is not limited to three (may be less than three or more than three).

In some embodiments, each of the plurality of codebooks may correspond to a corresponding HARQ in a plurality of hybrid automatic repeat request (HARQ) threads Threads, in which multiple HARQ threads are different from each other. For example, the first codebook may correspond to the first HARQ thread, and the value range of the first codebook is 0.33 to 0.89. The second codebook may correspond to the second HARQ thread, and the value range of the second codebook is 0.2 to 0.66. The third codebook may correspond to a third HARQ thread, and the third codebook has a small code block size of less than 400. Therefore, in HARQ-based communication between two communication devices, each HARQ thread of the plurality of HARQ threads may be related to or otherwise associated with the corresponding codebook of the plurality of codebooks. Therefore, the HARQ thread currently used in HARQ-based communication can be identified. Correspondingly, one of the plurality of codebooks can be selected, and one of the plurality of codebooks corresponds to the identified HARQ thread for encoding the data for sending.

In some embodiments, each of the plurality of codebooks corresponds to one or more registers, one or more buffers, one or more caches, and/or one or more memory cells The corresponding memory size (Kb). For example, the first codebook may correspond to the first storage size Kb=16. The second codebook may correspond to the second storage size Kb=12. The third codebook may correspond to the third storage size Kb=5. In the solution proposed according to the present invention, if a large codebook corresponding to a large memory size (for example, because the code block size of the data to be encoded is relatively large, or because the initial code rate is relatively high) is not Necessary, a small codebook corresponding to a small storage size can be selected for encoding. Therefore, it is possible to avoid using storage space larger than necessary (because a codebook larger than necessary is being selected), so the processing delay of encoding is shortened.

In some embodiments, all codebooks may share a basic matrix and use different zero-padding sizes. In some embodiments, different codebooks may correspond to different shift coefficient designs or share a shift coefficient design.

In some embodiments, depending on the initial code rate used to transmit the data, the code block size of the data, or both, which of the plurality of codebooks will be used. In some embodiments, if a large codebook corresponding to a large amount of encoding processing delay is not necessary for encoding, in order to The processing delay of the encoding is shortened, and the codebook is selected so that a small codebook that requires a small amount of encoding processing delay to encode.

Figure 2 shows an example logic flow 200 related to the design of a multicodebook embedded LDPC code based on an embodiment of the invention. The logic flow 200 may be implemented in or by an encoder or processor to implement various features and/or aspects of the concepts and/or solutions proposed by the present invention. More specifically, the logic flow 200 may involve selecting one or a plurality of rules used in the codebook from the plurality of codebooks embedded in the basic matrix of the QC-LDPC code, so that if the corresponding code has a large processing delay A large codebook is not necessary for encoding, and a small codebook with a small processing delay that requires encoding is selected for encoding. The logic flow 200 may include one or more operations, actions, or functions represented by one or more of blocks 210, 220, 230, 240, and 250. Although shown as discrete blocks, depending on the desired implementation, the various blocks of logic flow 200 may be divided into additional blocks, merged into fewer blocks, or deleted. The logic flow 200 may be implemented by each of the first device 1005 and the second device 1050 described below. For illustrative purposes only and not limited to scope, the description of the logic flow 200 is provided in the context of the second device 1050. The logic flow 200 may start at 210.

At 210, the logic flow 200 may involve the second device 1050 to determine whether the code block size of the material to be encoded is less than the threshold code block size. In the case where it is determined that the code block size of the material is smaller than the threshold code block size, the logic flow 200 may be performed from 210 to 220. In the case where it is determined that the code block size of the material is not less than the threshold code block size, the logic flow 200 may be executed from 210 to 230.

At 220, the logic flow 200 may involve the second device 1050 to select the first codebook among the plurality of codebooks. For example, a small size information matrix + parity matrix may be used as a basic matrix.

At 230, the logic flow 200 may involve the second device 1050 to determine whether the initial code rate for transmitting the data is greater than the threshold code rate. In the case where it is determined that the initial code rate is not greater than the threshold code rate, the logic flow 200 may be executed from 230 to 240. In the case where it is determined that the initial code rate is greater than the threshold code rate, the logic flow 200 may be performed from 230 to 250.

At 240, the logic flow 200 may involve the second device 1050 to select a plurality of codebooks In the second codebook in, for example, a medium-sized information matrix + parity matrix can be used as the basic matrix.

At 250, the logic flow 200 may involve the second device 1050 to select the third codebook among the plurality of codebooks. For example, a large size information matrix + parity matrix may be used as the basic matrix.

Here, the size of the third codebook is larger than the size of the second codebook. In addition, the size of the second codebook is larger than the size of the first codebook. Therefore, if a large codebook corresponding to a large storage size (for example, the code block size is greater than the threshold code block size or the initial code rate is greater than the threshold code rate) is not necessary for encoding, the logic flow 200 will select the small code corresponding to the small storage size Book, thereby minimizing the storage amount or storage size for storing the selected codebook. In other words, the logic flow 200 can help to shorten the processing delay of encoding.

FIG. 3 shows an exemplary quasi-row orthogonal layer design 300 based on an embodiment of the present invention. Orthogonality is beneficial to the throughput efficiency of LDPC decoders. In an LDPC code, several rows can be grouped together to form a layer, and the degree of each row (column) in the layer can be 1 or 0 (ie, orthogonality). In this case, this layer is called a pure row orthogonal layer.

Referring to FIG. 3, in the quasi-column orthogonal layer design 300, several columns can be grouped together to form a quasi-row orthogonal layer, such as layer 1, layer 2, and layer shown in FIG. 3. 3 and layer 4. In this example, in addition to one or more punctured columns, each row (column) in each of layers 1, 2, 2, 3, and 4 may be degree 1 or 0 ( That is, orthogonality). In the example shown in part (A) of FIG. 3, the two leftmost rows (columns) are punched rows. Each of the other rows (columns) in each of layer 1, layer 2, layer 3, and layer 4 is degree 1 or 0 (ie, has one or 0 non-null/non-null) bits Yuan, represented by "1", and other bits are zero/empty, represented by "0"). Advantageously, the quasi-column orthogonal layer design 300 provides orthogonality, helping to improve efficiency in decoder throughput.

Moreover, in the quasi-column orthogonal layer design 300, there is no Circle. In the example shown in part (B) of FIG. 3, according to the present invention, since there are loops in two punched rows, the corresponding layer is not considered as a quasi-column orthogonal layer.

FIG. 4 is an exemplary hybrid orthogonal layer design 400 based on an embodiment of the present invention. In the hybrid orthogonal layer design 400, the QC-LDPC code may include a plurality of ports of different degrees of orthogonality. In the example shown in FIG. 4, the darker color block represents bit 1, and the lighter color block represents bit 0. For example, the first part of the plurality of parts may be low-degree orthogonal and may correspond to a high code rate. Similarly, the second part of the plurality of parts may be medium-degree orthogonal, and may correspond to a medium code rate. Similarly, the third part of the plurality of parts may be orthogonal in height, and may correspond to a low code rate.

In the example shown in Fig. 4, the plural parts of different orthogonal degrees include the following: (1) The non-row orthogonal part includes plural rows and plural columns, and the plural rows and plural numbers The columns form at least one non-row orthogonal layer corresponding to a relatively high code rate; (2) The quasi-column orthogonal part includes a plurality of rows and a plurality of columns, the plurality of rows and the plurality of columns Forming at least one quasi-column orthogonal layer corresponding to a medium code rate; (3) a pure-row orthogonal part, which includes a plurality of rows and a plurality of columns, and the plurality of rows and the plurality of columns form a corresponding relative comparison At least one pure column orthogonal layer of low bit rate. Here, each of a plurality of rows in a non-row orthogonal part is a row with a degree of 2 or higher. In addition, one or more of the plurality of rows of the quasi-column orthogonal portion includes a punctured row with a degree of 2 or higher. Moreover, the remaining rows of the plurality of rows of the quasi-column orthogonal part may include non-punched rows whose degree is 1 or 0. Moreover, each of the plurality of rows of the orthogonal part of the pure column includes rows whose degree is 1 or 0.

FIG. 5 shows an example QC-LDPC code 500 supporting an extremely low code rate according to an embodiment of the present invention. Referring to FIG. 5, the QC-LDPC code 500 may include a parity matrix of plural parity bits and an information matrix of plural information bits. The columns of the information matrix and the parity matrix may include one or a plurality of rows of bits with a bit degree of 2 for each column. Moreover, each of the bits with a degree of 2 or one of a plurality of row bits with a degree of 2 may be used previously Parity bits or previously transmitted information bits. Moreover, for very low bit rates, one or more previous transmissions can be retransmitted. Accordingly, the extended row (row) may have a weight of 2. Check the node split for the row with a large weight.

Figure 6 shows an example core matrix design 600 according to an embodiment of the invention. Referring to FIG. 6, in the core matrix design 600, the QC-LDPC code may include a basic matrix, and a part of the basic matrix forms a core matrix corresponding to a code rate of at least a threshold. For example, in the example shown in Figure 6, the core matrix supports a code rate of 0.89.

Figure 7 shows an example concept 700 of a core basic matrix according to an embodiment of the invention. Please refer to Fig. 7, the core matrix may include a plurality of columns and a plurality of rows and a plurality of rows, of which two or more rows (columns) are punched rows, the plurality of punched rows have specific Bit pattern (for example, one or plural bits 0). In some embodiments, the specific bit pattern in the plurality of punching rows may include an isosceles right-angled triangle formed by a plurality of bit 0, and the right angle of the triangle corresponds to the upper left of the plurality of punching rows Bit 0 at the corner.

The core matrix may include a parity matrix including a plurality of rows and a plurality of columns of a plurality of bits. The core matrix may also include an information matrix including a plurality of rows and a plurality of columns of a plurality of bits. The parity matrix may include a matrix having a Wi-Fi pattern (for example, a Wi-Fi-like parity matrix). Moreover, more than one row of the information matrix may include a plurality of rows with a high density of bit 1 without or with one bit 0. The bits of the bottom column of the plurality of columns may include a first number of bits 1. The first number may be equal to the number of punching rows or greater than the number of punching rows (columns) by one.

In the example shown in part (A) of FIG. 7, the first few rows (for example, three columns) are composed of a Wi-Fi-like parity matrix, and the information matrix has an ultra-high density of bits 1. In particular, if not all of the bits included in each column in the information matrix are bit 1, then most of them are bit 1, with no zero or with one zero. Permutation and/or at any number of times After row replacement (for example, at least one column replacement, at least one row replacement, or a combination thereof), the punctured row includes a specific pattern of one or a plurality of bit 0s. The bottom row (row) may have 3 or 4 edge blocks, and one edge block (edge block) may correspond to a parity (Variable Node, VN) block. Two edge blocks may correspond to two punctured rows (for example, VN0 and VN1). In the case where there are four edge blocks, a fourth edge block can be added to increase the shortest distance.

In the example shown in part (B) of Fig. 7, an example pattern of the punching row is shown. For a basic matrix of size mxn (m columns by n rows), and assuming that p rows are punctured, use a plurality of isosceles right-angled triangles to construct an mxp matrix. The right angle of the triangle corresponds to the complex number of hits Bit 0 at the upper left corner of a row of holes. The other bits in the punctured row can be randomly selected as 0 or 1. Since row replacement and/or column replacement may be performed, the actual position of a specific pattern may be different from the upper left corner of the punched row.

Figure 8 is an example concept 800 showing a core basic matrix based on another embodiment of the invention. At concept 800, the core basic matrix includes a Wi-Fi pattern (or a parity matrix similar to the Wi-Fi pattern), a column, and the rest of the information matrix. The rest of the information matrix can be designed using one of multiple degree distributions. For example, the core matrix may include 5 rows of bits and 20 rows of bits. The 20-line variable node (VN) degree can include one of the following: [2,2,2,2,2,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3],[2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] ,[2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3], and [2,2,3 ,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]. The 5-row (row) bit check node (CN) degree can include one of the following: [13,10,14,17,2],[13,10,13,17,2],[13,10,13 ,18,3],[13,11,13,18,2],[13,10,14,18,2],[13,10,13,19,2],[14,10,13,18 ,1],[13,11,13,18,1],[13,10,14,18,1],[13,11,13,19,1],[13,10,13,18,2 ], and [13,10,13,18,1].

FIG. 9 shows a shift coefficient design 900 based on an embodiment of the present invention. For each Lifting factor (lifting factor), there is a table of corresponding shift values. Tables in different lifting factors can be nested design. In the shift coefficient design 900, an effective set of lifting factors can be defined for use in LDPC coding. In the example shown in Figure 9, the effective set of lifting factors includes: lifting factors of the following different values: Z=16, Z=24, Z=32, Z=48, Z=64, Z=96, Z =128, Z=192, Z=256 and Z=384. In the shift coefficient design 900, the effective set of lifting factors can be optimized to obtain an optimized set of lifting factors. The number of lifting factors in the optimized set is smaller than the number of lifting factors in the effective set. The shift coefficient table of the lift factor in the optimized set can be used as the shift coefficient table of the lift factor closest to and greater than or equal to the lift factor in the optimized set. For example, a table designed for the shift value of the lift factor Z=32 can be shared by the lift factor Z=48. Similarly, the table designed for the shift value of the lift factor Z=128 can be shared by the lift factor Z=192.

X={a x 2^j}

a

{9,11,13,15},j

{0,1,2,3,4,5}，提升因子的優化集合(Z)可以被定義為4組。使用Z

φ={a x 2^j}

a

{9,10,11,12,13,14,15,16},j

{0,1,2,3,4,5}，提升因子的有效集合可以被定義為8組。相應的移位值可以由4個移位係數表代表，該4個移位係數表代表可以對應到移位係數{288,352,416,480}。對於有效集合φ中的任何提升因子Z=a x 2^j，相應的移位係數可以通過

獲得，其中，p^m,n是â x 2⁵的移位係數表中第(m,n)個元素的移位係數，其中â是{9,11,13,15}中的最大值且â小於或者等於有效集合φ中的a，並且

。而且，f(Z)為擾動(perturbation)，是Z的函數，並可使用一表來表示。 For the purpose of illustration rather than limitation, in the LDPC codebook based on the present invention, Z is used

X={ax 2 ^j }

a

{9,11,13,15},j

{0,1,2,3,4,5}, the optimized set of lifting factors (Z) can be defined as 4 groups. Use Z

φ={ax 2 ^j }

a

{9,10,11,12,13,14,15,16},j

{0,1,2,3,4,5}, the effective set of lifting factors can be defined as 8 groups. The corresponding shift value can be represented by 4 shift coefficient tables, which can correspond to shift coefficients {288,352,416,480}. For any lifting factor Z=ax 2 ^j in the effective set φ, the corresponding shift coefficient can be obtained by

Obtained, where p ^m,n is the shift coefficient of the (m,n)th element in the shift coefficient table of â x 2 ⁵ where â is the maximum value in {9,11,13,15} and â Is less than or equal to a in the effective set φ, and

. Moreover, f(Z) is a perturbation, a function of Z, and can be expressed using a table.

The use of lifting factors allows the use of relatively small sets of basic matrices and relatively small sets of lifting factors to encode packets of various sizes. For example, the basic matrix size m x n can be used to encode packets of up to k=n-m information bits to obtain an encoded packet or codeword of n code bits. Using the lifting factor Z, the basic matrix can be lifted to produce the extended dimension Z. m x Z. Parity check matrix for n. The extended parity check matrix can then be used to encode up to Z. k packets of information bits to obtain Z. Codeword of n code bits. Moreover, the use of lifting factors can also allow efficient parallel encoding and decoding, thereby improving performance and reducing the complexity of description for large-size LDPC codes.

Design of shift coefficient table for larger code block size

For illustration purposes, FIGS. 15A-22B show a plurality of exemplary shift coefficient tables for relatively large code block sizes.

Each of FIGS. 15A to 15B is a schematic diagram of a portion of an exemplary shift coefficient table 1500 based on an embodiment of the present invention. In particular, the shift coefficient table 1500 is composed of part (A) in FIG. 15A and part (B) in FIG. 15B. Moreover, the shift coefficient table 1500 may correspond to a basic chart 1 (BG1) having a primitive element 7 (a=7) and a lifting factor 224.

Each of FIGS. 16A to 16B is a schematic diagram of a portion of an exemplary shift coefficient table 1600 based on an embodiment of the present invention. In particular, the shift coefficient table 1600 is composed of part (A) in FIG. 16A and part (B) in FIG. 16B. Moreover, the shift coefficient table 1600 may correspond to BG1 having the original element 15 (a=15) and the lifting factor 240.

Each of FIGS. 17A-17B is a schematic diagram of a portion of an exemplary shift coefficient table 1700 based on an embodiment of the present invention. In particular, the shift coefficient table 1700 is composed of part (A) in FIG. 17A and part (B) in FIG. 17B. Moreover, the shift coefficient table 1700 may correspond to BG1 having the original element 9 (a=9) and the lifting factor 288.

Each of FIGS. 18A to 18B is a schematic diagram of a part of an exemplary shift coefficient table 1800 based on an embodiment of the present invention. In particular, the shift coefficient table 1800 is composed of part (A) in FIG. 18A and part (B) in FIG. 18B. Moreover, the shift coefficient table 1800 may correspond to BG1 having the original element 5 (a=5) and the lifting factor 320.

Each of FIGS. 19A to 19B is a schematic diagram of a part of an exemplary shift coefficient table 1900 based on an embodiment of the present invention. In particular, the shift coefficient table 1900 is composed of part (A) in FIG. 19A and part (B) in FIG. 19B. Moreover, the shift coefficient table 1900 may correspond to BG1 having the original element 11 (a=11) and the lifting factor 352.

Each of FIGS. 20A to 20B is a schematic diagram of a part of an exemplary shift coefficient table 2000 based on an embodiment of the present invention. In particular, the shift coefficient table 2000 is composed of part (A) in FIG. 20A and part (B) in FIG. 20B. Moreover, the shift coefficient table 2000 may correspond to BG1 having the original element 3 (a=3) and the lifting factor 384.

Each of FIGS. 21A-21B is a schematic diagram of a portion of an exemplary shift coefficient table 2100 based on an embodiment of the present invention. In particular, the shift coefficient table 2100 is composed of part (A) in FIG. 21A and part (B) in FIG. 21B. Moreover, the shift coefficient table 2100 may correspond to BG1 having the original element 13 (a=13) and the lifting factor 208.

Each of FIGS. 22A-22B is a schematic diagram of a portion of an exemplary shift coefficient table 2200 based on an embodiment of the present invention. In particular, the shift coefficient table 2200 is composed of part (A) in FIG. 22A and part (B) in FIG. 22B. Moreover, the shift coefficient table 2200 may correspond to BG1 having the original element 2 (a=2) and the lifting factor 256.

FIG. 23 shows an exemplary logic flow 2300 related to selecting a shift coefficient table based on an embodiment of the present invention. The logic flow 2300 may be implemented in or by an encoder or processor to implement various features and/or aspects in the concepts and solutions proposed by the present invention. In particular, the logic flow 2300 may involve selecting one or a plurality of rules used in the shift coefficient table from the plurality of shift coefficient tables so that the shift coefficient table suitable for data of a relatively large code block size is selected. The logic flow 2300 may include one or more operations, actions, or functions represented by one or more of blocks 2310, 2320, 2330, and 2340. Although shown as discrete blocks, depending on the desired implementation, the various blocks of the logic flow 2300 can be divided into additional blocks and merged into fewer blocks, Or delete. The logic flow 2300 may be implemented by each of the first device 1005 and the second device 1050 described below. For illustrative purposes only and not limited to scope, the description of the logic flow 2300 is provided in the context of the first device 1005. The logic flow 2300 may start at 2310.

At 2310, the logic flow 2300 may involve the processor of the first device 1005 determining whether the code block size of the material to be encoded is less than or equal to the threshold code block size. In the case where it is determined that the code block size of the material is less than or equal to the threshold code block size, the logic flow 2300 may be executed from 2310 to 2320. In the case where the processor 1010 determines that the code block size of the data is greater than the threshold code block size, the logic flow 2300 may be executed from 2310 to 2330.

At 2320, logic flow 2300 may involve processor 1010 determining whether the code rate of the material to be encoded is less than or equal to the threshold code rate. In the case where the processor 1010 determines that the code rate of the data is less than or equal to the threshold code rate, the logic flow 2300 may be executed from 2320 to 2340. Otherwise, the processor 1010 determines that the code rate of the material is determined to be greater than the threshold code rate, and the logic flow 2300 may be executed from 2320 to 2330.

At 2330, the logic flow 2300 may involve the processor 1010 selecting or otherwise using the shift coefficient table corresponding to the base chart 1 (BG1).

At 2340, the logic flow 2300 may involve the processor 1010 selecting or otherwise using a shift coefficient table corresponding to the base chart 2 (BG2).

In the scheme proposed based on the present invention, no matter which shift coefficient table is selected, part or all (whole) of the selected shift coefficient table may be used in encoding. Moreover, the modulo (mod) of the value of the shift coefficient table selected or otherwise used for one or a plurality of lifting factors and the result of the modulo of any shift coefficient table shown in FIGS. 15A-22B The same, whether partly or overall.

Illustrative implementation

FIG. 10 shows an exemplary communication system 1000 based on an embodiment of the present invention. Communication The system may include a first device 1005 and a second device 1050, and the first device 1005 and the second device 1050 may communicate with each other via a communication link. The communication link 1040 may be a wireless link in some embodiments. Alternatively, the communication link 1040 may be a wired link in some other embodiments. In the environment of 5G NR communication, the communication link 1040 is a wireless communication link, for example, a multi-user multiple-input-and-multiple-output (MU-MIMO) communication link. Each of the first device 1005 and the second device 1050 can perform various functions as a communication device to implement the concepts, schemes, techniques, processes, and methods described herein with regard to QC-LDPC encoding, including regarding FIG. 1- Part or all of Figure 9 and those descriptions of processes 1100, 1200, 1300, 1400 described below. More specifically, each of the first device 1005 and the second device 1050 can implement the proposed multi-codebook embedded LDPC code design, hybrid orthogonal LDPC layer design, and extremely low code rate QC-LDPC support. Matrix design, core matrix design and shift coefficient design concepts and aspects of the program.

Each of the first device 1005 and the second device 1050 may be part of an electronic device, which may be a communication device, a computing device, a portable or mobile device, or a wearable device. For example, the first device 1005 may be on a Wi-Fi access point, smart phone, smart watch, smart bracelet, smart necklace, personal digital assistant or such as a tablet computer, laptop computer, notebook computer, desktop computer or servo Implemented in computing devices such as devices. Similarly, the second device 1050 can be on a Wi-Fi mobile client or site, smart phone, smart watch, smart bracelet, smart necklace, personal digital assistant or such as a tablet, laptop, desktop or servo Implemented in computing devices such as devices. Alternatively, each of the first device 1005 and the second device 1050 may be implemented in the form of one or more integrated circuit (IC) chips, such as but not limited to, one or more single-core processors, one or more Multi-core processors, or one or more complex instruction set calculation (complex-instruction-set-computing, CISC) processors.

Each of the first device 1005 and the second device 1050 may include a 10th At least a part of those elements shown in the figure. For example, the first device 1005 may include at least the processor 1010, and the second device 1050 may include at least the processor 1060. In addition, the first device may include a memory 1020, a transceiver 1030, and one or more antennas (represented by antennas 1036). The transceiver 1030 is configured to send and receive data wirelessly (for example, following one or more 3GPP standards, agreements , Specifications, and/or any applicable wireless protocols and standards, such as 5G NR). Each of the memory 1020 and the transceiver 1030 can be communicatively or operatively coupled to the processor 1010. Similarly, the second device 1050 may also include a memory 1070, a transceiver 1080, and one or more antennas (represented by the antenna 1086). The transceiver 1080 is configured to wirelessly transmit and receive data (for example, following one or more 3GPP Standards, agreements, specifications, and/or any applicable wireless protocols and standards, such as 5G NR). Each of the memory 1070 and the transceiver 1080 is communicatively or operatively coupled to the processor 1060. Each of the first device 1005 and the second device 1050 may further include other elements (for example, a power system, a display device, and a user interface device) which are not related to the solution proposed by the present invention, so for simplicity and conciseness, there is no It is also not shown in Figure 10.

The transceiver 1030 may be configured to wirelessly communicate in a single frequency band or multiple frequency bands. The transceiver 1030 may include a transmitter 1032 capable of wirelessly transmitting data and a receiver 1034 capable of wirelessly receiving data. In some embodiments, the transceiver 1030 is capable of transmitting/modulating (via the transmitter 1032) and receiving/demodulating (via the receiver 1034) as orthogonal frequency-division multiplexed (OFDM) radiated through the antenna 1036 ) Symbol data symbol. Similarly, the transceiver 1080 may be configured to wirelessly communicate in a single frequency band or multiple frequency bands. The transceiver 1080 may include data symbols capable of transmitting/modulating (via the transmitter 1082) and receiving/demodulating (via the receiver 1084) as OFDM symbols radiated through the antenna 1086.

Each of the memory 1020 and the memory 1070 may be a storage device configured to store one or more sets of codes, programs, and/or instructions and/or data therein. In the example shown in FIG. 10, the memory 1020 stores therein one or more sets of processor executable instructions 1022 and data 1024, And the memory 1070 stores one or more sets of processor executable instructions 1072 and data 1074 therein. Each of the memory 1020 and the memory 1070 may be implemented by any suitable technique, and may include volatile memory and/or non-volatile memory. For example, each of the memory 1020 and the memory 1070 may include a type of random access memory (RAM), such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM), and/or Zero-capacitor RAM (Z-RAM). Alternatively or additionally, the memory 520 may include a read-only memory (ROM), such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and/or erasable Programmable ROM (erasable programmable ROM, EEPROM). Alternatively or additionally, each of the memory 1020 and the memory 1070 may include a type of non-volatile random-access memory (NVRAM), such as flash memory, Solid state memory, ferroelectric RAM (ferroelectric RAM, FeRAM), magnetoresistive RAM (magnetoresistive RAM, MRAM) and/or phase-change (phase-change) memory.

In one aspect, each of the processor 1010 and the processor 1060 may be implemented in the form of one or more single-core processors, one or more multi-core processors, or one or more CISC processors. That is, according to the present invention, even if the singular term “processor” is used herein to refer to each of the processor 1010 and the processor 1060, according to the present invention, each of the processor 1010 and the processor 1060 is implemented in some Multiple processors may be included in a single processor in other implementations. In another aspect, each of the processor 1010 and the processor 1060 may be implemented in the form of hardware (and optionally firmware) with electronic components including, for example, but not limited to, one or more electronic components Crystal, one or plural diodes, one or plural capacitors, one or plural resistors, one or plural inductors, one or plural memristors and/or one or plural varactors A varactor is configured and arranged according to the present invention to achieve a specific purpose. In other words, in at least some embodiments, each of the processor 1010 and the processor 1060 is a dedicated-purpose processor that is specifically designed, arranged, and configured to perform specific tasks, according to In various embodiments of the present invention, this particular task includes the design of a shift coefficient table for QC-LDPC codes with larger code block sizes in mobile communications.

According to various embodiments of the present invention, the processor 1010 as a dedicated machine may include non-general and specially designed hardware circuits that are designed, arranged, and configured to perform QC for larger code block sizes in mobile communication -Specific tasks related to the design of the shift coefficient table of the LDPC code. In one aspect, according to various embodiments of the present invention, the processor 1010 may execute one or more sets of codes, programs, and/or instructions 1022 stored in the memory 1020 to perform various operations to render in mobile communication Design of shift coefficient table for QC-LDPC codes with larger code block size. On the other hand, according to various embodiments of the present invention, the processor 1010 may include an encoder 1012 and a decoder 1014, and the encoder 1012 and the decoder 1014 perform specific tasks and functions together to render a QC-LDPC code. For example, according to various concepts and schemes of the present invention, the encoder 1012 may be configured to encode data. Similarly, according to various concepts and solutions of the present invention, the decoder 1014 may be configured to decode data.

In some implementations, the processor 1010 may also include memory 1016, which may include one or more registers, one or more buffers, and/or one or more caches. In some implementations, the processor 1010 can utilize the memory 1016 to store the basic matrix of the QC-LDPC code, the selected codebook, the lifting factor, and/or one or a plurality of shift coefficient matrices. For example, the processor 1010 may generate a basic matrix and store it in the memory 1020, and when selecting a codebook from a plurality of codebooks embedded in the basic matrix, the processor 1010 may store the selected codebook in In memory 1016. Therefore, according to one or a plurality of rules of the logic flow 200, by selecting a codebook from a plurality of codebooks embedded in the basic matrix, the processing delay of encoding can be shortened. Therefore, by implementing various schemes according to the present invention (for example, by selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code to encode data for transmission), not only the function of the processor 1010 is improved (for example, The processing delay is shorter) and the underlying technology of data encoding is also improved (for example, the processing delay is shorter and the decoder throughput efficiency is improved).

According to various embodiments of the present invention, the processor 1060 as a dedicated machine may include non-general and specially designed hardware circuits that are designed, arranged, and configured to perform specific tasks related to QC-LDPC encoding. In one aspect, according to various embodiments of the present invention, the processor 1060 may execute one or more sets of codes, programs, and/or instructions 1072 stored in the memory 1070 to perform various operations related to QC-LDPC encoding. On the other hand, according to various embodiments of the present invention, the processor 1060 may include an encoder 1062 and a decoder 1064, which perform specific tasks and functions to render QC-LDPC encoding. For example, according to various concepts and schemes of the present invention, the encoder 1062 may be configured to encode data. Similarly, according to various concepts and solutions of the present invention, the decoder 1064 may be configured to decode data.

In some implementations, the processor 1060 may also include memory 1066, which may include one or more registers, one or more buffers, and/or one or more cache memories. In some embodiments, the processor 1060 may utilize the memory 1066 to store the base matrix of the QC-LDPC code, the selected codebook, the lifting factor, and/or the shift coefficient matrix. For example, the processor 1060 may generate a basic matrix and store it in the memory 1070, and when selecting a codebook from a plurality of codebooks embedded in the basic matrix, the processor 1060 may store the selected codebook in In memory 1066. Therefore, by selecting a codebook from a plurality of codebooks embedded in the basic matrix according to one or a plurality of rules of the logic flow 200, the processing delay of encoding can be shortened.

Each of the encoder 1012 and the encoder 1062 may be configured to have a plurality of electronic components that operate as an encoding chain to perform a plurality of operations related to encoding. For example, the encoding chain in each of the encoder 1012 and the encoder 1062 may perform the following: bit reordering, tone interleaving, mixed redundancy version (RV) design, Self-adjusting HARQ buffer, and code block grouping. Each of the decoder 1014 and the decoder 1064 may be configured to support various code rates of the codebook. The minimum code rate of the codebook supported by each of the decoder 1014 and the decoder 1064 may depend on the size of the corresponding lifting factor. In the proposed scheme, an upper limit of the size of the log-likelihood ratio (LLR) memory can be set. The lifting factor can be stored in the LLR memory, and the size of the LLR memory can be defined or otherwise defined as to how large the lifting factor can be. Correspondingly, by setting the upper limit of the LLR memory size, the maximum size of the extended parity check matrix generated from the basic matrix can be set, thereby setting the memory size of the extended parity check matrix to be stored Upper limit. In the first device 1005, one or more registers, one or more buffers, one or more cache memories, and/or the processor 1010 (eg, memory 1016) or the memory 1020 may be used One or more of the memory units to achieve LLR memory. In the second device 1050, by using one or more registers, one or more buffers, one or more cache memories, and/or in the processor 1060 (eg, memory 1066) or in the memory 1070 One or more memory units to achieve LLR memory.

In operation, for the forward link on the sending side, the encoder 1012 may receive data packets from the data source, process the data by performing encoding, interleaving, and symbol mapping on the data, and provide modulation symbols for the encoded data. The transmitter 1032 may multiplex modulation symbols and pilot symbols, perform spatial processing, and provide one or more output symbol streams. The transmitter 1032 (which may include one or a plurality of transmitters) may condition one or a plurality of output symbol streams by performing digital-to-analog conversion, filtering, amplification, and up-conversion to generate one or a plurality of forward chains For the channel signal, the one or a plurality of forward link signals passing through the antenna 1036 are radiated as an electromagnetic wave. On the receiving (RX) side, the receiver 1084 (which may include one or plural receivers) may receive one or plural forward link signals as electromagnetic waves via one or plural antennas of the antenna 1086. The receiver 1084 can also process the received signal by performing filtering, amplification, down conversion, and analog to digital conversion to obtain a plurality of samples. The receiver 1084 may also process a plurality of samples to obtain received symbols, and perform multiple input multiple output (MIMO) detection on the received symbols to provide the detected symbols. The decoder 1064 can perform symbolic solution by Mapping, deinterleaving, and decoding process the detected symbols to provide decoded data to the sink.

Similarly, on the reverse link, the encoder 1062 can receive data packets from the data source and process the data through decoding, interleaving, and symbol mapping to provide modulation symbols for the encoded data. The transmitter 1082 may multiplex modulation symbols and pilot symbols, perform spatial processing, and provide one or more output symbol streams. The transmitter 1082 (which may include one or a plurality of transmitters) may condition one or a plurality of output symbol streams by performing digital-to-analog conversion, filtering, amplification, and up-conversion to generate one or a plurality of reverse chains Signal, the one or more reverse link signals are radiated as electromagnetic waves through one or more antennas of the antenna 1086. On the receiving (RX) side, the receiver 1034 (which may include one or a plurality of receivers) may receive one or a plurality of reverse link signals as electromagnetic waves via one or a plurality of antennas of the antenna 1036. The receiver 1034 may process the received signal by performing filtering, amplification, down conversion, and analog to digital conversion to obtain a plurality of samples. The receiver 1034 may also process a plurality of samples to obtain received symbols, and perform MIMO detection on the received symbols to provide the detected symbols. The decoder 1014 may process the detected symbols by performing symbol demapping, deinterleaving, and decoding to recover the data sent by the second device 1050.

The processor 1010 may be configured to control or otherwise direct the operation of the first device 1005. The processor 1060 may be configured to control or otherwise direct the operation of the second device 1050. According to the scheme and concept of the present application, the processor 1010 can determine the size of the packet to be transmitted and/or received, and, accordingly, control the encoding by the encoder 1012 and the decoding by the decoder 1014, respectively. Similarly, according to the scheme and concept of the present application, the processor 1060 can determine the size of the packet to be transmitted and/or received, and, accordingly, control the encoding by the encoder 1062 and the decoding by the decoder 1064, respectively. For example, each of the processor 1010 and the processor 1060 may be configured to select a codebook from a plurality of codebooks embedded in the basic matrix of the QC-LDPC code for encoding, such that if a large number of encoding processing delays The large codebook is not necessary for coding, a small number of codes need to be selected Handle delayed small codebooks for encoding.

Each of the first device 1005 and the second device 1050 may be configured to perform each of the processes 1100, 1200, 1300, 1400, and 2400 described below. Therefore, to avoid redundancy and for simplicity, the operations of the first device 1005 and the second device 1050, and the operations of the processor 1010 and the processor 1060 are described in the context of the following processes 1100, 1200, 1300, 1400, and 2400. It is worth noting that although the following description is provided in the environment of the first device 1005, the following description also applies to the second device 1050.

Regarding the design of the shift coefficient table for QC-LDPC codes used for large code block sizes in mobile communications, the processor 1010 of the first device 1005 may establish a wireless communication link with the second device 1050 via the transceiver 1030 of the device 1005. The processor 1010 may wirelessly communicate with the second device 1050 via the transceiver 1030 via a wireless communication link. In wireless communication with the second device 1050, the processor 1010 may perform a plurality of operations. For example, the processor 1010 may perform the following: (1) select a first shift coefficient table from a plurality of shift coefficient tables; (2) generate a QC-LDPC code using at least a part of the first shift coefficient table and a basic matrix; (3) Select the codebook from the plurality of codebooks embedded in the QC-LDPC code; (4) Store the selected codebook to the memory associated with the processor; (5) Use the selected codebook to encode data to Generate a plurality of modulation symbols of the data; and (6) Control the transceiver 1030 to multiplex, convert, filter, amplify the modulation symbols, and radiate the modulation symbols as electromagnetic waves through one or more antennas 1036 of the first device to communicate via wireless The link sends the modulation symbol of the material to the second device 1050.

In some embodiments, the first shift coefficient table may include a basic shift coefficient table, which is arranged in 4 rows and 26 columns in the following pattern:

In some embodiments, the first shift coefficient table may include The shift coefficient table shown in FIG. 18B.

In some embodiments, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 5 (a=5) and the lifting factor 320. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 7 (a=7) and the lifting factor 224. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 15 (a=15) and the lifting factor 240. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 9 (a=9) and the lifting factor 288. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 11 (a=11) and the lifting factor 352. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 3 (a=3) and the lifting factor 384. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 13 (a=13) and the lifting factor 208. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 2 (a=2) and the lifting factor 256.

In some embodiments, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the processor 1010 may select one or a complex number related to either or both of the code block size and the code rate of the data Rule, select the first shift coefficient table for a relatively large code block size.

In some embodiments, when using at least a portion of the first shift coefficient table and the basic matrix to generate the QC-LDPC code, the processor 1010 may use the full portion of the first shift coefficient table and the basic matrix to generate the QC -LDPC code.

In some embodiments, when using at least a portion of the first shift coefficient table and the basic matrix to generate the QC-LDPC code, the processor 1010 may use a partial portion of the first shift coefficient table and the basic matrix to generate the QC -LDPC code.

In some embodiments, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the processor 1010 may select the second shift coefficient table, the value of the second shift coefficient table is one or The modulo of the plurality of lifting factors is the same as the modulo result of at least the first shift coefficient table.

In some embodiments, when using at least a portion of the first shift coefficient table and the basic matrix to generate the QC-LDPC code, the processor 1010 may use the full portion and the basic matrix of the second shift coefficient table to generate the QC -LDPC code.

In some embodiments, when using at least a portion of the first shift coefficient table and the basic matrix to generate the QC-LDPC code, the processor 1010 may use a partial portion of the second shift coefficient table and the basic matrix to generate the QC -LDPC code.

In some embodiments, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the processor 1010 may perform a plurality of operations (for example, regarding the logic flow 2300). For example, the processor 1010 may determine whether the code block size is less than or equal to the threshold code block size. In addition, the processor 1010 may determine whether the code rate is less than or equal to the threshold code rate. Moreover, in response to determining that the code block size is greater than the threshold code block size or in response to determining that the code rate is greater than the threshold code rate, the processor 1010 may select the first shift coefficient table corresponding to the basic chart 1 (BG1). Alternatively, in response to determining that the code block size is less than or equal to the threshold code block size and in response to determining that the code rate is less than or equal to the threshold code rate, the processor 1010 may select the first shift corresponding to the basic chart 2 (BG2) Coefficient table.

In some embodiments, each of the plurality of codebooks may correspond to a respective HARQ thread in a plurality of HARQ threads of the hybrid automatic repeat request, and the plurality of HARQ threads are different from each other.

In some embodiments, the processor 1010 may perform a plurality of operations when selecting a codebook from a plurality of codebooks. For example, the processor 1010 may determine whether the code block size of the material is smaller than the threshold code block size. In addition, in response to the code block size of the data being smaller than the threshold code block size, the processor 1010 may select the third codebook among the plurality of codebooks. Moreover, in response to the code block size of the data being not less than the threshold code block size, the processor 1010 may determine whether the initial code rate for transmitting the data is greater than the threshold code rate. Moreover, in response to the initial code rate being not greater than the threshold code rate, the processor 1010 may select the first Two codebooks. Moreover, in response to the initial code rate being greater than the threshold code rate, the processor 1010 may select the first codebook among the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

In some embodiments, the processor 1010 may perform a plurality of operations when selecting a codebook from a plurality of codebooks. For example, the processor 1010 may determine the code block size of the material. In addition, the processor 1010 may select a codebook by: (1) in response to the determined code block size being greater than the first threshold code block size, selecting the first codebook among the plurality of codebooks; (2) responding to the determination The code block size is greater than the second threshold code block size, select the second codebook in the plurality of codebooks; (3) In response to the determined code block size being greater than the third threshold code block size, select the plurality of codebooks The third codebook. The first threshold code block size may be larger than the second threshold code block size. The second threshold code block size may be larger than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

Illustrative process

FIG. 11 shows an exemplary process 1100 based on an embodiment of the present application. Process 1100 may represent aspects of implementing the proposed concepts and solutions, and the proposed concepts and solutions may, for example, be described with respect to some or all of FIGS. 1-10. In particular, the process 1100 may represent aspects of the proposed concepts and schemes related to QC-LDPC coding. Process 1100 may include one or more operations, actions, or functions shown in one or more of blocks 1110, 1120, 1130, and 1140. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1100 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 1100 may be performed in the order shown in FIG. 11 or in a different order. Process 1100 may be implemented by communication system 1000 and any variations thereof. For example, the process 1100 may be implemented in or by the first device 1005 and/or the second device 1050. For illustrative purposes only and not limited to scope, the process 1100 is described in the context of the first device 1005 as follows. Process 1100 can be opened Start at block 1110.

At 1110, the process 1100 may involve the processor 1010 of the first device 1005 generating a QC-LDPC code having a plurality of codebooks embedded therein. Process 1100 is performed from 1110 to 1120.

At 1120, process 1100 may involve processor 1010 selecting a codebook from a plurality of codebooks. The processor 1010 may execute from 1120 to 1130.

At 1130, process 1100 may involve processor 1010 encoding the material using the selected codebook. Process 1100 is performed from 1130 to 1140.

At 1140, the process 1100 may involve the processor 1010 sending the encoded material via the transceiver 1030 (eg, to the second device 1050).

In some embodiments, each of the plurality of codebooks may correspond to a respective HARQ thread of the plurality of HARQ threads, and the plurality of HARQ threads are different from each other. For example, the process 1100 may involve the processor 1010 communicating with the processor 1060 of the second device 1050 using HARQ. When selecting a codebook from a plurality of codebooks, the process 1100 may involve the processor 1010 to perform: (1) associate or otherwise associate each HARQ thread in the plurality of HARQ threads with corresponding codes in the plurality of codebooks (2) Identify the HARQ thread currently used to communicate with the second device 1050; and (3) Select one of the multiple codebooks, one of the multiple codebooks and the identified HARQ thread correspond. The selected codebook may be used in encoding the data to be sent to the second device 1050.

In some embodiments, when generating a QC-LDPC code having a plurality of codebooks embedded therein, the process 1100 may involve the processor 1010 generating a QC-LDPC code consisting of a basic matrix and one or a plurality of shift coefficient matrices . The basic matrix may include a parity matrix of plural parity bits and an information matrix of plural information bits. Each codebook in the plurality of codebooks may include a parity matrix and a corresponding part of an information matrix of a corresponding size, so that the sizes of the plurality of codebooks are different from each other.

In some embodiments, each of the plurality of codebooks may correspond to a shift coefficient Corresponding design in the plural design of the matrix.

In some embodiments, when generating a QC-LDPC code with a plurality of codebooks embedded therein, the process 1100 may involve the processor 1010 generating various shift value tables for each of the first set of lifting factors Lifting factor. Moreover, the process 1100 may involve the processor 1010 optimizing the first set of lifting factors to generate a second set of lifting factors. The number of lifting factors of the first set may be greater than the number of lifting factors of the second set. The first lifting factor may share the corresponding shift value table of the second lifting factor, where the first lifting factor is in the first set but not in the second set, and the second lifting factor is in both the first set and the second set. The value of the second lifting factor may be smaller than the value of the first lifting factor, and the second lifting factor is closer to the first lifting factor than other lifting factors in the first set.

In some embodiments, when selecting a codebook from a plurality of codebooks, the process 1100 may involve the processor 1010 selecting from a plurality of codebooks based on the initial code rate used to transmit the data and/or the code block size of the data Codebook.

In some embodiments, when selecting a codebook from a plurality of codebooks, the process 1100 may involve the processor 1010 performing a plurality of operations (eg, similar to those involved in the logic flow 200). For example, the process 1100 may involve the processor 1010 determining whether the code block size of the material is less than the threshold code block size. In response to the code block size of the data being less than the threshold code block size, the process 1100 may involve the processor 1010 selecting the third codebook among the plurality of codebooks. In response to the code block size of the data being not less than the threshold code block size, the process 1100 may involve the processor 1010 determining whether the initial code rate used to transmit the data is greater than the threshold code rate. In response to the initial code rate not being greater than the threshold code rate, the process 1100 may involve the processor 1010 selecting the second codebook among the plurality of codebooks. In response to the initial code rate being greater than the threshold code rate, the process 1100 may involve the processor 1010 selecting the first codebook among the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.

Alternatively or additionally, when selecting a codebook from a plurality of codebooks, the process 1100 may involve the processor 1010 performing a plurality of operations. For example, the process 1100 may involve the processor 1010 Determine the code block size of the data. Based on the determined result, in response to determining that the code block size is greater than the first threshold code block size, the process 1100 may involve the processor 1010 selecting the first codebook among the plurality of codebooks. Moreover, in response to determining that the code block size is greater than the second threshold code block size, the process 1100 may involve the processor 1010 selecting the second codebook among the plurality of codebooks. Moreover, in response to determining that the code block size is greater than the third threshold code block size, the process 1100 may involve the processor 1010 selecting a third codebook among the plurality of codebooks. The first threshold code block size may be larger than the second threshold code block size. The second threshold code block size may be larger than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.

FIG. 12 shows an exemplary process 1200 based on an embodiment of the present invention. Process 1200 may represent aspects of implementing the proposed concepts and solutions, which may be described, for example, with respect to some or all of Figures 1-10. Moreover, the process 1200 can represent aspects of the proposed concepts and solutions related to hybrid orthogonal LDPC layer design and very low bit rate QC-LDPC support. Process 1200 may include one or more operations, actions, and functions shown in one or more blocks of blocks 1210, 1220, and 1230. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1200 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 1200 may be performed in the order shown in FIG. 12, or in a different order. Process 1200 may be implemented by communication system 1000 and any variations thereof. For example, the process 1200 may be implemented in or by the first device 1005 and/or the second device 1050. For illustrative purposes only and not limited to scope, the process 1200 is described in the context of the first device 1005 as follows. Process 1200 may begin at block 1210.

At 1210, the process 1200 may involve the processor 1010 of the first device 1005 generating a QC-LDPC code, the QC-LDPC code including at least a quasi-row orthogonal layer. Process 1200 can be performed from 1210 to 1220.

At 1220, process 1200 may involve processor 1010 encoding using QC-LDPC codes data. Process 1200 can be performed from 1220 to 1230.

At 1230, the process 1200 may involve the processor 1010 sending the encoded material via the transceiver 1030 (to the second device 1050).

In some embodiments, at least one quasi-column orthogonal layer may include a plurality of rows and a plurality of columns of bits. One or the plurality of rows of the at least one quasi-column orthogonal layer may include at least one punctured row having a degree of 2 or more. The remaining rows of the plurality of rows of the at least one quasi-column orthogonal layer may include non-punched rows with a degree of 1 or 0.

In some embodiments, there may be no cycles in the perforated row.

In some embodiments, the QC-LDPC code may include a hybrid orthogonality design of a plurality of parts with different degrees of orthogonality. The first part of the plural parts of low degree orthogonality may correspond to a high code rate, and the second part of the plural parts of high degree orthogonality may correspond to a low code rate.

In some embodiments, the plural portions of different degrees of orthogonality include the following: (1) a non-column orthogonal portion, including plural columns and plural rows, the plural columns and the plural rows forming at least one A non-column orthogonal layer; (2) a quasi-column orthogonal portion, including a plurality of columns and a plurality of rows, the plurality of columns and the plurality of rows forming at least a quasi-column orthogonal layer; and (3) a pure column The orthogonal layer includes a plurality of columns and a plurality of rows, and the plurality of columns and the plurality of rows form at least one pure column orthogonal layer. Here, the plurality of rows of the non-column orthogonal portion may include at least one punctured row with a degree of 2 or more and a non-punched row with a degree of 1 or 0. One or more rows of the plurality of rows of the quasi-column orthogonal part may include at least one punctured row of degree 2 or higher. The remaining rows of the plural rows of the quasi-column orthogonal part may include non-punched rows with a degree of 1 or 0. Each row of the plurality of rows of the pure column orthogonal part may include a row with a degree of 1 or 0.

In some embodiments, the QC-LDPC code may include a parity matrix of a plurality of parity bits, and an information matrix of a plurality of information bits. One or a plurality of rows (row) through the information matrix and the parity matrix may include one or a plurality of rows with a bit degree of 2 per column.

In some embodiments, one of the plural bits with a degree of 2 or each of the plural columns with a degree of 2 may include the previously used parity bits or the previously transmitted information bits .

FIG. 13 shows an exemplary process 1300 based on an embodiment of the present application. Process 1300 may represent aspects of implementing the proposed concepts and solutions, such as those described with respect to some or all of Figures 1-10. More specifically, the process 1300 may represent aspects of the proposed concepts and schemes related to core matrix design. Process 1300 may include one or more operations, actions, and functions shown in one or more blocks of blocks 1310, 1320, and 1330. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1200 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 1300 may be executed in the order shown in FIG. 13 or in a different order. Process 1300 may be implemented by communication system 1000 and any variations thereof. For example, the process 1300 may be implemented in or by the first device 1005 and/or the second device 1050. For illustrative purposes only and not limited to scope, the process 1300 is described in the context of the first device 1005 as follows. Process 1300 may begin at block 1310.

At 1310, the process 1300 may involve the processor 1010 of the first device 1005 generating a QC-LDPC code, the QC-LDPC code including a basic matrix, a portion of which forms a core matrix corresponding to a code rate of at least a threshold. Process 1300 can be performed from 1310 to 1320.

At 1320, process 1300 may involve processor 1010 encoding the material using QC-LDPC codes. Process 1300 can be performed from 1320 to 1330.

At 1330, the process 1300 may involve the processor 1010 sending the encoded material via the transceiver 1030 (to the second device 1050).

In some embodiments, the code rate may be 0.89.

In some embodiments, the core matrix may include a plurality of rows and a plurality of columns of bits, and two or more of the plurality of rows may include punctured rows having a specific bit pattern.

In some embodiments, after any number of row permutations and/or column permutations (eg, at least one row permutation, at least one column permutation, or any combination of the two), in the plurality of perforated rows The specific bit pattern may include: one in a plurality of punching rows or a plurality of bits 0. After row replacement and/or column replacement, two examples of specific patterns including one or a plurality of bits 0 are shown in part (A) of FIG. 7. In some embodiments, the specific bit pattern in the punched row may include an isosceles right-angled triangle of bit 0, and the right angle of the triangle corresponds to bit 0 at the upper left corner of the punched row. An example of bit 0 of such an isosceles right triangle is shown in part (B) of FIG. 7.

In some embodiments, the core matrix may include a parity matrix of bits in rows and columns. The core matrix may also include an information matrix of a plurality of rows and a plurality of columns of bits. The parity matrix may include a matrix having a Wi-Fi style. In addition to the punctured rows of the core matrix, more than one row of the information matrix may include rows with high-density bit 1 and no or only one bit 0. The high-density bit row can correspond to a Wi-Fi style row.

In some embodiments, the bits of the bottom column of the plurality of columns may include the first number of bits 1. The first number may be equal to the number of puncturing rows, or larger than the number of puncturing rows by 0, 1, 2, or 3 (eg, larger). In some embodiments, a portion of the first number of bit 1 in the bottom column may correspond to the punctured row and the rightmost row of the core matrix, where the rightmost row of the core matrix is on Wi-Fi The right side of the style.

In some embodiments, the core matrix may include 5 columns of bits and 20 rows of bits. The degree of the 20-bit variable node can include one of the following: [2,2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3],[2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[ 2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3], and [2,2,3,3 ,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]. The degree of the 5-column bit check node can include one of the following: [13,10,14,17,2],[13,10,13,17,2],[13,10,13,18,3 ],[13,11,13,18,2],[13,10,14,18,2],[13,10,13, 19,2],[14,10,13,18,1],[13,11,13,18,1],[13,10,14,18,1],[13,11,13,19, 1], [13,10,13,18,2], and [13,10,13,18,1].

Figure 14 shows an exemplary process 1400 based on an embodiment of the invention. Process 1400 can represent aspects of implementing the proposed concepts and solutions, which can be described, for example, with respect to FIG. 9. More specifically, the process 1400 may represent aspects of the proposed concepts and schemes related to shift coefficient design. Process 1400 may include one or more operations, actions, or functions shown in one or more blocks of blocks 1410, 1420, and 1430. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1400 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 1400 may be executed in the order shown in FIG. 14 or in a different order. Process 1400 may be implemented by communication system 1000 and any variations thereof. For example, the process 1400 may be implemented in or by the first device 1005 and/or the second device 1050. For illustrative purposes only and not limited to scope, the process 1400 is described in the context of the first device 1005 as follows. Process 1400 may begin at block 1410.

At 1410, the process 1400 may involve the processor 1010 of the first device 1005 generating a QC-LDPC code. Process 1400 can be performed from 1410 to 1420.

At 1420, process 1400 may involve processor 1010 encoding the material using QC-LDPC codes. Process 1400 can be performed from 1420 to 1430.

At 1430, the process 1400 may involve the processor 1010 sending the encoded material via the transceiver 1030 (eg, to the second device 1050).

In generating the QC-LDPC code, the process 1400 may involve the processor 1010 performing a plurality of operations represented by sub-blocks 1412-1414.

In 1412, process 1400 may involve processor 1010 generating a corresponding shift value table for each lifting factor in the first set of lifting factors. Process 1400 can be performed from 1412 to 1414.

In 1414, the process 1400 may involve the processor 1010 optimizing the first set promotion Factor to generate a second set of boost factors.

The number of lifting factors in the first set may be greater than the number of lifting factors in the second set. The first lifting factor may share the corresponding shift value table of the second lifting factor, where the first lifting factor is in the first set but not in the second set, and the second lifting factor is in the first set and the second set. The value of the second lifting factor may be smaller than the value of the first lifting factor and closer to the first lifting factor than other lifting factors in the first set.

FIG. 24 shows an exemplary process 2400 of wireless communication based on an embodiment of the present invention. Process 2400 can represent aspects of implementing the proposed concepts and solutions, which can be described, for example, with respect to some or all of Figures 1-10, and 15A-23. More specifically, the process 2400 may represent aspects of the proposed concepts and schemes related to the design of the shift coefficient table of QC-LDPC codes used for large code block sizes in mobile communications. Process 2400 may include one or more operations, actions, and functions shown in one or more of blocks 2410 and 2420 and sub-blocks 24202, 24204, 24206, 24208, 24210, and 24212. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 2400 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 2400 may be executed in the order shown in FIG. 24, or in a different order. Process 2400 may be implemented by communication system 1000 and any variations thereof. For example, the process 2400 may be implemented in or by the first device 1005 and/or the second device 1050. For illustrative purposes only and not limited to scope, the process 1400 is described in the context of the first device 1005 as follows, but can also be applied to the device 1050. Process 2400 may begin at block 2410.

At 2410, the process 2400 may involve the processor 1010 of the first device 1005 establishing a wireless communication link with at least one other device (eg, the second device 1050) via the transceiver 1030 of the device 1005. Process 2400 can be performed from 2410 to 2420.

At 2420, the process 2400 may involve the processor 1010 passing through the transceiver 1030 The wireless communication link communicates wirelessly with other devices. In wireless communication with other devices, the process 2400 may involve the processor 1010 performing a plurality of operations represented by 24202, 24204, 24206, 24208, 24210, and 24212.

At 24202, the process 2400 may involve the processor 1010 selecting the first shift coefficient table from the plurality of shift coefficient tables. Process 2400 can be performed from 24202 to 24204.

At 24204, process 2400 can involve processor 1010 using at least a portion of the first shift coefficient table and the basic matrix to generate a QC-LDPC code. Process 2400 can be performed from 24204 to 24206.

At 24206, the process 2400 may involve the processor 1010 selecting a codebook from the plurality of codebooks embedded in the QC-LDPC code. Process 2400 can be performed from 24206 to 24208.

At 24208, the process 2400 may involve the processor 1010 storing the selected codebook to memory associated with the processor. Process 2400 can be performed from 24208 to 24210.

At 24210, process 2400 may involve processor 1010 encoding the data using the selected codebook to generate a plurality of modulation symbols for the data. Process 2400 can be performed from 24210 to 24212.

At 24212, the process 2400 may involve the processor 1010 controlling the transceiver 1030 to multiplex, convert, filter, amplify the modulation symbol, and radiate the modulation symbol through one or more threads 1036 of the first device 1005 as electromagnetic waves to pass through the wireless communication chain Way to send the modulation symbol of the data to other devices.

In some embodiments, the first shift coefficient table may include a basic shift coefficient table arranged in 4 columns and 26 rows in the following form:

In some embodiments, the first shift coefficient table may include The shift coefficient table shown in FIG. 18B.

In some embodiments, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 5 (a=5) and the lifting factor 320. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 7 (a=7) and the lifting factor 224. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 15 (a=15) and the lifting factor 240. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 9 (a=9) and the lifting factor 288. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 11 (a=11) and the lifting factor 352. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 3 (a=3) and the lifting factor 384. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 13 (a=13) and the lifting factor 208. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having the original element 2 (a=2) and the lifting factor 256.

In some implementations, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the process 2400 may involve the processor 1010 selecting the first block for a relatively large code block size according to one or more rules A shift coefficient table, wherein the one or more rules are related to either or both of the code block size and the code rate of the data.

In some embodiments, when generating QC-LDPC codes using at least a portion of the first shift coefficient table and the basic matrix, the process 2400 may involve the processor 1010 using the full portion of the first shift coefficient table and the basic matrix Generate QC-LDPC codes.

In some embodiments, when generating QC-LDPC codes using at least a portion of the first shift coefficient table and the basic matrix, the process 2400 may involve the processor 1010 using a partial portion of the first shift coefficient table and the basic matrix Generate QC-LDPC codes.

In some embodiments, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the process 2400 may involve the processor 1010 selecting the second shift coefficient table, the second shift coefficient The modulo result of the values in the table for one or more lifting factors is the same as the modulo result in at least the first shift coefficient table.

In some embodiments, when generating QC-LDPC codes using at least a portion of the first shift coefficient table and the basic matrix, the process 2400 may involve the processor 1010 using the full portion of the second shift coefficient table and the basic matrix Generate QC-LDPC codes.

In some embodiments, when generating QC-LDPC codes using at least a portion of the first shift coefficient table and the basic matrix, the process 2400 may involve the processor 1010 using a partial portion of the second shift coefficient table and the basic matrix Generate QC-LDPC codes.

In some embodiments, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the processor 2400 may involve the processor 1010 to perform the plurality of operations. For example, the processor 2400 may involve the processor 1010 to determine whether the code block size is less than or equal to the threshold code block size. In addition, the process 2400 may involve the processor 1010 determining whether the code rate is less than or equal to the threshold code rate. Also, the process 2400 may involve the processor 1010 selecting a first shift coefficient table corresponding to the base chart BG1 in response to determining that the code block size is greater than the threshold code block size or in response to determining that the code rate is greater than the threshold code rate. Alternatively, the process 2400 may involve the processor 1010 responding to determining that the code block size is less than or equal to the threshold code block size or responding to determining that the code rate is less than or equal to the threshold code rate, selecting the first shift coefficient table corresponding to the base chart BG2.

In some embodiments, each of the plurality of codebooks may correspond to a corresponding HARQ thread among the plurality of HARQ threads, where the plurality of HARQ threads are different from each other.

In some embodiments, when selecting a codebook from a plurality of codebooks, the process 2400 may involve the processor 1010 performing a plurality of operations. For example, the process 2400 may involve the processor 1010 performing a plurality of operations. For example, the process 2400 may involve the processor 1010 determining whether the code block size of the material is less than the threshold code block size. In addition, the process 2400 may involve the processor 1010 responding to the code block size of the data being smaller than the threshold code block size, selecting the third codebook among the plurality of codebooks. Moreover, in response to The code block size of the data is not less than the threshold code block size, and the process 2400 may involve the processor 1010 determining whether the initial code rate for transmitting the data is greater than the threshold code rate. Moreover, in response to the initial code rate not being greater than the threshold code rate, the process 2400 may involve the processor 1010 selecting the second codebook among the plurality of codebooks. Moreover, in response to the initial code rate being greater than the threshold code rate, the process 2400 may involve the processor 1010 selecting the first codebook among the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

In some embodiments, when selecting a codebook from a plurality of codebooks, the process 2400 may involve the processor 1010 performing a plurality of operations. For example, the process 2400 may involve the processor 1010 determining the code block size of the material. In addition, the process 2400 may involve the processor 1010 selecting a codebook by: (1) in response to determining that the code block size is greater than the first threshold code block size, selecting the first codebook among the plurality of codebooks; (2) responding to the determination The code block size is greater than the second threshold code block size, select the second codebook in the plurality of codebooks; (3) In response to determining that the code block size is greater than the third threshold code block size, select the third code in the plurality of codebooks this. The first threshold code block size may be larger than the second threshold code block size. The second threshold code block size may be larger than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

Additional information

The subject matter described herein sometimes shows different elements contained within or connected to other different elements. It should be understood that the architecture depicted in this way is only an example, and in fact many other architectures can be implemented to achieve the same function. In a conceptual sense, any component arrangement that achieves the same function is effectively "associated" so that the desired function is achieved. Therefore, any two elements combined here to achieve a specific function may be considered to be “associated” with each other, so that the desired function is achieved regardless of the architecture or intermediate components. Likewise, any two elements so associated can also be considered "operably connected" or "operably coupled" to each other to achieve the desired function, and any two elements that can be so associated can also be considered " Operably coupleable" to achieve the required work can. Specific examples of operably couplable include, but are not limited to, physically pairable and/or physically interacting elements and/or wirelessly interactable and/or wirelessly interacting elements and/or logically interacting and/or logically Interactive components.

In addition, with regard to the use of any plural and/or singular terms herein, those with ordinary knowledge in the art may convert from plural to singular and/or from singular to plural according to the context and/or application. For clarity, various singular/plural permutations can be clearly stated here.

In addition, those of ordinary skill in the art will understand that, in general, the terms used herein, especially the terms used in the scope of the attached patent application, such as the subject of the scope of the attached patent application, are generally intended to be "open" Terms, for example, the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "at least having", the term "comprising" should be interpreted as "including but not limited to", and so on. Those with ordinary knowledge in the field should further understand that if the intention requires a certain number of patent application records, this intention should be clearly recorded in the patent application scope, and if there is no such record, there is no such intention. For example, as an aid to understanding, the following appended patent application scope may include the use of introductory words "at least one" and "one or more" to introduce a description of the patent application scope. However, the use of these words should not be interpreted as the application of the patent scope record introduced by the indefinite article "a" or "an" defines any implementation of the scope of any specific patent application that includes the record of the patent application that is incorporated. Such records, even when the same patent application includes the introductory words "one or more" or "at least one", and unqualified articles such as "a" or "an", such as "a" and/or "an" , Should be interpreted to mean "at least one" or "one or more"; the same applies to the use of the definite article used to introduce the scope of the patent application. In addition, even if the specific number of the patent application scopes introduced is explicitly stated, those with ordinary knowledge in the field will recognize that such records should be interpreted as representing at least the number of records, for example, only "two records" There is no other modifier, which means at least two records, or two or more records. In addition, when using at least one similar to "A, B, and C" In the case of such conventions, usually this construction is intended in the sense that a person with ordinary knowledge in the field will understand the conventions, for example, "a system with at least one of A, B, and C" will include but is not limited to only having A, only B, only C, A and B together, A and C together, B and C together system, and/or A, B and C together system, etc. In those cases where a convention similar to at least one of "A, B, or C", etc. is used, generally this structure is intended in a sense that a person with ordinary knowledge in the field will understand the convention, for example, "have A, "A system of at least one of B or C" will include, but is not limited to, systems with only A, only B, and only C, systems with A and B together, systems with A and C together, systems with B and C together, And/or A, B and C together. Those with ordinary knowledge in the field will further understand that in fact, no matter in the embodiment, the scope of patent application or the drawings, any separated words and/or terms that represent two or more replacement conditions should be understood to include a plurality of One of the conditions, the possibility of either one condition or two conditions. For example, the phrase "A or B" will be understood to include the possibility of "A" or "B" or "A and B".

From the above, it can be understood that, for illustrative purposes, various embodiments disclosed in the present application have been described herein, and various modifications can be made without departing from the scope and spirit of the present application. Therefore, the various embodiments disclosed herein are not meant to be limiting, and the true scope and spirit are determined by the scope of the attached patent application.

100: basic matrix

I1: The first part of the information matrix

I2: The second part of the information matrix

I3: The third part of the information matrix

Claims (13)

A wireless communication method includes: a processor of a device establishes a wireless communication link with at least one other device via a transceiver of the device; and the processor wirelessly communicates with the other device via the wireless communication link as follows : Select the first shift coefficient table from the plural shift coefficient tables; use the basic matrix and at least a part of the first shift coefficient table to generate a quasi-loop low density parity check (QC-LDPC) code; from embedding to Selecting a codebook among a plurality of codebooks in the QC-LDPC code; storing the selected codebook to a memory related to the processor; encoding the data using the selected codebook to generate the data A plurality of modulation symbols; and control the transceiver to multiplex, convert, filter, amplify the modulation symbols and radiate the modulation symbols through one or more antennas of the device as electromagnetic waves for transmission via a wireless communication link The modulation symbol of the data to the other device, wherein the selection of the first shift coefficient table from the plurality of shift coefficient tables includes: according to any one of the code block size of the data and the code rate of the data or Two related one or more rules select the first shift coefficient table. The method according to item 1 of the patent application scope, wherein the first shift coefficient table includes: a basic shift coefficient table arranged in 4 columns and 26 rows in the following pattern:

The method according to item 1 of the patent application scope, wherein the first shift coefficient table includes part A and part B; wherein the part A is as follows:

Among them, the part B is as follows:

Wherein, the right side of the part A is connected to the left side of the part B. The method according to item 1 of the patent application scope, wherein the first shift coefficient table includes a shift coefficient table corresponding to the basic chart 1 (BG1) having the original element 5 and the lifting factor 320; or, The first shift coefficient table includes a shift coefficient table corresponding to the basic chart 1 (BG1) having the original element 7 and the lifting factor 224; or, the first shift coefficient table includes a shift coefficient table corresponding to the original element 15 and the lifting factor The shift coefficient table of the basic chart 1 (BG1) of 240; or, the first shift coefficient table includes a shift coefficient table corresponding to the basic chart 1 (BG1) having the original element 9 and the lifting factor 288; or, The first shift coefficient table includes a shift coefficient table corresponding to the basic chart 1 (BG1) having the original element 11 and the lifting factor 352; Alternatively, the first shift coefficient table includes a shift coefficient table corresponding to the basic chart 1 (BG1) with the original element 3 and the lifting factor 384; or, the first shift coefficient table includes a corresponding shift table with the original element 13 and the shift coefficient table of the basic chart 1 (BG1) of the lifting factor 208; or, the first shift coefficient table includes the shift coefficient corresponding to the basic chart 1 (BG1) having the original element 2 and the lifting factor 256 table. The method according to item 1 of the patent application scope, wherein the generating the QC-LDPC code using the basic matrix and at least a part of the first shift coefficient table includes using all the sums of the first shift coefficient table The basic matrix generates the QC-LDPC code. The method according to item 1 of the patent application scope, wherein the generating the QC-LDPC code using the basic matrix and at least a part of the first shift coefficient table includes: using a part of the first shift coefficient table and all The basic matrix generates the QC-LDPC code. The method according to item 1 of the patent application scope, wherein the selecting the first shift coefficient table from the plurality of shift coefficient tables includes selecting a second shift coefficient table, the second shift coefficient table The result of modulo one or more lifting factors by the value of is the same as the result of modulo in the first shift coefficient table. The method according to item 7 of the patent application scope, wherein generating the QC-LDPC code using the basic matrix and at least a part of the first shift coefficient table includes using all of the second shift coefficient table and the basic The matrix generates the QC-LDPC code. The method according to item 7 of the patent application scope, wherein generating the QC-LDPC code using the basic matrix and at least a part of the first shift coefficient table includes using a part of the second shift coefficient table and the basic The matrix generates the QC-LDPC code. The method according to item 1 of the patent application scope, wherein selecting the first shift coefficient table from the plurality of shift coefficient tables includes: Determining whether the code block size is less than or equal to a threshold code block size; and determining whether the code rate is less than or equal to a threshold code rate. The method of claim 10, wherein selecting the first shift coefficient table from the plurality of shift coefficient tables further comprises: in response to determining that the code block size is greater than the threshold code block size or in response to the determination code If the rate is greater than the threshold code rate, select the first shift coefficient table corresponding to Basic Chart 1 (BG1). The method of claim 10, wherein selecting the first shift coefficient table from the plurality of shift coefficient tables further includes: in response to determining that the code block size is less than or equal to the threshold code block size or in response to Determine that the code rate is less than or equal to the threshold code rate, and select the first shift coefficient table corresponding to the basic chart 2 (BG2). The method according to item 1 of the patent application scope, wherein each of the plurality of codebooks corresponds to a corresponding HARQ thread in a plurality of hybrid automatic repeat request (HARQ) threads, wherein the plurality of HARQ threads are different from each other.

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