TW201907671A - Shift coefficient table design for QC-LDPC codes for large block size in mobile communication - Google Patents

Abstract

A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Description

Design of shift coefficient table for QC-LDPC codes for large code block sizes in mobile communications

The present invention relates generally to mobile communications, and in particular, to a shift coefficient table for quasi-cyclic low-density parity-check (QC-LDPC) codes used in mobile communications for larger code block sizes. design.

Unless otherwise stated in this article, the methods described in this section are not prior art to the claims listed below, and should not be considered as prior art by inclusion in this section.

The 3rd Generation Partnership Project (3GPP) has approved plans to accelerate the development of 5th Generation (5G) new radio (NR) specifications, so it is expected that standards-based 5G NR wireless communication services may be launched in the near future. 3GPP also agreed that QC-LDPC will be used for the 5G NR data channel. However, details on how QC-LDPC-based encoding (eg, encoding and decoding) can be implemented have not been defined.

The following overview is illustrative only and is not intended to be limiting in any way. That is, the following overview is provided to introduce the concepts, gist, benefits, and advantages of the novel and non-obvious technologies described herein. The selection implementation is further described in the detailed description below. Therefore, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

In one aspect, a method of wireless communication may involve a processor of a device establishing a wireless communication link with at least one other device via a transceiver of the device. The method may also involve the processor performing wireless communication with other devices via the wireless communication link by: (a) selecting a first shift coefficient table from a plurality of shift coefficient tables; (b) using a basic matrix and a first At least a part of a shift coefficient table generates QC-LDPC codes; (c) selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; (d) storing the selected codebook to be relevant to the processor (E) encode the data using the selected codebook to generate a plurality of modulation symbols for the data; and (f) control the transceiver to multiplex, convert, filter, amplify, and pass the modulation symbols of the device One or more antennas radiate the modulation symbols as electromagnetic waves, so as to transmit the modulation symbols of the data to the other devices via a wireless communication link. When the first shift coefficient table is selected from the plurality of shift coefficient tables, the method further involves the processor according to one or a plurality of rules related to any one or two of the code block size and the code rate of the data. , Selecting the first shift coefficient table for a relatively large code block size.

It is worth noting that although the descriptions of the proposed schemes and various examples are provided below in the context of 5G NR wireless communications, according to other agreements, standards and specifications applicable to the implementation, the proposed concepts, schemes and any of them Variations / derivatives can be implemented in communication. Therefore, the scope of the proposed scheme is not limited to the description provided herein.

Detailed examples and implementations of the claimed subject matter are disclosed herein. It should be understood, however, that the disclosed embodiments and implementations are merely illustrative of the claimed subject matter and may be embodied in various forms. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that the description of this disclosure is thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In the following description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the embodiments and implementations presented.

Overview

The proposed concepts and solutions generally involve the following areas: multi-codebook embedded LDPC code design, mixed orthogonal LDPC layer design, extremely low code rate (CR) QC-LDPC support, kernel matrix design, and shift coefficients design. The areas of hybrid orthogonal LDPC layer design include new concepts and solutions for quasi-row orthogonal layer design and hybrid orthogonal layer design. A description of the proposed concepts and solutions is provided below with reference to FIGS. 1 to 9.

FIG. 1 illustrates an exemplary multi-codebook embedded LDPC code design according to an embodiment of the present invention. Referring to FIG. 1, a basic parity check matrix of a QC-LDPC code (interchangeably referred to herein as a “base matrix”) 100 according to the present invention may have a plurality of codebooks embedded therein.

As shown in FIG. 1, the basic matrix 100 may include a parity matrix of a plurality of parity bits and an information matrix of a plurality of information bits. In other words, the basic matrix 100 can be defined by a parity matrix and an information matrix, where the parity matrix has relatively few non-zero / non-empty bits (each represented by "1" in Figure 1) and most of the zero / empty bits Yuan (each represented by "0" in Figure 1). The parity matrix can also define a set of linear constraints on the code bits. Therefore, each of the plurality of codebooks embedded in the QC-LDPC code of the basic matrix 100 may include a parity matrix and a corresponding portion of a correspondingly sized information matrix, so that the sizes of the plurality of codebooks are different from each other. Therefore, regardless of the size, each codebook can constitute at least a part of the basic matrix. In the example shown in Figure 1, the codebook can be represented as follows: Codebook = (I1 or I2 or I3) + P

The mark "I1" represents the first part of the information matrix, the mark "I2" represents the second part of the information matrix, the mark "I3" represents the third part of the information matrix, and the mark "P" represents the parity matrix. Here, the size of I1 (for example, in terms of the number of bits and / or the size of the memory) is larger than the size of I2, and the size of I2 is larger than the size of I3.

The size of the obtained codebook can be changed according to the size of a part of the information matrix that forms the codebook together with the parity matrix. It is worth noting that although the embodiment shown in FIG. 1 describes three codebooks of different sizes due to the combination of I1 + P, I2 + P, and I3 + P, according to various embodiments of the present invention, different sizes The number of codebooks is not limited to three (may be less than three or more than three).

In some implementations, each of the plurality of codebooks may correspond to a corresponding HARQ thread in a plurality of hybrid automatic repeat request (HARQ) threads, where the plurality of HARQ threads are different from each other. For example, the first codebook may correspond to the first HARQ thread, and the value of the first codebook ranges from 0.33 to 0.89. The second codebook can correspond to a second HARQ thread, and the value of the second codebook ranges from 0.2 to 0.66. The third codebook may correspond to a third HARQ thread, and the third codebook has a small code block size of less than 400. Therefore, in the HARQ-based communication between two communication devices, each HARQ thread of the plurality of HARQ threads may be related to or corresponding to the corresponding codebook of the plurality of codebooks. Therefore, the HARQ thread currently used in HARQ-based communication can be identified. Correspondingly, a codebook among a plurality of codebooks may be selected, and a codebook in the plurality of codebooks corresponds to the identified HARQ thread for encoding the data for transmission.

In some embodiments, each codebook of the plurality of codebooks corresponds to one or more registers, one or more buffers, one or more caches, and / or one or more memory units. The corresponding memory size (Kb). For example, the first codebook may correspond to the first storage size Kb = 16. The second codebook may correspond to the second storage size Kb = 12. The third codebook may correspond to the third storage size Kb = 5. In the solution proposed according to the present invention, if a large codebook corresponding to a large memory size (for example, because the code block size of the material to be encoded is relatively large, or because the initial code rate is relatively high) is not suitable for encoding It is necessary to select a small codebook corresponding to a small storage size for encoding. Therefore, it is possible to avoid using a storage space larger than required (because a codebook larger than required is being selected), thereby shortening the processing delay of the encoding.

In some implementations, all codebooks can share a basic matrix and use different zero-padding sizes. In some embodiments, different codebooks may correspond to different shift coefficient designs or share a single shift coefficient design.

In some implementations, which one of the plurality of codebooks will be selected based on the initial code rate used to transmit the data, the code block size of the data, or both. In some embodiments, if a large codebook corresponding to a large number of encoding processing delays is not necessary for encoding, in order to shorten the encoding processing delay in the communication device, the codebook is selected such that a small codebook requiring a small amount of encoding processing delay is encoded.

FIG. 2 illustrates an example logic flow 200 related to the design of a multi-codebook embedded LDPC code based on an embodiment of the present invention. The logic flow 200 may be implemented in or by an encoder or processor to implement various features and / or aspects of the concepts and / or solutions proposed by the present invention. More specifically, the logic flow 200 may involve selecting one or a plurality of rules used in a codebook from a plurality of codebooks embedded in a basic matrix of a QC-LDPC code, so that if the processing delay of the corresponding encoding is large, A large codebook is not necessary for encoding, and a small codebook with a small amount of processing delay to be encoded is selected for encoding. The logic flow 200 may include one or more operations, actions, or functions represented by one or more of the blocks 210, 220, 230, 240, and 250. Although shown as discrete blocks, depending on the desired implementation, the various blocks of the logic flow 200 can be divided into additional blocks, merged into fewer blocks, or deleted. The logic flow 200 may be implemented by each of the first device 1005 and the second device 1050 described below. For illustrative purposes only and not limited in scope, the description of the logic flow 200 is provided in the context of the second device 1050. The logic flow 200 may begin at 210.

At 210, the logic flow 200 may involve the second device 1050 determining whether a code block size of the material to be encoded is smaller than a threshold code block size. When it is determined that the code block size of the data is smaller than the threshold code block size, the logic flow 200 may be executed from 210 to 220. When it is determined that the code block size of the data is not less than the threshold code block size, the logic flow 200 may be executed from 210 to 230.

At 220, the logic flow 200 may involve the second device 1050 selecting a first codebook among the plurality of codebooks.

At 230, the logic flow 200 may involve the second device 1050 determining whether the initial code rate for transmitting data is greater than a threshold code rate. When it is determined that the initial code rate is not greater than the threshold code rate, the logic flow 200 may be executed from 230 to 240. In the case where it is determined that the initial code rate is greater than the threshold code rate, the logic flow 200 may be executed from 230 to 250.

At 240, the logic flow 200 may involve the second device 1050 selecting a second codebook among the plurality of codebooks.

At 250, the logic flow 200 may involve the second device 1050 selecting a third codebook among the plurality of codebooks.

Here, the size of the third codebook is larger than that of the second codebook. In addition, the size of the second codebook is larger than that of the first codebook. Therefore, if a large codebook corresponding to a large storage size (for example, a code block size larger than a threshold code block size or an initial code rate larger than a threshold code rate) is not necessary for encoding, the logic flow 200 will select a small code corresponding to a small storage size This reduces the amount of storage or storage size used to store the selected codebook. That is, the logic flow 200 can help reduce the processing delay of the encoding.

FIG. 3 illustrates an exemplary quasi-row orthogonal layer design 300 based on an embodiment of the present invention. Orthogonality is beneficial to the throughput efficiency of the LDPC decoder. In the LDPC code, several rows can be grouped together to form a layer, and the degree of each column in the layer can be 1 or 0 (that is, orthogonality). In this case, this layer is called a pure row orthogonal layer.

Referring to FIG. 3, in the quasi-column orthogonal layer design 300, several columns can be grouped together to form a quasi-row orthogonal layer, such as layer 1, layer 2, and layer shown in FIG. 3 3 and layer 4. In this example, in addition to one or more punctured columns, each column in each of the layers 1, 2, 3, and 4 can be a degree of 1 or 0 ( (Ie, orthogonality). In the example shown in part (A) of Figure 3, the two leftmost rows (column) are the punched rows. Each of the other columns in each of layers 1, 2, 3, and 4 is a degree 1 or 0 (that is, has one or zero non-null bits (1), and the other bits are zero / empty, represented by "0"). Advantageously, the quasi-column orthogonal layer design 300 provides orthogonality, helping to improve efficiency in decoder throughput.

Moreover, in the quasi-column orthogonal layer design 300, there are no circles in the perforated rows in the quasi-column orthogonal layer. In the example shown in part (B) of FIG. 3, according to the present invention, the corresponding layer is not considered to be a quasi-column orthogonal layer due to the presence of a ring in two perforated rows.

FIG. 4 is an exemplary hybrid orthogonal layer design 400 shown based on an embodiment of the present invention. In the hybrid orthogonal layer design 400, the QC-LDPC code may include a plurality of ports with different degrees of orthogonality. In the example shown in Figure 4, the darker blocks represent bit 1 and the lighter blocks represent bit 0. For example, the first part of the plurality of parts may be low degree orthogonal and may correspond to a high code rate. Similarly, the second part of the plurality of parts may be medium degree orthogonal and may correspond to a medium code rate. Similarly, the third part of the plurality of parts may be orthogonal in height and may correspond to a low bit rate.

In the example shown in Figure 4, the plural parts of different degrees of orthogonality include the following: (1) non-row orthogonal parts, which include plural rows and plural columns, the plural rows and plural numbers The columns form at least one non-row orthogonal layer corresponding to a relatively high code rate; (2) a quasi-column orthogonal portion including a plurality of rows and a plurality of columns, the plurality of rows and the plurality of columns Forming at least one quasi-column orthogonal layer corresponding to a medium code rate; (3) a pure-row orthogonal portion, which includes a plurality of rows and a plurality of columns, and the plurality of rows and the plurality of columns form a corresponding comparison Low bit rate of at least one pure column orthogonal layer. Here, each of a plurality of columns in a non-row orthogonal portion is a row having a degree of 2 or higher. In addition, one or more of the plurality of rows of the quasi-column orthogonal portion include perforated rows having a degree of 2 or higher. Moreover, the remaining rows of the plurality of rows of the quasi-column orthogonal portion may include non-punctured rows having a degree of 1 or 0. Moreover, each of the plurality of rows of the pure column orthogonal portion includes rows having a degree of 1 or 0.

FIG. 5 illustrates an example QC-LDPC code 500 supporting an extremely low code rate based on an embodiment of the present invention. Referring to FIG. 5, the QC-LDPC code 500 may include a parity matrix of a plurality of parity bits and an information matrix of a plurality of information bits. The information matrix may include bits of one or a plurality of rows with a bit degree of 2 in each column. Moreover, each of the bits of degree 2 in one or a plurality of row bits of degree 2 may be a previously used parity bit or a previously transmitted information bit. Moreover, for very low bit rates, one or more previous transmissions can be retransmitted. Accordingly, an extended row can have a weight of 2. Check node splitting for rows with large weights.

FIG. 6 illustrates an example core matrix design 600 according to an embodiment of the invention. Please refer to FIG. 6. In the core matrix design 600, the QC-LDPC code may include a basic matrix, and a part of the basic matrix forms a core matrix corresponding to at least a threshold code rate. For example, in the example shown in Figure 6, the core matrix supports a code rate of 0.89.

FIG. 7 illustrates an example concept 700 of a core basic matrix according to an embodiment of the present invention. Please refer to FIG. 7, the core matrix may include a plurality of bits, a plurality of columns, and a plurality of rows. Among them, two or more rows are perforated rows, and the plurality of perforated rows have a specific Bit style (for example, one or more bits 0). In some embodiments, the specific bit pattern in the plurality of punched rows may include an isosceles right-angled triangle formed by the plurality of bit 0, and the right angle of the triangle corresponds to the upper left of the plurality of punched rows. Bit 0 in the corner.

The core matrix may include a parity matrix including a plurality of bits of a plurality of rows and a plurality of columns. The core matrix may also include an information matrix including a plurality of bits of a plurality of rows and a plurality of columns. The parity matrix may include a Wi-Fi-like matrix (for example, a Wi-Fi-like parity matrix). Moreover, the plurality of bits of more than one column of the information matrix may include bit 1 having a high density without or having a plurality of rows of one bit 0. The bits in the bottom column of the plurality of columns may include a first number of bits 1. The first number may be equal to the number of perforated rows or greater than the number of perforated rows.

In the example shown in part (A) of FIG. 7, the first few rows (for example, three columns) are composed of Wi-Fi-like parity matrices, and the information matrix has bit 1 of ultra-high density. In particular, if not all the bits included in each column in the information matrix are bit 1, most of them are bit 1, and do not have 0 or have 1 0. After any number of column permutations and / or row permutations (for example, at least one column permutation, at least one row permutation, or a combination thereof), the perforated row includes a specific pattern of one or more bits 0. The bottom row can have 3 or 4 edge blocks, and an edge block can correspond to a parity variable node (VN) block. Two edge blocks may correspond to two punched rows (for example, VN0 and VN1). Where there are four edge blocks, a fourth edge block can be added to increase the shortest distance.

In the example shown in part (B) of FIG. 7, an example pattern of a punch line is shown. For a basic matrix of size mxn (m columns by n rows), and assuming that p rows are perforated, use an isosceles right-angled triangle with bit 0 to build an mxp matrix whose right angles correspond to the plural Bit 0 at the top left corner of the hole row. The other bits in the punctured row can be randomly selected as 0 or 1. Since row and / or column replacement may be performed, the actual position of a particular pattern may be different from the upper left corner of the punched row.

FIG. 8 is an example concept 800 showing a core basic matrix based on another embodiment of the present invention. In Concept 800, the core basic matrix includes a Wi-Fi style (or a Wi-Fi-like parity matrix), a punctured column, and the rest of the information matrix. The remainder of the information matrix can be designed using one of a number of degree distributions. For example, the core matrix may include 5 row bits and 20 column bits. The 20-bit variable node (VN) degree can include one of the following: [2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], [2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3] , [2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], and [2, 2, 3 , 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3]. The test node (CN) degree of 5 rows can include one of the following: [13, 10, 14, 17, 2], [13, 10, 13, 17, 2], [13, 10, 13 18, 3], [13, 11, 13, 18, 2], [13, 10, 14, 18, 2], [13, 10, 13, 19, 2], [14, 10, 13, 18 , 1], [13, 11, 13, 18, 1], [13, 10, 14, 18, 1], [13, 11, 13, 19, 1], [13, 10, 13, 18, 2 ], And [13, 10, 13, 18, 1].

FIG. 9 shows a shift coefficient design 900 based on an embodiment of the present invention. For each lifting factor, there is a table of corresponding shift values. Tables in different boosting factors can be nested design. In the shift coefficient design 900, an effective set of boost factors may be defined for use in LDPC encoding. In the example shown in Figure 9, the effective set of boost factors includes: boost factors with different values: Z = 16, Z = 24, Z = 32, Z = 48, Z = 64, Z = 96, Z = 128, Z = 192, Z = 256 and Z = 384. In the shift coefficient design 900, the effective set of boost factors can be optimized to obtain an optimized set of boost factors. The number of boost factors in the optimized set is less than the number of boost factors in the effective set. The shift coefficient table of the optimized set can be used as the shift coefficient table that is closest to and less than or equal to the boost factor. For example, a table designed for shift values of the boosting factor Z = 32 may be shared by the boosting factor Z = 48. Similarly, tables designed for shift values of boost factor Z = 128 can be shared by boost factor Z = 192.

For the purpose of illustration and not limitation, in the LDPC codebook based on the present invention, Z is used Ҳ = {ax 2 ^j } a {9, 11, 13, 15}, j {0, 1, 2, 3, 4, 5}, the optimization set (Z) of the lifting factors can be defined as 4 groups. Use Z φ = {ax 2 ^j } a {9, 10, 11, 12, 13, 14, 15, 16}, j {0, 1, 2, 3, 4, 5}, the effective set of boost factors can be defined as 8 groups. The corresponding shift values can be represented by four shift coefficient tables, which represent the corresponding shift coefficients {288, 352, 416, 480}. For any lifting factor Z = ax 2 ^j in the effective set φ, the corresponding shift coefficient can be obtained by p _z ^{m, n} = (p ^{m, n} mod Ẑ) + f (Z), where p ^{m, n} is The shift coefficient of the (m, n) th element in the shift coefficient table of â x 2 ⁵ where â is the maximum value of {9, 11, 13, 15} and â is less than or equal to a, and Ẑ = â x 2 ^j . Moreover, f (Z) is a perturbation, a function of Z, and can be expressed using a table.

The use of boost factors allows encoding of packets of various sizes using a relatively small set of basic matrices and a relatively small set of boost factors. For example, the basic matrix size m x n can be used to encode packets of up to k = n-m information bits to obtain an encoded packet or codeword of n code bits. Using the lifting factor Z, the basic matrix can be lifted to generate a parity check matrix with an expanded dimension Z · m x Z · n. The extended parity check matrix can then be utilized to encode packets of up to Z · k information bits to obtain a codeword of Z · n code bits. Moreover, using a boost factor can also allow efficient parallel encoding and decoding, thereby improving performance, and reducing the description complexity for large-sized LDPC codes.

Design of shift coefficient table for larger code block sizes

For illustrative purposes, Figures 15 (A)-22 (B) illustrate a plurality of exemplary shift coefficient tables for relatively large code block sizes.

Each of FIGS. 15 (A) to 15 (B) is a schematic diagram of a part of an exemplary shift coefficient table 1500 based on an embodiment of the present invention. Specifically, the shift coefficient table 1500 is composed of part (A) in FIG. 15A and part (B) in FIG. 15B. Moreover, the shift coefficient table 1500 may correspond to a base chart 1 (BG1), which has a primitive element 7 (a = 7) and a boosting factor 224.

Each of FIGS. 16 (A) to 16 (B) is a schematic diagram of a part of an exemplary shift coefficient table 1600 based on an embodiment of the present invention. Specifically, the shift coefficient table 1600 is composed of part (A) in FIG. 16A and part (B) in FIG. 16B. Moreover, the shift coefficient table 1600 may correspond to BG1 having an original element 15 (a = 15) and a boosting factor 240.

Each of FIGS. 17 (A) to 17 (B) is a schematic diagram of a part of an exemplary shift coefficient table 1700 based on an embodiment of the present invention. Specifically, the shift coefficient table 1700 is composed of part (A) in FIG. 17A and part (B) in FIG. 17B. Moreover, the shift coefficient table 1700 may correspond to BG1 having an original element 9 (a = 9) and a boosting factor 288.

Each of FIGS. 18 (A) to 18 (B) is a schematic diagram of a portion of an exemplary shift coefficient table 1800 based on an embodiment of the present invention. Specifically, the shift coefficient table 1800 is composed of part (A) in FIG. 18A and part (B) in FIG. 18B. Moreover, the shift coefficient table 1800 may correspond to BG1 having an original element 5 (a = 5) and a boosting factor 320.

Each of FIGS. 19 (A) to 19 (B) is a schematic diagram of a part of an exemplary shift coefficient table 1900 based on an embodiment of the present invention. Specifically, the shift coefficient table 1900 is composed of part (A) in FIG. 19A and part (B) in FIG. 19B. Moreover, the shift coefficient table 1900 may correspond to BG1 having an original element 11 (a = 11) and a boosting factor 352.

Each of FIGS. 20 (A) to 20 (B) is a schematic diagram of a part of an exemplary shift coefficient table 2000 based on an embodiment of the present invention. Specifically, the shift coefficient table 2000 is composed of part (A) in FIG. 20A and part (B) in FIG. 20B. Moreover, the shift coefficient table 2000 may correspond to BG1 having an original element 3 (a = 3) and a boosting factor 384.

Each of FIGS. 21 (A) to 21 (B) is a schematic diagram of a part of an exemplary shift coefficient table 2100 based on an embodiment of the present invention. In particular, the shift coefficient table 2100 is composed of part (A) in FIG. 21A and part (B) in FIG. 21B. Moreover, the shift coefficient table 2100 may correspond to BG1 having an original element 13 (a = 13) and a boosting factor 208.

Each of FIGS. 22 (A) to 22 (B) is a schematic diagram of a part of an exemplary shift coefficient table 2200 based on an embodiment of the present invention. Specifically, the shift coefficient table 2200 is composed of part (A) in FIG. 22A and part (B) in FIG. 22B. Moreover, the shift coefficient table 2200 may correspond to BG1 having an original element 2 (a = 2) and a boost factor of 256.

FIG. 23 illustrates an exemplary logic flow 2300 related to selecting a shift coefficient table according to an embodiment of the present invention. The logic flow 2300 may be implemented in an encoder or a processor, or implemented by an encoder or a processor, to implement various features and / or aspects in the concepts and solutions proposed by the present invention. In particular, the logic flow 2300 may involve selecting one or a plurality of rules used in the shift coefficient table from the plurality of shift coefficient tables, so that a shift coefficient table suitable for data having a relatively large code block size is selected. Logic flow 2300 may include one or more operations, actions, or functions represented by one or more of blocks 2310, 2320, 2330, and 2340. Although shown as discrete blocks, depending on the desired implementation, the various blocks of the logic flow 2300 can be divided into additional blocks, merged into fewer blocks, or deleted. The logic flow 2300 may be implemented by each of the first device 1005 and the second device 1050 described below. For illustrative purposes only and not limited in scope, the description of the logic flow 2300 is provided in the context of the first device 1005. The logic flow 2300 may begin at 2310.

At 2310, the logic flow 2300 may involve the processor of the first device 1005 determining whether the code block size of the material to be encoded is less than or equal to a threshold code block size. When it is determined that the code block size of the data is less than or equal to the threshold code block size, the logic flow 2300 may be executed from 2310 to 2320. When the processor 1010 determines that the code block size of the data is larger than the threshold code block size, the logic flow 2300 may be executed from 2310 to 2330.

At 2320, the logic flow 2300 may involve the processor 1010 determining whether the code rate of the material to be encoded is less than or equal to a threshold code rate. When the processor 1010 determines that the bit rate of the data is less than or equal to the threshold bit rate, the logic flow 2300 may be executed from 2320 to 2340. Otherwise, the processor 1010 determines that the bit rate of the data is determined to be greater than the threshold bit rate, and the logic flow 2300 may be executed from 2320 to 2330.

At 2330, the logic flow 2300 may involve the processor 1010 selecting or otherwise using a shift coefficient table corresponding to the base chart 1 (BG1).

At 2340, the logic flow 2300 may involve the processor 1010 selecting or otherwise using a shift coefficient table corresponding to the basic graph 2 (BG2).

In the solution proposed based on the present invention, no matter which shift coefficient table is selected, part or all (whole) of the selected shift coefficient table may be used in encoding. Furthermore, the value of the shift coefficient table selected or otherwise used is modulo (mod) one or more boost factors and any shift shown in Figures 15 (A)-22 (B) The result of the modulus table is the same, both in part and in the whole.

Illustrative implementation

FIG. 10 illustrates an exemplary communication system 1000 according to an embodiment of the present invention. The communication system may include a first device 1005 and a second device 1050, and the first device 1005 and the second device 1050 may communicate with each other via a communication link. The communication link 1040 may be a wireless link in some embodiments. Alternatively, the communication link 1040 may be a wired link in some other implementations. In the environment of 5G NR communication, the communication link 1040 is a wireless communication link, for example, a multi-user multiple-input-and-multiple-output (MU-MIMO) communication link. Each of the first device 1005 and the second device 1050 may perform various functions as a communication device to implement the concepts, schemes, techniques, processes, and methods described herein with regard to QC-LDPC encoding, including with respect to FIG. 1- Part or all of FIG. 9 and those of the processes 1100, 1200, 1300, 1400 described below. More specifically, each of the first device 1005 and the second device 1050 can implement the proposed multi-codebook embedded LDPC code design, mixed orthogonal LDPC layer design, QC-LDPC support with extremely low bit rate, and basic Matrix design, core matrix design and shift coefficient design concepts and aspects of the solution.

Each of the first device 1005 and the second device 1050 may be part of an electronic device, which may be a communication device, a computing device, a portable or mobile device, or a wearable device. For example, the first device 1005 may be a Wi-Fi access point, a smart phone, a smart watch, a smart bracelet, a smart necklace, a personal digital assistant or such as a tablet, laptop, laptop, desktop computer or servo In computing devices such as processors. Similarly, the second device 1050 can be on a Wi-Fi mobile client or site, smartphone, smart watch, smart bracelet, smart necklace, personal digital assistant or such as a tablet, laptop, desktop computer or servo In computing devices such as processors. Alternatively, each of the first device 1005 and the second device 1050 may be implemented in the form of one or more integrated circuit (IC) chips, such as, but not limited to, one or more single-core processors, one or more A multi-core processor, or one or more complex-instruction-set-computing (CISC) processors.

Each of the first device 1005 and the second device 1050 may include at least a part of those elements shown in FIG. 10, respectively. For example, the first device 1005 may include at least a processor 1010, and the second device 1050 may include at least a processor 1060. In addition, the first device may include a memory 1020, a transceiver 1030, and one or more antennas (represented by antennas 1036). The transceiver 1030 is configured to wirelessly transmit and receive data (for example, following one or more 3GPP standards, protocols , Specifications, and / or any applicable wireless protocols and standards, such as 5G NR). Each of the memory 1020 and the transceiver 1030 may be communicatively or operatively coupled with the processor 1010. Similarly, the second device 1050 may also include a memory 1070, a transceiver 1080, and one or more antennas (represented by the antenna 1086). The transceiver 1080 is configured to send and receive data wirelessly (for example, following one or more 3GPP) Standards, protocols, specifications, and / or any applicable wireless protocols and standards, such as 5G NR). Each of the memory 1070 and the transceiver 1080 is communicatively or operatively coupled to the processor 1060. Each of the first device 1005 and the second device 1050 may further include other components (for example, a power system, a display device, and a user interface device) which are not related to the solution proposed by the present invention, so for simplicity and brevity, there is no It is shown in Fig. 10 and not described.

The transceiver 1030 may be configured to wirelessly communicate in a single frequency band or a plurality of frequency bands. The transceiver 1030 may include a transmitter 1032 capable of transmitting data wirelessly and a receiver 1034 capable of receiving data wirelessly. In some embodiments, the transceiver 1030 is capable of transmitting / modulating (via the transmitter 1032) and receiving / demodulating (via the receiver 1034) as orthogonal frequency-division multiplexed (OFDM) radiated through the antenna 1036 ) Information symbol. Similarly, the transceiver 1080 can be configured to wirelessly communicate in a single frequency band or a plurality of frequency bands. The transceiver 1080 may include data symbols capable of transmitting / modulating (via the transmitter 1082) and receiving / demodulating (via the receiver 1084) as OFDM symbols radiated through the antenna 1086.

Each of the memory 1020 and the memory 1070 may be a storage device configured to store one or more sets of codes, programs and / or instructions and / or information therein. In the example shown in FIG. 10, the memory 1020 stores therein one or more sets of processor-executable instructions 1022 and data 1024, and the memory 1070 stores therein one or more sets of processor-executable instructions 1072 and Information 1074. Each of the memory 1020 and the memory 1070 may be implemented by any suitable technique, and may include volatile memory and / or non-volatile memory. For example, each of the memory 1020 and the memory 1070 may include one type of random access memory (RAM), such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM), and / or Zero-capacitor RAM (Z-RAM). Alternatively or in addition, the memory 520 may include a read-only memory (ROM), such as a mask ROM, a programmable ROM (PROM), an erasable programmable ROM (EPROM), and / or an erasable Programmable ROM (erasable programmable ROM, EEPROM). Alternatively or additionally, each of the memory 1020 and the memory 1070 may include a type of non-volatile random-access memory (NVRAM), such as a flash memory, Solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), and / or phase-change memory.

In one aspect, each of the processors 1010 and 1060 may be implemented in the form of one or more single-core processors, one or more multi-core processors, or one or more CISC processors. That is, according to the present invention, even if the singular term "processor" is used herein to refer to each of the processor 1010 and the processor 1060, according to the present invention, each of the processor 1010 and the processor 1060 is implemented in some implementations. A plurality of processors may be included therein and a single processor may be included in other implementations. In another aspect, each of the processor 1010 and the processor 1060 may be implemented in the form of hardware (and optionally, firmware) with electronic components including, for example, but not limited to, one or more electrical components. Crystal, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors, and / or one or more varactors A varactor, which is configured and arranged according to the invention to achieve a specific purpose. In other words, in at least some embodiments, each of the processor 1010 and the processor 1060 is a special purpose processor that is specifically designed, arranged, and configured to perform a specific task. According to various embodiments of the present invention, the Specific tasks include the design of shift coefficient tables for QC-LDPC codes for larger code block sizes in mobile communications.

According to various embodiments of the present invention, the processor 1010 as a dedicated machine may include non-universal and specially designed hardware circuits that are designed, arranged, and configured to perform in mobile communications with QC for larger code block sizes. -Specific tasks related to the design of shift coefficient tables for LDPC codes. In one aspect, in accordance with various embodiments of the present invention, the processor 1010 may execute one or more sets of code, programs and / or instructions 1022 stored in the memory 1020 to perform various operations to render in mobile communications. Design of shift coefficient table for QC-LDPC codes with larger code block sizes. In another aspect, according to various embodiments of the present invention, the processor 1010 may include an encoder 1012 and a decoder 1014, and the encoder 1012 and the decoder 1014 perform specific tasks and functions together to render a QC-LDPC code. For example, the encoder 1012 may be configured to encode data according to various concepts and schemes of the present invention. Similarly, according to various concepts and solutions of the present invention, the decoder 1014 may be configured to decode data.

In some implementations, the processor 1010 may further include a memory 1016, which may include one or more registers, one or more buffers, and / or one or more cache memories. In some implementations, the processor 1016 may utilize the memory 1016 to store a basic matrix of the QC-LDPC code, a selected codebook, a boost factor, and / or one or a plurality of shift coefficient matrices. For example, the processor 1010 may generate a basic matrix and store it in the memory 1020, and when selecting a codebook from a plurality of codebooks embedded in the basic matrix, the processor 1010 may store the selected codebook in In memory 1016. Therefore, according to one or a plurality of rules of the logic flow 200, by selecting a codebook from a plurality of codebooks embedded in the basic matrix, the processing delay of encoding can be shortened. Therefore, by implementing various solutions according to the present invention (for example, by selecting a codebook from a plurality of codebooks embedded in a QC-LDPC code to encode data for transmission), not only the function of the processor 1010 is improved (for example, Shorter processing delays) and also improved underlying technologies for data encoding (for example, shorter processing delays and improved decoder throughput efficiency).

According to various embodiments of the present invention, the processor 1060 as a dedicated machine may include non-generic and specially designed hardware circuits that are designed, arranged, and configured to perform specific tasks related to QC-LDPC encoding. In one aspect, according to various embodiments of the present invention, the processor 1060 may execute one or more sets of codes, programs and / or instructions 1072 stored in the memory 1070 to perform various operations related to QC-LDPC encoding. In another aspect, according to various embodiments of the present invention, the processor 1060 may include an encoder 1062 and a decoder 1064 that perform specific tasks and functions to render QC-LDPC encoding. For example, the encoder 1062 may be configured to encode data according to various concepts and schemes of the present invention. Similarly, according to various concepts and solutions of the present invention, the decoder 1064 may be configured to decode data.

In some implementations, the processor 1060 may also include a memory 1066, which may include one or more registers, one or more buffers, and / or one or more cache memories. In some implementations, the processor 1060 may utilize the memory 1066 to store a basic matrix of the QC-LDPC code, a selected codebook, a boost factor, and / or a shift coefficient matrix. For example, the processor 1060 may generate a basic matrix and store it in the memory 1070, and when selecting a codebook from a plurality of codebooks embedded in the basic matrix, the processor 1060 may store the selected codebook in In memory 1066. Therefore, by selecting a codebook from a plurality of codebooks embedded in the basic matrix according to one or more rules of the logic flow 200, the processing delay of encoding can be shortened.

Each of the encoder 1012 and the encoder 1062 may be configured to have a plurality of electronic components that operate as a coding chain to perform a plurality of operations related to coding. For example, the encoding chain in each of the encoder 1012 and the encoder 1062 may be performed as follows: bit reordering, tone interleaving, mixed redundancy version (RV) design, Self-adjusting HARQ buffer, and code block grouping. Each of the decoder 1014 and the decoder 1064 may be configured to support various code rates of a codebook. The minimum code rate of the codebook supported by each of the decoder 1014 and the decoder 1064 may depend on the size of the corresponding boost factor. In the proposed scheme, an upper limit on the size of a log-likelihood ratio (LLR) memory can be set. The boost factor can be stored in LLR memory, and the size of the LLR memory can define or otherwise limit how large the boost factor size can be. Correspondingly, by setting the upper limit of the LLR memory size, the maximum size of the extended parity check matrix generated from the basic matrix can be set, thereby setting the memory size of the memory that needs to store the extended parity check matrix. Ceiling. In the first device 1005, by using one or more registers, one or more buffers, one or more cache memories, and / or in the processor 1010 (such as the memory 1016) or in the memory 1020 One or more memory units are used to implement LLR memory. In the second device 1050, by using one or more registers, one or more buffers, one or more cache memories, and / or in the processor 1060 (eg, the memory 1066) or in the memory 1070 One or more memory units to implement LLR memory.

In operation, for a forward link on the transmitting side, the encoder 1012 may receive a data packet from a data source, process the data by performing encoding, interleaving, and symbol mapping on the data, and provide modulation symbols for the encoded data. The transmitter 1032 may multiplex modulation symbols with pilot symbols, perform spatial processing, and provide one or a plurality of output symbol streams. The transmitter 1032 (which may include one or more transmitters) may condition one or more output symbol streams by performing digital-to-analog conversion, filtering, amplification, and up-conversion to generate one or more forward chains Signals, the one or more forward link signals passing through the antenna 1036 are radiated as electromagnetic waves. On the receiving (RX) side, the receiver 1084 (which may include one or a plurality of receivers) may receive one or a plurality of forward link signals as electromagnetic waves via one or a plurality of antennas of the antenna 1086. The receiver 1084 may also process the received signal by performing filtering, amplification, down conversion, and analog-to-digital conversion to obtain a plurality of samples. The receiver 1084 may also process a plurality of samples to obtain received symbols and perform multiple-input multiple-output (MIMO) detection on the received symbols to provide the detected symbols. The decoder 1064 may process the detected symbols by performing symbol demapping, deinterleaving, and decoding to provide decoded data to a sink.

Similarly, on the reverse link, the encoder 1062 can receive data packets from the data source and process the data through decoding, interleaving, and symbol mapping to provide modulation symbols for the encoded data. The transmitter 1082 may multiplex modulation symbols with pilot symbols, perform spatial processing, and provide one or more output symbol streams. The transmitter 1082 (which may include one or more transmitters) may condition one or more output symbol streams by performing digital-to-analog conversion, filtering, amplification, and up-conversion to generate one or more backlinks Signal, the one or more reverse link signals are radiated as electromagnetic waves through one or more antennas of the antenna 1086. On the receiving (RX) side, the receiver 1034 (which may include one or a plurality of receivers) may receive one or a plurality of reverse link signals as electromagnetic waves via one or a plurality of antennas of the antenna 1036. The receiver 1034 may process the received signal by performing filtering, amplification, down conversion, and analog-to-digital conversion to obtain a plurality of samples. The receiver 1034 may also process a plurality of samples to obtain the received symbols, and perform MIMO detection on the received symbols to provide the detected symbols. The decoder 1014 may process the detected symbols by performing symbol demapping, deinterleaving, and decoding to recover the data sent by the second device 1050.

The processor 1010 may be configured to control or otherwise direct the operation of the first device 1005. The processor 1060 may be configured to control or otherwise direct the operation of the first device 1050. According to the scheme and concept of the present application, the processor 1010 can determine the size of a packet to be transmitted and / or received, and, accordingly, respectively control the encoding by the encoder 1012 and the decoding by the decoder 1014. Similarly, according to the scheme and concept of the present application, the processor 1060 can determine the size of a packet to be transmitted and / or received, and correspondingly, control the encoding by the encoder 1062 and the decoding by the decoder 1064, respectively. For example, each of the processor 1010 and the processor 1060 may be configured to select a codebook from a plurality of codebooks embedded in a basic matrix of a QC-LDPC code for encoding, so that if corresponding to a large number of encoding processing delays A large codebook is not necessary for encoding, and a small codebook with a small amount of encoding processing delay needs to be selected for encoding.

Each of the first device 1005 and the second device 1050 may be configured to perform each of the processes 1100, 1200, 1300, 1400, and 2400 described below. Therefore, in order to avoid redundancy and for brevity, the operations of the first device 1005 and the second device 1050, and the operations of the processor 1010 and the processor 1060 are described in the environment of the following processes 1100, 1200, 1300, 1400, and 2400. It is worth noting that although the following description is provided in the environment of the first device 1005, the following description also applies to the second device 1050.

Regarding the design of the shift coefficient table for QC-LDPC codes for large code block sizes in mobile communications, the processor 1010 of the first device 1005 can establish a wireless communication link with the second device 1050 via the transceiver 1030 of the device 1005. The processor 1010 can wirelessly communicate with the second device 1050 via the wireless communication link of the transceiver 1030. In wireless communication with the second device 1050, the processor 1010 may perform a plurality of operations. For example, the processor 1010 may execute the following: (1) selecting a first shift coefficient table from a plurality of shift coefficient tables; (2) generating a QC-LDPC code using at least a part of the first shift coefficient table and a basic matrix; (3) Select the codebook from the plurality of codebooks embedded in the QC-LDPC code; (4) Store the selected codebook to the processor-related memory; (5) Use the selected codebook to encode the data to Generate a plurality of modulation symbols of the data; and (6) control the transceiver 1030 to multiplex, convert, filter, and amplify the modulation symbols, and radiate the modulation symbols as electromagnetic waves through one or more antennas 1036 of the first device for wireless communication The link sends a modulation symbol of the data to the second device 1050.

In some embodiments, the first shift coefficient table may include a basic shift coefficient table, which is arranged into 4 rows and 26 columns in the following style:

In some embodiments, the first shift coefficient table may include a shift coefficient table as shown in FIGS. 18A and 18B.

In some embodiments, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element of 5 (a = 5) and a boost factor of 320. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 7 (a = 7) and a boosting factor 224. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 15 (a = 15) and a boosting factor 240. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 9 (a = 9) and a boosting factor 288. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 11 (a = 11) and a boosting factor 352. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 3 (a = 3) and a boosting factor 384. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 13 (a = 13) and a boosting factor 208. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 2 (a = 2) and a boost factor of 256.

In some implementations, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the processor 1010 may be based on one or a complex number related to any one or both of the code block size and code rate of the data. As a rule, a first shift coefficient table is selected for a relatively large code block size.

In some embodiments, when using at least a part of the first shift coefficient table and the basic matrix to generate the QC-LDPC code, the processor 1010 may use the full portion of the first shift coefficient table and the basic matrix to generate the QC. -LDPC code.

In some embodiments, when using at least a part of the first shift coefficient table and a basic matrix to generate a QC-LDPC code, the processor 1010 may use a partial portion of the first shift coefficient table and a basic matrix to generate a QC. -LDPC code.

In some embodiments, when a first shift coefficient table is selected from a plurality of shift coefficient tables, the processor 1010 may select a second shift coefficient table, and the value of the second shift coefficient table is for one or a plurality of shift coefficient tables. The modulo of the lifting factor is the same as the modulo result of at least the first shift coefficient table.

In some embodiments, when using at least a part of the first shift coefficient table and the basic matrix to generate the QC-LDPC code, the processor 1010 may use the full portion of the second shift coefficient table and the basic matrix to generate the QC -LDPC code.

In some embodiments, when using at least a part of the first shift coefficient table and a basic matrix to generate a QC-LDPC code, the processor 1010 may use a partial portion of the second shift coefficient table and a basic matrix to generate a QC. -LDPC code.

In some embodiments, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the processor 1010 may perform a plurality of operations (eg, regarding the logic flow 2300). For example, the processor 1010 may determine whether a code block size is less than or equal to a threshold code block size. In addition, the processor 1010 may determine whether the code rate is less than or equal to a threshold code rate. Moreover, in response to determining that the code block size is greater than the threshold code block size or in response to determining that the code rate is greater than the threshold code rate, the processor 1010 may select a first shift coefficient table corresponding to the basic graph 1 (BG1). Alternatively, in response to determining that the code block size is less than or equal to the threshold code block size and in response to determining that the code rate is less than or equal to the threshold code rate, the processor 1010 may select a first shift corresponding to the basic graph 2 (BG2) Coefficient table.

In some embodiments, each codebook in the plurality of codebooks may correspond to a respective HARQ thread in the plurality of hybrid automatic repeat request HARQ threads, and the plurality of HARQ threads are different from each other.

In some embodiments, when selecting a codebook from a plurality of codebooks, the processor 1010 may perform a plurality of operations. For example, the processor 1010 may determine whether a code block size of the material is smaller than a threshold code block size. In addition, in response to the code block size of the data being smaller than the threshold code block size, the processor 1010 may select a third codebook among the plurality of codebooks. Moreover, in response to the code block size of the data being not less than the threshold code block size, the processor 1010 may determine whether the initial code rate used to transmit the data is greater than the threshold code rate. Moreover, in response to the initial code rate being not greater than the threshold code rate, the processor 1010 may select a second codebook among the plurality of codebooks. Moreover, in response to the initial code rate being greater than the threshold code rate, the processor 1010 may select a first codebook among the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

In some embodiments, when selecting a codebook from a plurality of codebooks, the processor 1010 may perform a plurality of operations. For example, the processor 1010 may determine a code block size of the material. In addition, the processor 1010 may select a codebook in the following ways: (1) in response to the determined code block size being larger than the first threshold code block size, selecting the first codebook among the plurality of codebooks; (2) in response to the determination The output code block size is larger than the second threshold code block size, and the second codebook in the plurality of codebooks is selected. (3) In response to the determined code block size being greater than the third threshold code block size, the plurality of codebooks are selected. Third codebook. The first threshold code block size may be larger than the second threshold code block size. The second threshold code block size may be larger than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

Illustrative process

FIG. 11 illustrates an exemplary process 1100 based on an embodiment of the present application. The process 1100 may represent aspects of implementing the proposed concepts and solutions, and the proposed concepts and solutions may be described, for example, with respect to some or all of FIGS. 1-10. In particular, the process 1100 may represent aspects of the proposed concepts and schemes related to QC-LDPC coding. Process 1100 may include one or more of the operations, actions, or functions shown in one or more of blocks 1110, 1120, 1130, and 1140. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1100 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks / sub-blocks of the process 1100 may be performed in the order shown in FIG. 11 or in a different order. Process 1100 may be implemented by communication system 1000 and any variations thereof. For example, the process 1100 may be implemented in the first device 1005 and / or the second device 1050, or performed by the first device 1005 and / or the second device 1050. For illustrative purposes only and not limited in scope, the process 1100 is described in the context of the first device 1005 as follows. Process 1100 may begin at block 1110.

At 1110, the process 1100 may involve the processor 1010 of the first device 1005 generating a QC-LDPC code, the QC-LDPC code having a plurality of codebooks embedded therein. Process 1100 is executed from 1110 to 1120.

At 1120, the process 1100 may involve the processor 1010 selecting a codebook from a plurality of codebooks. The processor 1010 may execute from 1120 to 1130.

At 1130, the process 1100 may involve the processor 1010 encoding the data using the selected codebook. Process 1100 is performed from 1130 to 1140.

At 1140, the process 1100 may involve the processor 1010 sending encoded material (eg, to the second device 1050) via the transceiver 1030.

In some implementations, each of the plurality of codebooks may correspond to a respective HARQ thread in the plurality of HARQ threads, and the plurality of HARQ threads are different from each other. For example, the process 1100 may involve the processor 1010 using HARQ to communicate with the processor 1060 of the second device 1050. When selecting a codebook from a plurality of codebooks, the process 1100 may involve the processor 1010 executing: (1) associating or otherwise associating each HARQ thread of the plurality of HARQ threads with the corresponding code in the plurality of codebooks (2) identifying the HARQ thread currently used to communicate with the second device 1050; and (3) selecting one of the plurality of codebooks, one of the plurality of codebooks and the identified HARQ thread correspond. The selected codebook may be used in encoding the material to be sent to the second device 1050.

In some embodiments, when generating a QC-LDPC code having a plurality of codebooks embedded therein, the process 1100 may involve the processor 1010 generating a QC-LDPC code composed of a basic matrix and one or a plurality of shift coefficient matrices. . The basic matrix may include a parity matrix of a plurality of parity bits and an information matrix of a plurality of information bits. Each codebook in the plurality of codebooks may include a parity matrix and a corresponding portion of an information matrix of a corresponding size, so that the sizes of the plurality of codebooks are different from each other.

In some embodiments, each codebook in the plurality of codebooks may correspond to a corresponding design in the plurality of designs of the shift coefficient matrix.

In some embodiments, when generating a QC-LDPC code with a plurality of codebooks embedded therein, the process 1100 may involve the processor 1010 generating each shift value table for each of the first set of boost factors Boost factor. Moreover, the process 1100 may involve the processor 1010 optimizing the first set of boost factors to generate a second set of boost factors. The number of boost factors in the first set may be greater than the number of boost factors in the second set. The first boosting factor may share the corresponding shift value table of the second boosting factor, where the first boosting factor is in the first set but not in the second set, and the second boosting factor is in both the first set and the second set. The value of the second boosting factor may be smaller than the value of the first boosting factor, and the second boosting factor is closer to the first boosting factor than other boosting factors in the first set.

In some embodiments, when selecting a codebook from a plurality of codebooks, the process 1100 may involve the processor 1010 selecting from the plurality of codebooks according to an initial code rate for transmitting data and / or a code block size of the data Codebook.

In some embodiments, when selecting a codebook from a plurality of codebooks, the process 1100 may involve the processor 1010 performing a plurality of operations (eg, similar to those involved in the logic flow 200). For example, the process 1100 may involve the processor 1010 determining whether the code block size of the material is less than a threshold code block size. In response to the code block size of the data being smaller than the threshold code block size, the process 1100 may involve the processor 1010 selecting a third codebook among the plurality of codebooks. In response to the code block size of the data being not less than the threshold code block size, the process 1100 may involve the processor 1010 determining whether the initial code rate used to transmit the data is greater than the threshold code rate. In response to the initial code rate being not greater than the threshold code rate, the process 1100 may involve the processor 1010 selecting a second codebook among the plurality of codebooks. In response to the initial code rate being greater than the threshold code rate, the process 1100 may involve the processor 1010 selecting a first codebook among the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.

Alternatively or additionally, when selecting a codebook from a plurality of codebooks, the process 1100 may involve the processor 1010 performing a plurality of operations. For example, the process 1100 may involve the processor 1010 determining a code block size of the material. Based on the determined result, in response to determining that the code block size is greater than the first threshold code block size, the process 1100 may involve the processor 1010 selecting the first codebook among the plurality of codebooks. Moreover, in response to determining that the code block size is greater than the second threshold code block size, the process 1100 may involve the processor 1010 selecting a second codebook among the plurality of codebooks. Moreover, in response to determining that the code block size is greater than the third threshold code block size, the process 1100 may involve the processor 1010 selecting a third codebook among the plurality of codebooks. The first threshold code block size may be larger than the second threshold code block size. The second threshold code block size may be larger than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.

FIG. 12 illustrates an exemplary process 1200 based on an embodiment of the invention. The process 1200 may represent aspects of implementing the proposed concepts and solutions, and the proposed concepts and solutions may be described, for example, with respect to some or all of FIGS. 1-10. Moreover, the process 1200 may represent aspects of the proposed concepts and solutions related to hybrid orthogonal LDPC layer design and QC-LDPC support for very low code rates. Process 1200 may include one or more of the operations, actions, and functions shown in one of the blocks 1210, 1220, and 1230 or a plurality of blocks. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1200 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks / sub-blocks of the process 1200 may be performed in the order shown in FIG. 12, or in a different order. Process 1200 may be implemented by communication system 1000 and any variations thereof. For example, the process 1200 may be implemented in the first device 1005 and / or the second device 1050, or performed by the first device 1005 and / or the second device 1050. For illustrative purposes only and not limited in scope, the process 1200 is described in the context of the first device 1005 as follows. Process 1200 may begin at block 1210.

At 1210, the process 1200 may be a processor 1010 involving the first device 1005 to generate a QC-LDPC code, the QC-LDPC code including at least a quasi-row orthogonal layer. Process 1200 may be performed from 1210 to 1220.

At 1220, the process 1200 may involve the processor 1010 encoding data using a QC-LDPC code. Process 1200 may be performed from 1220 to 1230.

At 1230, the process 1200 may involve the processor 1010 sending encoded data (to the second device 1050) via the transceiver 1030.

In some embodiments, the at least one quasi-column orthogonal layer may include bits of a plurality of rows and a plurality of columns. One or a plurality of rows of the at least one quasi-column orthogonal layer may include at least one punctured row with a degree of 2 or more. The remaining rows of the plurality of rows of the at least one quasi-column orthogonal layer may include non-perforated rows with a degree of 1 or 0.

In some embodiments, there may be no cycles in the punched rows.

In some embodiments, the QC-LDPC code may include a hybrid orthogonality design with a plurality of parts having different degrees of orthogonality. The first part of the plurality of parts with low degree of orthogonality may correspond to a high code rate, and the second part of the plurality of parts with high degree of orthogonality may correspond to a low code rate.

In some embodiments, the plurality of parts with different degrees of orthogonality include the following cases: (1) A non-column orthogonal part includes a plurality of columns and a plurality of rows, and the plurality of columns and the plurality of rows form at least one Non-column orthogonal layer; (2) a quasi-column orthogonal portion including a plurality of columns and a plurality of rows, the plurality of columns and the plurality of rows forming at least one quasi-column orthogonal layer; and (3) a pure column The orthogonal layer includes a plurality of columns and a plurality of rows, and the plurality of columns and the plurality of rows form at least one pure column orthogonal layer. Here, the plurality of rows of the non-column orthogonal portion may include at least one punctured row with a degree of 2 or more and a non-punched row with a degree of 1 or 0. One or a plurality of rows of the quasi-column orthogonal portion may include at least one punched row having a degree of 2 or higher. The remaining rows of the plurality of rows of the quasi-column orthogonal portion may include non-perforated rows with a degree of 1 or 0. Each of the plurality of rows of the pure column orthogonal portion may include rows having a degree of 1 or 0.

In some implementations, the QC-LDPC code may include a parity matrix of a plurality of parity bits, and an information matrix of a plurality of information bits. One or a plurality of row bits through the information matrix and the parity matrix may include one or a plurality of row bits having a degree of 2 in each column.

In some embodiments, each of the plurality of bits having a degree of two or the plurality of columns of a plurality of bits having a degree of two may each include a previously used parity bit or a previously transmitted information bit. .

FIG. 13 illustrates an exemplary process 1300 based on an embodiment of the present application. Process 1300 may represent aspects of implementing the proposed concepts and solutions, such as the concepts and solutions described with respect to some or all of Figures 1-10. More specifically, the process 1300 may represent aspects of the proposed concepts and solutions regarding core matrix design. Process 1300 may include one or more of the operations, actions, and functions shown in one of the blocks 1310, 1320, and 1330 or a plurality of blocks. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1200 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks / sub-blocks of process 1300 may be performed in the order shown in FIG. 13 or in a different order. Process 1300 may be implemented by communication system 1000 and any variations thereof. For example, the process 1300 may be implemented in the first device 1005 and / or the second device 1050, or performed by the first device 1005 and / or the second device 1050. For illustrative purposes only and not limited in scope, the process 1300 is described in the context of the first device 1005 as follows. Process 1300 may begin at block 1310.

At 1310, process 1300 may involve the processor 1010 of the first device 1005 generating a QC-LDPC code, the QC-LDPC code including a basic matrix, a portion of which forms a core matrix corresponding to at least a threshold code rate. Process 1300 may be performed from 1310 to 1320.

At 1320, the process 1300 may involve the processor 1010 encoding data using QC-LDPC codes. Process 1300 may be performed from 1320 to 1330.

At 1330, process 1300 may involve the processor 1010 sending encoded data (to the second device 1050) via the transceiver 1030.

In some embodiments, the code rate may be 0.89.

In some embodiments, the core matrix may include bits of a plurality of rows and columns, and two or more of the plurality of rows may include perforated rows having a specific bit pattern.

In some embodiments, after undergoing any number of row permutations and / or column permutations (eg, at least one row permutation, at least one column permutation, or any combination of the two), in a plurality of perforated rows The specific bit pattern may include one of a plurality of punctured rows or a plurality of bits 0. After row permutation and / or column permutation, two examples of a specific pattern including one or a plurality of bits 0 are shown in FIG. 7 (A). In some embodiments, the specific bit pattern in the punched row may include an isosceles right-angled triangle of bit 0, and the right angle of the triangle corresponds to bit 0 at the upper left corner in the punched row. An example of bit 0 of this isosceles right triangle is shown in part (B) of FIG. 7.

In some embodiments, the core matrix may include a parity matrix of bits in a plurality of rows and a plurality of columns. The core matrix may also include an information matrix of bits in a plurality of rows and a plurality of columns. The parity matrix may include a matrix having a Wi-Fi style. In addition to the perforated rows of the core matrix, more than one row of bits of the information matrix may include rows with high density bit 1 without or only one bit 0. The rows of high-density bits may correspond to Wi-Fi-style rows.

In some embodiments, the bits in the bottom column of the plurality of columns may include a first number of bits 1. The first number may be equal to the number of punched rows, or 0, 1, 2, or 3 (for example, larger) than the number of punched rows. In some embodiments, a portion of the first number of bits 1 in the bottom column may correspond to the punched row and the rightmost row of the core matrix, where the rightmost row of the core matrix is on Wi-Fi On the right side of the style.

In some embodiments, the core matrix may include 5 columns of bits and 20 rows of bits. The degree of a 20-bit variable node can include one of the following: [2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], [2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], [ 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], and [2, 2, 3, 3 , 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3]. The degree of the check node of the 5 columns of bits can include one of the following: [13, 10, 14, 17, 2], [13, 10, 13, 17, 2], [13, 10, 13, 18, 3 ], [13, 11, 13, 18, 2], [13, 10, 14, 18, 2], [13, 10, 13, 19, 2], [14, 10, 13, 18, 1], [13, 11, 13, 18, 1], [13, 10, 14, 18, 1], [13, 11, 13, 19, 1], [13, 10, 13, 18, 2], and [ 13, 10, 13, 18, 1].

FIG. 14 illustrates an exemplary process 1400 based on an embodiment of the invention. Process 1400 may represent aspects of implementing the proposed concepts and solutions, which may be described, for example, with respect to FIG. 9. More specifically, the process 1300 may represent aspects of the proposed concepts and schemes related to shift coefficient design. Process 1400 may include one or more of the operations, actions, or functions shown in one of the blocks 1410, 1420, and 1430 or a plurality of blocks. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1400 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks / sub-blocks of process 1400 may be performed in the order shown in FIG. 14 or in a different order. Process 1400 may be implemented by communication system 1000 and any variations thereof. For example, the process 1400 may be implemented in the first device 1005 and / or the second device 1050, or performed by the first device 1005 and / or the second device 1050. For illustrative purposes only and not limited in scope, the process 1400 is described in the context of the first device 1005 as follows. Process 1400 may begin at block 1410.

At 1410, the process 1400 may be a processor 1010 involving the first device 1005 to generate a QC-LDPC code. Process 1400 may be performed from 1410 to 1420.

At 1420, the process 1400 may involve the processor 1010 encoding data using QC-LDPC codes. Process 1400 may be performed from 1420 to 1430.

At 1430, the process 1400 may involve the processor 1010 sending encoded material (eg, to the second device 1050) via the transceiver 1030.

When generating the QC-LDPC code, the process 1400 may involve the processor 1010 performing a plurality of operations represented by sub-blocks 1412-1414.

In 1412, the process 1400 may involve the processor 1010 generating a corresponding shift value table for each of the first set of boosting factors. Process 1400 may be performed from 1412 to 1414.

In 1414, the process 1400 may involve the processor 1010 optimizing the first set of boost factors to generate a second set of boost factors.

The number of boost factors of the first set may be greater than the number of boost factors of the second set. The first boosting factor may share the corresponding shift value table of the second boosting factor, where the first boosting factor is located in the first set and not in the second set, and the second boosting factor is located in the first set and the second set. The value of the second boosting factor may be smaller than the value of the first boosting factor and closer to the first boosting factor than other boosting factors in the first set.

FIG. 24 illustrates an exemplary process 2400 of wireless communication based on an embodiment of the present invention. Process 2400 may represent aspects of implementing the proposed concepts and solutions, which may be described, for example, with respect to some or all of FIGS. 1-10, and 15 (A) -23. More specifically, the process 2400 may represent aspects of the proposed concepts and schemes related to the design of shift coefficient tables for QC-LDPC codes for large code block sizes in mobile communications. Process 2400 may include one or a plurality of one or more of the operations, actions, and functions shown in blocks 2410 and 2420 and sub-blocks 24202, 24204, 24206, 24208, 24210, and 24212. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 2400 may be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks / sub-blocks of process 2400 may be performed in the order shown in FIG. 24, or in a different order. Process 2400 may be implemented by communication system 1000 and any variations thereof. For example, the process 2400 may be implemented in the first device 1005 and / or the second device 1050, or performed by the first device 1005 and / or the second device 1050. For illustrative purposes only and not limited in scope, the process 1400 is described in the environment of the first device 1005 as follows, but the same can be applied to the device 1050 as well. Process 2400 may begin at block 2410.

At 2410, process 2400 may involve the processor 1010 of the first device 1005 establishing a wireless communication link with at least one other device (eg, the second device 1050) via the transceiver 1030 of the device 1005. Process 2400 may be performed from 2410 to 2420.

At 2420, process 2400 may involve the processor 1010 wirelessly communicating with other devices via the wireless communication link via the transceiver 1030. In wireless communication with other devices, the process 2400 may involve the processor 1010 performing a plurality of operations represented by 24202, 24204, 24206, 24208, 24210, and 24212.

At 24202, process 2400 may involve the processor 1010 selecting a first shift coefficient table from a plurality of shift coefficient tables. Process 2400 can be performed from 24202 to 24204.

At 24204, the process 2400 may involve the processor 1010 using at least a portion of the first shift coefficient table and a basic matrix to generate a QC-LDPC code. Process 2400 may be performed from 24204 to 24206.

At 24206, the process 2400 may involve the processor 1010 selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code. Process 2400 can be performed from 24206 to 24208.

At 24208, process 2400 may involve the processor 1010 storing the selected codebook into processor-related memory. Process 2400 can be performed from 24208 to 24210.

At 24210, process 2400 may involve processor 1010 encoding the data using the selected codebook to generate a plurality of modulation symbols for the data. Process 2400 may be performed from 24210 to 24212.

At 24212, process 2400 may involve the processor 1010 controlling the transceiver 1030 to multiplex, convert, filter, and amplify the modulation symbols, and radiate the modulation symbols as electromagnetic waves through one or more of the sky threads 1036 of the first device 1005 to pass the wireless communication chain It sends the modulation symbols of the data to other devices.

In some embodiments, the first shift coefficient table may include a basic shift coefficient table arranged in 4 columns and 26 rows in the following form:

In some embodiments, the first shift coefficient table may include a shift coefficient table as shown in FIGS. 18A to 18B.

In some embodiments, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 5 (a = 5) and a boost factor 320. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 7 (a = 7) and a boosting factor 224. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 15 (a = 15) and a boosting factor 240. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 9 (a = 9) and a boosting factor 288. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 11 (a = 11) and a boosting factor 352. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 3 (a = 3) and a boosting factor 384. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 13 (a = 13) and a boosting factor 208. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG1 having an original element 2 (a = 2) and a boost factor of 256.

In some embodiments, when selecting a first shift coefficient table from a plurality of shift coefficient tables, the process 2400 may involve the processor 1010 selecting a first shift coefficient table for a relatively large code block size according to one or a plurality of rules. A shift coefficient table, wherein the one or more rules are related to either or both of a code block size and a code rate of data.

In some embodiments, when using at least a part of the first shift coefficient table and the basic matrix to generate a QC-LDPC code, the process 2400 may involve the processor 1010 using the full portion of the first shift coefficient table and the basic matrix. Generate QC-LDPC codes.

In some implementations, when using at least a portion of the first shift coefficient table and a basic matrix to generate a QC-LDPC code, the process 2400 may involve the processor 1010 using a partial portion of the first shift coefficient table and a basic matrix. Generate QC-LDPC codes.

In some embodiments, when selecting a first shift coefficient table from a plurality of shift coefficient tables, the process 2400 may involve the processor 1010 selecting a second shift coefficient table, and the pair of values in the second shift coefficient table The modulo result of the one or more boosting factors is the same as the modulo result in at least the first shift coefficient table.

In some embodiments, when using at least a part of the first shift coefficient table and the basic matrix to generate a QC-LDPC code, the process 2400 may involve the processor 1010 using the full portion of the second shift coefficient table and the basic matrix. Generate QC-LDPC codes.

In some implementations, when using at least a part of the first shift coefficient table and a basic matrix to generate a QC-LDPC code, the process 2400 may involve the processor 1010 using a part of the second shift coefficient table and a basic matrix. Generate QC-LDPC codes.

In some embodiments, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the processor 2400 may involve the processor 1010 to perform a plurality of operations. For example, the processor 2400 may involve the processor 1010 determining whether a code block size is less than or equal to a threshold code block size. Further, the process 2400 may involve the processor 1010 determining whether the code rate is less than or equal to a threshold code rate. Moreover, the process 2400 may involve the processor 1010 selecting a first shift coefficient table corresponding to the basic graph BG1 in response to determining that the code block size is greater than a threshold code block size or in response to determining that the code rate is greater than a threshold code rate. Alternatively, the process 2400 may involve the processor 1010 selecting a first shift coefficient table corresponding to the basic graph BG2 in response to determining that the code block size is less than or equal to the threshold code block size or in response to determining that the code rate is less than or equal to the threshold code rate.

In some embodiments, each of the plurality of codebooks may correspond to a corresponding HARQ thread of the plurality of HARQ threads, where the plurality of HARQ threads are different from each other.

In some embodiments, when selecting a codebook from a plurality of codebooks, the process 2400 may involve the processor 1010 performing a plurality of operations. For example, the process 2400 may involve the processor 1010 performing a plurality of operations. For example, the process 2400 may involve the processor 1010 determining whether the code block size of the material is less than a threshold code block size. In addition, the process 2400 may involve the processor 1010 selecting a third codebook among the plurality of codebooks in response to the code block size of the data being smaller than the threshold code block size. Moreover, in response to the code block size of the data being not less than the threshold code block size, the process 2400 may involve the processor 1010 determining whether the initial code rate used to transmit the data is greater than the threshold code rate. Moreover, in response to the initial code rate being not greater than the threshold code rate, the process 2400 may involve the processor 1010 selecting a second codebook among the plurality of codebooks. Moreover, in response to the initial code rate being greater than the threshold code rate, the process 2400 may involve the processor 1010 selecting a first codebook among the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

In some embodiments, when selecting a codebook from a plurality of codebooks, the process 2400 may involve the processor 1010 performing a plurality of operations. For example, the process 2400 may involve the processor 1010 determining a code block size of the material. In addition, the process 2400 may involve the processor 1010 selecting a codebook by: (1) in response to determining that the code block size is greater than the first threshold code block size, selecting the first codebook among the plurality of codebooks; (2) responding to the determination The code block size is larger than the second threshold code block size, and the second codebook in the plurality of codebooks is selected; (3) in response to determining that the code block size is greater than the third threshold code block size, the third code in the plurality of codebooks is selected this. The first threshold code block size may be larger than the second threshold code block size. The second threshold code block size may be larger than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

Additional information

The subject matter described herein sometimes illustrates different elements contained within or connected to other different elements. It needs to be understood that the architecture depicted in this way is only an example, and many other architectures can actually be implemented to achieve the same functionality. In a conceptual sense, any component arrangement that achieves the same function is effectively "associated" such that the desired function is achieved. Thus, any two elements combined here to achieve a particular function may be considered to be "associated" with each other such that the desired function is achieved, regardless of architecture or intermediate components. Likewise, any two elements so associated can also be considered as "operably connected" or "operably coupled" to each other to achieve the desired function, and any two elements that can be so associated can also be considered as " Operable and Coupling "to achieve the required functionality. Specific examples of operable and coupleable include, but are not limited to, physically pairable and / or physically interacting elements and / or wirelessly interacting and / or wirelessly interacting elements and / or logically interacting and / or logically interacting Interactive components.

In addition, regarding the use of any plural and / or singular terminology herein, those having ordinary knowledge in the art can convert from plural to singular and / or from singular to plural according to the context and / or application. For the sake of clarity, various singular / plural permutations can be explicitly explained here.

In addition, those with ordinary knowledge in the art will understand that, in general, the terms used herein, especially those used in the scope of the attached patent application, such as the subject of the scope of the attached patent application, are generally intended to be "open" Terms, for example, the term "including" should be read as "including but not limited to", the term "having" should be read as "having at least", the term "including" should be read as "including but not limited to", and so on. Those with ordinary knowledge in the field should further understand that if the intention requires a certain number of patent application scope records, this intention should be clearly stated in the patent application scope, if there is no such record, there is no such intention. For example, as an aid to understanding, the scope of the attached patent application below may include introductory terms using "at least one" and "one or more" to introduce records of the scope of the patent application. However, the use of these words should not be construed as the application of the patent scope record introduced by the indefinite article "a" or "an" defines any implementation of the patent scope of any particular application that includes this introduced patent scope record including only one Such records, even when the same patent application scope includes introductory words "one or more" or "at least one", and non-limiting articles such as "a" or "an", such as "a" and / or "an" , Should be interpreted to mean "at least one" or "one or more"; the same applies to the use of restrictive articles used to introduce the scope of the patent application. In addition, even if the specific number of records of the scope of the patent application introduced is clearly stated, those skilled in the art will recognize that such records should be interpreted to indicate at least the number of records, for example, only "two records" Without other modifiers, it means at least two records, or two or more records. In addition, in the case of using a convention similar to at least one of "A, B, and C", etc., generally, this configuration is intended in the sense that a person having ordinary knowledge in the art will understand the convention, such as "having A, B "A system with at least one of C" will include, but is not limited to, a system with only A, only B, only C, A and B together, A and C together, B and C together, and / or A, B and C systems together, etc. In those cases that use conventions like at least one of "A, B or C", etc., usually this structure is intended in a sense that a person with ordinary knowledge in the field will understand the conventions, for example, "having A, "A system of at least one of B or C" will include, but is not limited to, a system with only A, only B, with only C, A and B together, a system with A and C together, a system with B and C together, And / or A, B and C together, etc. Those with ordinary knowledge in the art will further understand that, in fact, any separated word and / or term indicating two or more replacement conditions should be considered to include a plurality of One of the conditions, the possibility of either or both conditions. For example, the phrase "A or B" will be understood to include the possibility of "A" or "B" or "A and B".

From the above, it can be understood that, for the purpose of illustration, various embodiments disclosed in the present application have been described herein, and various modifications can be made without departing from the scope and spirit of the present application. Therefore, the various embodiments disclosed herein are not meant to be limiting, and the true scope and spirit are determined by the scope of the attached patent application.

100‧‧‧ Basic Matrix

I1‧‧‧ the first part of the information matrix

I2‧‧‧ Part Two of the Information Matrix

I3‧‧‧ Part Three of the Information Matrix

200‧‧‧ flow

210, 220, 230, 240, 250 ‧ ‧ ‧ blocks

300‧‧‧ Quasi-column orthogonal layer design

400‧‧‧ mixed orthogonal layer design

500‧‧‧QC-LDPC

600‧‧‧ Core Matrix

700‧‧‧ Core Basic Matrix

800‧‧‧ Core Basic Matrix

900‧‧‧ shift coefficient design

1000‧‧‧communication system

1005‧‧‧First device

1050‧‧‧Second Device

1036, 1086‧‧‧ Antenna

1030, 1080‧‧‧‧ Transceiver

1032, 1082 ‧‧‧ transmitter

1034, 1084 ‧‧‧ receiver

1010, 1060‧‧‧ processor

1012, 1062‧‧‧ Encoder

1014, 1064‧‧‧ decoder

1016, 1066‧‧‧Memory

1020, 1070‧‧‧Memory

1022, 1072 ‧ ‧ ‧ instructions

1024, 1074 ‧ ‧ ‧ data

1040‧‧‧communication link

1100‧‧‧process

1110, 1120, 1130, 1140 ‧‧‧ blocks

1200‧‧‧process

1210, 1220, 1230 ‧‧‧ blocks

1300‧‧‧process

1310, 1320, 1330 ‧‧‧ blocks

1400‧‧‧process

1410, 1420, 1430, 1412, 1414 ‧‧‧ blocks

1500‧‧‧ shift coefficient table

1600‧‧‧Shift coefficient table

1700‧‧‧Shift coefficient table

1800‧‧‧ shift coefficient table

1900‧‧‧ shift coefficient table

2000‧‧‧ shift coefficient table

2100‧‧‧Shift coefficient table

2200‧‧‧Shift coefficient table

2300‧‧‧process

2310, 2320, 2330, 2340 ‧‧‧ blocks

2400‧‧‧process

2410, 2420 ‧ ‧ ‧ blocks

24202, 24204, 24206, 24208, 24210, 24212, ‧‧‧ subblocks

The accompanying drawings are included to provide a further understanding of the application, and the drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present application and, together with the description, serve to explain principles of the application. It can be understood that the drawings are not necessarily drawn to scale, and some components are shown disproportionate to the dimensions in actual implementation to clearly illustrate the concept of the present application. FIG. 1 is a schematic diagram of an exemplary multi-codebook embedded LDPC code design based on an embodiment of the present application; FIG. 2 is a schematic diagram of an example logic flow related to a multi-codebook embedded LDPC code based on an embodiment of the present application; Figure 3 is a schematic diagram of an exemplary quasi-row orthogonal layer design based on an embodiment of the present application; Figure 4 is an exemplary hybrid orthogonal layer design based on an embodiment of the present application; Figure 5 is a schematic diagram of an exemplary QC-LDPC code supporting an extremely low code rate based on an embodiment of the present application; Figure 6 is an exemplary kernel matrix design based on an embodiment of the present application; FIG. 7 is a schematic diagram of an exemplary concept of a core basic matrix based on an embodiment of the present application; FIG. 8 is a schematic diagram of an exemplary concept of a core basic matrix based on another embodiment of the present application; FIG. 9 is based on the present application FIG. 10 is a block diagram of an exemplary communication system based on an embodiment of the present application; FIG. 10 is a block diagram of an exemplary communication system based on an embodiment of the present application; FIG. 11 is a diagram based on an embodiment of the present application A flowchart of an exemplary process; FIG. 12 is a flowchart of an exemplary process based on another embodiment of the present application; FIG. 13 is a flowchart of an exemplary process based on another embodiment of the present application; FIG. 14 Is a flowchart of an exemplary process based on another embodiment of the present application; each of FIG. 15 (A) and FIG. 15 (B) is a schematic diagram of an exemplary shift coefficient table based on an embodiment of the present application; Each of FIGS. 16 (A) and 16 (B) is a schematic diagram of some exemplary shift coefficient tables based on the embodiment of the present application; each of FIGS. 17 (A) and 17 (B) is FIG. 18 (A) and FIG. 18 (B) are schematic diagrams of some exemplary shift coefficient tables based on the embodiments of the present application; Each of FIG. 19 (A) and FIG. 19 (B) is a schematic diagram of some exemplary shift coefficient tables based on the embodiment of the present application; each of FIG. 20 (A) and FIG. 20 (B) is based on Schematic diagram of some exemplary shift coefficient tables in the embodiments of the present application; each of FIGS. 21 (A) and 21 (B) Each is a schematic diagram of a partial exemplary shift coefficient table based on an embodiment of the present application; each of FIG. 22 (A) and FIG. 22 (B) is a schematic diagram of a partial exemplary shift coefficient table based on an embodiment of the present application FIG. 23 is a schematic diagram of an exemplary logical flow for selecting a shift coefficient table based on an embodiment of the present application; FIG. 24 is a flowchart of an exemplary process based on another embodiment of the present application.

Claims (20)

A method for wireless communication includes: a processor of a device establishes a wireless communication link with at least one other device via a transceiver of the device; and the processor wirelessly communicates with the other device via the wireless communication link in the following manner : Selecting a first shift coefficient table from a plurality of shift coefficient tables; using a basic matrix and at least a part of the first shift coefficient table to generate a quasi-loop low-density parity check (QC-LDPC) code; Selecting a codebook from a plurality of codebooks in the QC-LDPC code; storing the selected codebook in a memory related to the processor; encoding the data using the selected codebook to generate the data A plurality of modulation symbols; and controlling the transceiver to multiplex, convert, filter, amplify the modulation symbols and radiate the modulation symbols as electromagnetic waves through one or more antennas of the device for transmission via a wireless communication link Modulating symbols of the data to the other device, wherein the selecting a first shift coefficient table from a plurality of shift coefficient tables includes: Either one of the code block size of the data and the code rate of the data, or one or two related rules, select the first shift coefficient table for a relatively large code block size. The method according to item 1 of the patent application scope, wherein the first shift coefficient table includes: a basic shift coefficient table arranged in 4 columns and 26 rows in the following pattern: The method according to item 1 of the scope of patent application, wherein the first shift coefficient table includes shift coefficient tables as shown in FIGS. 18A and 18B. The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to a basic chart 1 (BG1) having an original element of 5 (a = 5) and a boost factor of 320 . The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to a basic chart 1 (BG1) having an original element of 7 (a = 7) and a boost factor of 224 . The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to a basic chart 1 (BG1) having an original element of 15 (a = 15) and a boost factor of 240 . The method according to item 1 of the scope of patent application, wherein the first shift coefficient table includes a shift coefficient table corresponding to a basic chart 1 (BG1) having an original element 9 (a = 9) and a boost factor 288 . The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to a basic chart 1 (BG1) having an original element 11 (a = 11) and a boost factor 352 . The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to a basic chart 1 (BG1) having an original element of 3 (a = 3) and a boost factor of 384 . The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to a basic chart 1 (BG1) having an original element of 13 (a = 13) and a boost factor of 208 . The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to a basic chart 1 (BG1) having an original element 2 (a = 2) and a boost factor of 256 . The method according to item 1 of the scope of patent application, wherein the generating a QC-LDPC code using a basic matrix and at least a part of a first shift coefficient table includes: using all sums of the first shift coefficient table. The basic matrix generates the QC-LDPC code. The method according to item 1 of the scope of patent application, wherein the generating a QC-LDPC code using a basic matrix and at least a part of a first shift coefficient table includes: using a part of the first shift coefficient table and all The basic matrix generates the QC-LDPC code. The method according to item 1 of the scope of patent application, wherein the selecting a first shift coefficient table from a plurality of shift coefficient tables comprises: selecting a second shift coefficient table, and the second shift coefficient table The value of modulo the value of the one or a plurality of lifting factors is the same as the modulo result in the at least first shift coefficient table. The method according to item 14 of the scope of patent application, wherein generating a QC-LDPC code using a basic matrix and at least a part of a first shift coefficient table includes: using all of the second shift coefficient table and the basic Matrix, generating QC-LDPC codes. The method according to item 14 of the patent application scope, wherein generating a QC-LDPC code using a basic matrix and at least a part of a first shift coefficient table includes: using a part of the second shift coefficient table and the basic Matrix, generating QC-LDPC codes. The method according to item 1 of the scope of patent application, wherein selecting a first shift coefficient table from a plurality of shift coefficient tables includes: determining whether the code block size is less than or equal to a threshold code block size; and determining the Whether the code rate is less than or equal to the threshold code rate. The method according to item 17 of the patent application scope, wherein selecting the first shift coefficient table from the plurality of shift coefficient tables further includes: responding to determining that the code block size is greater than a threshold code block size or responding to a determination code If the rate is greater than the threshold code rate, the first shift coefficient table corresponding to the basic graph 1 (BG1) is selected. The method according to item 17 of the scope of patent application, wherein selecting the first shift coefficient table from the plurality of shift coefficient tables further includes: responding to determining that the code block size is less than or equal to a threshold code block size or responding to It is determined that the code rate is less than or equal to the threshold code rate, and a first shift coefficient table corresponding to the basic graph 2 (BG2) is selected. The method according to item 1 of the scope of patent application, wherein each of the plurality of codebooks corresponds to a corresponding HARQ thread in a plurality of hybrid automatic repeat request (HARQ) threads, wherein the plurality of codebooks HARQ threads are different from each other.