TWI669915B - Coding methods - Google Patents

Abstract

The present invention provides a plurality of encoding methods, wherein an encoding method includes: generating a type of cyclic low density parity check code, the cyclic low density parity check code having a plurality of built-in codebooks; selecting a code from the plurality of codebooks And encoding the data using the selected codebook.

Description

Coding method

The present invention relates to information encoding and decoding, and more particularly to a variety of methods and apparatus for Quasi-Cyclic-Low-Density Parity-Check (QC-LDPC) encoding.

Third Generation Partnership Project ^{(The 3 rd Generation Partnership Project,} 3GPP) has approved a number of programs to accelerate the fifth-generation (5G) New Radio (New Radio, NR) the development of specifications, therefore, can be expected in the near future In the future, 5G NR wireless communication services based on multiple standards can be launched. 3GPP has also agreed to use QC-LDPC in the 5G NR data channel. However, the specific details of how to perform QC-LDPC based encoding and decoding have not been defined.

In view of this, the present invention provides various novel concepts and mechanisms related to QC-LDPC encoding and decoding, which can be implemented in next generation communications, whether wired or wireless, including 5G NR wireless communications.

An encoding method according to an embodiment of the invention includes: generating a type of cyclic low density parity check code, the cyclic low density parity check code having a plurality of codebooks; selecting a code from the plurality of codebooks And encoding the data using the selected codebook.

An encoding method according to another embodiment of the present invention includes: generating a type of cyclic low density parity check code; and encoding the data using the cyclic low density parity check code, wherein the cyclic low density parity check code The generation further includes: being one of a plurality of lifting factors Each of the first set of spread factors produces a respective shift values table; and the first set of the plurality of spread factors is optimized to produce a second set of the plurality of spread factors The total number of expansion factors of the first set is greater than the total number of expansion factors of the second set, wherein a first spreading factor shares a shift value table of a second spreading factor, wherein the first spreading factor exists In the first set but not in the second set, the second spreading factor is present in both the first set and the second set, and wherein the second spreading factor is numerically smaller than the first The spreading factor is closer to the first spreading factor than the other spreading factors in the first set.

An encoding method according to another embodiment of the present invention includes: generating a type of cyclic low density parity check code, the cyclic low density parity check code including at least one type of quasi-row orthogonal layer; The class loop low density parity check code encodes the data.

An encoding method according to still another embodiment of the present invention includes: generating a type of cyclic low density parity check code, wherein the cyclic low density parity check code comprises a base matrix, and a part of the basic matrix forms a core matrix (kernel matrix), the core matrix corresponding to at least one threshold value (Code Rate, CR); and encoding the data using the cyclic low-density parity check code, wherein the core matrix includes multiple bits a plurality of rows and a plurality of rows, wherein two or more of the plurality of rows include a plurality of punctured columns, the plurality of truncated rows having a plurality of rows One of the bits is a specific pattern.

One of the advantages of the various encoding methods of the present invention is that it provides a variety of methods for encoding using QC-LDPC codes.

100, 500‧‧‧QC-LDPC code

200‧‧‧Logical process

210~250, 1110~1140, 1210~1230, 1310~1330, 1410~1430‧‧

300‧‧‧Class Orthogonal Layer Design

400‧‧‧Mixed Orthogonal Layer Design

600‧‧‧core matrix design

700, 800‧‧‧ example concepts

900‧‧‧Transition parameter design

1000‧‧‧Communication system

1005‧‧‧ first device

1010, 1060‧‧‧ processor

1012, 1062‧‧ ‧ encoder

1014, 1064‧‧‧ decoder

1020, 1070‧‧‧ memory

1022, 1072‧‧

1024, 1074‧‧‧ data

1030, 1080‧‧‧ transceiver

1032, 1082‧‧‧transmitters

1034, 1084‧‧‧ Receiver

1050‧‧‧second device

1100, 1200, 1300, 1400‧‧‧ operations

Part of the I1-I3‧‧‧ information matrix

1 is a schematic diagram of a multiple built-in LDPC code design according to an embodiment of the present invention.

2 is an example logic related to multiple built-in LDPC code designs according to an embodiment of the present invention. A schematic diagram of the process 200.

FIG. 3 is a diagram showing an example of a column-like orthogonal layer design 300 in accordance with an embodiment of the present invention.

4 is a schematic diagram of an example of a hybrid orthogonal layer design 400 in accordance with an embodiment of the present invention.

FIG. 5 is a diagram showing an example of a QC-LDPC code 500 supporting an extremely low code rate according to an embodiment of the present invention.

FIG. 6 is a diagram showing an example of a core matrix design 600 in accordance with an embodiment of the present invention.

FIG. 7 is a schematic diagram of an exemplary concept 700 of a core base matrix in accordance with an embodiment of the present invention.

Figure 8 is a schematic illustration of an example concept 800 of a core base matrix in accordance with another embodiment of the present invention.

FIG. 9 is a schematic diagram of an example shift parameter design 900 in accordance with an embodiment of the present invention.

FIG. 10 is a schematic diagram of an example communication system 1000 in accordance with an embodiment of the present invention.

11 is a schematic diagram of an example operation 1100 in accordance with an embodiment of the present invention.

Figure 12 is a schematic illustration of an example operation 1200 in accordance with an embodiment of the present invention.

Figure 13 is a schematic illustration of an example operation 1300 in accordance with an embodiment of the present invention.

Figure 14 is a schematic illustration of an example operation 1400 in accordance with an embodiment of the present invention.

Certain terms are used throughout the description and claims to refer to particular elements. Those of ordinary skill in the art should understand that hardware manufacturers may refer to the same component by different nouns. This specification and the scope of the patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The words "including" and "including" as used throughout the specification and the scope of the patent application are an open term and should be interpreted as "including but not limited to". "About" means that within the acceptable error range, those skilled in the art can solve the technical problem within a certain error range, and basically achieve the technical effect. In addition, "coupling The term "connected" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, the first device can be directly electrically connected to the second device, or can be electrically connected to the second device through other devices or connection means. Device. The term "connected" is used herein to include any direct and indirect, wired and wireless means of connection. The following is a description of the preferred embodiments of the present invention, and is intended to illustrate the scope of the invention, and the scope of the present invention is defined by the scope of the appended claims.

Detailed embodiments and embodiments related to the present invention are described herein. It should be understood, however, that the various embodiments and embodiments described herein are intended to illustrate the claimed invention in various forms. However, the description of the present invention may be embodied in a variety of forms and should not be construed as being limited to the various embodiments and embodiments described herein; The scope of the invention is fully described by those of ordinary skill in the art. The details of the known features and techniques are omitted in the following description in order to avoid unnecessary obscuring of the various embodiments and embodiments presented.

It should be noted that although the various encoding methods and apparatus provided by the present invention are described below in the context of 5G NR wireless communication, any variants/derivations of the various encoding methods and apparatus provided by the present invention are possible under other protocols, Suitable communications for implementation by standards and specifications. Therefore, the mechanism provided by the present invention is not limited to the description in the specification.

Overview

The various concepts and mechanisms provided by the present invention are generally related to the following fields: multi-embedded low density parity check (LDPC) code design, hybrid orthogonal LDPC layer design, pole QC-LDPC support, core matrix design, and shift-coefficient design for extreme low code rate (CR). The field of hybrid orthogonal LDPC layer design includes novel concepts and mechanisms of class-column orthogonal layer design and hybrid orthogonal layer design. The description of these proposed concepts and mechanisms is provided below with reference to Figures 1 through 9.

1 is a schematic diagram of a multiple built-in LDPC code design according to an embodiment of the present invention. Referring to FIG. 1, the QC-LDPC code 100 according to the present invention may have a plurality of built-in codebooks.

As shown in FIG. 1, the QC-LDPC code 100 may include a basic matrix including a parity matrix and an information matrix, wherein the parity matrix includes a plurality of parity bits, and the information matrix includes multiple Information bits. Correspondingly, each of the plurality of codebooks may include a part of a corresponding size in the parity matrix and the information matrix, so that the sizes of the plurality of codebooks may be different. In the embodiment shown in Fig. 1, a codebook can be expressed as follows: Codebook = (I1 or I2 or I3) + P

The mark "I1" indicates the first part of the information matrix, the mark "I2" indicates the second part of the information matrix, the mark "I3" indicates the third part of the information matrix, and the mark "P" indicates the parity matrix. Here, the size of I1 (for example, the number of bits and/or the size of the memory) is larger than the size of I2, and the size of I2 is larger than the size of I3.

Thus, the size of the synthesized codebook can vary depending on the size of the portion of the information matrix used to form the codebook with the co-located matrix. It should be noted that although the embodiment shown in FIG. 1 displays three codebooks of different sizes due to different combinations I1+P, I2+P and I3+P, in various embodiments according to the present invention, different sizes The number of multiple codebooks is not limited to three (may be less than or more than three).

In some embodiments, each of the plurality of codebooks may each correspond to one of a plurality of Hybrid Automatic Repeat Request (HARQ) threads, the HARQ thread, each of the plurality of HARQ threads Not the same. For example, the first codebook may correspond to the first HARQ thread, and the first codebook may have a value ranging from 0.33 to 0.89. The second codebook may correspond to the second HARQ thread, and the second codebook may have a value ranging from 0.2 to 0.66. The third codebook may correspond to a third HARQ thread, the third codebook having a minimum code block size of less than 400.

In some embodiments, each of the plurality of codebooks can each correspond to an information node block size (Kb). For example, the first codebook may correspond to the first information node block size Kb=16. The second codebook may correspond to the second information node block size Kb=12. The third codebook may correspond to the third information node block size KB=5.

In some embodiments, all codebooks can share a single base matrix with different zero-padding sizes. In some embodiments, different codebooks may correspond to different shift parameter designs, or share one shift parameter design.

In some embodiments, selecting which codebook to use from among the plurality of codebooks may be based on an initial code rate of the data transmission, a code block size of the material, or both.

2 is a schematic diagram of an example logic flow 200 associated with multiple built-in LDPC code designs in accordance with an embodiment of the present invention. Logic flow 200 may be implemented in a decoder or processor, or implemented using an encoder or processor to implement various features and/or aspects of the various concepts and mechanisms presented herein. More specifically, logic flow 200 may be related to selecting a codebook from a plurality of codebooks. Logic flow 200 may include one or more operations, actions, or functions represented by one or more of blocks 210, 220, 230, 240, and 250. Although shown as separate blocks, depending on implementation requirements, multiple blocks of logic flow 200 may be partitioned into additional blocks, combined into fewer blocks, or partially omitted. The logic flow 200 can be implemented by each of the first device 1005 and the second device 1050 described below. The description of the logic flow 200 is provided below with the textual description of the second device 1050 for illustrative purposes only and not for limiting the scope of the invention. The logic flow 200 can begin at block (step) 210.

In step 210, the logic flow 200 may include the second device 1050 determining whether the code block size of one of the data to be encoded is less than a threshold block size. In the event that it is determined that the code block size of the data is less than the threshold code block size, logic flow 200 may proceed from step 210 to step 220. In the event that it is determined that the code block size of the data is not less than the threshold code block size, logic flow 200 may proceed from step 210 to step 230.

In step 220, the logic flow may include the second device 1050 selecting one of the plurality of codebooks (ie, using a small-sized information matrix and a parity matrix as the base matrix).

In step 230, the logic flow may include the second device 1050 determining whether an initial code rate for data transmission is greater than a threshold rate. In the event that it is determined that the initial code rate is not greater than the threshold rate, logic flow 200 may proceed from step 230 to step 240. In the event that it is determined that the initial code rate is greater than the threshold rate, logic flow 200 may proceed from step 230 to step 250.

In step 240, the logic flow 200 may include the second device 1050 selecting one of the plurality of codebooks (ie, the information matrix of the in-use size and the parity matrix as the base matrix).

In step 250, the logic flow 200 may include the second device 1050 selecting one of the plurality of codebooks and the third codebook (ie, using a large-sized information matrix and a parity matrix as the base matrix).

Here, one of the third codebooks has a size larger than one of the second codebooks. In addition, the size of the second codebook is larger than a size of the first codebook.

FIG. 3 is a diagram showing an example of a column-like orthogonal layer design 300 in accordance with an embodiment of the present invention. Orthogonality facilitates the throughput efficiency of the LDPC decoder. In LDPC encoding, several columns can be divided into a group to form a layer, and each row within the layer can be a degree one (i.e., orthogonality). In this case, the layer is referred to as a pure row orthogonal layer.

Referring to FIG. 3, in the class column orthogonal layer design 300, several columns can be divided into a group to form a class of column orthogonal layers. Each row within the layer may be one degree (ie, orthogonal) except one or more truncated lines. In the example shown in part (A) of Figure 3, the two leftmost rows are truncated rows.

Further, in the class column orthogonal layer design 300, there are no cycles in a plurality of truncated lines in the class column orthogonal layer. In the example shown in part (B) of Fig. 3, since a loop is stored in two truncated lines, the corresponding layer is not regarded as a class of orthogonal layers according to the present invention.

4 is a schematic diagram of an example of a hybrid orthogonal layer design 400 in accordance with an embodiment of the present invention. In the hybrid orthogonal layer design 400, the QC-LDPC code can include multiple ports of different degrees of orthogonality. In the example shown in Figure 4, multiple blocks of darker colors represent multiple bits, which are lighter. A plurality of blocks of color represent a plurality of bits 0. For example, the first of the plurality of portions can be low orthogonal and can correspond to a high code rate. Likewise, the second portion of one of the plurality of portions can be moderately orthogonal and can correspond to a medium code rate. Similarly, one of the plurality of portions may be highly orthogonal and may correspond to a low code rate.

In the example shown in FIG. 4, the plurality of portions of different orthogonalities include the following cases: (1) a non-column orthogonal portion including a plurality of columns and a plurality of rows, the plurality of columns and the plurality of rows Forming at least one non-column orthogonal layer corresponding to a relatively high one or more code rates; (2) a class of column orthogonal portions including a plurality of columns and a plurality of rows, the plurality of columns forming the plurality of rows Corresponding to at least one type of column orthogonal layer of one or more medium code rates of the device; and (3) a pure column orthogonal layer comprising a plurality of columns and a plurality of rows, the plurality of columns forming corresponding to the plurality of rows At least one pure column orthogonal layer of relatively low one or more code rates. Here, each of the plurality of rows of the non-column orthogonal portion has a row orthogonality of 2 or higher. In addition, one or more of the plurality of rows of the orthogonal portion of the class include a plurality of truncated rows having an orthogonality of 2 or higher. Furthermore, the remaining plurality of rows of the plurality of rows of the orthogonal portion of the class include a plurality of non-truncated rows having an orthogonality of one. Further, each of the plurality of rows of the pure column orthogonal portion includes one row having an orthogonality of one.

FIG. 5 is a diagram showing an example of a QC-LDPC code 500 supporting an extremely low code rate according to an embodiment of the present invention. Referring to FIG. 5, the QC-LDPC code 500 may include one of a plurality of parity bits and one information matrix of a plurality of information bits. The information matrix may include one or more columns of bits, each of which has a degree of orthogonality of two. In addition, each of the plurality of bits having a degree of orthogonality of 2 in the one or more columns of the orthogonality of 2 may be the previously used parity or previously transmitted information. Bit.

FIG. 6 is a diagram showing an example of a core matrix design 600 in accordance with an embodiment of the present invention. Referring to FIG. 6, in the core matrix design 600, a QC-LDPC code may include a basic matrix, and a portion of the basic matrix forms a core matrix corresponding to a code rate having at least one threshold value. For example, in the example shown in Figure 6, the core matrix supports a code rate of 0.89.

Figure 7 is a diagram showing an exemplary concept 700 of a core base matrix in accordance with an embodiment of the present invention. intention. Referring to FIG. 7, the core matrix may include a plurality of columns of a plurality of columns and a plurality of rows, wherein there are two or more behavioral truncation rows having a specific pattern of one of the plurality of bits (for example, one or more bits 0). In some embodiments, the specific pattern of the plurality of bits in the plurality of truncated lines may comprise an isosceles right triangle formed by the plurality of bits 0, and the right angle of the isosceles right triangle corresponds to the plurality of truncated lines One of the bits 0 in the upper left corner.

The core matrix may comprise a co-located matrix comprising a plurality of columns of a plurality of columns and a plurality of rows. The core matrix may also include an information matrix comprising a plurality of columns of a plurality of columns and a plurality of rows. The co-located matrix includes a matrix having a Wi-Fi pattern (eg, a parity matrix like a Wi-Fi pattern). In addition, a plurality of bits of more than one column of the information matrix may include a plurality of columns having a high density of one bit 1 and no or only one bit 0. A plurality of bits of the bottom column of one of the plurality of columns may include a first number of bits 1. The first amount may be equal to one of the plurality of truncated rows or one greater than the number of the plurality of truncated rows.

In the example shown in part (A) of Fig. 7, the first few columns (for example, three columns) are composed of a parity matrix like Wi-Fi, and the information matrix has a plurality of bits 1 of very high density. More specifically, the bits included in each column of the information matrix, if not all of the bits 1, are mostly bit 1, with no or only one bit 0. After any number of rows of permutations and/or column permutations (eg, at least one row permutation, at least one column permutation, or any combination thereof), the truncated row includes one or more of the particular patterns of one of the bits 0. An edge block may correspond to a variable node (VN) block. Two edge blocks may correspond to two truncated lines (eg, VN0 and VN1). In the case where there are four edge blocks, a fourth edge block can be added to increase the shortest distance.

In the example shown in part (B) of Fig. 7, an example pattern of the truncated line is shown. For a base matrix of size mxn, and assuming that the p-row is truncated, an isosceles right-angled triangle of a plurality of bits 0 is used to construct an mxp matrix whose right angle corresponds to one of the upper left corners of one of the plurality of truncated lines Bit 0. The other of the one or more truncated lines may be randomly selected to be 0 or 1. Due to possible execution Row and column permutation and/or row permutation, therefore, the actual position of a particular pattern may be different from the upper left corner of the one or more truncated lines.

Figure 8 is a schematic illustration of an example concept 800 of a core base matrix in accordance with another embodiment of the present invention. In concept 800, the core matrix includes a Wi-Fi pattern (or a parity matrix like a Wi-Fi graphic), a plurality of truncated lines, and the remainder of the information matrix. This remainder of the information matrix can be designed using one of a plurality of degree distributions. For example, the core matrix can include 5 columns of bits and 20 rows of bits. One of the 20 rows of VN degrees may include one of the following: [2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,3,3],[2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[ 2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3], and [2,2,3,3 , 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3]. One of the five columns of Check Node (CN) degrees may include one of the following: [13, 10, 14, 17, 2], [13, 10, 13, 17, 2], [13, 10 ,13,18,3],[13,11,13,18,2],[13,10,14,18,2],[13,10,13,19,2],[14,10,13 ,18,1],[13,11,13,18,1],[13,10,14,18,1],[13,11,13,19,1],[13,10,13,18 , 2], and [13, 10, 13, 18, 1].

FIG. 9 is a schematic diagram of an example shift parameter design 900 in accordance with an embodiment of the present invention. For each spreading factor, there may be a shift value table comprising a corresponding plurality of shift values. These shift value tables for different spreading factors can be nested designed. In the shift parameter design 900, one of a plurality of spreading factors may be defined as being used for LDPC encoding. In the example shown in FIG. 9, the effective set of the plurality of spreading factors includes a plurality of spreading factors of the following different values: Z=16, Z=24, Z=32, Z=48, Z=64, Z= 96, Z=128, Z=192, Z=256 and Z=384. In shift parameter design 900, the active set of multiple spread factors can be optimized to obtain an optimized set of one of a plurality of spread factors. The number of spreading factors in the optimized set is less than the number of spreading factors in the active set. A table of shift values that are designed for a plurality of shift values that are closest to and less than or equal to the spread factor within the optimized set can be used. For example, a shift value table for a plurality of shift values designed for the spreading factor Z=32 can be shared by the spreading factor Z=48. Similarly, designed for the expansion factor Z=128 The shift value table can be shared by the spreading factor Z=192.

For illustrative purposes only and not limitation, in an LDPC codebook according to the present invention, Z is used. ,j {0, 1, 2, 3, 4, 5}, one of a plurality of expansion factors (Z) can be defined as four sets. The corresponding plurality of shift values may be represented using four shift parameter tables, which may correspond to shift parameters of the shift parameters {288, 352, 416, 480}. For any expansion factor Z=ax 2j within the effective set φ, the corresponding shift parameter can be transmitted through To obtain, where pm,n are the shift parameters of the (m,n)th element in the shift parameter table of â x 25, where â is the largest within {9,11,13,15} Value, â is less than or equal to a, and . In addition, f(Z) is a disturbance and is a function of Z and can be represented using a table.

Description of implementation

FIG. 10 is a schematic diagram of an example communication system 1000 in accordance with an embodiment of the present invention. The communication system can include a first device 1005 and a second device 1050, which can communicate with one another via a communication link 1040. Communication link 1040 may be a wireless link in some embodiments, or a wired link in other embodiments. Each of the first device 1005 and the second device 1050 can perform a variety of functions as a communication device to implement the concepts, mechanisms, techniques, operations, and methods described herein in connection with QC-LDPC encoding, including with the first Figures to some or all of the contents of Figure 9 and operations 1100, 1200, and 1300 described below. More specifically, each of the first device 1005 and the second device 1050 can be implemented with multiple built-in LDPC code designs, hybrid orthogonal LDPC layer design, very low bit rate QC-LDPC support, core matrix design, and shift parameters. Design aspects of the proposed concepts and mechanisms.

Each of the first device 1005 and the second device 1050 can be part of an electronic device, which can be a communication device, a computing device, a portable or mobile device, or a wearable device. For example, the first device 1005 can be implemented as a Wi-Fi access point, a smart phone, a smart watch, a smart bracelet, a smart necklace, a number of assistants, or a computing device. Set (such as a tablet, a laptop, a laptop, a desktop computer or a server). Similarly, the second device 1050 can be implemented as a Wi-Fi mobile client (client) or station, a smart phone, a smart watch, a smart bracelet, a smart necklace, and a number of assistants. Or a computing device (such as a tablet, a laptop, a laptop, a desktop computer, or a server). Alternatively, the first device 1005 and the second device 1050 may be implemented in the form of one or more integrated-circuit (IC) chips, such as but not limited to, one or more single-core processors, one or Multiple multi-core processors, or one or more Complex-Instruction-Set-Computing (CISC) processors.

Each of the first device 1005 and the second device 1050 may include at least some of the components shown in FIG. 10, respectively. For example, the first device 1005 can include at least one processor 1010, and the second device 1050 can include at least one processor 1060. In addition, the first device 1005 can include a memory 1020 and/or a transceiver 1030 configured to wirelessly transmit and receive data (eg, conforming to one or more 3GPP standards, protocols, specifications, and/or any applicable Wireless protocols and standards). Each of the memory 1020 and the transceiver 1030 can be communicably and operatively coupled to the processor 1010. Similarly, the second device 1050 can also include a memory 1070 and/or a transceiver 1080, wherein the transceiver 1080 is configured to wirelessly transmit and receive data (eg, conforming to the IEEE 802.11 specification and/or any applicable wireless protocol and standard). The memory 1070 and each of the transceivers 1080 can be communicably and operatively coupled to the processor 1060. Each of the first device 1005 and the second device 1050 may further include other components (eg, a power system, a display device, and a user interface device) that are not closely related to the mechanisms provided by the present invention and thus are not displayed This is illustrated in Figure 10 or here for simplification and simplification.

The transceiver 1030 can be configured to communicate wirelessly over a single frequency band or multiple frequency bands. The transceiver 1030 can include a transmitter 1032 and a receiver 1034, the transmitter 1032 can wirelessly transmit data, and the receiver 1034 can receive data wirelessly. Similarly, transceiver 1080 can be configured To perform wireless communication in a single frequency band or multiple frequency bands. The transceiver 1080 can include a transmitter 1082 and a transceiver 1084, the transmitter 1082 can wirelessly transmit data, and the receiver 1084 can receive data wirelessly.

Each of the memory 1020 and the memory 1070 can be a storage device configured to store one or more code, programs, and/or sets of instructions and/or stored therein. In the example shown in FIG. 10, memory 1020 stores one or more sets of processor-executable instructions 1022 and stored therein data 1024, and memory 1070 stores one or more of processor-executable instructions 1072. Collect and store the information 1074. Each of memory 1020 and memory 1070 can be implemented using suitable techniques and can include volatile memory and/or non-volatile memory. For example, each of the memory 1020 and the memory 1070 may include a type of random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), thyristor. Random access memory (Thyristor RAM, T-RAM) and / or zero capacitance random access memory (Z-RAM). Alternatively or additionally, each of the memory 1020 and the memory 1070 may include a type of read only memory (ROM), such as a mask-type read ROM (ROM), a programmable ROM (PROM), Erasable programmable ROM (EPROM) and/or electrically erasable programmable ROM (EEPROM). Alternatively or additionally, each of the memory 1020 and the memory 1070 may include a non-Volatile Random-Access Memory (NVRAM) such as a flash memory, a solid state memory, or a ferroelectric Random access memory (Ferroelectric RAM, FeRAM), magnetoresistive random access memory (MRAM) and/or phase-change memeory.

In one aspect, each of processor 1010 and processor 1060 can be implemented in the form of one or more single core processors, one or more multi-core processors, or one or more CISC processors. In other words, even though a singular "one processor" is used herein to refer to each of processor 1010 and processor 1060, each of processor 1010 and processor 1060 may be included in some embodiments in accordance with the present invention. A plurality of processors, and a single processor in still other embodiments in accordance with the invention. In another aspect, each of the processor 1010 and the processor 1060 can be implemented as a usage configuration and used in real In the form of hardware (and, optionally, firmware) of a plurality of electronic components according to the specific objects of the present invention, such electronic components may be, for example but not limited to, one or more transistors, one or more diodes One or more capacitors, one or more resistors, one or more inductors, one or more memristors, or one or more varactors. In other words, in at least some embodiments, each of processor 1010 and processor 1060 is a special purpose machine specifically designed, arranged, and configured to perform the specifics including QC-LDPC encoding in accordance with various embodiments of the present invention. task.

The processor 1010, as a special purpose machine, may include non-universal and specially designed hardware circuits that are designed and configured to perform specific tasks associated with QC-LDPC encoding in accordance with various embodiments of the present invention. In one aspect, processor 1010 can execute one or more sets of code, programs, and/or instructions 1022 stored in memory 1020 to perform multiple operations to generate QC-LDPC encoding in accordance with various embodiments of the present invention. . In another aspect, processor 1010 can include an encoder 1012 and a decoder 1014 that are combined with decoder 1014 for performing a plurality of specific tasks to generate QC-LDPC encoding in accordance with various embodiments of the present invention. . For example, encoder 1012 can be configured to encode data in accordance with a number of concepts and mechanisms of the present invention. Similarly, decoder 1014 can be configured to decode data in accordance with a number of concepts and mechanisms of the present invention.

The processor 1060, as a special purpose machine, may include non-universal and specially designed hardware circuits that are designed and configured to perform particular tasks associated with QC-LDPC encoding in accordance with various embodiments of the present invention. In one aspect, processor 1060 can execute one or more sets of code, programs, and/or instructions 1072 stored in memory 1070 to perform multiple operations to generate QC-LDPC encoding in accordance with various embodiments of the present invention. . In another aspect, processor 1060 can include an encoder 1062 and a decoder 1064 that are combined together to perform a plurality of specific tasks to generate QC-LDPC encoding in accordance with various embodiments of the present invention. . For example, encoder 1062 can be configured to encode data in accordance with a number of concepts and mechanisms of the present invention. Likewise, decoder 1064 can be configured to decode data in accordance with a number of concepts and mechanisms of the present invention.

Each of the first device 1005 and the second device 1050 can be configured to implement each of the operations 1100, 1200, and 1300 described below. Therefore, to avoid redundancy and brevity, multiple operations of the first device 1005 and the second device 1050, as well as the processor 1010 and the processor 1060, are described below with operations 1100, 1200, and 1300. It should be noted that although the following description provides a textual description of the first device 1005, the following description is equally applicable to the second device 1050.

11 is a schematic diagram of an example operation 1100 in accordance with an embodiment of the present invention. Operation 1100 may represent one aspect of implementing the concepts and mechanisms provided by the present invention, for example, relating to some or all of Figures 1 through 9. More specifically, operation 1100 can represent a number of concepts and mechanisms provided by the present invention related to multiple built-in LDPC code designs and shift parameter designs. Operation 1100 can include one or more operations, actions, or functions as displayed by one or more of blocks 1110, 1120, 1130, and 1140. Although shown as separate blocks, depending on implementation requirements, multiple blocks of operation 1100 may divide additional blocks, combine into fewer blocks, or omit portions of the blocks. Moreover, the plurality of blocks/sub-blocks of operation 1100 may be performed in the order shown in FIG. 11, or may be replaced with a different order. Operation 1100 can be implemented by communication system 1000 and any variations thereof. For example, operation 1100 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. Operation 1100 is described below with first device 1005 for purposes of illustration and not limitation of the scope of the invention. Operation 1100 can begin at block (step) 1110.

In step 1110, operation 1100 can include the processor 1010 of the first device 1005 generating a QC-LDPC code including one of a plurality of built-in codebooks. Operation 1100 can proceed from step 1110 to 1120.

In step 1120, operation 1100 can include the processor 1010 selecting a codebook from the plurality of codebooks. Operation 1100 can proceed from step 1120 to step 1130.

In step 1130, operation 1100 can include the processor 1010 encoding the data using the selected codebook. Operation 1100 can proceed from step 1130 to step 1140.

In step 1140, operation 1100 can include: processor 1010 transmitting through transceiver 1030 The encoded data is sent (e.g., sent to the second device 1050).

In some embodiments, each of the plurality of codebooks may each correspond to one of a plurality of HARQ threads, the plurality of HARQ threads being different.

In some embodiments, when generating a QC-LDPC code having a plurality of built-in codebooks, operation 1100 can include: processor 1010 generating the QC-LDPC code, the QC-LDPC code including a base matrix and a shift Parameter matrix. The basic matrix may include a parity matrix and an information matrix, wherein the parity matrix includes a plurality of parity bits, and the information matrix includes a plurality of information bits. Each of the plurality of codebooks may include the co-located matrix and a portion of a corresponding respective size in the information matrix such that the plurality of codebooks have different sizes.

In some embodiments, each of the plurality of codebooks can each be designed corresponding to one of a plurality of designs of the shift parameter matrix.

In some embodiments, when generating a QC-LDPC code having a plurality of built-in codebooks, the operation 1100 can include the processor 1010 generating one of each of the first set of the plurality of spreading factors. Shift value table. Moreover, operation 1100 can include the processor 1010 optimizing the first set of the plurality of spreading factors to generate a second set of the plurality of spreading factors. The number of the plurality of spreading factors of the first set may be greater than the number of the plurality of spreading factors of the second set. One of the first spreading factors present in the first set but not present in the second set may share a shift value table that is present in both the first set and the second set of one of the second set. The second spreading factor is likely to be numerically less than the first spreading factor and is closer to the first spreading factor than the other spreading factors in the first set.

In some embodiments, when the codebook is selected from the plurality of codebooks, operation 1100 can comprise, based on one of an initial code rate for data transmission, a code block size of the data, or both, processor 1010 The codebook is selected from the plurality of codebooks.

In some embodiments, when the codebook is selected from the plurality of codebooks, operation 1100 can be To include: The processor 1010 performs a number of operations (eg, similar to the operations included in the logic flow 200). For example, operation 1100 can include the processor 1010 determining whether the code block size of the data is less than a threshold block size. When the code block size of the data is less than the threshold code block size, in response, operation 1100 can include the processor 1010 selecting one of the plurality of codebooks and the third codebook. When the code block size of the data is not less than the threshold code block size, in response, operation 1100 can include the processor 1010 determining whether an initial code rate for one of the data transmissions is greater than a threshold rate. When the initial code rate is not greater than the threshold rate, in response, operation 1100 can include the processor 1010 selecting one of the plurality of codebooks and the second codebook. When the initial code rate is greater than the threshold rate, in response, operation 1100 can include the processor 1010 selecting one of the plurality of codebooks for the first codebook. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.

Alternatively or additionally, when the codebook is selected from the plurality of codebooks, operation 1100 can include the processor 1010 performing a plurality of other operations. For example, operation 1100 can include the processor 1010 determining a code block size for the data. Based on the result of the decision, operation 1100 can include the processor 1010 selecting a first codebook of the plurality of codebooks as a response to determine that the code block size is greater than a first threshold code block size. Additionally, operation 1100 can include the processor 1010 selecting a second codebook of the plurality of codebooks as a response to determine that the code block size is greater than a second threshold code block size. Moreover, operation 1100 can include the processor 1010 selecting a third codebook of the plurality of codebooks as a response to determine that the code block size is greater than a third threshold code block size. The size of the first threshold block is greater than the size of the second threshold block. The second threshold code block size may be larger than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.

Figure 12 is a schematic illustration of an example operation 1200 in accordance with an embodiment of the present invention. Operation 1200 may represent one aspect of implementing the various concepts and mechanisms provided by the present invention, such as those described in connection with some or all of Figures 1 through 9. More specifically, operation 1200 can represent orthogonal to hybrid The LDPC layer design and the extremely low bit rate QC-LDPC support one aspect of the various concepts and mechanisms proposed by the present invention. Operation 1200 can include one or more of the operations, actions, or functions illustrated by one or more of blocks 1210, 1220, and 1230. Although shown as separate blocks, depending on implementation requirements, multiple blocks of operation 1200 may divide additional blocks, combine into fewer blocks, or omit portions of the blocks. Moreover, the plurality of blocks/sub-blocks of operation 1200 may be performed in the order shown in FIG. 12, or may be performed in other different orders. Operation 1200 can be implemented by communication system 1000 and any variations thereof. For example, operation 1200 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. The description of operation 1200 is provided below with the textual description of first device 1005 for illustrative purposes only and not for limiting the scope of the invention. Operation 1200 can begin at block (step) 1210.

In step 1210, operation 1200 can include the processor 1010 of the first device 1005 generating a QC-LDPC code, the QC-LDPC code including at least one type of column orthogonal layer. Operation 1200 can proceed from step 1210 to step 1220.

In step 1220, operation 1200 can include the processor 1010 encoding the data using the QC-LDPC code. Operation 1200 can proceed from step 1220 to step 1230.

In step 1230, operation 1200 can include the processor 1010 transmitting the encoded data (eg, to the second device 1050) via the transceiver 1030.

In some embodiments, the at least one type of column orthogonal layer may include a plurality of columns of a plurality of columns and a plurality of rows, and the one or more rows of the plurality of rows of the at least listed column orthogonal layer may include positive At least one truncated line with a degree of intersection of 2 or higher. The remaining rows of the plurality of rows of the at least one type of column orthogonal layer may include non-truncated rows having an orthogonality of 1 or 0.

In some embodiments, there may be no loops within multiple truncated rows.

In some embodiments, the QC-LDPC code can include a hybrid orthogonal design having portions of different orthogonalities. One of the plurality of portions of low orthogonality has A second portion of the plurality of portions that may correspond to a high code rate, high orthogonality, may correspond to a low code rate.

In some embodiments, the plurality of portions of different orthogonalities comprise some or all of the following: (1) a non-column orthogonal portion comprising a plurality of columns and a plurality of rows, the plurality of columns forming the plurality of rows At least one non-column orthogonal layer; (2) a type of column orthogonal portion comprising a plurality of columns and a plurality of rows, the plurality of columns forming at least one type of column orthogonal layer with the plurality of rows; and (3) a pure column The orthogonal layer includes a plurality of columns and a plurality of rows, and the plurality of columns and the plurality of rows form at least one pure column orthogonal layer. The plurality of rows of the non-column orthogonal portion may include at least one truncated row having an orthogonality of 2 or higher and a plurality of non-truncated rows having an orthogonality of 1 or 0. One or more of the plurality of rows of the orthogonal portion of the class of columns may include at least one truncated row having an orthogonality of 2 or higher. The plurality of remaining rows of the plurality of rows of the orthogonal portion of the column may include a plurality of non-truncated rows having an orthogonality of 1 or 0. Each of the plurality of rows of the pure column orthogonal portion may include one row having an orthogonality of 1 or 0.

In some embodiments, the QC-LDPC code can include a parity matrix and an information matrix, wherein the parity matrix includes a plurality of parity bits, and the information matrix includes a plurality of information bits. The information matrix and one or more columns in the co-located matrix may include one or more columns with a bit orthogonality of 2 per column.

In some embodiments, each of the plurality of bits having an orthogonality of 2 and the one or more columns having a degree of orthogonality of 2 may include a previously used parity bit or a previously transmitted information bit. yuan.

Figure 13 is a schematic illustration of an example operation 1300 in accordance with an embodiment of the present invention. Operation 1300 may represent one of a number of concepts and mechanisms proposed by the present invention, such as related to some or all of Figures 1 through 9. More specifically, operation 1300 can represent one of a number of concepts and mechanisms proposed by the present invention related to core matrix design. Operation 1300 can include one or more operations, actions, or functions as illustrated by one or more of blocks 1310, 1320, and 1330. Although shown as separate blocks, depending on implementation requirements, multiple blocks of operation 1300 may divide additional blocks, combine into fewer blocks, or omit portions of the blocks. In addition, multiple blocks/subblocks of operation 1300 may be in accordance with The order shown in Figure 13 is performed, or it can be performed in other different orders. Operation 1300 can be implemented by communication system 1000 and any variations thereof. For example, operation 1300 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. The description of operation 1300 is provided below with the textual description of first device 1005 for illustrative purposes only and not for limiting the scope of the invention. Operation 1300 can begin at block (step) 1310.

In step 1310, operation 1300 may include: the processor 1010 of the first device 1005 generates a QC-LDPC code, the QC-LDPC code includes a basic matrix, and a portion of the basic matrix forms a core matrix, the core matrix corresponding to Has a code rate of at least one threshold. Operation 1300 can proceed from step 1310 to step 1320.

In step 1320, operation 1300 can include the processor 1010 encoding the data using the QC-LDPC code. Operation 1300 can proceed from step 1320 to step 1330.

In step 1330, operation 1300 can include the processor 1010 transmitting the encoded data (eg, to the second device 1050) via the transceiver 1030.

In some embodiments, the code rate can be 0.89.

In some embodiments, the core matrix can include multiple columns of multiple columns and multiple rows. Two or more of the plurality of rows may include a plurality of truncated rows having a particular pattern of one of the plurality of bits.

In some embodiments, after any number of row permutations and/or column permutations (eg, at least one row permutation, at least one column permutation, or any combination of the two), the plurality of truncated rows are separated by a plurality of bits The particular pattern can include one or more bits 0 within the plurality of truncated lines. Two examples of a particular pattern comprising one or more bits 0 after row permutation and/or column permutation are shown in part (A) of Figure 7. In some embodiments, the specific pattern of the plurality of bits in the plurality of truncated lines may include one of a plurality of bit 0 isosceles right triangles, and the right angle of the triangle corresponds to one of the plurality of truncated lines One of the bits at the corner is 0. One of the plurality of bits 0 is an example of an isosceles right triangle as shown in Figure 7 (B) is shown.

In some embodiments, the core matrix can include a co-located matrix that includes a plurality of columns of a plurality of columns and a plurality of rows. The core matrix may also include an information matrix comprising a plurality of columns of a plurality of columns and a plurality of rows. The parity matrix can include a matrix having a Wi-Fi pattern. In addition to the plurality of truncated lines of the core matrix, more than one column of the information matrix may include a plurality of columns having a high density bit 1 and no or only one bit 0. The plurality of columns of the high density bits may correspond to a plurality of columns of the Wi-Fi pattern.

In some embodiments, the bottom column of one of the plurality of columns of the plurality of columns can include the first number of bits 1. The first number may be equal to the number of the plurality of truncated lines or greater than the number of the plurality of truncated lines by 1, 2 or 3 (eg, larger). In some embodiments, the first number of the plurality of bits 1 in the bottom column may correspond to the plurality of truncated lines and one of the rightmost rows of the core matrix, wherein the core matrix and the Wi-Fi pattern A right hand is handed over.

In some embodiments, the core matrix can include 5 columns of bits and 20 rows of bits. One of the 20 rows of VN degrees may include one of the following: [2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,3,3],[2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[ 2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] and [2,2,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]. One of the five columns of detection nodes may include one of the following:: [13, 10, 14, 17, 2], [13, 10, 13, 17, 2], [13, 10, 13, 18, 3], [13,11,13,18,2],[13,10,14,18,2],[13,10,13,19,2],[14,10,13,18,1] , [13,11,13,18,1],[13,10,14,18,1],[13,11,13,19,1],[13,10,13,18,2] and [ 13,10,13,18,1].

Figure 14 is a schematic illustration of an example operation 1400 in accordance with an embodiment of the present invention. Operation 1400 may represent one of a number of concepts and mechanisms proposed by the present invention, such as those described in connection with FIG. More specifically, operation 1400 can represent one of a number of concepts and mechanisms proposed by the present invention related to shift parameter design. Operation 1400 can include, for example, blocks 1410, 1420, and 1430, and sub-areas One or more of the operations, actions or functions illustrated by one or more of blocks 1412 and 1414. Although shown as separate blocks, depending on implementation requirements, multiple blocks of operation 1400 may divide additional blocks, combine into fewer blocks, or omit portions of the blocks. Moreover, the plurality of blocks/sub-blocks of operation 1400 may be performed in the order shown in FIG. 14, or may be performed in other different orders. Operation 1400 can be implemented by communication system 1000 and any variations thereof. For example, operation 1400 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. The description of operation 1400 is provided below in the text of first device 1005 for illustrative purposes only and not for limiting the scope of the invention. Operation 1400 can begin at block (step) 1410.

In step 1410, operation 1400 can include the processor 1010 of the first device 1005 generating a QC-LDPC code. Operation 1400 can proceed from step 1410 to step 1420.

In step 1420, operation 1400 can include the processor 1010 encoding the data using the QC-LDPC code. Operation 1400 can proceed from step 1420 to step 1430.

In step 1430, operation 1400 can include the processor 1010 transmitting the encoded data (e.g., to the second device 1050) via the transceiver 1030.

In generating the QC-LDPC code, operation 1400 can include the processor 1010 performing a plurality of operations represented by the sub-blocks (steps) 1412 and 1414.

In step 1412, operation 1400 can include the processor 1010 generating a respective one of a shift value table for each of the first set of the plurality of spread factors, the shift value table including a plurality of shift values. Operation 1400 can proceed from step 1412 to step 1414.

In step 1414, operation 1400 can include the processor 1010 optimizing the first set of the plurality of spreading factors to generate a second set of the plurality of spreading factors.

The number of one of the plurality of spreading factors in the first set is likely to be greater than the number of one of the plurality of spreading factors of the second set. One of the first spreading factors present in the first set but not in the second set may share one of the second spreading factors present in the first set and the second set Bit value table. The second spreading factor may be numerically less than the first spreading factor and closer to the first spreading factor than other spreading factors in the first set.

Supplementary explanation

The substance described herein is sometimes shown as distinct components, which may be included or coupled to different other components. It should be understood that the architectures described herein are merely illustrative and may be implemented in various other architectures that perform the same functions. At the conceptual level, multiple components of any arrangement that perform the same function are effectively "associated" to achieve the desired functionality. Therefore, any two components herein combined to achieve a particular function can be seen as "associated" with each other to achieve the desired functionality, regardless of its architecture or intermediate components. Similarly, any two components so associated can also be considered as "operably connected" or "operably coupled" to each other to achieve the desired functionality. Specific embodiments of operative coupling include, but are not limited to, physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components And/or logically interacting and/or logically interactable components.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

Claims (12)

An encoding method includes: generating a type of cyclic low-density parity check code, the cyclic low-density parity check code having a plurality of built-in codebooks, wherein different codebooks in the plurality of codebooks correspond to different shift parameters Designing; selecting a codebook from the plurality of codebooks; and encoding the data using the selected codebook. The encoding method according to claim 1, wherein the basic matrix comprises one of a plurality of parity bits and one information matrix of the plurality of information bits, and wherein each of the plurality of codebooks The portion includes the part of the parity matrix corresponding to one of the information matrices, so that the sizes of the plurality of codebooks are different. The encoding method of claim 1, wherein the step of selecting the codebook from the plurality of codebooks comprises: transmitting an initial code rate based on the data transmission, a code block size of the data, or a combination of the two And selecting the codebook from the plurality of codebooks. The encoding method of claim 1, wherein the step of selecting the codebook from the plurality of codebooks comprises: determining whether a code block size of the data is smaller than a threshold size; and responding to the data The code block size is smaller than the threshold code block size, and the selection is more a third codebook of the codebook; the size of the code block in response to the data is not less than the size of the threshold code block, determining whether an initial code rate of the data transmission is greater than a code rate; in response to the initial code rate No more than the threshold rate, selecting a second codebook of the plurality of codebooks; and selecting a first codebook of the plurality of codebooks in response to the initial code rate being greater than the threshold code rate, wherein the first codebook One of the codebooks has a size larger than one of the second codebooks, and wherein the size of the second codebook is greater than one of the third codebooks. The encoding method of claim 1, wherein the step of selecting the codebook from the plurality of codebooks comprises: determining a code block size of the data; and selecting the codebook by: determining the When the code block size is greater than a first threshold code block size, in response, selecting a first codebook of the plurality of codebooks; when determining that the code block size is greater than a second threshold code block size, in response, selecting the a second codebook of the plurality of codebooks; when determining that the code block size is greater than a third threshold code block size, selecting a third codebook of the plurality of codebooks, wherein the first threshold code block size is greater than The second threshold code block size, wherein the second threshold code block size is greater than the third threshold code block size. An encoding method comprising: Generating a cyclic low-density parity check code having a plurality of built-in codebooks, wherein different codebooks in the plurality of codebooks correspond to different shift parameter designs; and using the class The cyclic low-density parity check code encodes the data, wherein the generating of the cyclic low-density parity check code further comprises: generating a shift of each of the first set of the plurality of spreading factors a value table; and optimizing the first set of the plurality of spreading factors to generate a second set of one of the plurality of spreading factors, wherein a total of one of the expansion factors of the first set is greater than a total of one of the second set The first spreading factor shares a shifting value table of a second spreading factor, wherein the first spreading factor is present in the first set but not in the second set, and the second spreading factor is simultaneously Between the first set and the second set, and wherein the second spreading factor is numerically less than the first spreading factor and compared to other spreading factors in the first set Closer to the first spreading factor. An encoding method includes: generating a cyclic low-density parity check code, the cyclic low-density parity check code having a plurality of built-in codebooks, wherein different codebooks in the plurality of codebooks correspond to different shift parameters Designed, the cyclic low density parity check code comprises at least one type of column orthogonal layer; The data is encoded using this type of cyclic low density parity check code. The encoding method of claim 7, wherein the at least one type of column orthogonal layer comprises a plurality of columns and a plurality of rows, wherein one of the plurality of columns of the at least one type of column orthogonal layer Or a plurality of columns comprising at least one truncated row having an orthogonality of 2 or more, and wherein the at least one type of column orthogonal layer comprises a plurality of non-truncated rows having an orthogonality of 1 or 0. According to the coding method of claim 7, wherein the cyclic low density parity check code comprises a hybrid orthogonal design, the hybrid orthogonal design comprising multiple parts of different orthogonalities, wherein a low degree positive The first portion of the plurality of portions corresponds to a high code rate, and wherein a second portion of the plurality of portions orthogonal to a height corresponds to a low code rate. The encoding method of claim 9, wherein the plurality of portions of different orthogonalities comprise: a non-column orthogonal portion comprising a plurality of columns and a plurality of rows, the plurality of columns forming the plurality of rows At least one non-column orthogonal layer; a type of column orthogonal portion comprising a plurality of columns and a plurality of rows, the plurality of columns and the plurality of rows forming the at least one type of column orthogonal layer; and a pure column orthogonal portion, including a plurality of columns and a plurality of rows, the plurality of columns forming at least one pure column orthogonal layer, wherein the plurality of rows of the non-column orthogonal portions comprise at least one of orthogonality of 2 or more Truncated lines and multiple non-truncated lines with an orthogonality of 1 or 0. An encoding method includes: generating a type of cyclic low-density parity check code, the cyclic low-density parity check code having a plurality of built-in codebooks, wherein different codebooks in the plurality of codebooks correspond to different shift parameters The cyclic low-density parity check code comprises a basic matrix, a portion of the basic matrix forming a core matrix, the core matrix corresponding to a code rate of at least one threshold; and using the cyclic low-density parity check The code encodes the data, wherein the core matrix comprises a plurality of columns and a plurality of bits of the plurality of rows, wherein two or more of the plurality of rows comprise a plurality of truncated rows, the plurality of truncated rows having A specific pattern of one of a plurality of bits. The encoding method of claim 11, wherein the specific pattern of the plurality of bits in the plurality of truncated lines comprises one or more bits 0, the one or more bits 0 being located Over or under at least one row of permutations, at least one column permutation, or both of the truncated rows.