CN110741554A - Shift coefficient table design for large code block size QC-LDPC codes in mobile communications - Google Patents

Abstract

A processor of a device establishes a wireless communication link with at least other devices via a transceiver of the device, the processor wirelessly communicates with the other devices via the wireless communication link by selecting a th table of shift coefficients from a plurality of tables of shift coefficients, selecting a th table of shift coefficients from the plurality of tables of shift coefficients, generating a quasi-cyclic low density parity check (QC) -LDPC code using a base matrix and a th table of shift coefficients of at least portions, selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code, storing the selected codebook to a memory associated with the processor, encoding data using the selected codebook to generate a plurality of modulation symbols for the data, controlling the transceiver to multiplex, convert, filter, amplify, and radiate the modulation symbols as electromagnetic waves through or more antennas of the device to transmit modulation signals for the data to the other devices via the wireless communication link.

Description

Shift coefficient table design for large code block size QC-LDPC codes in mobile communications

Cross-referencing

This application claims priority to US provisional patent application No. 62/525,797 filed on 28.6.2017 and is part of the part-on-part (CIP) application No. 15/594,239 filed on 12.5.2017.

Technical Field

The present invention relates generally to mobile communications, and more particularly to a shift coefficient table design for quasi-cyclic low-density parity-check (QC-LDPC) codes for larger code block sizes in mobile communications.

Background

Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims set forth below and are not admitted to be prior art by inclusion in this section.

The third generation partnership project (3GPP) has approved a plan to accelerate the development of fifth generation (5G) New Radio (NR) specifications, and thus it is expected that standards-based 5G NR wireless communication services will be launched in the near future. 3GPP also agrees that QC-LDPC will be used for the 5G NR data channel. However, details on how QC-LDPC based encoding (e.g., encoding and decoding) may be implemented have not been defined.

Disclosure of Invention

The following summary is provided to introduce concepts, points, benefits and advantages of the novel and non-obvious technology described herein, the following detailed description further describes select implementations.

In aspects, a method of wireless communication may involve a processor of a device establishing a wireless communication link with at least other devices via a transceiver of the device, the method may also involve the processor wirelessly communicating with the other devices via the wireless communication link by (a) selecting a th table of shift coefficients from a plurality of tables of shift coefficients, (b) generating a QC-LDPC code using a base matrix and at least a portion of a th table of shift coefficients, (c) selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code, (d) storing the selected codebook to a memory associated with the processor, (e) encoding data using the selected codebook to generate a plurality of modulation symbols for the data, and (f) controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through or more antennas of the device for transmission of modulation symbols for the data to the other devices via the wireless communication link, the codebook when the 8292 th table of shift coefficients is selected from the plurality of tables of shift coefficients, the coefficient tables, the method further comprising processing the code block 28 and the coefficient table at least 4934 size of the plurality of code rate related data according to the code rate rule of the plurality of coefficients.

It is worthy to note that although the following description of the proposed scheme and various examples is provided in the context of 5G NR wireless communications, the proposed concept, scheme and any variants/derivatives thereof may be implemented in communications, depending on other protocols, standards and specifications to which the implementation is applicable. Accordingly, the scope of the proposed solution is not limited by the description provided herein.

Drawings

The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of the application, the drawings illustrating embodiments of the application and together with the description serve to explain the principles of the application, it being understood that the drawings are not to scale and that are shown not to scale with the dimensions in actual implementation to clearly illustrate the concepts of the application.

FIG. 1 is a schematic diagram of an exemplary multi-codebook embedded LDPC code design based on embodiments of the present application;

FIG. 2 is a schematic diagram of an example logic flow associated with a multi-codebook embedded LDPC code in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of an exemplary quasi-row (quad-row) orthogonal layer design, based on embodiments of the present application;

FIG. 4 is a schematic diagram of an exemplary hybrid (hybrid) orthogonality layer design, according to an embodiment of the present application;

FIG. 5 is a diagram of an exemplary QC-LDPC code supporting very low code rates, according to an embodiment of the present application;

FIG. 6 is an exemplary core (kernel) matrix design based on embodiments of the present application;

FIG. 7 is a schematic diagram of an exemplary concept of a core fundamental matrix based on embodiments of the present application;

FIG. 8 is a schematic diagram of an exemplary concept of a core fundamental matrix based on another embodiment of the present application;

FIG. 9 is a schematic diagram of an exemplary shift coefficient design based on embodiments of the present application;

fig. 10 is a block diagram of an exemplary communication system in accordance with an embodiment of the present application;

FIG. 11 is a flow chart of an exemplary process in accordance with an embodiment of the present application;

FIG. 12 is a flow chart of an exemplary process based on another embodiment of the present application;

FIG. 13 is a flow chart of an exemplary process based on another embodiment of the present application;

FIG. 14 is a flow chart of an exemplary process based on another embodiment of the present application;

each of fig. 15(a) and 15(B) is a schematic diagram of a partial exemplary shift coefficient table according to an embodiment of the present application;

16(A) and 16(B) are schematic diagrams of a partial exemplary shift coefficient table based on an embodiment of the present application for every ;

17(A) and 17(B) are schematic diagrams of a partial exemplary shift coefficient table based on an embodiment of the present application for every ;

each bits in fig. 18(a) and 18(B) are schematic diagrams of a partial exemplary shift coefficient table according to an embodiment of the present application;

fig. 19(a) and 19(B) are schematic diagrams of each partial exemplary shift coefficient tables according to the embodiment of the present application;

each of fig. 20(a) and 20(B) is a schematic diagram of a partial exemplary shift coefficient table according to an embodiment of the present application;

fig. 21(a) and 21(B) are schematic diagrams of each partial exemplary shift coefficient tables according to the embodiment of the present application;

22(A) and 22(B) are schematic diagrams of a partial exemplary shift coefficient table based on an embodiment of the present application for every ;

FIG. 23 is a schematic diagram of an exemplary logic flow for selecting a shift coefficient table in accordance with an embodiment of the present application;

fig. 24 is a flow chart of an exemplary process based on another embodiment of the present application.

Detailed Description

Detailed examples and embodiments of the claimed subject matter are disclosed herein. However, it is to be understood that the disclosed embodiments and implementations are merely illustrative of the claimed subject matter, which can be embodied in various forms. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In the following description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

SUMMARY

The proposed concepts and schemes relate generally to the fields of multi-codebook embedded LDPC code design, hybrid orthogonal LDPC layer design, QC-LDPC support for very low Code Rate (CR), core (kernel) matrix design, and shift coefficient design.

FIG. 1 illustrates an exemplary multi-codebook embedded LDPC code design according to an embodiment of the present invention. Referring to fig. 1, a basic parity check matrix (interchangeably referred to herein as a "basic matrix") 100 of a QC-LDPC code according to the present invention may have a plurality of codebooks embedded therein.

As shown in FIG. 1, the base matrix 100 may include a parity matrix (parity matrix) of a plurality of parity bits and an information matrix of a plurality of information bits, in other words, the base matrix 100 may be defined by a parity matrix and an information matrix, wherein the parity matrix has relatively few non-zero/non-null bits (each represented by "1" in FIG. 1) and most zero/null bits (each represented by "0" in FIG. 1). The parity matrix may further define sets of linear constraints on code bits. accordingly, each of a plurality of codebooks embedded in the QC-LDPC code of the base matrix 100 may include a parity matrix and a corresponding portion of an information matrix of a corresponding size such that the sizes of the plurality of codebooks are different from each other.

Codebook (I1 or I2 or I3) + P

The label "I1" denotes the th part of the information matrix, the label "I2" denotes the second part of the information matrix, the label "I3" denotes the third part of the information matrix, and the label "P" denotes the parity matrix, where the size of I1 (e.g., in terms of number of bits and/or size of memory) is larger than the size of I2, and the size of I2 is larger than the size of I3.

It is noted that while the embodiment shown in FIG. 1 depicts three codebooks of varying sizes formed as a result of the combination of I1+ P, I2+ P, and I3+ P, the number of codebooks of varying sizes is not limited to three (possibly less than three or more than three) in accordance with various embodiments of the present invention.

In embodiments, each of a plurality of codebooks may correspond to a respective HARQ thread of a plurality of hybrid automatic repeat request (HARQ) threads (threads), wherein the plurality of HARQ threads are different from each other, for example, the codebook may correspond to the HARQ thread, the codebook ranging from 0.33 to 0.89. the second codebook may correspond to the second HARQ thread, the second codebook ranging from 0.2 to 0.66. the third codebook may correspond to the third HARQ thread, the third codebook having a small code block size of less than 400. therefore, in HARQ based communications between two communication devices, each of the plurality of HARQ threads may be associated or otherwise associated with a respective one of the plurality of codebooks. therefore, a respective one of of the plurality of codebooks may be selected to identify of the plurality of codebooks for encoding HARQ data.

In embodiments, each of a plurality of codebooks corresponds to a respective store (memory) size (Kb) in or more registers, or more buffers, or more buffers (caches), and/or or more storage units, for example, the th codebook may correspond to the th store size Kb 16. the second codebook may correspond to the second store size Kb 12. the third codebook may correspond to the third store size Kb 5. in the proposed solution according to the invention, if a large codebook corresponding to a large store (memory) size is not necessary for encoding (e.g., because the codeblock size of the data to be encoded is relatively large, or because the initial code rate is relatively high), a small codebook corresponding to a small store size may be selected for encoding.

In embodiments, all codebooks may share base matrices, with different zero-padding (zero-padding) sizes in embodiments, different codebooks may correspond to different shift coefficient designs or share shift coefficient designs.

In some embodiments , if a large codebook corresponding to a large amount of coding processing delay is not necessary for encoding, to shorten the processing delay of encoding in a communication device, the codebook is selected such that a small codebook requiring a small amount of coding processing delay is encoded.

FIG. 2 illustrates an example logic flow 200 related to multi-codebook embedded LDPC code design based on embodiments of the present invention the logic flow 200 may be implemented in or by an encoder or a processor to implement various features and/or aspects of the concepts and/or schemes presented by the present invention more particularly, the logic flow 200 may involve or more rules for use in selecting a codebook from a plurality of codebooks embedded in a base matrix of a QC-LDPC code such that a small codebook requiring a small amount of processing delay to encode is selected if a large codebook having a large amount of processing delay corresponding to encoding is not necessary for encoding the logic flow 200 may include 32 or more operations, actions or functions represented by or more of blocks 210,220,230,240, and 250.

At 210, the logic flow 200 may involve the second device 1050 determining whether a code block size of the data to be encoded is less than a threshold code block size. Logic flow 200 may execute from 210 to 220 where it is determined that the code block size of the data is less than the threshold code block size. Logic flow 200 may proceed from 210 to 230 where it is determined that the code block size of the data is not less than the threshold code block size.

At 220, the logic flow 200 may involve the second device 1050 selecting an th codebook of the plurality of codebooks.

At 230, logic flow 200 may involve second device 1050 determining whether an initial code rate for transmitting data is greater than a threshold code rate. Logic flow 200 may proceed from 230 to 240 where it is determined that the initial code rate is not greater than the threshold code rate. Logic flow 200 may proceed from 230 to 250 where it is determined that the initial code rate is greater than the threshold code rate.

At 240, logic flow 200 may involve second means 1050 selecting a second codebook of the plurality of codebooks.

At 250, logic flow 200 may involve second device 1050 selecting a third codebook of the plurality of codebooks.

In this regard, the size of the third codebook is larger than the size of the second codebook, in addition, the size of the second codebook is larger than the size of the codebook, so if a large codebook corresponding to a large memory size (e.g., a code block size larger than a threshold code block size or an initial code rate larger than a threshold code rate) is not necessary for encoding, the logic flow 200 will select a small codebook corresponding to a small memory size, thereby minimizing the amount of memory or memory size used to store the selected codebook.

Fig. 3 shows an exemplary quasi-row (quadrature-row) orthogonal layer design 300 based on an embodiment of the present invention the Orthogonality (Orthogonality) contributes to the throughput (throughput) efficiency of the LDPC decoder in LDPC codes, several rows (row) may be grouped together to form a layer, and the degree of each columns (column) in the layer may be 1 or 0 (i.e., Orthogonality).

Referring to fig. 3, in a quasi-row orthogonal layer design 300, several rows may be grouped together at to form quasi-row (quasi-row) orthogonal layers, such as layer 1, layer 2, layer 3, and layer 4 shown in fig. 3. in this example, in addition to or more perforated columns (puncuted columns), each column (column) in each of layers 1,2, 3, and 4 may be either degree 1 or 0 (i.e., orthogonality). in the example shown in part (a) of fig. 3, the two leftmost columns (columns) are perforated columns in each of the other columns (columns) in each of layers 1,2, 3, and 4 are either degree 1 or 0 (i.e., have or 0 non-zero/non-null bits, denoted by "1", and the other null bits are zero/0, and the other is advantageously used to improve the efficiency of the quasi-row design 300.

Also, in quasi-orthogonal layer design 300, there are no rings (circles) in the perforated columns in the quasi-orthogonal layer. In the example shown in part (B) of fig. 3, according to the present invention, since there are rings in two perforated columns (columns), the corresponding layer is not considered as a quasi-row orthogonal layer.

Fig. 4 is an exemplary hybrid orthogonal layer design 400 shown based on an embodiment of the invention in the hybrid orthogonal layer design 400, the QC-LDPC code may include multiple portions (locations) of different degrees of orthogonality in the example shown in fig. 4, the darker colored block represents bit 1 and the lighter colored block represents bit 0. for example, the th portion of the multiple portions may be low degree orthogonal and may correspond to a high code rate.

In the example shown in FIG. 4, the plurality of portions of different orthogonal degrees include (1) a non-row (non-row) orthogonal portion including a plurality of columns and a plurality of rows, the plurality of columns and the plurality of rows forming at least non-row (non-row) orthogonal layers corresponding to the relatively high code rate, (2) a quasi-row orthogonal portion including a plurality of columns and a plurality of rows, the plurality of columns and the plurality of rows forming at least quasi-row orthogonal layers corresponding to the medium code rate, (3) a pure-row (pure-row) orthogonal portion including a plurality of columns and a plurality of rows, the plurality of columns and the plurality of rows forming at least pure-row orthogonal layers corresponding to the relatively low code rate.

Fig. 5 illustrates an example QC-LDPC code 500 supporting a very low code rate based on an embodiment of the present invention, referring to fig. 5, the QC-LDPC code 500 may include a parity matrix of a plurality of parity bits and an information matrix of a plurality of information bits, the information matrix may include or more row (row) bits with a bit degree of 2 every rows, and, moreover, each bits of the bits with a bit degree of 2 of the or more row (row) bits with a degree of 2 may be a previously used parity bit or a previously transmitted information bit.

Fig. 6 shows an example core matrix design 600 according to an embodiment of the invention please refer to fig. 6, in the core matrix design 600, a QC-LDPC code may comprise base matrices, part of which forms a core matrix corresponding to a code rate of at least threshold, for example, in the example shown in fig. 6, the core matrix supports a code rate of 0.89.

Fig. 7 illustrates an exemplary concept 700 of a core fundamental matrix according to an embodiment of the invention, please refer to fig. 7, the core matrix may include a plurality of bits in a plurality of rows and a plurality of columns, wherein two or more columns (columns) are punctured columns having a specific bit pattern (e.g., or more bits 0.) in embodiments, the specific bit pattern in the plurality of punctured columns may include an isosceles (isosceles) right triangle formed by the plurality of bits 0, the right angle of the triangle corresponding to the bit 0 at the upper left corner of the plurality of punctured columns.

The parity matrix may include a matrix having a Wi-Fi pattern (e.g., a Wi-Fi like parity matrix). moreover, bits of more than one rows (row) of the information matrix may include bits 1 having a high density and no or multiple rows (row) having bits 0. the bits of the bottom row of the multiple rows may include a th number of bits 1. the th number may be equal to or 1 greater than the number of punctured columns (columns).

In the example shown in part (a) of fig. 7, the first few rows (e.g., 3 rows) are composed of a Wi-Fi like parity matrix and the information matrix has an ultra-high density of bits 1. in particular, the bits included in every rows in the information matrix are mostly, if not all, bits 1, have no 0 or 10 after any number of row permutations (permatations) and/or column permutations (e.g., at least row permutations, at least column permutations, or combinations thereof), the punctured column includes a specific pattern of or more bits 0.

In the example shown in part (B) of fig. 7, an example pattern of punctured columns is shown for a base matrix of size m x n (m rows by n columns) and assuming that p columns are punctured, a m x p matrix is constructed using a plurality of bits 0 isosceles right triangles whose right angles correspond to bits 0 at the top left corner of of the plurality of punctured columns, the other bits in the punctured columns may be randomly selected to be 0 or 1.

Fig. 8 is an exemplary concept 800 showing a core fundamental matrix based on another embodiment of the present invention, in the concept 800, the core fundamental matrix includes Wi-Fi patterns (or parity matrices like Wi-Fi patterns), punctured columns (column), and the remaining part of the information matrix, the remaining part of the information matrix may be designed using of a plurality of degree distributions (degree distributions), for example, Variable Node (VN) degrees of bits of a core matrix may include of [2,2,2,2,2,3,3,3,3,3,3,3,3, 3.

Fig. 9 shows a shift coefficient design 900 based on an embodiment of the invention, for every lifting factors (lifting factors), there is a table of corresponding shift values, tables in different lifting factors may be nested designed (nested design) in the shift coefficient design 900, an active set of lifting factors may be defined for use in LDPC coding in the example shown in fig. 9, the active set of lifting factors includes lifting factors of different values, Z16, Z24, Z32, Z48, Z64, Z96, Z128, Z192, Z256 and Z384 in the shift coefficient design 900, the active set of lifting factors may be optimized to obtain an optimized set of lifting factors, the number of lifting factors in the optimized set is the shift coefficient set that is less than the number of lifting factors in the active set 128, the optimized set may be used as the shift coefficient table and the table may be equal to the shifting factor for which Z is the most similar lifting factor, Z is equal to the table, Z is shared by similar lifting factor for use in the shift coefficient design table.

For purposes of illustration and not limitation, in LDPC codebooks in accordance with the present invention are used

The optimized set of lifting factors (Z) may be defined as 4 groups. Use of

The active set of lifting factors may be defined as 8 groups. The corresponding shift value may be represented by 4 shift coefficient tables, which may correspond to shift coefficients {288,352,416,480 }. For active set

Any lifting factor Z of a x 2^jThe corresponding shift coefficient may be obtained by

Obtaining, wherein pm and n are

Is used for the (m, n) -th element of the shift coefficient table, wherein

Is the maximum of {9,11,13,15} andis less than or equal to the sum of a,and is

Also, f (Z) is a perturbation (perturbation), is a function of Z, and can be represented using the table.

The use of lifting factors allows packets of various sizes to be encoded using a relatively small set of base matrices (sets) and a relatively small set of lifting factors. For example, the basic matrix size m x n may be used to encode a packet of up to k ═ n-m information bits to obtain an encoded packet or codeword of n code bits. The base matrix may be expanded (lift) using a lifting factor Z to produce an expanded parity-check matrix of dimension Z · m × Z · n. The extended parity check matrix may then be utilized to encode packets of up to Z · k information bits to obtain codewords of Z · n code bits. Furthermore, the use of the lifting factor may also allow efficient parallel encoding and decoding, thereby improving performance and reducing description complexity for large-sized LDPC codes.

Shift coefficient table design for larger code block sizes

For purposes of illustration, fig. 15(a) -22 (B) illustrate a number of exemplary shift coefficient tables for relatively large code block sizes.

Each of fig. 15(a) -15 (B) is a schematic diagram of the portion of an exemplary shift coefficient table 1500 according to an embodiment of the present invention, hi particular, the shift coefficient table 1500 is composed of the (a) portion of fig. 15A and the (B) portion of fig. 15B, and furthermore, the shift coefficient table 1500 may correspond to a base graph 1(BG1), the base graph 1(BG1) having a primary (primary) element 7(a ═ 7) and a lifting factor 224.

Each of fig. 16(a) -16 (B) is a schematic diagram of part of an exemplary shift coefficient table 1600 in accordance with an embodiment of the present invention, hi particular, the shift coefficient table 1600 is composed of part (a) in fig. 16A and part (B) in fig. 16B, and furthermore, the shift coefficient table 1600 may correspond to BG1 having original elements 15(a ═ 15) and a lifting factor 240.

Each of fig. 17(a) -17 (B) is a schematic diagram of the portion of an exemplary shift coefficient table 1700 according to an embodiment of the present invention, hi particular, the shift coefficient table 1700 is composed of the (a) portion of fig. 17A and the (B) portion of fig. 17B, and the shift coefficient table 1700 may correspond to BG1 having the original element 9(a ═ 9) and the lifting factor 288.

Each of fig. 18(a) -18 (B) is a schematic diagram of part of an exemplary shift coefficient table 1800 in accordance with an embodiment of the present invention in particular, the shift coefficient table 1800 is composed of part (a) in fig. 18A and part (B) in fig. 18B, and furthermore, the shift coefficient table 1800 may correspond to BG1 having original element 5(a ═ 5) and lifting factor 320.

Each of fig. 19(a) -19 (B) is a schematic diagram of the portion of an exemplary shift coefficient table 1900 according to an embodiment of the present invention, in particular, the shift coefficient table 1900 is composed of the (a) portion in fig. 19A and the (B) portion in fig. 19B, and furthermore, the shift coefficient table 1900 may correspond to BG1 having the original element 11(a ═ 11) and the lifting factor 352.

Each of fig. 20(a) -20 (B) is a schematic diagram of part of an exemplary shift coefficient table 2000 in accordance with an embodiment of the present invention, hi particular, the shift coefficient table 2000 is composed of part (a) of fig. 20A and part (B) of fig. 20B, and the shift coefficient table 2000 may correspond to BG1 having an original element 3(a ═ 3) and a lifting factor 384.

Each of fig. 21(a) -21 (B) is a schematic diagram of part of an exemplary shift coefficient table 2100 according to an embodiment of the present invention in particular, the shift coefficient table 2100 is composed of part (a) in fig. 21A and part (B) in fig. 21B, and furthermore, the shift coefficient table 2100 may correspond to BG1 having original elements 13(a ═ 13) and a lifting factor 208.

Each of fig. 22(a) -22 (B) is a schematic diagram of part of an exemplary shift coefficient table 2200 based on an embodiment of the present invention, hi particular, the shift coefficient table 2200 is composed of part (a) of fig. 22A and part (B) of fig. 22B, and the shift coefficient table 2200 may correspond to BG1 having an original element 2(a ═ 2) and a lifting factor 256.

Fig. 23 illustrates an exemplary logic flow 2300 associated with selecting a shift coefficient table in accordance with an embodiment of the invention the logic flow 2300 may be implemented in or by an encoder or a processor to implement various features and/or aspects of the concepts and schemes presented herein in particular, the logic flow 2300 may involve or more rules for use in selecting a shift coefficient table from a plurality of shift coefficient tables such that a shift coefficient table suitable for relatively large code block size material is selected the logic flow 2300 may include or more operations, acts or functions represented by one or more of blocks 2310,2320,2330, and in 2340.

At 2310, the logic flow 2300 may involve the processor of the apparatus 1005 determining whether a code block size of the data to be encoded is less than or equal to a threshold code block size.

At 2320, logic flow 2300 may involve processor 1010 determining whether a code rate of data to be encoded is less than or equal to a threshold code rate. Logic flow 2300 may proceed from 2320 to 2340 where processor 1010 determines that the code rate of the data is less than or equal to the threshold code rate. Otherwise, when processor 1010 determines that the code rate of the data is determined to be greater than the threshold code rate, logic flow 2300 may proceed from 2320 to 2330.

At 2330, logic flow 2300 may involve processor 1010 selecting or otherwise using a shift coefficient table corresponding to base chart 1(BG 1).

At 2340, logic flow 2300 may involve processor 1010 selecting or otherwise using a shift coefficient table corresponding to base graph 2(BG 2).

Moreover, the modulus (mod) of the values of the selected or otherwise used shift coefficient table to or more lifting factors is the same as the modulus results of any of the shift coefficient tables shown in FIGS. 15(A) -22 (B), whether in part or in whole.

Illustrative embodiments

Fig. 10 illustrates an exemplary communication system 1000 based on embodiments of the invention the communication system may include th and second devices 1005, 1050, and th and second devices 1005, 1050 may communicate with each other via communication links the communication link 1040 may be a wireless link in embodiments alternatively the communication link 1040 may be a wired link in other embodiments in the environment of 5G NR communication the communication link 1040 is a wireless communication link, e.g., a multi-user multiple-input-multiple-output (MU-MIMO) communication link, th and second device 1050 may perform various functions as communication devices to implement the concepts described herein with respect to QC-LDPC coding, schemes, techniques, procedures and methods including those described with respect to some or all of fig. 1-9 and processes 1100,1200,1300,1400 described more particularly with respect to those described with respect to fig. 1-9, the second device may design the code rate of the LDPC code design matrix design, the LDPC code design scheme, the LDPC code design matrix design scheme, and the LDPC code design scheme may support the various code design factors of the LDPC code design.

For example, device 1005 may be implemented in a Wi-Fi mobile client or station, a smartphone, a smartwatch, a smartnecklace, a personal digital assistant, or a computing device such as a tablet computer, a laptop computer, a notebook computer, a desktop computer, or a server likewise, second device 1050 may be implemented in a Wi-Fi mobile client or station, a smartphone, a smartwatch, a smartbracelet, a smartnecklace, a personal digital assistant, or a computing device such as a tablet computer, a laptop computer, a desktop computer, or a server or alternatively, device 1005 and second device 1050 may be implemented in the form of or more single core processors, or more Integrated Circuit (IC) chips such as, but not limited to, or more single core processors, or more, or more Integrated Circuit (IC) chips, or more complex computing-core processors such as, a complex computing-sc 26.

Each of the apparatus 1005 and the second apparatus 1050 may include at least portions of those shown in fig. 10, respectively, for example, the 1 th apparatus 1005 may include at least a processor 1010, the second apparatus 1050 may include at least a processor 1060, furthermore, the th apparatus may include a memory 1020, transceivers 1030 and 3 or more antennas (represented by antenna 1036), the transceiver 1030 may be configured to wirelessly transmit and receive data (e.g., conforming to or more 3GPP standards, protocols, specifications, and/or any applicable wireless protocols and standards, such as 5G NR), the memory 1020 and each of the transceiver 1030 may be communicatively or operatively coupled to the processor 1010 similar, the second apparatus 1050 may also include a memory 1070, the transceivers 1080 and or more antennas (represented by antenna 1086), the transceiver 1080 may be configured to wirelessly transmit and receive data (e.g., or more 3GPP standards, 1070, and/or 1080 a plurality of antennas (represented by antenna 1086), the transceiver 1080 and the transceiver 1080 may be configured to wirelessly transmit and receive data (e.g., may not be coupled to a simple NR) in the present invention, and may not be described in relation to the user equipment 1005 and/or to the present invention.

The transceiver 1030 may be configured to wirelessly communicate in a single band or multiple bands, the transceiver 1030 may include a transmitter 1032 capable of wirelessly transmitting data and a receiver 1034 capable of wirelessly receiving data, in some embodiments, the transceiver 1030 may be capable of transmitting/modulating (via the transmitter 1032) and receiving/demodulating (via the receiver 1034) data symbols that are Orthogonal Frequency Division Multiplexed (OFDM) symbols radiated by an antenna 1036.

In the example shown in fig. 10, memory 1020 may store or more sets of processor-executable instructions 1022 and data 1024 therein, and memory 1070 may store or more sets of processor-executable instructions 1072 and data 1074 each of memory 1020 and memory 1070 may be implemented by any suitable technique and may include volatile memory and/or non-volatile memory, for example, each of memory 1020 and memory 1070 may include types of Random Access Memory (RAM) such as dynamic RAM (dram), (static RAM), thyristor RAM (T-RAM) and/or zero capacitor RAM (Z-RAM) 520 alternatively or additionally, memory types of Read Only Memory (ROM) such as mask ROM, (eprom) and/or programmable ROM (prom) (eprom) and/or erasable programmable ROM (Z-RAM) (NVRAM), and optionally phase change memory (RAM) such as magnetoresistive Random Access Memory (RAM) or nonvolatile RAM) (RAM) such as nonvolatile RAM (RAM), nonvolatile RAM (RAM) and/or nonvolatile RAM (RAM) such as nonvolatile RAM (RAM) and nonvolatile RAM (RAM).

In aspects, each of processors 1010 and 1060 may be implemented in the form of 0 or more single-core processors, or more multi-core processors, or or more CISC processors, that is, according to the present invention, even though the singular term "processor" is used herein to refer to each of processors 1010 and 1060, according to the present invention, each of processors 1010 and 1060 may include multiple processors in some embodiments and a single processor in other embodiments, in further aspects, each of processors 1010 and 1060 may be implemented in hardware (and optionally firmware) with electronic components including, for example, but not limited to, or more transistors, or more diodes, or more capacitors, or more resistors, or more inductors, or more resistors, or more code blocks, or more dedicated to carry out various configurations of the invention, which may be arranged in accordance with LDPC 638 or cmos code blocks, or other specific tasks, or other implementations of which may be implemented in accordance with various tasks 638, or others, or may be implemented in accordance with the invention in a specific design of a variable capacitance-c configuration table, or other way of which may be arranged in accordance with the invention, including various tasks 638, or specific tasks, which may be implemented in accordance with various tasks, designated as a configuration of a configuration scheme, or a configuration scheme for implementation in which may be implemented in accordance with the invention, which may be implemented in accordance with a configuration of a variable capacitance for implementation of a configuration of a variable capacitance for implementation.

According to various embodiments of the present invention, processor 1010, which is a dedicated machine, may comprise hardware circuitry not generally and specifically designed designed to perform specific tasks related to the design of a table of shift coefficients for QC-LDPC codes of larger code block sizes in mobile communications in aspects according to various embodiments of the present invention, processor 1010 may execute sets or sets of codes stored in memory 1020, programs and/or instructions 1022 to perform various operations to provide (render) a table of shift coefficients for QC-LDPC codes of larger code block sizes in mobile communications in aspects according to various embodiments of the present invention, processor 1012 may comprise encoder 1012 and decoder 1014, which encoder and decoder 1014 function to perform specific tasks and functions to provide (render) a QC-LDPC code 1014.

In implementations, processor 1010 may also include memory 1016, which may include or more registers (registers), or more buffers, and/or or more caches (caches). in implementations, processor 1016 may utilize memory 1016 to store a base matrix of the QC-LDPC code, a selected codebook, a lifting factor, and/or or more matrices of shift coefficients.for example, processor 1010 may generate and store a base matrix in memory 1020, and upon selecting a codebook from a plurality of codebooks embedded in the base matrix, processor 1010 may store the selected codebook in memory 1016. thus, processing delay of the encoding may be reduced by selecting a codebook from the plurality of codebooks embedded in the base matrix according to or more rules of logic flow 200. accordingly, by implementing various schemes according to the present invention (e.g., by selecting a codebook from the plurality of codebooks embedded in the base matrix, not only for improved processing of the QC-LDPC code, but also for improved processing of the encoded data (e.g., lower throughput coding delay) and shorter processing delay (e.g., decoder 1010).

Processor 1060, which may be a special-purpose machine according to various embodiments of the present invention, may include hardware circuitry not generally and specifically designed designed, arranged and configured to perform specific tasks related to QC-LDPC encoding in aspects, according to various embodiments of the present invention, processor 1060 may execute sets or sets of codes, programs and/or instructions 1072 stored in memory 1070 to perform various operations related to QC-LDPC encoding in another aspect, according to various embodiments of the present invention, processor 1060 may include an encoder 1062 and a decoder 1064 that perform specific tasks and functions to provide (render) QC-LDPC encoding.

In implementations, processor 1060 may also include a memory 1066, which may include or more registers, or more buffers, and/or or more caches, in implementations, processor 1060 may utilize memory 1066 to store a base matrix of the QC-LDPC codes, a selected codebook, a lifting factor, and/or a shift coefficient matrix.

For example, the coding chain in each of the encoder 1012 and the encoder 1062 may perform bit reordering, tone interleaving, hybrid Redundancy Version (RV) design, self-adjusting HARQ buffering, and code block grouping as follows, each of the decoder 1014 and the decoder 1064 may be configured to support various code rates of a codebook, the lowest code rate of each supported codebook of the decoder 1014 and the decoder 1064 may depend on the size of the corresponding lifting factor, the lifting factor may be set in the proposed scheme, the lifting factor may be set in a log-likelihood ratio (log-likelihood ratio, LLR) memory size, the lifting factor may be stored in LLR memory, the memory size may define or otherwise define how large the lifting factor may be set by a plurality of bit buffer units, a plurality of bit buffer units, a plurality of bit units.

In operation, for a forward link (forward link) on the transmit side, an encoder 1012 may receive data packets from a data source, process the data by performing encoding, interleaving, and symbol mapping on the data, and provide modulation symbols for the encoded data.a transmitter 1032 may multiplex (condition) or more output symbol streams with pilot symbols, perform spatial processing, and provide or more output symbol streams.a transmitter 1032 (which may include or more transmitters) may condition (condition) the or more output symbol streams by performing digital-to-analog conversion, filtering, amplifying, and up-converting to produce or more forward link signals which are radiated as electromagnetic waves by or more antennas of an antenna 1036.a receiver 1084 (which may include or more receivers) may receive or more forward link signals as MIMO via or more antennas of an antenna 1086.a receiver 1084 may also perform filtering and down-conversion to provide a plurality of received symbols to a receiver (de-sampling) to obtain a plurality of received symbols which may be interleaved, decoded by performing de-sampling on a plurality of antennas 1084 to obtain a plurality of received symbols.

Similarly, on the reverse (reverse) link, an encoder 1062 may receive data packets from a data source and process the data by encoding, interleaving, and symbol mapping to provide modulation symbols for the encoded data.A transmitter 1082 may multiplex (condition) or more output symbol streams with pilot symbols, perform spatial processing, and provide or more output symbol streams.A transmitter 1082 (which may include or more transmitters) may condition (condition) the or more output symbol streams by performing digital-to-analog conversion, filtering, amplification, and upconversion to produce or more reverse link signals, which or more reverse link signals are radiated as electromagnetic waves through or more antennas of antenna 1086. on the Receive (RX) side, a receiver 1034 (which may include or more receivers) may receive or more reverse link signals as MIMO via or more antennas of antenna 1036, receive the multiple received reverse link signals as MIMO, and may perform filtering, amplification, downconversion, and symbol mapping to provide a second sampled data symbols that may be detected by the receiver 1034, deinterleaved to provide a second sampled data symbol stream.

Processor 1010 may be configured to control or otherwise direct the operation of device 1005 processor 1060 may be configured to control or otherwise direct the operation of device 1050 in accordance with the aspects and concepts of the present application, processor 1010 may be capable of determining a size of a packet to be transmitted and/or received and, accordingly, controlling encoding by encoder 1012 and decoding by decoder 1014, respectively, likewise, in accordance with the aspects and concepts of the present application, processor 1060 may be capable of determining a size of a packet to be transmitted and/or received and, accordingly, controlling encoding by encoder 1062 and decoding by decoder 1064, respectively, for example, each of processor 1010 and processor 1060 may be configured to select a codebook from a plurality of codebooks embedded into a base matrix of a QC-LDPC code for encoding, such that if a large amount corresponding to a large amount of encoding processing delay is not necessary for encoding, a small codebook with a small amount of encoding processing delay may need to be selected for encoding.

Each of the device 1005 and the second device 1050 may be configured to perform each of the processes 1100,1200,1300,1400 and 2400 described below, so, to avoid redundancy and for brevity, the operation of the device 1005 and the second device 1050, and the operation of the processor 1010 and the processor 1060 are described in the context of the following processes 1100,1200,1300,1400 and 2400.

With regard to shift coefficient table design for QC-LDPC codes of large code block sizes in mobile communications, processor 1010 of apparatus 1005 may establish a wireless communication link with second apparatus 1050 via transceiver 1030 of apparatus 1005 the processor 1010 may be in wireless communication with second apparatus 1050 via a wireless communication link, in wireless communication with second apparatus 1050, processor 1010 may perform a plurality of operations, for example, processor 1010 may perform (1) selecting a th shift coefficient table from the plurality of shift coefficient tables, (2) generating the QC-LDPC code using at least a portion of the th shift coefficient table and a base matrix, (3) selecting a codebook from a plurality of codebooks embedded into the QC-LDPC code, (4) storing the selected codebook to a memory associated with the processor, (5) encoding the data using the selected codebook to generate a plurality of modulation symbols for the data, and (6) controlling transceiver 1030 to multiplex, convert, filter, amplify, and transmit the modulation symbols to the wireless communication apparatus 1036 via electromagnetic wave modulation symbol as a radiation modulation chain for the second apparatus 1050.

In embodiments, the shift coefficient table may include a basic shift coefficient table arranged as 4 rows (row)26 columns (column) in the following pattern:

in embodiments, the shift coefficient table may include a shift coefficient table as shown in fig. 18A and 18B.

In embodiments, the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 5 (a-5) and a lifting factor 320, alternatively, the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 7 (a-7) and a lifting factor 224, alternatively, the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 15 (a-15) and a lifting factor 240, alternatively, the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 9 (a-9) and a lifting factor 288, alternatively, the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 11 (a-11) and a lifting factor 352, alternatively, the th shift table may include a shift coefficient table corresponding to BG1 with original element 3 (a-3) and a lifting factor 384, alternatively, the BG1 th shift coefficient table may include a shift coefficient table with a shifting factor 38, 3638 th shift coefficient table may include a shifting coefficient table corresponding to BG 8938 (a) and a lifting factor 38).

In embodiments, in selecting the th table of shift coefficients from the plurality of tables of shift coefficients, the processor 1010 may select the th table of shift coefficients for a relatively larger block size according to or more rules relating to either or both of the code block size and the code rate of the data.

In embodiments, when generating a QC-LDPC code using th shift coefficient table at least parts and the base matrix, processor 1010 may generate the QC-LDPC code using th shift coefficient table full (run) and the base matrix.

In implementations, when generating the QC-LDPC code using shift coefficient table at least part and the base matrix, processor 1010 may generate the QC-LDPC code using shift coefficient table part (partial) and the base matrix.

In , when selecting the th table of shift coefficients from the plurality of tables of shift coefficients, processor 1010 may select a second table of shift coefficients whose modulo (modulo) of or more lifting factors is the same as the modulo result of at least the th table of shift coefficients.

In embodiments, when generating the QC-LDPC code using the th shift coefficient table at least parts and the base matrix, the processor 1010 may generate the QC-LDPC code using the full (contribution) and the base matrix of the second shift coefficient table.

In implementations, in generating the QC-LDPC code using the th shift coefficient table at least part and the base matrix, the processor 1010 may generate the QC-LDPC code using the part (partial portion) of the second shift coefficient table and the base matrix.

In some embodiments, processor 1010 may perform a plurality of operations (e.g., with respect to logic flow 2300) when selecting the th shift coefficient table from the plurality of shift coefficient tables, for example, processor 1010 may determine whether the code block size is less than or equal to a threshold code block size.

In , each of the plurality of codebooks may correspond to a respective HARQ thread of the plurality of hybrid automatic repeat request, HARQ, threads, the plurality of HARQ threads being different from one another.

In embodiments, the processor 1010 may perform a plurality of operations in selecting a codebook from a plurality of codebooks.for example, the processor 1010 may determine whether a code block size of the data is less than a threshold code block size.

In some implementations , the processor 1010 may perform a plurality of operations in selecting a codebook from a plurality of codebooks.A processor 1010 may determine a codeblock size for the data, in addition, the processor 1010 may select a codebook by (1) selecting a codebook from the plurality of codebooks in response to the determined codeblock size being greater than a threshold codeblock size, (2) selecting a second codebook from the plurality of codebooks in response to the determined codeblock size being greater than a second threshold codeblock size, and (3) selecting a third codebook from the plurality of codebooks in response to the determined codeblock size being greater than a third threshold codeblock size, the threshold codeblock size may be greater than the second threshold codeblock size, the second threshold codeblock size may be greater than the third threshold codeblock size, the codeblock size may be greater than the second codebook size, and the second codebook size may be greater than the third codebook size.

Illustrative Process

Fig. 11 shows an exemplary process 1100 based on embodiments of the application, process 1100 may represent aspects of implementing the proposed concepts and schemes, which may be described, for example, in part or in whole with respect to fig. 1-10, hi particular, process 1100 may represent aspects of the proposed concepts and schemes related to QC-LDPC encoding process 1100 may include of blocks 1110,1120,1130 and 1140 or or more of the operations, actions, or functions shown.

At 1110, process 1100 may involve processor 1010 of device 1005 generating a QC-LDPC code having a plurality of codebooks embedded therein process 1100 proceeds from 1110 to 1120.

At 1120, process 1100 may involve processor 1010 selecting a codebook from a plurality of codebooks. Processor 1010 may execute from 1120 to 1130.

At 1130, process 1100 may involve processor 1010 encoding using the selected codebook. From 1130, process 1100 proceeds to 1140.

At 1140, process 1100 may involve processor 1010 transmitting the encoded data (e.g., to second device 1050) via transceiver 1030.

In embodiments, each of a plurality of codebooks may correspond to a respective HARQ thread of a plurality of HARQ threads that are different from one another. for example, process 1100 may involve processor 1010 communicating with processor 1060 of second apparatus 1050 using HARQ. in selecting a codebook from the plurality of codebooks, process 1100 may involve processor 1010 performing (1) associating or otherwise associating each HARQ threads of the plurality of HARQ threads to a respective codebook of the plurality of codebooks, (2) identifying the HARQ thread currently in use for communicating with second apparatus 1050, and (3) selecting of the plurality of codebooks, of which correspond to the identified HARQ thread.

In embodiments, in generating a QC-LDPC code having a plurality of codebooks embedded therein, process 1100 may involve processor 1010 generating a QC-LDPC code comprised of a base matrix and or more shift coefficient matrices.

In embodiments, each of the plurality of codebooks may correspond to a respective design of the plurality of designs of shift coefficient matrices.

In embodiments, in generating a QC-LDPC code having multiple codebooks embedded therein, process 1100 may involve processor 1010 generating tables of shift values for each 0 lifting factor of a set of lifting factors, and process 1100 may involve processor 1010 optimizing a 1 th set of lifting factors to generate a second set of lifting factors, the number of th set lifting factors may be greater than the number of second set lifting factors, th lifting factors may share a corresponding table of shift values for the second lifting factors, where the th lifting factor is in the set but not in the second set, the second lifting factor is in both the th set and the second set, the value of the second lifting factor may be less than the value of the th lifting factor, and the second lifting factor is closer to the th lifting factor than the other lifting factors in the set.

In , in selecting a codebook from a plurality of codebooks, process 1100 may involve processor 1010 selecting a codebook from a plurality of codebooks in accordance with an initial code rate for transmitting data and/or a code block size of the data.

In some embodiments, in selecting a codebook from a plurality of codebooks, process 1100 may involve processor 1010 performing a plurality of operations (e.g., similar to those involved in logic flow 200). for example, process 1100 may involve processor 1010 determining whether a code block size of data is less than a threshold code block size. in response to the code block size of the data being less than the threshold code block size, process 1100 may involve processor 1010 selecting a third codebook from the plurality of codebooks. in response to the code block size of the data not being less than the threshold code block size, process 1100 may involve processor 1010 determining whether an initial code rate for transmitting the data is greater than a threshold code rate. in response to the initial code rate not being greater than the threshold code rate, process 1100 may involve processor 1010 selecting a second codebook from the plurality of codebooks. in response to the initial code rate being greater than the threshold code rate, process 1100 may involve processor 1010 selecting a codebook from the plurality of codebooks. the size of the may be greater than the size of the second codebook.

Alternatively, or additionally, the process 1100 may involve the processor 1010 performing a plurality of operations in selecting a codebook from a plurality of codebooks.A process 1100 may involve the processor 1010 determining a code block size of the data based on a result of the determining, the process 1100 may involve the processor 1010 selecting a th codebook of the plurality of codebooks in response to determining that the code block size is greater than a th threshold code block size.moreover, the process 1100 may involve the processor 1010 selecting a second codebook of the plurality of codebooks in response to determining that the code block size is greater than a second threshold code block size.A process 1100 may involve the processor 1010 selecting a third codebook of the plurality of codebooks.a third threshold code block size may be greater than a second threshold code block size.a second threshold code block size may be greater than a third threshold code block size.a size of the codebook may be greater than a size of the second codebook.

Fig. 12 shows an exemplary process 1200 based on embodiments of the invention, process 1200 may represent aspects of implementing the proposed concepts and schemes, which may be described, for example, in part or in whole with respect to fig. 1-10, moreover, process 1200 may represent aspects of the proposed concepts and schemes relating to hybrid orthogonal (hybrid orthogonal) LDPC layer designs and extremely low code rate QC-LDPC support, process 1200 may include blocks or multiple operations, acts and functions illustrated by blocks 1210,1220 and 1230, or multiple blocks, although shown as discrete blocks, various blocks of process 1200 may be divided into additional blocks, combined into fewer blocks, or deleted depending on the desired embodiment, and the blocks/sub-blocks of process 1200 may be performed in the order shown in fig. 12, or performed in a different order, process 1200 may be implemented by communication system 1000 and any variation thereof, process 1200 may be implemented in device 1005 and/or a second device, or by and/or a second device , process 1200 may be described for purposes only beginning with the context of the second device 1210, and the process 1200 may be described below for purposes of the first device 1210.

At 1210, process 1200 may involve the processor 1010 of the th device 1005 generating a QC-LDPC code that includes at least a quasi-row (quadrature-row) orthogonal layer process 1200 may be performed from 1210 to 1220.

At 1220, process 1200 may involve processor 1010 encoding using a QC-LDPC code. Process 1200 may proceed from 1220 to 1230.

At 1230, process 1200 may involve processor 1010 transmitting the encoded data (to the second device 1050) via transceiver 1030.

In embodiments, at least quasi-parallel orthogonal layers may include multiple columns and multiple rows of bits or more of the multiple columns (columns) of at least quasi-parallel orthogonal layers may include at least perforated columns of degree 2 or more, the remaining of the multiple columns of at least quasi-parallel orthogonal layers may include non-perforated columns of degree 1 or 0.

In embodiments, there may be no rings (cycles) in the puncture columns.

In embodiments, the QC-LDPC codes can include a hybrid orthogonality design with multiple parts of different degrees of orthogonality of the multiple parts of low degree of orthogonality can correspond to a high code rate and a second of the multiple parts of high degree of orthogonality can correspond to a low code rate.

in some embodiments, the multiple sections of different degrees of orthogonality includes (1) non-row orthogonal section including a plurality of rows and a plurality of columns, the plurality of rows and the plurality of columns forming at least non-row orthogonal layers, (2) 5639 quasi-row orthogonal section including a plurality of rows and a plurality of columns, the plurality of rows and the plurality of columns forming at least quasi-row orthogonal layers, and (3) pure-row orthogonal layers including a plurality of rows and a plurality of columns, the plurality of rows and the plurality of columns forming at least pure-row orthogonal layers.

or more row (row) bits through the information matrix and the parity matrix may include or more row (row) bits with a degree of bits per row of 2.

In embodiments, each bits of the bits of degree 2 or the multiple bits of degree 2 of the multiple rows may include previously used parity bits or previously transmitted information bits.

Although shown as discrete blocks, various blocks of process 1200 may be divided into additional blocks, combined into fewer blocks, or eliminated depending on the desired implementation, and furthermore, the blocks/sub-blocks of process 1300 may be performed in the order shown in FIG. 13, or performed in a different order the process 1300 may be implemented by communication system 1000 and any variations thereof, for example, the process 1300 may be implemented in device 1005 and/or second device 1050, or implemented by 361005 device and/or second device 1050. the process 1300 may be implemented for purposes of illustration only in the context of the process 1300, and is not limited to the context of the process 1050, which may be described below for purposes of the context of the process 1310, the process 1300 may be implemented by 361005 device 1005 device, the context of the process 1050, and so on.

At 1310, process 1300 may involve the processor 1010 of the th device 1005 generating a QC-LDPC code that includes a base matrix, portion of which forms a core matrix corresponding to a code rate of at least thresholds process 1300 may be performed from 1310 to 1320.

At 1320, process 1300 may involve processor 1010 encoding the data using a QC-LDPC code. Process 1300 may proceed from 1320 to 1330.

At 1330, the process 1300 may involve the processor 1010 sending the encoded data (to the second device 1050) via the transceiver 1030.

In embodiments, the code rate may be 0.89.

In embodiments, the core matrix may include a plurality of columns and a plurality of rows of bits, and two or more of the plurality of columns may include perforated columns having a particular bit pattern.

In embodiments, after any number of column permutations (permatations) and/or row permutations (e.g., at least column permutations, at least row permutations, or any combination thereof), a particular bit pattern in a plurality of punctured columns may include or more bits 0 in the plurality of punctured columns, two examples of a particular pattern including or more bits 0 after column permutations and/or row permutations are shown in FIG. 7, part (A), in embodiments, a particular bit pattern in a punctured column may include an isosceles right triangle of bits 0, the right angle of the triangle corresponding to the upper left bit 0 in the punctured column, an example of bit 0 of such an isosceles right triangle is shown in part (B) of FIG. 7.

In embodiments, the core matrix may include a parity matrix of a plurality of columns and a plurality of rows of bits, the core matrix may also include an information matrix of a plurality of columns and a plurality of rows of bits, the parity matrix may include a matrix having a Wi-Fi pattern, in addition to punctured columns of the core matrix, or more rows (row) of bits of the information matrix may include rows (row) having high density bits of 1 and no or only bits of 0.

In embodiments, the bits of the bottom row of the plurality of rows may include bit 1 of the th th number may be equal to or 0,1, 2, or 3 (e.g., greater) than the number of perforated columns at embodiments, the portion of bit 1 of the th number in the bottom row may correspond to a perforated column and a rightmost column (column) of the core matrix, where the rightmost column (column) of the core matrix is on the right side of the Wi-Fi pattern.

In embodiments, the degrees of variable nodes of the core matrix that may include 5 row bits and 20 column bits, 20 column bits may include of [2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3], [2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3, 5 row bits may include ,10,13,1, 13,10,13,1, 13,1, 13,1, 13.

FIG. 14 shows an exemplary process 1400 based on embodiments of the invention, process 1400 may represent aspects of implementing the proposed concepts and schemes, which may be described, for example, with respect to FIG. 9 more particularly, process 1300 may represent aspects of the proposed concepts and schemes related to shift coefficient design Process 1400 may include one or more of the operations, acts, or functions illustrated by blocks or blocks in blocks 1410,1420, and 1430, , although illustrated as discrete blocks, various blocks of process 1400 may be divided into additional blocks, combined into fewer blocks, or deleted depending on the desired implementation, and further, the blocks/sub-blocks of process 1400 may be performed in the order illustrated in FIG. 14, or in a different order.

At 1410, process 1400 may involve processor 1010 of device 1005 at generating a QC-LDPC code process 1400 may proceed from 1410 to 1420.

At 1420, process 1400 may involve processor 1010 encoding the data using a QC-LDPC code. Process 1400 may proceed from 1420 to 1430.

At 1430, the process 1400 may involve the processor 1010 transmitting the encoded data (e.g., to the second apparatus 1050) via the transceiver 1030.

In generating the QC-LDPC code, process 1400 may involve processor 1010 performing a number of operations represented by sub-blocks 1412-1414.

In 1412, process 1400 may involve processor 1010 generating a corresponding table of shift values for each lifting factors of the th set of lifting factors process 1400 may proceed from 1412 to 1414.

In 1414, the process 1400 may involve the processor 1010 optimizing th set of boosting factors to produce a second set of boosting factors.

The th set of lifting factors may have a number of lifting factors greater than the second set of lifting factors the th lifting factor may share a corresponding table of shift values for the second lifting factor, where the th lifting factor is in the th set and not in the second set, the second lifting factor is in the th set and the second set.

Fig. 24 shows an exemplary process 2400 of wireless communication based on embodiments of the invention, process 2400 may represent aspects of implementing the proposed concepts and schemes, which may be described, for example, with respect to fig. 1-10 and 15(a) -part or all of fig. 23 more particularly, process 2400 may represent aspects of the proposed concepts and schemes related to a table design of shift coefficients for QC-LDPC codes for large code block sizes in mobile communications process 2400 may include or more of the illustrated or more operations, actions and functions in blocks 2410 and 2420 and sub-blocks 24202,24204,24206,24208,24210 and 24212, although shown as discrete blocks, depending on the desired implementation, the various blocks of process 2400 may be divided into additional blocks, combined into fewer blocks, or deleted, and the blocks/sub-blocks of process 2400 may be performed in the order shown in fig. 24, or in a different order, process 2400 may be performed by communication system 1000 and any variation thereof, process 1005 may be implemented in second embodiment and/second embodiment 1050, or apparatus 1005 may be illustrated in second embodiment 1050/, and process 1005 may be applied to second apparatus 1005, or device 1005, and/1005 may be also be described in second embodiment 1050/, in second embodiment, and/361005.

At 2410, the process 2400 may involve the processor 1010 of the th device 1005 establishing, via the transceiver 1030 of the device 1005, a wireless communication link with at least other devices (e.g., the second device 1050). the process 2400 may proceed from 2410 to 2420.

At 2420, process 2400 may involve processor 1010 wirelessly communicating with other devices over a wireless communication link via transceiver 1030. In wireless communication with other devices, the process 2400 may involve the processor 1010 performing various operations represented by 24202,24204,24206,24208,24210 and 24212.

At 24202, process 2400 may involve processor 1010 selecting a th shift coefficient table from a plurality of shift coefficient tables process 2400 may proceed from 24202 to 24204.

At 24204, process 2400 may involve processor 1010 generating a QC-LDPC code using at least portions of the th shift coefficient table and the base matrix, process 2400 may be performed from 24204 to 24206.

At 24206, process 2400 may involve processor 1010 selecting a codebook from a plurality of codebooks embedded into a QC-LDPC code. Process 2400 may proceed from 24206 to 24208.

At 24208, process 2400 can involve processor 1010 storing the selected codebook in a memory associated with the processor. Process 2400 may proceed from 24208 to 24210.

At 24210, process 2400 can involve processor 1010 encoding data using the selected codebook to generate a plurality of modulation symbols for the data. Process 2400 may proceed from 24210 to 24212.

At 24212, the process 2400 may involve the processor 1010 controlling the transceiver 1030 to multiplex, convert, filter, amplify, and radiate the modulation symbols as electromagnetic waves by the or more antenna threads 1036 of the device 1005 to transmit the modulation symbols of data to other devices via the wireless communication link.

In embodiments, the th table of shift coefficients may include a basic table of shift coefficients arranged in 4 rows and 26 columns in the following form:

in embodiments, the shift coefficient table may include a shift coefficient table as shown in fig. 18A-18B.

In embodiments, the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 5 (a-5) and a lifting factor 320, or the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 7 (a-7) and a lifting factor 224, or the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 15 (a-15) and a lifting factor 240, or the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 9 (a-9) and a lifting factor 288, or the th shift coefficient table may include a shift coefficient table corresponding to BG1 with original element 11 (a-11) and a lifting factor 352, or the th shift table may include a shift coefficient table corresponding to BG1 with original element 3 (a-3) and a lifting factor 384, or the BG1 th shift coefficient table may include a shift coefficient table 38 (a-38) with a shifting factor 38, or a shifting coefficient table may include a shift coefficient table corresponding to BG1 and a lifting factor 38.

In , in selecting the th table of shift coefficients from the plurality of tables of shift coefficients, process 2400 may involve processor 1010 selecting the th table of shift coefficients for a relatively larger code block size according to or more rules, where the or more rules relate to either or both of code block size and code rate of the data .

In , in generating a QC-LDPC code using at least the portion of the th shift coefficient table and the base matrix, process 2400 may involve processor 1010 generating the QC-LDPC code using the full (filling portion) of the th shift coefficient table and the base matrix.

In , in generating the QC-LDPC code using at least the portion of the th shifted coefficient table and the base matrix, process 2400 may involve processor 1010 generating the QC-LDPC code using the portion (partialration) of the th shifted coefficient table and the base matrix.

In , in selecting the th table of shift coefficients from the plurality of tables of shift coefficients, process 2400 may involve processor 1010 selecting a second table of shift coefficients having a modulus of values for or more lifting factors that is the same as the modulus in at least the th table of shift coefficients.

In , in generating the QC-LDPC code using at least the portion of the th table of shift coefficients and the base matrix, process 2400 may involve processor 1010 generating the QC-LDPC code using the (full portion) full and base matrices of the second table of shift coefficients.

In , in generating the QC-LDPC code using at least the portion of the th table of shift coefficients and the base matrix, process 2400 may involve processor 1010 generating the QC-LDPC code using the portion (partialration) of the second table of shift coefficients and the base matrix.

In embodiments, the processor 2400 may involve the processor 1010 performing a plurality of operations when selecting a th shift coefficient table from the plurality of shift coefficient tables, for example, the processor 2400 may involve the processor 1010 determining whether the code block size is less than or equal to a threshold code block size, further, the process 2400 may involve the processor 1010 determining whether the code rate is less than or equal to a threshold code rate, further, the process 2400 may involve the processor 1010 selecting an th shift coefficient table corresponding to the base graph BG1 in response to determining that the code block size is greater than the threshold code block size or in response to determining that the code rate is greater than the threshold code rate, or the process 2400 may involve the processor 1010 selecting a th shift table corresponding to the base graph BG2 in response to determining that the code block size is less than or equal to the threshold code block size or in response to determining that the code rate is less than or equal to the threshold code rate.

In , each of the plurality of codebooks may correspond to a respective HARQ thread of the plurality of HARQ threads, where the plurality of HARQ threads are different from one another.

In embodiments, the process 2400 may involve the processor 1010 performing a plurality of operations when selecting a codebook from a plurality of codebooks.e.g., the process 2400 may involve the processor 1010 performing a plurality of operations.e.g., the process 2400 may involve the processor 1010 determining whether a code block size of data is less than a threshold code block size.additionally, the process 2400 may involve the processor 1010 selecting a third codebook from the plurality of codebooks in response to the code block size of the data being less than the threshold code block size. moreover, in response to the code block size of the data not being less than the threshold code block size, the process 2400 may involve the processor 1010 determining whether an initial code rate for transmitting the data is greater than a threshold code rate.

In embodiments, the process 2400 may involve the processor 1010 performing a plurality of operations in selecting a codebook from a plurality of codebooks.A process 2400 may involve the processor 1010 determining a code block size of the data, further, the process 2400 may involve the processor 1010 selecting a codebook by (1) selecting a codebook of the plurality of codebooks in response to determining that the code block size is greater than a th threshold code block size, (2) selecting a second codebook of the plurality of codebooks in response to determining that the code block size is greater than a second threshold code block size, (3) selecting a third codebook of the plurality of codebooks in response to determining that the code block size is greater than a third threshold code block size.

Additional description

The subject matter described herein sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely examples, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "operably couplable," to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

Furthermore, with respect to the use of any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. For clarity, various singular/plural permutations (permutation) may be explicitly set forth herein.

In addition, those skilled in the art will understand that generally, terms used herein, particularly in the appended claims, such as the main subject of the appended claims, are generally intended as "open" terms, e.g., the term "including" should be read as "including but not limited to," the term "having" should be read as "having at least" or "including" should be read as "including but not limited to," etc. those skilled in the art should further understand that if a number of applications is intended for , such an intent should be expressly stated in the application scope, if no such recitation is intended to be absent of such recitation, for example, as an aid to understanding, the following appended patent application scope may include the use of "at least 1" and " 2 or more" to introduce the application scope, such use of such terms should not be interpreted as that any application scope including the introductory phrases "a" or "may be interpreted as" B "that" may include at least one of the same or "B" which is intended to introduce "B" or "B" may include at least one of "B5, or" may be interpreted as "including at least one of the same, or" B3, or "may be interpreted as" including at least one of the same, or "including a" or B3, or C3, and so long as a or C3, or C3, or C3, or C3, or C3, or C3, or C3, or C3, or C3, or C.

From the foregoing, it will be appreciated that various embodiments disclosed herein have been described herein for purposes of illustration, and that various modifications may be made without deviating from the scope and spirit of the invention. Accordingly, the various embodiments disclosed herein are not meant to be limiting, with the true scope and spirit being determined by the following claims.

Claims (20)

1, A method of wireless communication, comprising:

the processor of the device establishes a wireless communication link with at least other devices via the transceiver of the device, and

the processor wirelessly communicates with the other apparatus via the wireless communication link by:

selecting th shift coefficient table from the plurality of shift coefficient tables;

generating a quasi-cyclic low density parity check (QC-LDPC) code using a base matrix and a th shift coefficient table of at least parts;

selecting a codebook from a plurality of codebooks embedded into the QC-LDPC code;

storing the selected codebook in a memory associated with the processor;

encoding data using the selected codebook to generate a plurality of modulation symbols for the data; and

control the transceiver to multiplex, convert, filter, amplify, and radiate the modulated symbols as electromagnetic waves through or more antennas of the device to transmit the modulated symbols of data to the other device via a wireless communication link,

wherein the selecting th shift coefficient table from the plurality of shift coefficient tables comprises selecting the th shift coefficient table for a relatively larger code block size according to or more rules related to any or both of the code block size of the data and the code rate of the data.

2. The method of claim 1, wherein the th table of shift coefficients comprises a basic table of shift coefficients arranged in 4 rows and 26 columns in the following pattern:

3. the method of claim 1, wherein the th shift coefficient table comprises a shift coefficient table as shown in fig. 18A and 18B.

4. The method of claim 1, wherein the th table of shift coefficients comprises a table of shift coefficients corresponding to base graph 1(BG1) with original element 5 (a-5) and a lifting factor 320.

5. The method of claim 1, wherein the th table of shift coefficients comprises a table of shift coefficients corresponding to base graph 1(BG1) with original element 7 (a-7) and lifting factor 224.

6. The method of claim 1, wherein the th table of shift coefficients comprises a table of shift coefficients corresponding to base graph 1(BG1) with original element 15 (a-15) and lifting factor 240.

7. The method of claim 1, wherein the th table of shift coefficients comprises a table of shift coefficients corresponding to base graph 1(BG1) with primitive element 9 (a-9) and a lifting factor 288.

8. The method of claim 1, wherein the th table of shift coefficients comprises a table of shift coefficients corresponding to base graph 1(BG1) with original element 11 (a-11) and lifting factor 352.

9. The method of claim 1, wherein the th table of shift coefficients comprises a table of shift coefficients corresponding to base graph 1(BG1) with original element 3 (a-3) and a lifting factor 384.

10. The method of claim 1, wherein the th table of shift coefficients comprises a table of shift coefficients corresponding to base graph 1(BG1) with original element 13 (a-13) and lifting factor 208.

11. The method of claim 1, wherein the th table of shift coefficients comprises a table of shift coefficients corresponding to base graph 1(BG1) with original element 2 (a-2) and lifting factor 256.

12. The method of claim 1, wherein the generating a QC-LDPC code using a base matrix and at least a th shift coefficient table of parts comprises generating the QC-LDPC code using all of the th shift coefficient table and the base matrix.

13. The method of claim 1, wherein the generating a QC-LDPC code using a base matrix and a th shift coefficient table of at least parts comprises generating the QC-LDPC code using a part of the th shift coefficient table and the base matrix.

14. The method of claim 1, wherein the selecting th table of shift coefficients from the plurality of tables of shift coefficients comprises selecting a second table of shift coefficients having values or more modulo factors having the same modulo result as in the at least th table of shift coefficients.

15. The method of claim 14, wherein generating the QC-LDPC code using a base matrix and at least a th shift coefficient table of parts comprises generating the QC-LDPC code using all of the second shift coefficient table and the base matrix.

16. The method of claim 14, wherein generating the QC-LDPC code using a base matrix and a th shift coefficient table of at least parts comprises generating the QC-LDPC code using a part of the second shift coefficient table and the base matrix.

17. The method of claim 1, wherein selecting the th shift coefficient table from the plurality of shift coefficient tables comprises:

determining whether the code block size is less than or equal to a threshold code block size; and

determining whether the code rate is less than or equal to a threshold code rate.

18. The method of claim 17, wherein selecting the th shift coefficient table from the plurality of shift coefficient tables further comprises selecting the th shift coefficient table corresponding to base chart 1(BG1) in response to determining that the code block size is greater than a threshold code block size or in response to determining that the code rate is greater than a threshold code rate.

19. The method of claim 17, wherein selecting the th shift coefficient table from the plurality of shift coefficient tables further comprises selecting the th shift coefficient table corresponding to base graph 2(BG2) in response to determining that the code block size is less than or equal to a threshold code block size or in response to determining that the code rate is less than or equal to a threshold code rate.

20. The method of claim 1, wherein each codebooks of the plurality of codebooks correspond to respective HARQ threads of a plurality of hybrid automatic repeat request (HARQ) threads, wherein the plurality of HARQ threads are different from each other.

Images