TWI690073B - Floating diffusion of image sensor with low leakage current - Google Patents

Abstract

An image sensor including a photodiode, a floating diffusion region, a first, second, and third doped region of a semiconductor material, and a first capacitor is presented. The photodiode is disposed in the semiconductor material to generate image charge in response to incident light. The floating diffusion region is disposed in the semiconductor material proximate to the photodiode. The floating diffusion region is at least partially surrounded by the first doped region of the semiconductor material. The second doped region and the third doped region of the semiconductor material each have an opposite polarity of the floating diffusion region and the first doped region. The floating diffusion region and at least part of the first doped region are laterally disposed between the second doped region and the third doped region. The first capacitor is positioned proximate to a first interface between the first doped region and the second doped region or a second interface between the first doped region and the third doped region.

Description

Floating diffusion of image sensor with low leakage current

The present invention relates generally to semiconductor devices, and specifically but not exclusively relates to CMOS image sensors.

Image sensors have become ubiquitous. It is widely used in digital devices such as still cameras, cellular phones, video cameras, and in medical, automotive, security, and other applications. The technology used to manufacture image sensors continues to make rapid progress. For example, the need for higher resolution and lower power consumption has promoted further miniaturization and integration of these devices.

A typical image sensor operates as follows. The image light from the external scene is incident on the image sensor. The image sensor includes a plurality of photosensitive elements, so that each photosensitive element absorbs a part of incident image light. The photosensitive elements (for example, photodiodes) included in the image sensor each generate image charges immediately after absorbing the image light. The amount of image charge generated is proportional to the intensity of the image light. The generated image charge can be used to generate images representing external scenes.

However, as the miniaturization of the image sensor progresses, defects in the image sensor architecture become more obvious and can reduce the image quality of the image. For example, excessive current leakage in a specific area of the image sensor can cause high dark current, sensor noise, white pixel defects, etc. These defects can significantly degrade the image quality from the image sensor, which can lead to reduced yield and increased production costs.

This article describes an example of an apparatus for an image sensor that includes floating diffusion with low leakage current. In the following description, numerous specific details are stated to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein may be practiced without one or more of these specific details, or may be practiced using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "an example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Therefore, the phrases "in an instance" or "in an embodiment" that appear throughout the specification may not all refer to the same instance. Furthermore, such specific features, structures, or characteristics may be combined in any suitable manner in one or more examples.

Throughout this manual, several technical terms are used. These terms will assume their ordinary meanings in the field to which they belong, unless otherwise specifically defined herein or the context in which they are used will clearly imply otherwise. It should be noted that in this document, device names and symbols are used interchangeably (for example, Si and silicon); however, the two have the same meaning.

In some embodiments, an image sensor including a floating diffusion region with low leakage current is described. Minimizing or reducing leakage current at or near the floating diffusion area of the image sensor can help improve image quality, improve yield, and extend operating life. For example, the leakage current at or near the floating diffusion region may affect the signal read from the floating diffusion region by the readout circuit due to shortcomings such as high dark current, white pixel defects, low signal-to-noise ratio, and the like. For example, white pixel defects can be related to current leakage, and the current leakage comes from areas that are subjected to mechanical stress during fabrication, areas that are subjected to electrical stress during device operation, or a combination of the two. When the image charge, image data, or image signal is stored in the floating diffusion area for a long period of time (eg, 0.1 millisecond) before reading, the leakage current may be a particularly significant problem. Therefore, some image sensors that utilize a global shutter architecture and/or lateral overflow integration capacitors may be prone to encounter these problems caused by leakage current due to their tendency to store image charges for long periods of time. However, embodiments of the present invention alleviate or reduce such problems by utilizing the image sensor architecture described herein. For example, such embodiments may allow for an increase in full well capacity and then increase the high dynamic range.

Embodiments of the present invention utilize image sensor architectures with various features to form image sensors that include floating diffusion with low leakage current. For example, in some embodiments, the floating diffusion region is an N+ implanted region in a semiconductor material. The N+ implant region may have implant damage in a region of the semiconductor material that at least partially surrounds one of the N+ implant regions, NLDD (n-type lightly doped drain). Implant damage may be caused by manufacturing techniques (eg, implants used to form the N+ implant area) and correspond to mechanical stress areas or damage areas of the image sensor that may cause current leakage. In some embodiments, the effect of implantation damage can be at least partially mitigated by incorporating N-doped regions of the semiconductor material that at least partially surround the NLDD region. Subsequently, the NLDD region is placed between the N-doped region and the N+ implanted region. The configurations described for the N+ implanted region, NLDD region, and N-doped region can prevent the depleted regions close to the N+ region (eg, from the transfer transistor, reset transistor, etc.) from extending to have implant damage Area (eg, NLDD area) (and therefore may not be affected by the area).

In the same or other embodiments, the floating diffusion region is at least partially surrounded by a capacitor that is biased to a negative voltage to shield the Si surface (eg, of semiconductor material). The negative bias prevents the Si surface from being depleted. In one embodiment, a negatively biased capacitor (eg, MOS capacitor) is used to make the surface located near or at the surface of the semiconductor material and close to the floating diffusion region (eg, N+ implanted region) -Interface traps are quenched. The trapped sites and dangling bonds close to the surface of the semiconductor material can increase the dark current of the image sensor. The increased dark current due to surface-interface traps can be partially alleviated by capacitors. In some embodiments, the capacitor may be a metal oxide semiconductor (MOS) capacitor, wherein the metal may be polysilicon (polysilicon), tungsten (W), etc., and the oxide may be a dielectric such as SiO ₂ (eg, Thermally grown or deposited on the semiconductor material), and the semiconductor may correspond to a portion of the semiconductor material.

In some embodiments, the silicon nitride (Si ₃ N ₄ ) sidewalls are deposited between the gate electrode (eg, a transfer gate, reset gate, etc.) as an insulator and the chemical barrier of the image sensor At the interface. However, the silicon nitride sidewalls can cause additional mechanical stress on the semiconductor material, which leads to crystal defects and may cause increased leakage current. Therefore, in some embodiments, the silicon nitride sidewalls can be explicitly omitted in the image sensor architecture so that Si ₃ N ₄ does not coat the sidewalls of the gate electrode. More precisely, the NLDD region can directly extend to the sidewall of the gate electrode.

In the same or other embodiments, the floating diffusion region (eg, N+ implanted region) is at least partially surrounded by a P+ doped region of one of the semiconductors. The P+ doped region is at least partially surrounded by one of the semiconductor P- doped regions, so that the P- region is disposed between the N+ implanted region and the P+ region. The P+ region surrounded by the P- region serves as a gettering region for attracting impurities in the semiconductor material. For example, metal or heavy metal impurities can migrate or diffuse from the semiconductor material toward the P+ region to reduce its energy. Therefore, the P+ region surrounded by the P- region can be used to reduce generation-recombination centers caused by impurities, and these generation-recombination centers can be one source of leakage current or white pixel defects.

FIGS. 1A- 1C are top and cross-sectional illustrations of an example image sensor 100 including a floating diffusion with low leakage current according to the teachings of the present invention. 1A to 1C as shown in the display, the image sensor 100 comprises a semiconductor material 101, photodiode 103, pinned layer 106, p well 107, floating diffusion 109, a gate dielectric 110, a first doped region 111, a second doped region 117, a third doped region 123, a first capacitor 153, a second capacitor 163, a transfer gate 171, and a reset gate 175. The first doped region 111 includes a first portion 113 and a second portion 115. The second doped region 117 and the third doped region 123 each include a third portion 121/127 and a fourth portion 119/125, respectively. The first capacitor 153 includes a first dielectric layer 155 and a first electrode 157. The second capacitor includes a second dielectric layer 165 and a second electrode 167.

In some embodiments, various materials and manufacturing techniques may be used to form the image sensor 100. The semiconductor material 101 may have a Si composition (for example, single crystal Si or polycrystalline Si). The first electrode 157 and/or the second electrode 167 may have a composition including tungsten or polysilicon. The first dielectric layer 155 and the second dielectric layer 165 may have SiO ₂ , HfO _2, or any other suitable dielectric medium composition known to those skilled in the art. Other metals, semiconductors, and insulating materials can also be used for the image sensor 100, as known to those skilled in the art. The doped regions of the semiconductor material 101 can be formed by diffusion, implantation, and the like. The image sensor 100 may be manufactured using manufacturing techniques such as photolithography, chemical etching, ion implantation, thermal evaporation, chemical vapor deposition, and sputtering, which are known to those skilled in the art.

FIG. 1A is a top view illustration of an image sensor 100 according to the teachings of the present invention. As illustrated, the image sensor 100 will be explained along two directions orthogonal to each other. The first direction is along line AA', and the second direction is along line BB'.

FIG. 1B shows the system according to the teachings of the present invention taken along line A-A 'cut of FIG. 1A cross-sectional view of the image sensor 100 illustrated one. As illustrated, the photodiode 103 is disposed in the semiconductor material 101 to generate image charges in response to incident light. In some embodiments, the photodiode 103 may be a pinned or partially pinned photodiode, wherein the pinned layer 106 is disposed between the first side 102 of one of the semiconductor materials 101 and the photodiode 103 between. The semiconductor material 101 has a first side 102 opposite a second side 104. The pinned layer 106 can reduce dark current and improve the quantum efficiency of the photodiode 103 by suppressing surface-interface trapping close to the first side 102 of the semiconductor material 101.

As illustrated, the transfer gate 171 is electrically coupled between the photodiode 103 and the floating diffusion region 109. The image charge generated by the photodiode 103 can be transferred to the floating diffusion region 109 in response to a transfer signal applied to the transfer gate 171. In some embodiments, the transfer gate is a vertical transfer gate. In other words, the transfer gate can be part of a vertical transistor. Similarly, the reset gate 175 is electrically coupled to the floating diffusion region 109 to draw image charges from the floating diffusion region 109 in response to a reset signal applied to one of the reset gate 175. As illustrated, the gate dielectric 110 is disposed between the first side 102 of the semiconductor material 101 and both the transfer gate 171 and the reset gate 175.

In the illustrated embodiment, the floating diffusion region 109 is disposed in the semiconductor material 101 close to the photodiode 103. More specifically, in some embodiments, the floating diffusion region 109 and the photodiode 103 are oriented along the first direction AA'. The floating diffusion region is at least partially surrounded by the first doped region 111, one of the semiconductor materials. The first doped region 111 may include a first portion 113 disposed between the floating diffusion region 109 and the second portion 115 of the first doped region 111. In some embodiments, the first doping concentration of one of the semiconductor materials 101 decreases from the floating diffusion region 109 to the second portion 115 of the first doped region 111. For example, in some embodiments, the floating diffusion region 109 has an N+ doping distribution, the first portion 113 has an n-type lightly doped distribution (eg, n-type lightly doped drain), and The second part 115 has an N-doping profile.

In some embodiments, the configuration of the first doped region 111 and the floating diffusion region 109 reduces leakage current by keeping implant damage away from a depleted region. For example, in some embodiments, the floating diffusion region 109 and the first doped region 111 may be at least partially disposed within the p-well 107. Therefore, as illustrated, the second portion 115 of the first doped region 111 is placed close to the p-well 107. The depleted region may correspond to a region of the semiconductor material 101 where the second portion 115 (n-type) and the p-well 107 (p-type) interface (eg, the interface 135 below the transfer gate 171 and/or the reset gate) Interface 139 below pole 175). Implantation damage (eg, due to the implantation technique used to make the floating diffusion region 109) can extend into the first portion 113 but not into the second portion 115. In other words, a depleted region close to the photodiode 103 (eg, near the first side 102 of the semiconductor material 101 and between the floating diffusion region 109 and the photodiode 103) does not extend to the point where implantation damage may exist In the floating diffusion region 109. Therefore, the second portion 115 can act as a barrier and limit the impact of implantation damage on the depleted area. The implantation damage in the non-depleted regions (for example, the floating diffusion region 109 and the first part 113) should not have a negative effect on dark current or introduce white pixel defects.

FIG 1C illustrates lines along the line B-B 'cut the image sensor in FIG. 1A illustrates a cross-sectional view of one of 100 according to the teachings of the present invention. As illustrated, the semiconductor material 101 of the image sensor 100 includes a second doped region 117 and a third doped region 123. In some embodiments, the second doped region 117 and the third doped region 123 have the opposite of the floating diffusion region 109 and the first doped region 111 (eg, the first portion 113 and the second portion 115) One polarity. In some embodiments, the floating diffusion region 109 and the first doped region 111 are n-type (eg, the electron concentration is greater than the hole concentration), and the second doped region 117 and the third doped region 123 It is p-type (for example, the hole concentration is greater than the electron concentration).

As illustrated, at least a portion of the floating diffusion region 109 and the first doped region 111 (eg, a portion of the first portion 113 and a portion of the second portion 115) are laterally disposed on the second doped region 117 and the third Between the doped regions 123. In some embodiments, the floating diffusion region 109, the first doped region 111 (eg, the first portion 113 and the second portion 115), the second doped region 117, and the third doped region 123 extend to the semiconductor The first side 102 of the material 101.

In the same or other embodiments, the second doped region 117 may include a third portion 121 and a fourth portion 119. The third doped region 123 may also include a third portion 127 and a fourth portion 125. As illustrated, the third part 121 may be at least partially surrounded by the fourth part 119. Similarly, the third portion 127 may also be at least partially surrounded by the fourth portion 125. The third portion 121/127 may have a P+ doping profile or concentration, and the fourth portion 119/125 may have a P- doping profile or concentration.

The second doped region 117 and the third doped region 123 may represent gettering sites for absorbing impurities in the semiconductor material 101. For example, impurities or defects in the semiconductor material 101 can be actively transferred from the first doped region 111 to the second doped region 117 or the third doped region 123. By providing a positive vantage point where impurities can reside or diffuse (eg, the third part 121/127), the effect of such impurities on the leakage current of the image sensor 100 can be at least partially mitigated.

In some embodiments, the second portion 115 of the first doped region 111 extends laterally along the first side 102 of the semiconductor material 101. The second portion 115 may meet or interface with the second doped region at a first interface 134. Similarly, the second portion 115 may meet or interface with the third doped region 123 at a second interface 138.

In the same or other embodiments, the first capacitor 153 and the second capacitor 163 may be disposed close to the first interface 134 and the second interface 138. For example, the first capacitor 153 may be located close to the first interface 134 between the first doped region 111 (eg, the first portion 113 and the second portion 115) and the second doped region 117. In other embodiments, the first capacitor 153 may be positioned close to the second interface 138 between the first doped region 111 and the third doped region 123. In still other embodiments, the image sensor 100 may include a first capacitor 153 and a second capacitor 163. The first capacitor 153 may be positioned close to the first interface 134 and the second capacitor 163 may be positioned close to the second interface 138. As illustrated, the first capacitor 153 may extend laterally from at least the first portion 115 of the first doped region 111 to the third portion 121 of the second doped region 117. Similarly, the second capacitor 153 may extend laterally from at least the first portion 115 of the first doped region 111 to the third portion 127 of the third doped region 123. In addition, the first capacitor 153, the second capacitor 163, and the floating diffusion region 109 are oriented along the second direction BB'. The second direction is orthogonal to the first direction.

In some embodiments, the first capacitor 153 and the second capacitor 163 are metal oxide semiconductor (MOS) capacitors. For example, the first capacitor 153 may include a first dielectric layer 155 and a first electrode 157. A first segment of the semiconductor material 101 disposed close to the first dielectric layer 153 can be regarded as a semiconductor part of the first capacitor 153. The first segment is located close to the first interface 134. As illustrated, the first dielectric layer 155 is disposed between the first electrode 157 and the first segment of semiconductor material. More specifically, the first dielectric layer 155 may extend from the first electrode 157 to the first side 102 of the semiconductor material 101 and be disposed between the first electrode 157 and the first interface 134. The second capacitor 163 may include a second dielectric layer 165 and a second electrode 167. Similarly, the second segment of the semiconductor material 101 disposed close to the second dielectric layer 165 can be regarded as the semiconductor part of the second capacitor 163. The second segment is positioned close to the second interface 138. As illustrated, the second capacitor 163 may have an element position configuration similar to the first capacitor 153. More specifically, the second dielectric layer 165 may be disposed between the second electrode 167 and the second interface 138.

In some embodiments, the first capacitor 153 and/or the second capacitor 163 may be used to shield the semiconductor material 101 from the first side 102 and the corresponding first capacitor 153 or second capacitor that may be close to the semiconductor material 101 163 The effects of localized crystal defects, surface-interface charge traps, dangling bonds, impurities, etc. For example, in some embodiments, the first capacitor 153 is electrically coupled to the second capacitor 163 and is positioned close to the first side 102 of the semiconductor material 101. Therefore, in response to the bias (eg, negative bias) applied to the first capacitor 153 and the second capacitor 163, the floating diffusion region 109 and the first interface 134 or the floating diffusion region 109 may be crossed across the first side 102 A hole is induced laterally with the second interface 138. The generated holes can quench the surface-interface trapping state close to the first side 102 of the semiconductor material 101. Quenching the surface-interface trapped states can prevent these trapped states from affecting the leakage current (eg, dark current, white pixel defects, etc.) of the image sensor 100.

Figure 2 shows a diagram of the image sensor may comprise FIGS. 1A to 1C according to the teachings of the present invention is a circuit diagram of one embodiment 100 of one of the unit 4T pixel cell embodiment. The 4T unit pixel unit may include a photodiode 103, a transfer gate/transistor 171, a floating diffusion region 109, a reset gate/transistor 175, a source follower transistor 285, a column selection transistor 287, and storage Node Structure (SS) 253. SS 253 may be coupled to one or more capacitors (e.g., FIGS. 1A to 1C of the first capacitor 153 and second capacitor 163).

During a readout operation of one of the photodiodes 103, the transfer transistor 171 receives a transfer signal that causes the transfer transistor 171 to transfer the image charge accumulated in the photodiode 103 to the floating diffusion region 109. In some embodiments, when the floating diffusion region 109 is positively storing image charges, a bias voltage (eg, a negative bias voltage) may be applied to SS 253 to induce holes to quench surface-interface trap sites to mitigate Accidental leakage of image charge from floating diffusion 109. The reset transistor RST 175 is coupled to the floating diffusion region 109 in response to a reset signal or reset under the control of the reset signal (for example, discharging or charging the floating diffusion region 109 to a predetermined voltage). The floating diffusion region is also coupled to the gate of the source follower transistor SF 285, which in turn is coupled to the column select transistor RS 287. The SF 285 serves as a source follower, thereby providing a high impedance output from the floating diffusion region 209. RS 287 selectively couples the output of the pixel circuit to a row of bit lines under the control of a column selection signal. In some embodiments, the transfer signal, reset signal, and column select signal are generated by a control circuit (not illustrated).

FIG 3 illustrates a system according to the teachings of the present invention may comprise 300 is shown a block diagram of one example of the image sensor of FIGS. 1A to 1C, one 100 of the imaging system. The imaging system 300 includes a pixel array 310, a readout circuit 316, functional logic 320, and a control circuit 324. In one embodiment, the pixel array 310 is a two-dimensional (2D) array of photodiodes or image sensor pixels (eg, pixels P1, P2..., Pn). As illustrated, the photodiodes are arranged in columns (eg, columns R1 to Ry) and rows (eg, rows C1 to Cx) to obtain image data of people, places, objects, etc., and then the images can be used Data to reproduce 2D images of people, places, objects, etc. However, the photodiodes are not necessarily arranged in columns and rows, but other configurations may be adopted.

In one example, after each image sensor photodiode/pixel in the pixel array 310 has acquired its image data or image charge, the image data is read by the readout circuit 316 and then transferred to the functional logic 320. In various examples, the readout circuit 316 may include an amplification circuit, an analog-to-digital conversion (ADC) conversion circuit, or others. The function logic 320 may only store the image data, or even manipulate the image data by applying post-image effects (eg, crop, rotate, remove red eye, adjust brightness, adjust contrast, or others). In one example, the readout circuit 316 can read out a column of image data (illustrated) at a time along the readout row line, or can read images using various other techniques (not illustrated), such as serial readout or simultaneous All pixels are read out in full parallel.

In another embodiment, the control circuit 324 is coupled to the pixel array 310 to control the operation of the plurality of photodiodes in the pixel array 310. For example, the control circuit 324 may generate a shutter signal for controlling image acquisition. In the illustrated example, the shutter signal is a global shutter signal that simultaneously activates all pixels in the pixel array 310 to simultaneously capture their corresponding image data or image charge during a single acquisition window. In another embodiment, image acquisition is synchronized with the lighting effect (eg, a flash).

The above explanations of the illustrated examples of the present invention (including those set forth in the Summary of the Invention) are not intended to be exhaustive or to limit the present invention to the precise forms disclosed. Although specific examples of the invention are set forth herein for illustrative purposes, those skilled in the art should recognize that various modifications can be made within the scope of the invention.

Such modifications can be made to the present invention in view of the above detailed description. The terms used in the scope of the attached patent application should not be construed as limiting the invention to the specific examples disclosed in this specification. Rather, the scope of the present invention will be completely determined by the scope of the attached patent application, and the scope of the patent application will be explained according to the principle of interpretation of the created claim.

100 Image sensor 101 Semiconductor materials 102 First side 103 Photoelectric Diode 104 Second side 106 Pinned layer 107 p well 109 Floating diffusion/floating diffusion area 110 Gate Dielectric 111 The first doped region 113 Part I 115 Part Two 117 Second doped region 119 Part Four 121 Part Three 123 Third doped region 125 Part Four 127 Part Three 134 First interface 135 Interface 138 Second interface 139 Interface 153 First capacitor 155 First dielectric layer 157 First electrode 163 Second capacitor 165 Second dielectric layer 167 Second electrode 171 Transfer Gate/Transfer Transistor 175 Reset gate/transistor/transistor reset 253 Storage node structure 285 Source Follower Transistor Transistor 287 Column selection transistor 300 imaging system 310 pixel array 316 readout circuit 320 functional logic 324 Control circuit AA' line/first direction BB' line/second direction C1-Cx line P1-Pn pixels R1-Ry column

A non-limiting and non-exhaustive example of the present invention is explained with reference to the following figures, wherein similar element symbols refer to similar parts in all views unless otherwise specified.

FIG. 1A is a top view illustration of an example image sensor according to the teachings of the present invention.

FIG. 1B shows the system along line A-A 'cut of the image sensor in FIG. 1A illustrates a cross-sectional view of one of the accordance with the teachings of the present invention.

One of the image sensor in FIG. 1C illustrates a cross-sectional based accordance with the teachings of the present invention taken along line B-B 'shown in FIG. 1A cut in the.

Figure 2 shows a diagram of the image sensor may comprise one of FIGS. 1A to 1C a circuit diagram of one embodiment of the 4T pixel cell embodiment of the unit according to the teachings of the present invention.

FIG 3 illustrates a system according to the teachings of the present invention is shown an imaging system may comprise one of the image sensor of FIGS. 1A to 1C, one example of a block diagram.

Throughout the several views of the diagram, corresponding reference characters indicate corresponding components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity, and are not necessarily drawn to scale. For example, to help promote understanding of various embodiments of the present invention, the size of some of the elements in the figures may be exaggerated relative to other elements. Moreover, common and well-known elements that are useful or necessary in commercially feasible embodiments are generally not shown to facilitate a clearer understanding of these various embodiments of the present invention.

100 Image sensor 101 Semiconductor materials 109 Floating diffusion/floating diffusion area 113 Part I 115 Part Two 119 Part Four 121 Part Three 125 Part Four 127 Part Three 157 First electrode 167 Second electrode 171 Transfer gate/Transistor 175 Reset gate/transistor/transistor reset AA' line/first direction BB' line/second direction

Claims (20)

An image sensor, including: A photodiode, which is placed in a semiconductor material to generate image charge in response to incident light; A floating diffusion region disposed in the semiconductor material close to the photodiode, wherein the floating diffusion region is at least partially surrounded by a first doped region of the semiconductor material; A second doped region and a third doped region of the semiconductor material each have a polarity opposite to the floating diffusion region and the first doped region, wherein the floating diffusion region and the first doped region At least a portion of the doped region is laterally disposed between the second doped region and the third doped region; and A first capacitor close to a first interface between the first doped region and the second doped region or close to the first doped region and the third doped region Between one of the second interfaces. The image sensor of claim 1, wherein the floating diffusion region and the first doped region are n-type, and wherein the second doped region and the third doped region are p-type. The image sensor of claim 1, wherein the first doped region includes a first portion, the first portion is disposed between the floating diffusion region and a second portion of the first doped region, wherein A first doping concentration of the semiconductor material decreases from the floating diffusion region to the second portion of the first doped region. The image sensor of claim 3, wherein a depleted region close to the photodiode does not extend into the floating diffusion region. The image sensor of claim 3, wherein the second doped region and the third doped region each include a third portion at least partially surrounded by a fourth portion, wherein a first portion of the semiconductor material The second doping concentration decreases from the third part to the fourth part. The image sensor according to claim 5, wherein the third portion and the fourth portion have a P+ doping distribution and a P- doping distribution, respectively. The image sensor of claim 5, wherein the second doped region and the third doped region are absorption sites for absorbing impurities in the semiconductor material. The image sensor of claim 5, wherein the first capacitor is positioned close to the first interface, and wherein the first capacitor extends at least laterally from the first portion of the first doped region to the second This third part of the doped region. The image sensor of claim 8, wherein the first capacitor includes a first dielectric layer and a first electrode, wherein the first dielectric layer is disposed between the first electrode and the first interface. The image sensor according to claim 9, wherein a composition of the first electrode includes tungsten or polysilicon. The image sensor of claim 8 further includes: A second capacitor positioned close to the second interface, and wherein the second capacitor extends at least laterally from the first portion of the first doped region to the third portion of the third doped region . The image sensor according to claim 11, wherein the second capacitor includes a second dielectric layer and a second electrode, wherein the second dielectric layer is disposed between the second electrode and the second interface. The image sensor of claim 11, wherein the floating diffusion region, the first doped region, the second doped region, and the third doped region extend to a first side of the semiconductor material, The first side is opposite to a second side of the semiconductor material. The image sensor of claim 13, wherein the first capacitor is electrically coupled to the second capacitor, wherein the first capacitor and the second capacitor are positioned close to the first side of the semiconductor material, and wherein In response to a negative bias applied to one of the first capacitor and the second capacitor, across the first side and laterally between the floating diffusion region and the first interface or between the floating diffusion region and the second interface Induce electric holes. If the image sensor of claim 1, further includes: A transfer gate electrically coupled between the photodiode and the floating diffusion region in response to a transfer signal applied to the transfer gate to transfer the image charge from the photodiode to The floating diffusion area. The image sensor according to claim 15, wherein the transfer gate is a vertical transfer gate. If the image sensor of claim 1, further includes: A reset gate is electrically coupled to the floating diffusion region, wherein the reset gate resets the image charge in the floating diffusion region in response to a reset signal. The image sensor of claim 1, wherein the floating diffusion area and the photodiode are oriented along a first direction, wherein the first capacitor and the floating diffusion area are oriented along a second direction, and wherein the The first direction is orthogonal to the second direction. If the image sensor of claim 1, further includes: A pinned layer is disposed between a first side of the semiconductor material and the photodiode, and wherein the photodiode system is partially pinned to the photodiode. If the image sensor of claim 1, further includes: A p-well is located close to the photodiode, wherein the floating diffusion region and the first doped region are at least partially disposed in the p-well.

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