CN113035892A

CN113035892A - Photosensitive pixel, image sensor and manufacturing method thereof

Info

Publication number: CN113035892A
Application number: CN202011517536.2A
Authority: CN
Inventors: 黄信耀; 洪丰基; 林政贤; 许慈轩; 卢彦池
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-12-24
Filing date: 2020-12-21
Publication date: 2021-06-25
Also published as: KR102406820B1; KR20210082337A

Abstract

A light-sensitive pixel, comprising: the semiconductor device includes a substrate, a photosensitive region, a floating diffusion region, a transfer gate, and a control electrode. The photosensitive region is located within the substrate. The floating diffusion region is located in the substrate beside the photosensitive region. A transfer gate is disposed on the substrate and extends into the photosensitive region. A control electrode is located on the substrate and extends into the floating diffusion region.

Description

Photosensitive pixel, image sensor and manufacturing method thereof

Technical Field

Embodiments of the present disclosure relate to a photosensitive pixel, and more particularly, to an image sensor including a photosensitive pixel and a method of fabricating the same.

Background

Complementary Metal-Oxide-Semiconductor (CMOS) image sensors (CIS) are used in many applications including, for example, digital cameras. The image sensor converts the optical image into digital data that can be represented as a digital image. An image sensor includes an array (or grid) of pixels for detecting light and recording the intensity (brightness) of the detected light. The pixel array responds to light by accumulating charge. The accumulated charge is then used (e.g., by other circuitry) to provide color and brightness signals for use in a suitable application, such as a digital camera.

Disclosure of Invention

The disclosed embodiments provide a photosensitive pixel, which includes a substrate, a photosensitive region, a floating diffusion region, a transfer gate, and a control electrode. A photosensitive region is located within the substrate. A floating diffusion region is located in the substrate beside the photosensitive region. A transfer gate is disposed on the substrate and extends into the photosensitive region. A control electrode is located on the substrate and extends into the floating diffusion region.

An embodiment of the present disclosure provides an image sensor, including a plurality of pixels, and at least one of the pixels includes: the first photosensitive region, the first transfer grid, the second photosensitive region, the second transfer grid, the floating diffusion region and the control electrode. The first photosensitive area is located in the substrate. A first transfer gate is disposed on a front side of the substrate and extends into the first photosensitive region. The second photosensitive region is located in the substrate. A second transfer gate is disposed on the front side of the substrate and extends into the second photosensitive region. A floating diffusion region is disposed from the front side of the substrate to a location within the substrate, wherein the floating diffusion region is common between the first photosensitive region and the second photosensitive region. A control electrode on the front side of the substrate and extending into the floating diffusion region.

Embodiments of the present disclosure provide a method for manufacturing an image sensor, including the sub-step of: doping the substrate with a first dopant; forming a first photosensitive region within the substrate by doping the substrate with a second dopant different from the first dopant; forming a floating diffusion region in the substrate beside the first photosensitive region; forming a first transfer gate on a front side of the substrate and extending into the first photosensitive region; and forming a control electrode on the front side of the substrate and extending into the floating diffusion region.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A through 1E are schematic cross-sectional views of various stages in a method of manufacturing an image sensor according to some exemplary embodiments of the present disclosure.

Fig. 2 is a schematic top view of a pixel, according to some exemplary embodiments of the present disclosure.

Fig. 3 is an equivalent circuit diagram of an image sensor according to some exemplary embodiments of the present disclosure.

Fig. 4A-4C are potential well diagrams depicting the transfer of charge from a photosensitive region to a floating diffusion region in an image sensor, according to some comparative embodiments of the present disclosure.

Fig. 5A-5C are potential well diagrams showing charge transfer from a photosensitive region to a floating diffusion region in an image sensor, according to some exemplary embodiments of the present disclosure.

The reference numbers illustrate:

102: a substrate;

102 FT: a front side;

102 BK: a back side;

104A: a gate dielectric;

104B: a dielectric layer;

106: an interlayer dielectric layer;

108: a carrier substrate;

110: an anti-reflection layer;

112: a color filter;

114: a microlens;

130A: a lightly doped well;

130B: a heavily doped well;

a1, a2, A3, a4, a 5: a first doping well;

b1, B2, B3: a second doping well;

DC: a drive circuit;

FD: a floating diffusion region;

OP1, OP 2: an opening;

PD, PD1, PD2, PD3, PD 4: a light sensing area;

PXL: a pixel;

RST: a reset transistor;

sb1, Sb2, Sb3, Sb 4: a sub-pixel;

SEL: a selection transistor;

SF: a source follower transistor;

TxT: a transfer gate transistor;

tx, Tx1, Tx2, Tx3, Tx 4: a transfer gate;

va: a control electrode;

VDD: a DC voltage supply terminal;

vout: and (4) an output end.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a second feature over or on a first feature may include embodiments in which the second feature is formed in direct contact with the first feature, and may also include embodiments in which additional features may be formed between the second feature and the first feature such that the second feature may not be in direct contact with the first feature. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms, such as "below …," "below …," "lower," "on …," "above …," "overlying," "above …," "upper," and similar terms, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1A through 1E are schematic cross-sectional views of various stages in a method of manufacturing an image sensor according to some exemplary embodiments of the present disclosure. Referring to fig. 1A, a substrate 102 having a front side 102FT and a back side 102BK is provided. In some embodiments, substrate 102 may include any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or associated therewith. In some embodiments, the substrate 102 is doped with a first dopant having a first conductivity type. In addition, a plurality of first doping wells (a1, a2, A3, a4, and a5) belonging to the first conductive type are formed in the substrate 102. In some embodiments, each of the first doping wells (a1, a2, A3, a4, and a5) has the same or different doping concentration, and such doping concentration may be adjusted based on design requirements. For example, the first doped well (a1, a2, A3, a4, and a5) may have a doping concentration of from about 10¹⁴From about 10 per cubic centimeter¹⁹Doping concentration in the range per cubic centimeter. Although five first doping wells (a1, a2, A3, a4, and a5) are shown in fig. 1A, it should be noted that the number of first doping wells in the substrate 102 is not limited thereto. In some alternative embodiments, the number of first doping wells and the area of the doping wells may be appropriately adjusted based on design requirements.

Furthermore, in some embodiments, a photosensitive region (PD) may be formed within the substrate 102 by doping the substrate 102 with a second dopant having a second conductivity type. In certain embodiments, the second dopant is different from the first dopant. For example, in one exemplary implementationIn one example, the first dopant is a P-type dopant and the second dopant is an N-type dopant. However, the present disclosure is not limited thereto. In some other embodiments, the first dopant is an N-type dopant and the second dopant is a P-type dopant. As shown in fig. 1A, in some embodiments, the photosensitive region PD is formed by forming a plurality of second doping wells (B1, B2, and B3) within the substrate 102. In some embodiments, the second doping well (B1, B2, and B3) may have a doping from about 10¹⁴From about 10 per cubic centimeter¹⁹Doping concentration in the range per cubic centimeter. In one exemplary embodiment, the doping concentration of the second doping well (B1, B2, and B3) increases from the front side 102FT of the substrate 102 to the back side 102BK of the substrate. In other words, the second doping well B2 may have a higher doping concentration than the second doping well B1, and the second doping well B3 may have a higher doping concentration than the second doping well B2. However, this is not to be construed as limiting the present disclosure. In some embodiments, each of the second doping wells (B1, B2, and B3) has the same or different doping concentration, and such doping concentrations may be adjusted based on design requirements. Similarly, the number of second doping wells and the area of the doping wells may be appropriately adjusted based on design requirements.

As further shown in fig. 1A, in some embodiments, the photosensitive region PD is embedded within the substrate 102 and surrounded by the first doping well (a1, a2, A3, a4, and a 5). In some embodiments, the photosensitive regions PD are capable of accumulating image charge in response to incident light when the incident light is irradiated. For example, in some embodiments, the photo-sensing region PD and the substrate 102 contact each other to form a P-N junction photodiode (P-N junction photodiode) configured to convert radiation into an electrical signal.

In some embodiments, a floating diffusion region (FD) is disposed within the substrate 102 beside the photosensitive region PD. For example, the floating diffusion region FD is disposed from the front side 102FT of the substrate 102 to a location within the substrate 102. In certain embodiments, the floating diffusion region FD is located on the first doping well a2 of the substrate 102. In addition, the floating diffusion region FD may include a lightly doped well 130A of the second conductive type and a heavily doped well 130B of the second conductive type. In some embodiments, the lightly doped well 130A is located on a first doped well a2 of the substrate 102 and the heavily doped well 130B is located on the lightly doped well 130A. In one exemplary embodiment, when the photosensitive region PD is doped with an N-type dopant and the substrate 102 is doped with a P-type dopant, then the floating diffusion region FD may include a lightly doped N-well 130A and a heavily doped N-well 130B. In some embodiments, the floating diffusion region FD may act as a capacitor for storing image charge.

Referring to fig. 1B, after doping the substrate 102 to form various doped regions, the substrate 102 may be patterned to form openings (OP1, OP 2). In some embodiments, the patterning process may include a photolithography process and an etching process. For example, in some embodiments, an opening OP1 extending into the photosensitive PD is formed in the substrate 102, and another opening OP2 extending into the floating diffusion region FD is formed in the substrate 102. In an exemplary embodiment, the opening OP1 extends through the second doping well B3 and toward the second doping well B1 of the photosensitive region PD. Furthermore, in some embodiments, the opening OP2 extends through the floating diffusion region FD and towards the first doping well a2 of the substrate 102. In some embodiments, the depth of opening OP1 is substantially equal to the depth of opening OP 2. In some embodiments, opening OP1 and opening OP2 are patterned in the same step.

In some embodiments, after forming the opening OP1 and the opening OP2, the gate dielectric 104A may be formed in the opening OP1 and the dielectric layer 104B may be formed in the opening OP 2. In some embodiments, the gate dielectric 104A is conformally formed on the sidewalls of the opening OP1 to cover the photosensitive region PD. In a similar manner, the dielectric layer 104B is conformally formed on the sidewalls of the opening OP2 to cover the floating diffusion region FD. In some embodiments, the gate dielectric 104A and the dielectric layer 104B are formed of the same material. However, the present disclosure is not limited thereto. In alternative embodiments, the gate dielectric 104A and the dielectric layer 104B may be formed of different materials.

In an exemplary embodiment, the gate dielectric 104A and the dielectric layer 104B are formed of: such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric materials. High-k dielectric materials are typical dielectric materials having a dielectric constant greater than 4. In some embodiments, the high-k dielectric material may comprise a metal oxide. Examples of metal oxides for high-k dielectric materials include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof. In some embodiments, the gate dielectric 104A and the dielectric layer 104B may be formed using a suitable process, such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), thermal oxidation, UV-ozone oxidation, or a combination thereof. Further, the gate dielectric 104A and the dielectric layer 104B may be formed in the same step, or may be formed in different steps according to the selection of their materials.

Referring to fig. 1C, in some embodiments, after forming the gate dielectric 104A and the dielectric layer 104B, a transfer gate Tx (e.g., a vertical transfer gate) and a control electrode Va are formed over the gate dielectric 104A and the dielectric layer 104B and within the opening OP1 and the opening OP2, respectively. In some embodiments, the transfer gate Tx is located on the front side 102FT of the substrate 102 and extends into the photosensitive region PD. In some embodiments, the transfer gate Tx is surrounded by the gate dielectric 104A and is spaced apart from the photosensitive region PD by the gate dielectric 104A. In certain embodiments, the transfer gate Tx extends into the substrate 102 through the second doping well B3 and extends toward the second doping well B1 of the photosensitive region PD. In some embodiments, the control electrode Va is located on the front side 102FT of the substrate 102 and extends into the floating diffusion region FD. In some embodiments, the control electrode Va is surrounded by the dielectric layer 104B and is spaced apart from the floating diffusion region FD by the dielectric layer 104B. In certain embodiments, the control electrode Va extends into the floating diffusion region FD and into the substrate 102 such that the control electrode Va is surrounded by the first doped well a2, the lightly doped well 130A, and the heavily doped well 130B.

Furthermore, in an exemplary embodiment, the depth of the transfer gate Tx extending into the photosensitive region PD is substantially equal to the depth of the control electrode Va extending into the floating diffusion region FD. In one exemplary embodiment, the depth of the transfer gate Tx and the depth of the control electrode Va are 0.05 micrometers or more than 0.05 micrometers. Although the depth of the transfer gate Tx and the depth of the control electrode Va are illustrated as being substantially equal, the disclosure is not limited thereto. In some alternative embodiments, the depth of the transfer gate Tx is different from the depth of the control electrode Va. For example, the depth of the transfer gate Tx may be greater than the depth of the control electrode Va. Alternatively, the depth of the transfer gate Tx may be less than the depth of the control electrode Va.

In some embodiments, the transfer gate Tx and the control electrode Va may be formed in the same step and of the same material. However, the present disclosure is not limited thereto. In some alternative embodiments, the transfer gate Tx and the control electrode Va may be formed in different steps and of different materials. In some embodiments, the transfer gate Tx and the control electrode Va may be made of a material such as polysilicon or metal. Further, the transfer gate Tx and the control electrode Va may be formed by using a suitable process such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), plating, or a combination thereof.

In an exemplary embodiment, the transfer gate Tx and the control electrode Va are formed after the first doping well (a1, a2, A3, a4, and a5) and the second doping well (B1, B2, and B3) are formed in the substrate 102. However, the present disclosure is not limited thereto. In some alternative embodiments, the first doping well (a1, a2, A3, a4, and a5) and the second doping well (B1, B2, and B3) may be formed after the transfer gate Tx and the control electrode Va are formed. In other words, the doping of the substrate 102 may be performed after the transfer gate Tx and the control electrode Va are formed to form various doped regions.

Referring to fig. 1D, in a next step, one or more interlayer dielectric layers 106 may be formed over the transfer gate Tx and the control electrode Va to cover the transfer gate Tx and the control electrode Va. In some embodiments, the interlayer dielectric layer 106 may comprise one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant of less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide). In some embodiments, a plurality of contacts (not shown) may be arranged within the interlayer dielectric layer 106 to be electrically connected to the transfer gate Tx, the control electrode Va, and may extend toward the floating diffusion region FD. In an exemplary embodiment, the carrier substrate 108 may also be attached or bonded to the front side 102FT of the substrate 102 by the interlayer dielectric layer 106. The carrier substrate 108 may be a handling wafer, an application-specific integrated circuit (ASIC), other sensing circuitry, or any applicable structure that can support, assist, or work in conjunction with image sensor circuitry.

Referring to FIG. 1E, in some embodiments, an antireflective layer 110 is disposed over the backside 102BK of the substrate 102. In some embodiments, the anti-reflective layer 110 may comprise an oxidized, nitrided, high-k dielectric material, such as aluminum oxide (AlO), tantalum oxide (tanalum oxide; TaO), hafnium oxide (HfNium oxide; HfO), hafnium silicon oxide (HfNium silicon oxide; HfSiO), hafnium aluminum oxide (HfNium aluminum oxide; HfAlO), or hafnium tantalum oxide (HfNium tanalum oxide; HfTaO), or combinations thereof. As further shown in fig. 1E, a plurality of color filters 112 are disposed over the back side 102BK of the substrate 102 over the anti-reflective layer 110. For example, the anti-reflective layer 110 is sandwiched between the color filter 112 and the substrate 102. The plurality of color filters 112 are each configured to transmit incident radiation or a particular wavelength of incident light. For example, a first color filter (e.g., a red filter) may transmit light having a wavelength within a first range, while a second color filter (e.g., a green filter) may transmit light having a wavelength within a second range different from the first range. In some embodiments, a plurality of color filters 112 may be arranged within a grid structure overlying the substrate 102. In some embodiments, the grid structure may include a dielectric material.

Further, in some embodiments, a plurality of microlenses 114 can be disposed over the plurality of color filters 112 over the back side 102BK of the substrate 102. In some embodiments, the microlenses 114 have substantially flat bottom surfaces and curved upper surfaces that abut the plurality of color filters 112. In certain embodiments, the curved upper surface is configured to focus incident radiation or light. During operation of the image sensor, incident radiation or light is focused by the microlenses 114 onto the underlying photosensitive regions PD, where electron-hole pairs may be generated to produce a photocurrent. To this end, the sub-pixel Sb of the image sensor according to some exemplary embodiments of the present disclosure may be completed.

Fig. 2 is a schematic top view of a pixel, according to some exemplary embodiments of the present disclosure. As shown in fig. 2, an image sensor is described that includes a pixel PXL having four sub-pixels (Sb1, Sb2, Sb3, Sb 4). However, the present disclosure is not limited thereto. In some alternative embodiments, the pixel PXL may have three subpixels or more than three subpixels according to design requirements. The sub-pixels (Sb1, Sb2, Sb3, Sb4) described herein are the same as the sub-pixels Sb described in fig. 1A to 1E. Accordingly, like reference numerals may be used to describe the same or similar components. In addition, a plurality of doping wells (a first doping well and a second doping well) are omitted from fig. 2 for ease of explanation.

Referring to fig. 2, in some embodiments, the pixel PXL includes four sub-pixels (Sb1, Sb2, Sb3, Sb4) arranged in parallel. In an exemplary embodiment, the first subpixel Sb1 includes a first photosensitive region PD1 located within the substrate 102 and a first transfer gate Tx1 extending into the first photosensitive region PD 1. The second subpixel Sb2 includes a second photosensitive region PD2 located within the substrate 102 and a second transfer gate Tx2 extending into the second photosensitive region PD 2. The third subpixel Sb3 includes a third photosensitive region PD3 located within the substrate 102 and a third transfer gate Tx3 extending into the third photosensitive region PD 3. Similarly, the fourth sub-pixel Sb4 includes a fourth photosensitive region PD4 located within the substrate 102 and a fourth transfer gate Tx4 extending into the fourth photosensitive region PD 4. In some embodiments, the photosensitive regions (PD1, PD2, PD3, PD4) of each of the sub-pixels (Sb1, Sb2, Sb3, and Sb4) may be formed in the same step. Further, the transfer gate (Tx1, Tx2, Tx3, Tx4) of each of the sub-pixels (Sb1, Sb2, Sb3, and Sb4) may be formed in the same step.

In an exemplary embodiment, the floating diffusion region FD is shared among the first photosensitive region PD1, the second photosensitive region PD2, the third photosensitive region PD3, and the fourth photosensitive region PD 4. In other words, the image charges accumulated in each of the photosensitive regions (PD1, PD2, PD3, and PD4) can be transferred to the same floating diffusion FD for readout. In some embodiments, the floating diffusion region FD may overlap the first, second, third, and fourth photosensitive regions PD1, PD2, PD3, and PD 4. Furthermore, in some embodiments, the control electrode Va extends into the floating diffusion region FD and into the substrate 102, where the control electrode Va is capacitively coupled to the floating diffusion region FD.

In some embodiments, the pixel PXL of the image sensor may further include a plurality of reset transistors (RST), a plurality of select transistors (select transistors) SEL, and a plurality of source follower transistors (source follower transistors) SF on the substrate 102 adjacent to the transfer gates (Tx1, Tx2, Tx3, Tx 4). In some embodiments, the reset transistor RST, the select transistor SEL, and the source follower transistor SF are located on the front side 102FT of the substrate 102 beside the transfer gates (Tx1, Tx2, Tx3, Tx 4). In some embodiments, each of the reset transistor RST, the select transistor SEL, and the source follower transistor SF may include a gate electrode (not shown) disposed over the substrate 102 and a pair of source/drain (S/D) regions (not shown) disposed within the substrate 102. During operation of the image sensor, the transfer gates (Tx1, Tx2, Tx3, Tx4) control the transfer of charge from the photosensitive regions (PD1, PD2, PD3, and PD4) to the floating diffusion region FD. If the charge level within the floating diffusion region FD is sufficiently high, the source follower transistor SF is activated and the charge is selectively output according to the operation of the selection transistor SEL for addressing.

Fig. 3 is an equivalent circuit diagram of an image sensor according to some exemplary embodiments of the present disclosure. In an exemplary embodiment, when incident light (containing photons of sufficient energy) strikes photosensitive region PD (which may be any of photosensitive region PD1, photosensitive region PD2, photosensitive region PD3, photosensitive region PD4 mentioned above), electron-hole pairs are generated and a photocurrent (or charge) is also generated. In some embodiments, the transfer gate transistor TxT (which may include any of the transfer gate Tx1, transfer gate Tx2, transfer gate Tx3, transfer gate Tx4 mentioned above) provides the function of selectively transferring charge or photo current to the floating diffusion region FD.

For example, in an exemplary embodiment, the transfer gate transistor TxT may be biased to generate an electric field such that a channel for movement of charges is generated. In some embodiments, as a result of the electric field generated, the charge stored in the photosensitive region PD is pulled out and into the channel of the transfer gate transistor TxT. These charges may then travel through the channel of the transfer gate transistor TxT to reach the floating diffusion region FD.

As further shown in fig. 3, a reset transistor RST is electrically connected between the DC voltage supply terminal VDD and the floating diffusion region FD to selectively clear charge at the floating diffusion region FD. For example, the reset transistor RST may discharge or charge the floating diffusion region FD to a preset voltage in response to a reset signal. In some embodiments, a bias voltage may be applied to the control electrode Va, and the control electrode Va may be electrically coupled to the floating diffusion region FD to form a capacitor, such that the amount of charge accumulated in the floating diffusion region FD may be increased. The source follower transistor SF is electrically connected between the DC voltage supply terminal VDD and the output terminal Vout and is gated by the floating diffusion region FD to allow the charge level at the floating diffusion region FD to be observed without removing charge. In some embodiments, the source follower transistor SF can provide a high impedance output. For example, the source follower transistor SF may be an amplifier transistor that amplifies a signal of the floating diffusion region FD for a readout operation. A select transistor SEL (or row select transistor) is electrically connected between the source follower transistor SF and the output terminal Vout to selectively output a voltage proportional to the charge at the floating diffusion region FD. In addition, a current source may be connected between the selection transistor SEL and the output terminal Vout.

During operation, the image sensor is exposed to the optical image for a predetermined integration period. During this period, the image sensor records the intensity of light incident on the photosensitive region PD by accumulating electric charges proportional to the intensity of light. After a predetermined integration period, the accumulated charge amount is read. In some embodiments, the accumulated charge amount of the photosensitive region PD is read by briefly activating the reset transistor RST to clear the charge stored at the floating diffusion region FD. Subsequently, the selection transistor SEL is activated and the accumulated charges of the photosensitive region PD are transferred to the floating diffusion region FD by activating the transfer gate transistor TxT for a predetermined transfer period. During a predetermined transition period, the voltage at the output terminal Vout is monitored. As the charge is transferred, the voltage at the output terminal Vout changes. After a predetermined transfer period, the change in voltage observed at the output terminal Vout is proportional to the intensity of the light recorded at the photosensitive region.

In an exemplary embodiment, the circuit diagram of the image sensor shown in fig. 3 may be a driving circuit for performing a readout function. However, the circuit diagram of the image sensor shown in fig. 3 is only an example, and the present disclosure is not limited thereto. In some alternative embodiments, the image sensor may have a different circuit design. For example, the drive circuit is depicted as a four transistor (4T) circuit in FIG. 3. However, in some alternative embodiments, the driver circuit DC may be a 3T circuit, a 5T circuit, or any other suitable circuit.

Fig. 4A-4C are potential well diagrams depicting the transfer of charge from a photosensitive region to a floating diffusion region in an image sensor, according to some comparative embodiments of the present disclosure. In the comparative embodiment shown in fig. 4A to 4C, the operation of the image sensor including all the elements of the sub-pixel Sb shown in fig. 1E except the control electrode Va is described. Referring to fig. 4A, during operation of the image sensor, image charges are accumulated in the photosensitive region PD. In some embodiments, the minimum potential or barrier potential (barrier potential) controlled by the transfer gate Tx (or transfer gate transistor TxT) is located between the photosensitive region PD and the floating diffusion region FD. Referring to fig. 4B, when a bias is applied to the transfer gate Tx (or when the transfer gate transistor TxT is turned on), the barrier potential is lowered, which causes the charges accumulated in the photosensitive region PD to be transferred to the floating diffusion region FD. Referring to fig. 4C, after the transfer gate Tx is closed, the charges stored in the floating diffusion region FD are read out to selectively output image data. In some embodiments, the accumulated charge in the photosensitive region PD may not be completely consumed or transferred, depending on the ability of the floating diffusion region FD to store charge. For example, in the comparative embodiment, the full well capacity of the floating diffusion region FD (see fig. 4B) can be reached. Thus, some of the accumulated charge may overflow back to the photosensitive region PD. Therefore, overflow (blooming) may occur, which in turn affects the quality of the output image.

Fig. 5A-5C are potential well diagrams showing charge transfer from a photosensitive region to a floating diffusion region in an image sensor, according to some exemplary embodiments of the present disclosure. In the exemplary embodiment shown in fig. 5A to 5C, the operation of the image sensor including all the elements (having the control electrode Va) of the sub-pixel Sb shown in fig. 1E is described. Referring to fig. 5A, during operation of the image sensor, image charges are accumulated in the photosensitive region PD. In some embodiments, the minimum potential or barrier potential controlled by the transfer gate Tx (or transfer gate transistor TxT) is the same as described in fig. 4A. However, since there are instances during readout where the control electrode (Va) is capacitively coupled to the floating diffusion region FD, the amount of charge (voltage) accumulated in the floating diffusion region FD may increase or increase. Thus, referring to fig. 5B, when a bias is applied to the transfer gate Tx (or when the transfer gate transistor TxT is turned on), the potential barrier is lowered, which allows the charges accumulated in the photosensitive region PD to be transferred to the floating diffusion region FD without overflowing. Subsequently, referring to fig. 4C, after the transfer gate Tx is closed, the charges stored in the floating diffusion region FD are read out to selectively output image data. In an exemplary embodiment, the control electrode Va is used to increase the full well capacity of the floating diffusion region FD, and may mitigate the overflow effect.

In the above-mentioned embodiments, the image sensor includes a pixel having a control electrode capacitively coupled to a floating diffusion region. Thus, during operation of the image sensor, the full well capacity of the floating diffusion region FD may be increased and the amount of charge stored in the floating diffusion region FD may be increased. Overall, the overflow effect can be mitigated and the performance of the image sensor can be improved. The image sensor may also be suitable for dual conversion gain (dual conversion gain) applications.

According to some embodiments of the present disclosure, a photosensitive pixel includes: the semiconductor device includes a substrate, a photosensitive region, a floating diffusion region, a transfer gate, and a control electrode. The photosensitive region is located within the substrate. The floating diffusion region is located in the substrate beside the photosensitive region. A transfer gate is disposed on the substrate and extends into the photosensitive region. A control electrode is located on the substrate and extends into the floating diffusion region.

In some embodiments, the light-sensitive pixel further comprises a dielectric layer within the substrate separating the control electrode from the floating diffusion region, wherein the control electrode is capacitively coupled to the floating diffusion region. In some embodiments, the photosensitive pixel further comprises a gate dielectric within the substrate, thereby spacing the transfer gate from the photosensitive region of the substrate. In some embodiments, the light-sensitive pixel further includes a reset transistor, a select transistor, and a source follower transistor on the substrate adjacent to the transfer gate.

According to some other embodiments of the present disclosure, an image sensor includes a plurality of pixels. At least one pixel among the plurality of pixels includes a first photosensitive region, a first transfer gate, a second photosensitive region, a second transfer gate, a floating diffusion region, and a control electrode. The first photosensitive area is located in the substrate. A first transfer gate is disposed on the front side of the substrate and extends into the first photosensitive region. The second photosensitive region is located in the substrate. A second transfer gate is disposed on the front side of the substrate and extends into the second photosensitive region. A floating diffusion region is disposed from a front side of the substrate to a location within the substrate, wherein the floating diffusion region is shared between the first photosensitive region and the second photosensitive region. The control electrode is located on the front side of the substrate and extends into the floating diffusion region.

In some embodiments, the image sensor further comprises: a first gate dielectric within the substrate and separating the first transfer gate from the first photosensitive region, and a second gate dielectric within the substrate and separating the second transfer gate from the second photosensitive region. In some embodiments, the image sensor further comprises a color filter and a microlens on a back side of the substrate opposite the front side.

According to yet another embodiment of the present disclosure, a method of manufacturing an image sensor is described. The method comprises the following steps. The substrate is doped with a first dopant. A first photosensitive region is formed within the substrate by doping the substrate with a second dopant different from the first dopant. A floating diffusion region is formed in the substrate beside the first photosensitive region. A first transfer gate is formed on the front side of the substrate and extends into the first photosensitive region. A control electrode is formed on the front side of the substrate and extends into the floating diffusion region.

In some embodiments, wherein forming the first transfer gate comprises: forming an opening extending into the first photosensitive region of the substrate; forming a first gate dielectric on sidewalls of the opening to cover the first photosensitive region; and forming the first transfer gate in the opening and over the substrate, wherein the first transfer gate is surrounded by the first gate dielectric. In some embodiments, forming the control electrode comprises: forming an opening extending into the floating diffusion region of the substrate; forming a dielectric layer on sidewalls of the opening to cover the floating diffusion region; and forming the control electrode in the opening and over the substrate, wherein the control electrode is surrounded by the dielectric layer. In some embodiments, forming the floating diffusion comprises: forming a lightly doped well of a second conductivity type on a first doped well of the substrate having a first conductivity type; and forming a heavily doped well of the second conductivity type over the lightly doped well, wherein the control electrode extends into the floating diffusion region and into the substrate such that the control electrode is surrounded by the first doped well, the lightly doped well, and the heavily doped well. In some embodiments, the method further comprises: forming a second photosensitive region within the substrate by doping the substrate with the second dopant; and forming a second transfer gate on a front side of the substrate and extending into the second photosensitive region, wherein the floating diffusion region is shared between the first photosensitive region and the second photosensitive region. In some embodiments, the method further comprises: providing a color filter and a microlens on a back side of the substrate opposite the front side.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A light-sensitive pixel, comprising:

a substrate;

a photosensitive region located within the substrate;

a floating diffusion region located within the substrate beside the photosensitive region;

a transfer gate disposed on the substrate and extending into the photosensitive region; and

a control electrode on the substrate and extending into the floating diffusion region.

2. A light-sensitive pixel as defined in claim 1, wherein the floating diffusion region is on a first doped well of the substrate having a first conductivity type, and the floating diffusion region includes a lightly doped well of a second conductivity type on the first doped well and a heavily doped well of the second conductivity type on the lightly doped well.

3. The light-sensitive pixel of claim 2, wherein the control electrode extends into the floating diffusion region and into the substrate such that the control electrode is surrounded by the first doped well, the lightly doped well, and the heavily doped well.

4. A photosensitive pixel according to claim 1, wherein a depth of the transfer gate extending into the photosensitive region is equal to a depth of the control electrode extending into the floating diffusion region.

5. An image sensor comprising a plurality of pixels, and at least one pixel among the plurality of pixels comprises:

a first photosensitive region located within the substrate;

a first transfer gate disposed on a front side of the substrate and extending into the first photosensitive region;

a second photosensitive region located within the substrate;

a second transfer gate disposed on the front side of the substrate and extending into the second photosensitive region;

a floating diffusion region disposed from the front side of the substrate to a location within the substrate, wherein the floating diffusion region is common between the first photosensitive region and the second photosensitive region; and

a control electrode on the front side of the substrate and extending into the floating diffusion region.

6. The image sensor of claim 5, wherein the at least one pixel among the plurality of pixels further comprises:

a third photosensitive region located within the substrate;

a third transfer gate disposed on the substrate and extending into the third photosensitive region;

a fourth photosensitive region located within the substrate; and

a fourth transfer gate disposed on the substrate and extending into the fourth photosensitive region,

wherein the floating diffusion region is shared among the first photosensitive region, the second photosensitive region, the third photosensitive region, and the fourth photosensitive region.

7. The image sensor of claim 5, wherein the floating diffusion region is located on a first doped well of the substrate having a first conductivity type, and the floating diffusion region comprises a lightly doped well of a second conductivity type located on the first doped well, and a heavily doped well of the second conductivity type located on the lightly doped well.

8. The image sensor of claim 7, wherein the control electrode extends into the floating diffusion region and into the substrate such that the control electrode is surrounded by the first doped well, the lightly doped well, and the heavily doped well.

9. The image sensor of claim 7, further comprising a dielectric layer within the substrate separating the control electrode from the floating diffusion region, wherein the control electrode is capacitively coupled to the floating diffusion region.

10. A method of fabricating an image sensor, comprising:

doping the substrate with a first dopant;

forming a first photosensitive region within the substrate by doping the substrate with a second dopant different from the first dopant;

forming a floating diffusion region in the substrate beside the first photosensitive region;

forming a first transfer gate on a front side of the substrate and extending into the first photosensitive region; and

a control electrode is formed on the front side of the substrate and extends into the floating diffusion region.