TWI690035B - 具有高機械強度的半導體封裝及半導體晶圓 - Google Patents

具有高機械強度的半導體封裝及半導體晶圓 Download PDF

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TWI690035B
TWI690035B TW107146178A TW107146178A TWI690035B TW I690035 B TWI690035 B TW I690035B TW 107146178 A TW107146178 A TW 107146178A TW 107146178 A TW107146178 A TW 107146178A TW I690035 B TWI690035 B TW I690035B
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layer
semiconductor substrate
rigid support
semiconductor
front surface
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TW107146178A
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TW201933554A (zh
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隆慶 王
杜震
陳波
魯軍
約瑟 何
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大陸商萬民半導體（澳門）有限公司
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Abstract

一種半導體封裝及半導體晶圓，分開半導體晶圓，形成多個半導體封裝。半導體晶圓具有一個半導體基板、一個金屬層、一個附著層、一個剛硬的支撐層、一個鈍化層以及多個接觸墊。半導體封裝具有一個半導體基板、一個金屬層、一個附著層、一個剛硬的支撐層、一個鈍化層以及多個接觸墊。剛硬的支撐層的厚度大於半導體基板的厚度。金屬層的厚度小於半導體基板的厚度。整個剛硬的支撐層可以由單獨的晶體矽材料或多晶矽材料製成。單獨的晶體矽材料或多晶矽材料可以由回收的矽晶圓製成。使用回收的矽晶圓的好處在於節省成本。

Description

具有高機械強度的半導體封裝及半導體晶圓
本發明主要涉及一種具有小於一百微米的半導體基板的半導體晶圓。更確切地說，本發明涉及的半導體封裝，是由具有高機械強度的半導體晶圓製成的。
用於電池保護應用的共同汲極金屬-氧化物-半導體場效電晶體(MOSFET)晶片級封裝(CSP)以及半導體功率封裝的半導體封裝，通常具有厚度為一百微米或一百微米以上的半導體基板。半導體基板產生大量的直流電阻。減小半導體基板的厚度至一百微米以下，從而減小直流電阻，對提高電學性能是十分有利的。
當半導體基板的厚度減小時，半導體封裝的機械強度降低。在本發明的示例中，增加一個楊氏係數為100G帕斯卡或以上的剛硬的支撐層，以提高機械強度。
本發明提出了一種半導體器晶圓及半導體封裝，可以提高機械強度。
為了達到上述目的，本發明將半導體晶圓分開，以形成多個半導體封裝。半導體晶圓具有一個半導體基板、一個金屬層、一個附著層、一個剛硬的支撐層、一個鈍化層以及多個接觸墊。剛硬支撐層的厚度大於半導體基板的厚度。金屬層的厚度小於半導體基板的厚度。半導體封裝具有一個半導體基板、一個金屬層、一個附著層、一個剛硬的支撐層、一個鈍化層以及多個接觸墊。
剛硬的支撐層整體是由一個單獨的晶體矽材料或多個晶體矽材料製成。單獨的晶體矽材料或多個晶體矽材料可以由申請專利範圍的矽晶圓製成。使用申請專利範圍的矽晶圓的好處是可以降低成本。申請專利範圍的矽晶圓是一個用過的矽晶圓或一個循環使用的矽晶圓。
本發明提高了半導體晶圓及半導體封裝的機械強度及電學性能。
100、200:半導體晶圓
102、302、402:接觸墊
102A、302A、402A:鋁層
102B、302B、402B:鎳-金層
120、320、420:半導體基板
122、142、162、182、341、441:正面
124、144、164、184、343:背面
140、340、440:金屬層
160、360、460:附著層
180、380、480:支撐層
190、390、490:鈍化層
220:水平劃線
240:垂直劃線
260、300、400:參考數量、半導體封裝
311、313:源極
321、323:閘極
411:第一電極
413:第二電極
440A、440B:金屬墊
481:空間
497:通孔
圖1表示在本發明的示例中，半導體晶圓的側視圖。
圖2表示在本發明的示例中，具有劃線的另一種半導體晶圓的後視圖。
圖3A表示在本發明的示例中，一個共同汲極MOSFET CSP的剖面圖。
圖3B表示在本發明的示例中圖3A所示的共同汲極MOSFET SCP的前視圖。
圖4A表示在本發明的示例中，半導體功率封裝的剖面圖，圖4B表示其前視圖。
圖1表示在本發明的示例中，半導體晶圓100的側視圖。可以將半導體晶圓100分開，形成多個半導體封裝(例如圖2所示的參考數量260，圖3A所示的參考數量300，或圖4A所示的參考數量400)。半導體晶圓100具有一個半導體基板120、一個金屬層140、一個附著層160、一個剛硬的支撐層180以及多個接觸墊102。附著層160及剛硬的支撐層180最好使用不導電或電絕緣的材料製成。半導體晶圓100還具有可選的鈍化層190。多個接觸墊102的數量可以變化(雖然圖1僅表示出了六個接觸墊102)。多個接觸墊102中的每個接觸墊102都包括一個鋁層102A以及一個鎳-金層102B。鈍化層190覆蓋著鋁層102A的一邊。鎳-金層102B的正面垂直延伸到鈍化層190的正面上方。
半導體基板120具有一個正面122及一個背面124。背面124在正面122的反面。金屬層140具有一個正面142及一個背面144。背面144在正面142的反面。附著層160具有一個正面162及一個背面164。背面164在正面162的反面。剛硬的支撐層180具有一個正面182及一個背面184。背面184在正面182的反面。
在本發明的示例中，金屬層140的正面142直接連接到半導體基板120的背面124上。附著層160的正面162直接連接到金屬層140的背面144上。剛硬的支撐層180的正面182直接連接到附著層160的背面164上。在一個示例中，多個接觸墊102連接到半導體基板120的正面122上。在另一個示例中，多個接觸墊102直接連接到半導體基板120的正面122上。
在本發明的示例中，鈍化層190直接連接到半導體基板120的正面122上。鈍化層190也直接連接到多個接觸墊102的側面上。
在本發明的示例中，半導體基板120包括多個半導體元件(圖中沒有表示出)。多個半導體元件的每個半導體元件各自的背面以及半導體基板 120的背面124都是共面的。在本發明的示例中，多個半導體元件的厚度小於或等於50微米。
在本發明的示例中，剛硬的支撐層180的“剛硬的”一詞是指剛硬的支撐層180的材料比膠帶膜材料(對於一個示例，是聚醯亞胺材料，對於另一個示例，Oh等人發明的美國專利申請號15/197,609的保護膜)更加剛硬。加強多個半導體封裝的每個半導體封裝剛硬的支撐層180(例如，圖2所示的參考數量260、圖3A所示的參考數量300或圖4A所示的參考數量400)。半導體基板120越薄，多個半導體封裝的每個半導體封裝的電學性能越好。半導體基板120的厚度小於85微米比較有利。在本發明的示例中，半導體基板120的厚度範圍為15微米至50微米，以實現預定義的電學性能要求。多個半導體封裝中的每個半導體封裝，必須承受預定義的壓力，而不會破裂。如果半導體封裝的機械性能要求裡包含安全係數的話，那麼剛硬的支撐層180的強度必須更高。
在本發明的示例中，沿圖1所示平行於Z軸的方向，測量厚度。在本發明的示例中，剛硬的支撐層180的厚度是在正面182及背面184之間最短的距離。在本發明的示例中，半導體基板120的絕大部分是由矽材料製成的。在本發明的示例中，剛硬的支撐層180的厚度大於半導體基板120的厚度。在一個示例中，半導體基板的厚度等於或小於50微米，剛硬的支撐層180的厚度範圍為50至300微米。在本發明的示例中，我們希望半導體封裝(具有3.05mm×1.77mm平面尺寸)可以承受2.15牛頓，而不會破裂。
在本發明的示例中，金屬層140的厚度小於半導體基板120的厚度，從而減小了半導體封裝的總重量。在本發明的示例中，金屬層140的厚度範圍為1微米至15微米。在一個示例中，整個金屬層140都由鎳製成。在另一個示例中，整個金屬層140都由銅製成。在另一個示例中，整個金屬層140都由鋁製成。在另一個示例中，整個金屬層140都由鋼製成。
在本發明的示例中，整個剛硬的支撐層180都由相對很高的楊氏係數的材料製成，材料中含有一種單獨的晶體矽材料、多個晶體矽材料或氮化矽材料(Si3N4)。在本發明的示例中，整個剛硬的支撐層180都由具有很高的楊氏係數的材料製成，包括雙馬來醯亞胺三嗪材料、玻璃材料、FR-4、FR-5或氧化矽材料(SiO2)。這樣的好處是節省成本，並且減輕半導體封裝的重量。
在本發明的示例中，整個剛硬的支撐層180都由單獨的晶體矽材料或多晶矽材料製成。在本發明的示例中，單獨的晶體矽材料或多晶矽材料由回收的矽晶圓製成。使用回收的矽晶圓的好處在於降低成本。回收的矽晶圓是使用過的矽晶圓或循環使用的矽晶圓。在一個示例中，使用過的矽晶圓可以是之前用於測試的。利用蝕刻製程及研磨製程處理回收的矽晶圓，形成單獨的晶體矽材料或多晶矽材料。
在本發明的示例中，整個剛硬的支撐層180由氮化矽材料製成。
在本發明的示例中，整個剛硬的支撐層180由雙馬來醯亞胺三嗪材料製成。
在本發明的示例中，整個剛硬的支撐層180由FR-4製成。
在本發明的示例中，整個剛硬的支撐層180由氧化矽材料製成。
圖2表示在本發明的示例中，分開半導體晶圓200以製備多個半導體封裝260的後視圖。多個水平劃線220及多個垂直劃線240形成在半導體晶圓200上。在本發明的示例中，沿多個劃線分開半導體晶圓200，從而製成多個分開的半導體封裝。
圖3B表示在本發明的示例中，一個共同汲極MOSFET CSP 300的前視圖。圖3A表示共同汲極MOSFET CSP 300沿平面AA’的剖面圖。在本發明的示例中，半導體基板320是圖1所示的半導體基板120的一部分。金屬層340是圖1所示的金屬層140的一部分。附著層360是圖1所示的附著層160的一部分。剛硬 的支撐層380是圖1所示的剛硬的支撐層180的一部分。鈍化層390是圖1所示的鈍化層190的一部分。接觸墊302是圖1所示的多個接觸墊102的一部分。接觸墊302可以包括一個鋁層302A及一個鎳-金層302B。
半導體封裝300具有一個半導體基板320、一個金屬層340、一個附著層360、一個剛硬的支撐層380、一個鈍化層390以及多個接觸墊302。多個接觸墊302的數量可以變化(儘管圖3A僅表示出了三個接觸墊302)。多個接觸墊302的每個接觸墊都可以包括一個鋁層302A及一個鎳-金層302B。
在本發明的數量中，鈍化層390直接連接到半導體基板320的正面341上。鈍化層390也直接連接到多個接觸墊302的側面上。
在本發明的示例中，剛硬的支撐層380的“剛硬的”一詞是指剛硬的支撐層380的材料比膠帶膜材料更加剛硬。在本發明的示例中，半導體基板320的厚度小於85微米，最好是在15微米至50微米的範圍內，以獲得預定義的電學性能要求。多個半導體封裝的每個半導體封裝都必須承受預定義的強度，而不會破裂。如果半導體封裝的機械性能要求裡包含了安全係數，那麼剛硬的支撐層380的強度必須更高。
在本發明的示例中，兩個分離的、獨立的閘極321及323，以及兩個分離的、獨立的源極311及313位於共同汲極MOSFET CSP 300的正面341上。共同汲極在共同汲極MOSFET CSP 300的背面343上。金屬層340是具有連續均勻的厚度的單獨的一塊，覆蓋著共同汲極MOSFET CSP 300的整個背面343(不同於具有空間481的圖4所示的金屬層440)。
圖4B表示在本發明的示例中，半導體功率封裝400的前視圖。圖4A表示半導體功率封裝400沿平面BB’的剖面圖。在本發明的示例中，半導體基板420是圖1所示的半導體基板120的一部分。金屬層440是圖1所示的金屬層140的一部分。附著層460是圖1所示的附著層160的一部分。剛硬的支撐層480是圖1 所示的剛硬的支撐層180的一部分。鈍化層490是圖1所示的鈍化層190的一部分。接觸墊402是圖1所示的多個接觸墊102的一部分。接觸墊402可以包括一個鋁層402A及一個鎳-金層402B。
在本發明的示例中，第一電極411及第二電極413位於半導體功率封裝400的正面441上。金屬層440被多個空間481分開，形成多個金屬墊440A及440B。多個空間481用與附著層460相同的附著材料填充。多個通孔497穿通半導體功率封裝400的半導體基板420。多個通孔497將多個接觸墊402分別電連接到並且機械連接到金屬層440的多個金屬墊440A及440B。
所屬技術領域具有通常知識者應理解所述的實施例可能存在修正。例如多個接觸墊102的總數量可能變化。在本發明的範圍內，還可能存在各種修正及變化。本發明由所附的申請專利範圍限定。
儘管本發明的內容已經藉由上述較佳實施例作了詳細介紹，但應當認識到上述的描述不應被認為是對本發明的限制。在所屬技術領域具有通常知識者閱讀了上述內容後，對於本發明的多種修改及替代都將是顯而易見的。因此，本發明的保護範圍應由所附的申請專利範圍來限定。
100:半導體晶圓
102:接觸墊
102A:鋁層
102B:鎳-金層
120:半導體基板
122、142、162、182:正面
124、144、164、184:背面
140:金屬層
160:附著層
180:支撐層

Claims (11)

  1. 一種半導體晶圓，其包括：具有正面及背面的一半導體基板，該半導體基板的正面在其背面的對面，其中該半導體基板的厚度等於或小於50微米；具有正面及背面的一金屬層，該金屬層的正面在其背面的對面，該金屬層的正面直接連接到該半導體基板的背面；具有正面及背面的一附著層，該附著層的正面在其背面的對面，該附著層的正面直接連接到該金屬層的背面；具有正面及背面的一剛硬的支撐層，該剛硬的支撐層的正面在其背面的對面，該剛硬的支撐層的正面直接連接到該附著層的背面；以及複數個接觸墊，其連接到該半導體基板的正面；其中該剛硬的支撐層的厚度大於該半導體基板的厚度，其中該剛硬的支撐層的厚度在50微米至300微米範圍內；並且其中該剛硬的支撐層比一膠帶膜材料更加剛硬；其中該附著層及該剛硬的支撐層都是不導電的。
  2. 如申請專利範圍第1項所述的半導體晶圓，還包括一鈍化層，直接連接到該半導體基板的正面，以及該複數個接觸墊的側面。
  3. 如申請專利範圍第1項所述的半導體晶圓，其中該金屬層的厚度小於該半導體基板的厚度，該金屬層的厚度在1微米至15微米範圍內，其中整個該金屬層由選自鎳、銅、鋁及鋼的材料製成。
  4. 如申請專利範圍第1項所述的半導體晶圓，其中整個該剛硬的支撐層是由一單獨的晶體矽材料或一多晶矽材料製成，其中該單獨的晶體矽材料或該多晶矽材料由回收的矽晶圓製成。
  5. 如申請專利範圍第1項所述的半導體晶圓，其中整個該剛硬的支撐層由雙馬來醯亞胺三嗪材料製成。
  6. 如申請專利範圍第1項所述的半導體晶圓，其中整個該剛硬的支撐層由選自玻璃、FR-4、FR-5、氧化矽及氮化矽的材料製成。
  7. 一種半導體封裝，包括：具有正面及背面的一半導體基板，該半導體基板的正面在其背面的對面；具有正面及背面的一金屬層，該金屬層的正面在其背面的對面，金屬層的正面直接連接到該半導體基板的背面；具有正面及背面的一附著層，該附著層的正面在其背面的對面，該附著層的正面直接連接到該金屬層的背面；具有正面及背面的一剛硬的支撐層，該剛硬的支撐層的正面在其背面的對面，該剛硬的支撐層的正面直接連接到該附著層的背面；以及複數個接觸墊，連接到該半導體基板的正面；其中該剛硬的支撐層的厚度大於該半導體基板的厚度；其中該剛硬的支撐層比一膠帶膜材料更加剛硬；並且其中該附著層及該剛硬的支撐層都是不導電的。
  8. 如申請專利範圍第7項所述的半導體封裝，其中該半導體封裝是一種共同汲極金屬-氧化物-半導體場效應結構(MOSFET) 晶片級封裝(CSP)，用於電池保護應用；其中兩個閘極及兩個源極位於共同汲極MOSFET CSP的正面上；並且其中共同汲極位於共同汲極MOSFET CSP的背面上。
  9. 如申請專利範圍第7項所述的半導體封裝，其中該半導體封裝是一半導體功率封裝；其中一第一電極及一第二電極位於該半導體功率封裝的正面上；其中複數個通孔穿過該半導體功率封裝的該半導體基板；並且其中該複數個通孔將該複數個接觸墊電連接到並且機械連接到複數個金屬墊。
  10. 如申請專利範圍第9項所述的半導體封裝，其中該複數個金屬墊之間的空間用附著材料填充。
  11. 一種半導體封裝，包括：具有正面及背面的一半導體基板，該半導體基板的正面在其背面的對面；具有正面及背面的一金屬層，該金屬層的正面在其背面的對面，該金屬層的正面直接連接到該半導體基板的背面；具有正面及背面的一附著層，該附著層的正面在其背面的對面，該附著層的正面直接連接到該金屬層的背面；具有正面及背面的一剛硬的支撐層，該剛硬的支撐層的正面在其背面的對面，該剛硬的支撐層的正面直接連接到該附著層的背面；以及 複數個接觸墊，其連接到該半導體基板的正面；其中該剛硬的支撐層的厚度大於該半導體基板的厚度；其中該剛硬的支撐層比一膠帶膜材料更加剛硬；並且其中整個該剛硬的支撐層是由一單獨的晶體矽材料或一多晶矽材料製成，其中該單獨的晶體矽材料或該多晶矽材料由回收的矽晶圓製成。
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