TWI689903B - Driving circuit and driving method - Google Patents

Abstract

A driving circuit being configured to provide data signals to data lines is provided. The driving circuit includes at least a first switch, a second switch and at least a compensating capacitor. Source of the first switch receives one of the data signals and provided to the data line connected to the drain of the first switch. Source of the second switch receives another data signal and provided to another data line. The first compensating capacitor is connected to the drain of the first switch. The sources of the first and the second switches are connected to the same source, and the compensating capacitor receive a compensating signal while the second switch is transmitting the data signal. A driving method is also provided.

Description

Drive circuit and drive method

The invention relates to a driving circuit and a driving method; in particular, to a driving circuit and a driving method of a display device.

In the development of modern science and technology, technologies related to flat panel displays have always been a subject of constant attention. In order to achieve higher-speed and higher-resolution display images, the thin film transistors used to drive pixels are constantly being improved, and multiplexers are now used to reduce the frame of the display and the number of driving chips.

However, when the data lines are sequentially charged by the multiplexer or demultiplexer, the data lines that are not opened will have a parasitic capacitance with the transistor due to floating, and then when other transistors are turned on The voltage drop of the gate signal generates feedthrough, which causes the voltage levels of multiple data lines connected to a multiplexer to be too different, which affects the display quality.

The invention provides a driving circuit, which can effectively maintain the signal on the data line to provide a good display effect.

The invention provides a driving method for multiple data lines, which can maintain the signals of these data lines at a good voltage level, so that the display images driven by these data lines have good quality.

The driving circuit of the present invention is used to provide multiple data signals to multiple data lines. The driving circuit includes at least a first switch, a second switch, and at least a first compensation capacitor. The first switch receives one of the data signals from the source and provides it to the data line connected to the drain. The second switch receives another data signal from the source and provides it to another data line connected to the drain. The first compensation capacitor is connected to the drain of the first switch. The sources of the first switch and the second switch are connected to the same signal source. The second switch transmits the data signal after the first switch transmits the data signal, and when the second switch transmits the data signal, the first compensation capacitor also receives a compensation signal.

One of the data lines driven by the driving method of the present invention is connected to the second switch, and the remaining data lines are respectively connected to the first switch. The driving method includes: turning on the first switch and providing a data signal via one of the first switches to the data line connected to the first switch; and the second switch turning on and providing the data signal after the first switch passes the data signal to the data line To the data line connected to the second switch. The first compensation capacitor is connected to the drain of the first switch, and the first compensation capacitor receives a compensation signal when the second switch is turned on.

As can be seen from the above, the driving circuit and driving method proposed by the present invention can be maintained at an appropriate voltage level after the data line receives the data signal.

100,200,300,400 ‧‧‧ drive circuit

110,210‧‧‧channel

Cgd1, Cgd3, Cgd4, Cgd6, Cgd7, Cgd9 parasitic capacitance

Cc1, Cc2, Cc3, Cc4, Cc5, Cc6, Cc9 ‧‧‧ Compensation capacitor

COM‧‧‧Common electrode

D1, D3, D4, D6, D7, D9 ‧‧‧ Drain

Data0, Data1, Data2, Data3 ‧‧‧ data signal

Display1, Display2, Display3, Display4, Display5, Display6, Display7, Display8, Display9, Display10‧‧‧ data line

G1, G2, G3, G4, G5, G6, G7, G8, G9, G10 ‧‧‧ gate

Gate1, Gate2, Gate5, Gate6, Gate7, Gate8, Gate9, Gate10, SR‧‧‧Gate signal

P1-P5‧‧‧ data point

S1/S2, S3 ‧‧‧ source line

Source1, Source2, Source3, Source4 ‧‧‧ signal source

Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw7, Sw8, Sw9, Sw10‧‧‧ switch

1A is a circuit schematic diagram of the drive circuit of the first embodiment of the present invention; FIG. 1B is a wiring schematic diagram of the drive circuit of the first embodiment of the present invention; FIG. 2A is a circuit schematic diagram of the drive circuit of the second embodiment of the present invention; FIG. 2B 2C is a schematic cross-sectional view of a driving circuit and a display electrode of a second embodiment of the present invention; 3A is a circuit schematic diagram of a driving circuit according to a third embodiment of the present invention; FIGS. 3B and 3C are signal schematic diagrams of display elements controlled by the driving circuit according to the third embodiment of the present invention; FIG. 4 is a driving circuit according to a fourth embodiment of the present invention. Circuit schematic diagram of the circuit.

The driving circuit proposed by the present invention can control, for example, a liquid crystal display device; specifically, the driving circuit proposed by the present invention can control liquid crystal using a thin-film transistor (Thin-Film Transistor, TFT) or a multiplexer (Multiplexer) The display device can preferably control a display device formed by a low-temperature polysilicon TFT, but the present invention is not limited to the above-mentioned application fields. The driving circuit provided by the present invention is used to provide a data signal to a data line of a display device or a display module. The driving circuit and the driving method provided by the present invention will be described in detail in the following embodiments.

FIG. 1A is a schematic circuit diagram of a driving circuit according to a first embodiment of the invention. Please refer to FIG. 1A. In the first embodiment of the present invention, the driving circuit 100 includes a first switch Sw1 and a second switch Sw2 connected between the signal source Source 1 and the data lines Display 1, Display 2. In this embodiment, the first switch Sw1 and the second switch Sw2 are, for example, thin-film transistors, but the invention is not limited thereto.

The driving circuit 100 of this embodiment sequentially turns on the first switch Sw1 and the second switch Sw2 to sequentially transmit the data signal from the signal source Source 1 to the data line Display 1 and the data line Display 2. Specifically, the first switch Sw1 of this embodiment is turned on by the gate signal Gate 1 transmitted to the gate G1, so that the signal from the signal source Source 1 can be transmitted to the data line Display 1; the second switch Sw2 borrows It is turned on by the gate signal Gate 2 transmitted to the gate G2, so that the data signal from the signal source Source 1 can be transmitted to the data line Display 2. in other words, By turning on the first switch Sw1 and the second switch Sw2 in sequence, the data signal from the signal source Source 1 can be transmitted to these data lines Display 1, Display 2 in turn. The driving circuit of this embodiment further includes a compensation capacitor connected between the first switch Sw1 and the second switch Sw2. Specifically, the first compensation capacitor Cc1 of this embodiment is connected between the drain D1 of the first switch Sw1 and the gate G2 of the second switch Sw2, that is, when the second switch Sw2 is turned on by the gate signal Gate 2 At this time, the gate signal Gate 2 will also charge the first compensation capacitor Cc1 at the same time.

In this embodiment, since the gate signal Gate1 needs to have a voltage rise and fall to open the gate G1, and at the same time, a parasitic capacitance Cgd1 is formed between the gate G1 and the drain D1 of the first switch Sw1, so when the first switch Sw1 needs to When it is closed and the second switch Sw2 has not been turned on, the gate voltage Gate1 will also decrease the voltage of the data line Display 1 due to the feed-through effect during the lowering process, which in turn affects the voltage level of the display electrode connected to the data line Display 1. By connecting the compensation capacitor Cc1 between the gate G2 and the drain D1 (that is, the data line Display 1), the gate signal Gate2 can also increase the voltage of the Display 1 through the compensation capacitor, that is, compensate the data line Display 1 The voltage loss of Feedthrough, so as to maintain the data line Display 1 at an appropriate voltage level.

FIG. 1B is a wiring diagram of the first embodiment of the present invention. 1B, the source line S1/S2 from the signal source Source 1 extends to a plurality of channels 110, and these channels 110 are, for example, semiconductor channels. The source line S1/S2 forms the first switch Sw1 by the gate G1 formed by the line passing the gate signal Gate1 and the line connected to the data line Display 1; the source line S1/S2 passes the gate signal Gate2 The gate G2 formed by the line and the line connected to the data line Display 2 form a second switch Sw2. The extended portion of the line transmitting the gate signal Gate2 and the extended portion connected to the data line Display 1 form a compensation capacitor Cc 1, so the drive circuit 100 can reduce the data line Display 1 by compensating the compensation signal Cc1 from the gate signal Gate 2 The impact of feedthrough during the fall of gate signal Gate 1.

In this embodiment, the above-mentioned first switch Sw1 and second switch Sw2 can be formed as a demultiplexer (Demultiplexer), so as to distribute the data signal from a signal source Source 1 to different data lines Display 1, Display 2 And the compensation capacitor Cc1 can avoid the voltage drop of the data line Display 1 during the demultiplexer switching process.

The control circuit proposed by the present invention is not limited to the number of data circuits that the control circuit can control in the above embodiments. 2A is a schematic circuit diagram of a driving circuit in a second embodiment of the invention. Referring to FIG. 2A, in the second embodiment of the present invention, the control circuit 200 is connected to three data lines Display 3, Display 4, Display 5, and the first switch Sw3, Sw4 and the second switch Sw5 are used to The data signal of the source 2 is turned on by the gate signals Gate 3, Gate 4, and Gate 5 in sequence and distributed to the above-mentioned data lines Display 3-5. Specifically, the first switches Sw3, Sw4 and the second switch Sw5 of this embodiment form, for example, a demultiplexer.

In this embodiment, a first compensation capacitor Cc2 is connected between the gate G5 of the second switch Sw5 and the drain D3 of the first switch Sw3; and between the gate of the second switch Sw5 and the drain D4 of the first switch Sw4 Connect the first compensation capacitor Cc3. Therefore, when the second switch Sw5 is turned on by the gate signal Gate 5, the gate signal Gate 5 can be simultaneously transmitted to the compensation capacitors Cc2 and Cc3 to increase the voltage of the data lines Display 3, Display 4, thereby maintaining the data lines Display 3, Display The voltage level of 4 reduces the voltage drop caused by Feedthrough caused by the parasitic capacitances Cgd3 and Cgd4.

2B is a schematic diagram of the wiring of the driving circuit of the second embodiment of the present invention. 2B, in the driving circuit 200 of this embodiment, the signal source Source 2 provides a data signal to the Channel 210, by providing gate signals Gate 3, Gate 4, Gate 5 in sequence to open some channels 210 at gate levels G3, G4, G5 to transmit data signals from source S1/S2 and S3 to data line Display 3, respectively Display 4 and Display 5. At the same time, the extension of the metal layer providing the gate signal Gate 5 and the extension of the metal layer forming the data line Display 3 form a compensation capacitor Cc2; the other extension of the metal layer providing the gate signal Gate 5 and forming the data line Display The extended portion of the metal layer of 4 forms a compensation capacitor Cc3. Therefore, by compensating the capacitors Cc2 and Cc3, the voltage levels of the data lines Display 3 and Diplay 4 can be increased by the gate signal Gate5 to maintain them in an appropriate range.

2C is a schematic cross-sectional view of a driving circuit and a display electrode according to a second embodiment of the invention. 2C, the channel 210 is formed by a semiconductor layer, for example. The line transmitting the gate signal Gate 3, the line transmitting the gate signal Gate 5 (that is, the gate G5 of the second switch Sw 5), and the line transmitting the gate signal SR in the pixel in the display area A1 are It is formed by the first metal layer; the source lines S1/S2 connected to the signal source Source 2, the lines forming the drain D3 and the source Sp and the drain Dp in the pixel are formed by the second metal layer. The first metal layer is located above the second metal layer, so in the multiplexer area A2, the second metal layer can also form a compensation capacitor Cc2 with the first metal layer in the first metal layer that transmits the gate signal Gate 5 to maintain The voltage levels of the drain D3 and the source Sp. Therefore, when the gate signal SR in the display pixel is turned on and the data signal is transferred to the pixel electrode ITO through the drain Dp, the compensation by the compensation capacitor Cc2 can prevent the data line from being caused by parasitic capacitance, feedthrough, etc. The voltage drop, in turn, affects the quality of the screen formed by the display electrode ITO.

The driving circuit proposed by the present invention may further include a second compensation capacitor to maintain the voltage level of the data line. FIG. 3A is a circuit diagram of a driving circuit in a third embodiment of the invention Figure. Please refer to FIG. 3A, the signal source Source 3 provides a data signal, and the gate signals Gate6, Gate7, Gate8 are sequentially transmitted to the first switches Sw6, Sw7, Sw8, the gates G6, G7, G8 to turn on these switches to transmit the data signal to Data lines Display6, Display7, Display8.

In this embodiment, a second compensation capacitor Cc4 is connected between the drain D6 of the first switch Sw6 and the gate G7 of the first switch Sw7. Therefore, when the gate signal Gate7 turns on the first switch Sw7, the second compensation capacitor Cc4 can also increase the voltage of the data line Display 6 by receiving the gate signal Gate7, thereby reducing the formation between the gate G6 and the drain D6 The effect of Feedthrough caused by the parasitic capacitance Cgd6. On the other hand, the gate G8 of the second switch Sw8 and the respective drains D6 and D7 of the first switches Sw6 and Sw7 are also connected with the first compensation capacitors Cc5 and Cc6, thereby reducing the gate G6 and the drain D6 The influence of the feedthrough caused by the parasitic capacitance Cgd6 formed between the gate and the parasitic capacitance Cgd7 formed between the gate G7 and the drain D7.

FIG. 3B is a signal diagram of a display element controlled by a driving circuit according to a third embodiment of the invention. Please refer to FIG. 3B, which shows the data signal Data 1 of the above-mentioned data line Display 6 and the pixel voltage Pixel A, the gate signals Gate6, Gate7, Gate8, and the pixel gate signal SR. For example, in this embodiment, the pixel voltage Pixel A connected to the data line Display 6 is increased to 3.80422 volts at time P1, for example. With the above-mentioned first compensation capacitors Cc5, Cc6 and second compensation capacitor Cc4, when Source3 is turned on, it can be maintained at 3.8267 volts at time P2 and 3.97243 volts at time P3, respectively. After the gate signal SR is turned off, it can also be maintained at 3.44966 volts at time P4, that is, the charging ratio is still maintained at about 86%. Therefore, the compensation capacitors Cc4, Cc5, and Cc6 can reliably maintain the charging ratio of the data signal Data 1.

Further, please refer to FIG. 3C, which further illustrates the data signal Data7 of the data line Display7 and the data signal Data8 of the data line Display8. It can be seen that after receiving data signals from these data lines, at time P5, the data signal Pixel A can still be maintained at 3.44966 volts, and the charging ratio is maintained at 86.24%; the data signal Pixel B can also be maintained at 3.47955 volts, charging The ratio is maintained at 86.98%; the data signal Pixel C can also be maintained at 3.44443 volts, and the charging ratio is maintained at 86.11%. It can be seen from the above that the driving circuit provided by the embodiment of the present invention can indeed maintain the quality of the data signal on the data line and achieve a relatively uniform pixel voltage. On the other hand, with the first compensation capacitor and the second compensation capacitor described above, when a plurality of first switches and second switches provided by, for example, a demultiplexer are used to provide data signals to the data lines, the same set of data lines It will not cause uneven charging ratio due to parasitic capacitance or Feedthrough, further ensuring the display effect.

The compensation signal of the present invention is not limited to being provided by the gates of other switches in the multiplexer. In other embodiments of the present invention, the compensation signal may also be provided by a common electrode. Referring to FIG. 4, in the driving circuit 400 of the fourth embodiment of the present invention, the data line Display9 is connected to the signal source Source4 through the first switch Sw9; the data line Display10 is connected to the signal source Source4 through the second switch Sw10. The first switch Sw9 is turned on by the gate signal Gate9 transmitted to the gate G9, so that the signal from the signal source Source4 can be transmitted to the data line Display9; the second switch Sw10 is turned on by the gate signal Gate10 transmitted to the gate G10 , So that the signal from the signal source Source4 can be passed to the data line Display10.

In this embodiment, the driving circuit 400 is connected to the common electrode COM through a first compensation capacitor Cc9 between the data line Display9 and the drain D9 of the first switch Sw9. When the first switch Sw9 is to be turned off, the gate signal Gate9 also reduces the voltage of the data line Display9 due to the feed-through effect caused by the parasitic capacitance Cgd9 during the reduction process. Therefore, the common electrode COM can compensate the data line by increasing the voltage when the gate signal Gate10 is transferred to the second switch Sw10 The Display9 voltage loss due to Feedthrough allows the Display9 data line to maintain an appropriate voltage level.

In other words, in an embodiment of the present invention, a method for driving a group of data lines can simultaneously increase the voltage level of the common electrode each time a gate signal is provided to one of the data lines, thereby batching through the capacitor To increase the voltage of the data signal in the Floating data line. In other words, the compensation capacitor is not limited to the gate connected to the second switch, but can also be connected to the common electrode.

In summary, the driving circuit proposed by the present invention includes a compensation capacitor, so that the voltage of the data lines that previously provided the data signals can be increased while the lines are switched in the multiplexer to provide the data signals, thereby maintaining the voltage levels of these data lines It should be in the proper range. The driving method provided by the present invention also provides the gate signal received by the second switch to the compensation capacitor every time the data signal is provided through the second switch, so as to increase the voltage of the data line that has previously received the data signal, Maintain the overall voltage level.

100‧‧‧Drive circuit

Cgd1‧‧‧parasitic capacitance

Cc1‧‧‧ Compensation capacitor

D1‧‧‧ Jiji

Display 1, Display 2‧‧‧Data line

G1, G2 ‧‧‧ gate

Gate1, Gate2‧‧‧‧Gate signal

Source1‧‧‧Signal source

Sw1, Sw2‧‧‧ switch

Claims (11)

A driving circuit for controlling a multiplexer of a display device. The multiplexer is used to provide multiple data signals to multiple data lines to transmit the data signals to a display area through the data lines. The display area includes at least A pixel, the pixel receives a gate signal, the driving circuit includes: at least a first switch, receives one of the data signals from the source and provides to one of the data lines connected to the drain; a second switch, Receiving another data signal from the source and providing it to another data line connected to the drain; and at least one first compensation capacitor connected to the drain of the first switch; wherein, the gate signal is turned on During the period, the first switch and the second switch are allowed to transmit the data signal; wherein the sources of the first switch and the second switch are connected to the same signal source, and the second switch transmits the data after the first switch The data signal is transmitted after the signal, and when the second switch transmits the data signal, the first compensation capacitor also receives a compensation signal. When the driving circuit described in item 1 of the patent application scope includes a plurality of the first switches, it further includes: at least a second compensation capacitor connected to one of the drains of the first switch and the next to transmit the data signal Between the gates of the first switch. The driving circuit as described in item 1 of the patent application scope, wherein the first compensation capacitor is connected between the gate of the second switch and the drain of the first switch; when the second switch transmits the data signal, A second gate signal of the second switch is transferred to the first compensation capacitor as the compensation signal. The driving circuit as described in item 1 of the patent application scope further includes a common electrode; the first compensation capacitor is connected between the drain of the first switch and the common electrode, and the compensation signal is transmitted by the common electrode. The driving circuit as described in item 1 of the patent application scope further includes: a first metal layer forming the gate of the second switch; a second metal layer formed above the first metal layer and the second The metal layer forms the source and the drain of the first switch; part of the first metal layer is located below the drain forming the first switch to form the first compensation capacitor. The driving circuit as described in item 1 of the patent application scope, wherein the first switch and the second switch form a demultiplexer. A driving method for multiple data lines to transmit the data signals to a display area through the data lines, the display area includes at least one pixel, the pixel receives a gate signal, and one of the data lines is connected To a second switch, the remaining data lines are each connected to a first switch. The driving method includes: turning on the gate signal; turning on the first switch and providing a data signal through one of the first switches to The data line connected to the first switch; and the second switch is turned on after the first switch transmits the data signal to the remaining data lines and provides a data signal to the data line connected to the second switch; wherein A first compensation capacitor is connected to the drain of the first switch. The first compensation capacitor receives a compensation signal when the second switch is turned on. According to the driving method described in Item 7 of the patent application range, when there are multiple first switches, a drain is connected between each drain of the first switch and the gate of the other first switch that is turned on next. A second compensation capacitor, and after the step of transmitting the data signal to the data line through the first switch, the method further includes: turning on another first switch with a gate signal and providing a data signal to the other through the other first switch The connected data line, and the gate signal is also transferred to the second compensation capacitor. The driving method as described in item 7 of the patent application scope, wherein the gate of the second switch is connected to the drain of the first switch, and the second switch is turned on with a gate signal, and the gate signal is also transmitted The first compensation capacitor is used as the compensation signal. The driving method as described in item 7 of the patent application range, wherein the first compensation capacitor is connected between the drain of the first switch and a common electrode, and when the second switch is turned on, the common electrode transmits the compensation signal To the first compensation capacitor. The driving method as described in item 7 of the patent application scope, wherein the first switch and the second switch are formed as a demultiplexer, and the demultiplexer is turned on with a clock signal; wherein the time when the second switch is turned on Corresponding to the time when the clock signal is turned off, the time when the first switch is turned on corresponds to the time when the clock signal is turned on and the remaining time.

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