KR101006445B1 - Driving apparatus for flat panel display - Google Patents

Abstract

The present invention relates to a driving device of a flat panel display device capable of securing a charging time and a compensation time of an analog amplifier.

A plurality of pixels, a gray voltage generator generating two sets of gray voltages, a plurality of data lines connected to the pixels to transfer data voltages, and a voltage corresponding to an image signal among the gray voltages as the data voltages; And a data driver including a plurality of data driver ICs applied to a data line, wherein the data driver IC is configured to convert a voltage from the digital analog converter to select a voltage corresponding to the video signal among the gray voltages. First and second amplifiers for amplifying, and a plurality of transmission gates coupled to the amplifiers.

In this way, by compensating and charging alternately through a plurality of amplifiers, the compensation time and the charging time can be sufficiently secured to improve the image quality.

LCD, Switching Device, Transistor, Capacitor, Threshold Voltage, Polycrystalline, Monocrystalline, Amorphous, SOG, Transfer Gate, Compensation, Charging

Description

Driving device for flat panel display {DRIVING APPARATUS FOR FLAT PANEL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 illustrates an example of an SOG type liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 5 is a detailed block diagram of the analog amplifier and 6TG shown in FIG.

FIG. 6 is a diagram illustrating an example of the analog amplifier shown in FIG. 5.

FIG. 7 is a timing chart showing on / off timings of switching elements of the analog amplifier shown in FIG.

FIG. 8 is a timing diagram illustrating an on / off timing of the switching element and an operating timing of the analog amplifier shown in FIG. 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive device for a flat panel display device, and more particularly to a drive device for a liquid crystal display device.                         

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

On the other hand, amorphous, polycrystalline and monocrystalline silicon are used as the material of such TFTs.

Amorphous silicon (hereinafter referred to as 'a-Si') TFT-LCD is a liquid crystal panel assembly provided on a substrate, a data driver IC for driving the liquid crystal panel assembly, a gate driver IC and a printed circuit board for connecting them It is provided. Such a-Si TFT-LCD has only a pixel in the liquid crystal panel assembly due to low electric field mobility, and separately fabricates a driver IC and mounts it on a glass substrate.

In contrast, poly-silicon TFT-LCD includes a liquid crystal panel assembly, a data driver IC for driving the liquid crystal panel assembly, and a gate driver IC on a glass substrate. Such poly-Si TFT-LCD integrates driving circuits such as data driver IC and gate driver IC in the liquid crystal panel assembly on the glass substrate, greatly reducing the number of signal lines connected to the outside, improving product reliability and significantly reducing production costs. Can be. In addition, due to the high electric field mobility, the poly-Si TFT having a smaller size than that of the a-Si TFT is used as the switching element of the pixel. For this reason, research on Poly-Si TFT-LCDs is being actively conducted.

The biggest advantage of Poly-Si TFT-LCD is that it can embed a circuit composed of MOS transistors on a low-cost glass substrate used in a-Si TFT-LCD. Currently, low temperature polycrystalline silicon (LTPS) technology can be used to form all of the gate driver ICs or portions of each of the gate driver and data driver ICs on a glass substrate, and further, the entire system including a signal controller. A system on glass (SOG) for integrating on a glass substrate has also been possible.

Meanwhile, the aforementioned data driver includes a shift register, a sampling latch, a holding latch, a DAC, and an analog amplifier. Among them, the analog amplifier is designed to be insensitive to the threshold voltage to achieve output stability.

On the other hand, when the data driver is integrated in the liquid crystal panel assembly, not only the performance of the circuit but also the area occupied by the circuit becomes important. Therefore, in order to reduce an area, an analog amplifier constituting a data driver and a data line connected thereto are often used in a 1: n demultiplexing scheme.

However, since the analog amplifier must perform both compensation and charging of the threshold voltage during one horizontal period 1H, the charging time is insufficient, resulting in deterioration of image quality.

Accordingly, an object of the present invention is to provide a driving device of a flat panel display device capable of sufficiently securing a charging time and a compensation time.

According to an aspect of the present invention, there is provided a driving apparatus of a flat panel display device including a plurality of pixels, generating a plurality of gray voltages, and a data voltage connected to the pixels. And a data driver including a plurality of data lines to be transmitted and a plurality of data driver ICs which apply a voltage corresponding to an image signal among the gray voltages to the data lines as the data voltages. And a digital analog converter for selecting a voltage corresponding to the video signal among voltages, first and second amplifiers for amplifying a voltage from the digital analog converter, and a plurality of transmission gates connected to the amplifier.

Meanwhile, the driving device of the flat panel display device may further include first and second switching elements connected between the digital analog converter and the first and second amplifiers, respectively.

In addition, the first and second switching elements may be alternately turned on at predetermined time intervals.

The transmission gate may include first to third transmission gates connected to the first amplifier and fourth to sixth transmission gates connected to the second amplifier.

In this case, the first and second amplifiers include a capacitor, a plurality of switching elements, and a plurality of transistors, and preferably compensate for threshold voltages of the plurality of transistors. Meanwhile, while one of the first and second amplifiers performs the compensation, the other may charge the data line connected through the transmission gate.

The flat panel display may be a liquid crystal display and may also be a system on glass (SOG).

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

An analog amplifier for a flat panel display according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention. 3 illustrates an example of an SOG type liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a block diagram of a data driver of the liquid crystal display according to the exemplary embodiment.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.                     

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n .

As illustrated in FIG. 4, the data driver 500 may include a shift register 501, a first latch 503, a second latch 505, a digital-to-analog converter (DAC) 507, and an output buffer 509. It is connected to the data line (D ₁ -D _m ) of the liquid crystal panel assembly 300, and selects the gray voltage from the gray voltage generator 800 to apply to the pixel as a data signal, and consists of a plurality of integrated circuits .

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

In the example shown in FIG. 3, the data driver 500 and the gate driver 400 are integrated in the liquid crystal panel assembly 300, and the signal controller 600 is mounted to the assembly 300 on the substrate in the form of a chip. have. In the drawing, the power supply IC 700 is a circuit element that generates the aforementioned gate on voltage V _on and gate off voltage V _off . The display area refers to an area where pixels and signal lines G ₁ -G _n and D ₁ -D _m are disposed.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV for controlling the output timing of the gate on pulse, and a gate on pulse. An output enable signal OE or the like that defines a width.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The shift register 501 of the data driver 500 receives the data clock signal HCLK and the horizontal synchronizing start signal STH from the signal control unit 600 and sequentially shifts the horizontal synchronizing start signal STH to the first latch ( 503).

The first latch 503 or the sampling latch receives the image data R ', G', and B 'corresponding to the pixels of one row based on the signal from the shift register 501 and sequentially receives the second latch 503 or the sampling latch. It goes down to the latch 505.

The second latch 505 or the holding latch stores the image data R ', G', and B 'and sends them to the DAC 507 according to a predetermined signal. There may be a number of predetermined signals. In FIG. 4, an output enable signal OE is illustrated.

The DAC 507 selects a gray voltage corresponding to each of the image data R ', G', and B 'among the gray voltages from the gray voltage generator 800, thereby making the image data R', G ', and B' different. ) Is converted into a corresponding data voltage, and the converted data voltage is an analog signal.

The output buffer 509 amplifies the data voltage from the DAC 507. This amplification operation will be described later in detail.                     

The 6TG 511 is composed of six transmission gates and selectively transfers the output from the output buffer 509 to the data lines D1-Dm according to the switching control signal CONT _SW . It explains in detail.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“column inversion”) or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( "Dot reversal")

As described above, the data driver 500 of the liquid crystal display outputs an image signal converted into an analog signal through the DAC 507 through the output buffer 509 as a data line. Since the output buffer 509 is formed of an analog amplifier, the embodiment of the present invention is referred to as an analog amplifier. Hereinafter, the driving device of the liquid crystal display including the analog amplifier will be described in detail with reference to FIGS. 5 to 8. do.

FIG. 5 is a detailed block diagram of the analog amplifier 509 and 6TG 511 shown in FIG. 4, and FIG. 6 is a diagram showing an example of the first and second amplifiers shown in FIG. FIG. 7 is a timing diagram showing on / off timings of switching elements of the analog amplifier shown in FIG. 6, and FIG. 8 shows on / off timings of the switching elements shown in FIG. 5 and operations of the first and second amplifiers. Is a timing diagram.

As shown in FIG. 5, the analog amplifier of the driving apparatus according to the embodiment of the present invention includes first and second amplifiers, and three transmission gates TG1-TG3 connected thereto.

As shown in FIG. 6, the first and second amplifiers include a plurality of switching elements SW1-SW5, a capacitor C, and a plurality of transistors N1, N2.

First, the structure and operation of the first and second amplifiers shown in FIG. 6 will be described. Here, an operation performed by the first and second amplifiers is an operation for compensating the threshold voltage, hereinafter referred to as a compensation operation, and a time required for such a compensation operation is called a compensation time.

The transistor N2 is an NMOS transistor, the first terminal and the second terminal of which are connected to the switching element SW5, and the third terminal of the transistor N2 is connected to the predetermined voltage V ₁ through the switching element SW1.

Transistor N1 is also an NMOS transistor, where the first terminal is connected to the second terminal of transistor N2, the second terminal is connected to a constant driving voltage V _DD , and the third terminal is a constant current source I. It is connected to earth via

Both ends of the capacitor C are connected to the input voltage V _in through the switching elements SW3 and SW4, respectively, and the first terminal and the third terminal of the transistor N2 through the switching elements SW5 and SW2. It is connected to each terminal.

Next, the operation of the first and second amplifiers will be described.

It is assumed that the threshold voltages of the two transistors N1 and N2 are the same.

First, all the switching elements except for the switching element SW3 are turned on at a time t ₁ . Then, current flows through the turned-on switching elements SW1 and SW2 so that the capacitor C is charged with a voltage corresponding to the voltage difference between the node A and the node B. FIG.

Here, Vc is the initial value _{(V in (initial))} of the capacitor (C) and the voltage across, V _{in (initial)} input voltage (V _in). At this time, the difference between the initial value V _{in (initial)} and the predetermined voltage V ₁ must be a size capable of turning on the transistor N2. That is, the value is larger than the value obtained by adding the rated threshold voltage and the error of the transistor N2 (this is referred to as an "effective threshold voltage").

In this way, when the voltage value is adjusted by the two voltages V _in and V ₁ , a wide range of selection for adjustment can be made, and precise adjustment is possible.

When the voltage Vc becomes equal to or greater than the effective threshold voltage of the transistor N2, the transistor N2 is turned on, and then the switching element SW1 is turned off at a time t ₂ . The capacitor C and the transistor N2 then form a closed circuit. The capacitor C decreases the voltage while flowing a current through the transistor N2, and reaches a voltage corresponding to the effective threshold voltage of the transistor N2. At this time, the transistor N2 is turned off to be in an open state, and the capacitor C stores the effective threshold voltage V _th2 of the transistor N2.

Next, at time t ₃ , only the switching device SW3 is turned on, and the remaining switching devices SW1, SW2, SW4, and SW5 are all turned off, and the size of the input voltage V _in is changed to V _{in (final)} . Since the input voltage V _in is applied to the node B, the node A voltage becomes a value obtained by adding the voltage charged to the capacitor C and the input voltage V _{in (final)} .

On the other hand, an NMOS transistor is generally composed of three terminals, a gate, a source, and a drain. A channel region exists between the source and the drain, and an insulating film is interposed between the channel region and the gate. Since transistor N1 operates in a saturation area, that is, an active area, as is known, an NMOS transistor can be equivalently replaced by a voltage controlled current source. In FIG. 5, the current flowing between the drain, which is the second terminal of the transistor N1, and the source, which is the third terminal, is the same as that of the constant current source I.

Where W and L are the width and length of the channel region, μ is the electron mobility, and C is the capacitance per unit area of the insulating film located under the gate. V _gs is the difference between the gate voltage and the source voltage, and V _th1 is the effective threshold voltage of the transistor N1. At this time, the voltage between the gate sources (V _gs ) is V _gs = V _A -V _out , and V _th1 = V _th2 ,

Substituting Equation 3 into Equation 5,

Becomes

Therefore, if V _{in (final)} = Vd + (2I / k) ^1/2 , V _out = Vd. For example, when the image data is converted into an analog voltage by the DAC 507, the target data voltage is converted into a value obtained by adding a voltage corresponding to the second right term to the target data voltage in advance. The output voltage V _out then becomes the target data voltage.

Next, the above-described operation is repeated one time (t _4), all the switching elements (SW1-SW5) are turned-off time (t _5).

The above-described switching elements SW1-SW5 may also be implemented with MOS transistors.

In this manner, when the effective threshold voltages of the transistors N1 and N2 are stored in the capacitor C, the output voltage V _out is independent of the threshold voltages of the transistors N1 and N2, and thus, when the transistors N1 and N2 are manufactured. Depending on process conditions, even if the threshold voltage is not uniform or changes, a constant output voltage can be obtained.

As described above, the first and second amplifiers charge the data lines D ₁ -D _m through the transfer gates TG1 -TG6 connected thereto after the compensation operation.

Referring again to FIG. 5, a transmission gate TG1 -TG3 is connected to the first amplifier, and a transmission gate TG4 -TG6 is connected to the second amplifier. In addition, the first and second amplifiers are connected to the DAC 507 through the switching elements SW6 and SW7, respectively.

First, the switching device SW6 is turned on according to the switching control signal CONT _SW so that the first amplifier performs a compensation operation.

As described above, this is an operation until the input voltage V _in is applied to the amplifier to generate the output voltage V _out , and corresponds to the compensation time shown in FIG. 8. The compensation operation of the first amplifier is performed before the gate clock signal CPV becomes high, as shown in FIG. 8.

Subsequently, while generating the output voltage V _out , the transfer gate TG1 is turned on to transfer the output voltage to the data line D ₁ .

Meanwhile, the second amplifier performs the compensation operation while the first amplifier performs the charging operation while the switching device SW7 is turned on according to the switching control signal CONT _SW , and then outputs the output voltage V _out through the transmission gate TG4. Is transferred to the data line D ₄ .

In this manner, the first and second amplifiers alternately operate and sequentially apply the data voltage, which is the output voltage V _out , to all the data lines D ₁ -D _m to the transmission gates TG1 -TG6 connected thereto. Then, data is applied to one row of pixels at a time corresponding to one horizontal period 1H of the gate clock signal CPV.

As described above, the use of two amplifiers can double the compensation time for one horizontal period (H) compared to using one conventional amplifier, thereby compensating between the amplifiers located in the plurality of data driving ICs. The deviation can be reduced. In addition, since the charging time is also doubled as compared with the related art, it is possible to sufficiently charge and the image quality is also improved.

On the other hand, it can be seen that the area occupied in the liquid crystal panel assembly is increased by using two amplifiers, but the area occupied by the data driver IC itself is insignificant, so there is no increase in the area.

As described above, by driving using two amplifiers, it is possible to secure sufficient charging time and compensation time to improve image quality.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

For example, the present invention can be applied to a device requiring an analog amplifier insensitive to a change in threshold voltage, for example, a flat panel display such as an organic light emitting display (OLED).

In other words, the structure of the OLED is almost the same as that of the liquid crystal display except that the organic EL element is disposed in the pixel so that the organic EL element emits light by flowing a current proportional to the applied data voltage. The OLED includes a column driver corresponding to the data driver of the liquid crystal display, converts a digital signal into an analog signal, and then amplifies and applies the digital signal to the pixel. In this case, too, an analog amplifier that is independent of the change in the threshold voltage is required, and it is important to have sufficient charging time and compensation time.

Claims (8)

A driving device of a flat panel display device including a plurality of pixels, A gray voltage generator generating two gray voltages; A plurality of data lines connected to the pixels to transfer data voltages, and A data driver including a plurality of data driver ICs applying a voltage corresponding to an image signal among the gray voltages to the data line as the data voltage; Including, The data driving IC A digital analog converter for selecting a voltage corresponding to the video signal among the gray voltages; First and second amplifiers for amplifying the voltage from the digital to analog converter, A plurality of transmission gates connected to the amplifier, and First and second switching elements connected between the digital analog converter and the first and second amplifiers, respectively Including, And the first and second switching elements are alternately turned on at time intervals. delete delete In claim 1, The transfer gate may include first to third transfer gates connected to the first amplifier and fourth to sixth transfer gates connected to the second amplifier. In claim 4, The first and second amplifiers A capacitor, a plurality of switching elements and a plurality of transistors, Capable of compensating threshold voltages of the plurality of transistors Driving device for flat panel display. In claim 5, And one of the first and second amplifiers performs the compensation while the other charges the data line connected through the transmission gate. In claim 1, And the flat panel display is a liquid crystal display. In claim 7, And the flat panel display is a system on glass (SOG).

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