TWI683538B - Control circuit, control method, selection circuit and power management integrated circuit - Google Patents

Control circuit, control method, selection circuit and power management integrated circuit Download PDF

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TWI683538B
TWI683538B TW107137523A TW107137523A TWI683538B TW I683538 B TWI683538 B TW I683538B TW 107137523 A TW107137523 A TW 107137523A TW 107137523 A TW107137523 A TW 107137523A TW I683538 B TWI683538 B TW I683538B
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input
circuit
signal
transistor
control
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TW201933771A (en
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周元隆
唐新偉
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大陸商矽力杰半導體技術（杭州）有限公司
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    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract

本發明提供了一種控制電路、控制方法、選擇電路及電源管理積體電路，所述的控制電路在控制選擇電路時，通過加速響應電路在需要斷開的輸入電路還來不及斷開時，加速比較信號的翻轉速度，以使得兩個輸入電路快速的進入所需的狀態，有效地減小了兩個輸入端的衝擊電流，增強了電源管理積體電路系統和電源管理積體晶片的穩定性。The invention provides a control circuit, a control method, a selection circuit and a power management integrated circuit. When the control circuit controls the selection circuit, the acceleration response circuit accelerates the comparison when the input circuit that needs to be disconnected is too late to disconnect The inversion speed of the signal enables the two input circuits to quickly enter the desired state, effectively reduces the inrush current at the two input terminals, and enhances the stability of the power management integrated circuit system and the power management integrated chip.

Description

控制電路、控制方法、選擇電路及電源管理積體電路Control circuit, control method, selection circuit and power management integrated circuit

本發明屬於電力電子技術領域，尤其涉及一種控制電路、控制方法、選擇電路及電源管理積體電路。The invention belongs to the technical field of power electronics, and particularly relates to a control circuit, a control method, a selection circuit, and a power management integrated circuit.

圖1為現有的一種最大值選擇電路的結構示意圖，其主要包括由二極體D1和開關K1構成的第一輸入電路、由二極體D2與開關K2構成的第二輸入電路，以及用於控制第一輸入電路和第二輸入電路通斷狀態，以選擇第一輸入電路和第二輸入電路中所接收的輸入信號較大的一路接入輸出端Vmax的控制電路。第一輸入電路接收第一輸入信號Vin1，第二輸入電路接收第二輸入信號Vin2，第一輸入電路與第二輸入電路的輸出端公連接以作為最大值選擇電路的輸出端Vmax。控制電路主要有比較器和邏輯電路構成，比較器用於比較第一輸入信號Vin1與Vin2的大小，以輸出比較信號S0。如圖2的邏輯電路工作波形圖所示，邏輯電路將比較信號S0轉換成分別帶開關K1與開關K2的死區時間dt的控制信號S1、S2，以分別控制開關K1與開關K2的通斷狀態，當第二輸入信號Vin2上升至大於第一輸入信號Vin1時，比較器S0翻轉，且觸發控制信號S1翻轉，以控制開關K1關斷，控制信號S2經過一個死區時間dt後翻轉，以控制開關K2導通，以將使得第一輸入電路反向阻斷，第二輸入電路接入輸出端Vmax，反之，當第一輸入信號Vin1上升至大於第二輸入信號Vin2時，比較器S0翻轉，且觸發控制信號S2翻轉，以控制開關K2關斷，控制信號S1經過一個死區時間dt後翻轉，以控制開關K1導通，以將使得第二輸入電路反向阻斷，第一輸入電路接入輸出端Vmax。二極體D1與D2可以保證在死區時間dt內，輸出端Vmax仍有最大值的輸出信號（Vin1,Vin2）max-Vnp，其中Vnp為二極體的開啟電壓。 在圖1所示的這種最大值選擇電路中，當輸入信號之間進行快速轉換時，可能會使得兩個輸入端之間產生較大的衝擊電流問題。其原因在於，如圖3所示，其為圖1所示的最大值選擇電路的工作波形圖，當第二輸入信號Vin2快速超過第一輸入信號Vin1與Vnp之和時，始終工作的比較器因偏置電流較小而存在一個不可忽略的輸出延時Td，使得比較信號S0需要經過固有延時Td後才翻轉，則在固有延時Td內會產生從第二輸入信號Vin2的輸入端由經二極體D2和不及關斷的K1到第一輸入信號Vin1的輸入端的衝擊電流Iin2_1。假如在固有延時Td時間內，第二輸入信號Vin2和第一輸入信號Vin1的差值不斷加大，Iin2_1也會持續加大，這會帶來兩方面的不利。第一，第一輸入信號Vin2會將第一輸入信號Vin1的輸入端的電壓帶高，造成第一輸入信號Vin1的輸入端的前端系統超壓。第二，在晶片中，巨大電流從二極體D2流過，容易局部過熱損壞晶片，或者激發附近的寄生器件，產生閂鎖（latch up），造成晶片損壞。1 is a schematic structural diagram of an existing maximum value selection circuit, which mainly includes a first input circuit composed of a diode D1 and a switch K1, a second input circuit composed of a diode D2 and a switch K2, and Control the on and off states of the first input circuit and the second input circuit to select the control circuit of the first input circuit and the second input circuit that receives the larger input signal and accesses the output terminal Vmax. The first input circuit receives the first input signal Vin1, the second input circuit receives the second input signal Vin2, and the first input circuit is connected to the output terminal of the second input circuit as the output terminal Vmax of the maximum value selection circuit. The control circuit is mainly composed of a comparator and a logic circuit. The comparator is used to compare the magnitudes of the first input signals Vin1 and Vin2 to output the comparison signal S0. As shown in the operation waveform diagram of the logic circuit in FIG. 2, the logic circuit converts the comparison signal S0 into control signals S1 and S2 with the dead time dt of the switches K1 and K2 respectively to control the on and off of the switches K1 and K2 respectively In the state, when the second input signal Vin2 rises to be greater than the first input signal Vin1, the comparator S0 toggles and triggers the control signal S1 to toggle to control the switch K1 to turn off, and the control signal S2 toggle after a dead time dt, Control the switch K2 to be turned on so that the first input circuit is reversely blocked and the second input circuit is connected to the output terminal Vmax. Conversely, when the first input signal Vin1 rises to be greater than the second input signal Vin2, the comparator S0 reverses, And trigger the control signal S2 to turn over to control the switch K2 to turn off, the control signal S1 to turn over after a dead time dt, to control the switch K1 to turn on, so that the second input circuit is reversely blocked, and the first input circuit is connected Output Vmax. The diodes D1 and D2 can ensure that within the dead time dt, the output terminal Vmax still has the maximum output signal (Vin1, Vin2) max-Vnp, where Vnp is the turn-on voltage of the diode. In the maximum value selection circuit shown in FIG. 1, when the input signals are rapidly switched, a large inrush current problem may occur between the two input terminals. The reason is that, as shown in FIG. 3, it is an operation waveform diagram of the maximum value selection circuit shown in FIG. 1. When the second input signal Vin2 quickly exceeds the sum of the first input signals Vin1 and Vnp, the comparator always operates There is a non-negligible output delay Td due to the small bias current, so that the comparison signal S0 needs to be inverted after the inherent delay Td, then the inherent delay Td will be generated from the input terminal of the second input signal Vin2 The body D2 and the inrush current Iin2_1 less than the off K1 to the input end of the first input signal Vin1. If the difference between the second input signal Vin2 and the first input signal Vin1 continues to increase within the inherent delay time Td, Iin2_1 will continue to increase, which will bring two disadvantages. First, the first input signal Vin2 will bring the voltage of the input terminal of the first input signal Vin1 high, causing the front-end system of the input terminal of the first input signal Vin1 to overpressure. Second, in the wafer, a huge current flows from the diode D2, which is easy to cause local overheating to damage the wafer, or to excite nearby parasitic devices, resulting in latch up, causing damage to the wafer.

有鑑於此，本發明提供了一種控制電路、控制方法及選擇電路，以在輸入信號進行快速切換時，加上比較信號的快速翻轉，減小固有延遲時間，使得選擇電路的各個輸入電路儘快的進入正常狀態。 一種控制電路，用於控制兩路輸入電路的通斷狀態，以選擇其中一路輸入電路接入輸出端，其特徵在於，包括加速響應電路， 當需要斷開的一路輸入電路還未斷開時，該加速響應電路輸出加速信號，以加速需要斷開的一路輸入電路的斷開。 較佳地，所述的控制電路還包括比較電路，該比較電路用於比較兩個輸入電路的輸入信號，以產生比較信號，該加速信號通過加速該比較信號的翻轉來加速需要斷開的一路輸入電路的斷開。 較佳地，所述的控制電路還包括邏輯電路，其特徵在於，該邏輯電路根據該比較信號產生與兩路輸入電路相對應的控制信號，以控制其中一路輸入電路導通，另一路輸入電路斷開。 較佳地，該比較電路包括比較器，該加速信號用於增加該比較器的偏置電流，以減小該比較器的輸出延時，來加速該比較信號的翻轉。 較佳地，兩個輸入電路所對應的輸入信號分別為第一輸入信號、第二輸入信號，該加速響應電路接收第一輸入信號、第二輸入信號以及對應的控制信號，以產生該加速信號。 較佳地，若需要選擇輸入信號較大的一路輸入電路接入輸出端，則當較大的輸入信號與較小的輸入信號之差達到預定值時，且輸入信號較小的一路輸入電路仍未斷開時，該加速響應電路開始工作，以加速該比較信號的翻轉，直到輸入信號較小的一路輸入電路斷開時停止工作。 較佳地，該加速響應電路包括第一誤差電路、第二誤差電路， 當兩個該輸入信號中的第一輸入信號的值大於第一疊加值，且兩個該輸入信號中的第二輸入信號對應的第二輸入電路仍未斷開時，該第一誤差電路工作，並根據該第一輸入信號的值與該第一疊加值之間的差值產生第一誤差信號，以作為該加速信號，該第一疊加值為該第二輸入信號的值與一預定值的疊加值， 當該第二輸入信號的值大於第二疊加值，且該第一輸入電路仍未斷開時，該第二誤差電路工作，並根據該第二輸入信號的值與該第二疊加值之間的差值產生第二誤差信號，以作為該加速信號，該第二疊加值為該第一輸入信號的值與第二預定值的疊加值。 較佳地，第三開關電路，由用於控制該第二輸入電路的第二控制信號控制，當該第三開關電路導通時，該第一誤差信號作為該加速信號被傳輸至該比較電路， 第四開關電路，由用於控制第一輸入電路的第一控制信號控制，當該第四開關電路導通時，該第二誤差信號作為該加速信號被傳輸至該比較電路。 較佳地，該第一誤差電路包括第一電晶體、第二電晶體和第三電晶體， 該第二誤差電路包括第四電晶體、第五電晶體和第六電晶體， 該第三開關電路包括第一反相器和第七電晶體， 該第四開關電路包括第二反向器和第八電晶體， 該第一電晶體的第一端接收該第一輸入信號，第二端通過該第七電晶體與該第二電晶體相連，該第一電晶體的控制端接收該第二輸入信號，該第二電晶體與該第三電晶體構成第一電流鏡，該第二控制信號通過該第一反相器被傳輸至該第七電晶體的控制端， 該第四電晶體的第一端接收該第二輸入信號，第二端通過該第八電晶體與該第五電晶體相連，該第四電晶體的控制端接收該第一輸入信號，該第五電晶體與該第六電晶體構成第二電流鏡，該第一控制信號通過該第二反相器被傳輸至該第八電晶體的控制端， 該第一電晶體在該第一輸入信號的值大於該第一疊加值時導通，該第七電晶體在該第二控制信號有效期間導通，當該第一電晶體與第七電晶體均導通時，該第一電流鏡輸出該第一誤差信號，該第一電晶體的閾值電壓的值為該第一預定值， 該第四電晶體在該第二輸入信號的值大於該第二疊加值時導通，該第八電晶體在該第一控制信號有效期間導通，當該第四電晶體與第八電晶體均導通時，該第二電流鏡輸出該第二誤差信號，該第四電晶體的閾值電壓的值為該第二預定值。 較佳地，該輸入電路中的第一輸入電路包括第一二極體和第一開關，該輸入電路中的第二輸入電路包括第二二極體和第二開關， 該第一二極體與該第一開關並聯，且該第一二極體的陽極端接收該第一輸入信號，陰極端與該第二二極體的陰極端相連， 該第二二極體與該第二開關並聯，且該第二二極體的陽極接收該第二輸入信號， 該第一二極體與第二二極體的相連端作為該輸出端。 較佳地，若需要選擇輸入信號較小的一路輸入電路接入輸出端，則當較大的輸入信號與較小的輸入信號之差達到預定值時，且輸入信號較大的一路輸入電路仍未斷開時，該加速響應電路開始工作，以加速該比較信號的翻轉，直到輸入信號較大的一路輸入電路斷開時停止工作。 較佳地，該邏輯電路根據該比較信號以及該第一開關與第二開關的死區時間，生成帶該死區時間資訊的該第一控制信號與第二控制信號， 該第一輸入信號大於該第二輸入信號後，該第一控制信號控制該第一開關導通，該第二控制信號控制該第二開關關斷， 該第二輸入信號大於該第一輸入信號後，該第一控制信號控制該第一開關關斷，該第二控制信號控制該第二開關導通。 一種控制方法，用於控制兩路輸入電路的通斷狀態，以選擇其中一路輸入電路接入輸出端，其特徵在於， 當需要斷開的另一路輸入電路還未斷開時，加速需要斷開的一路輸入電路的斷開。 較佳地，所述的控制方法還包括，比較兩個輸入電路的輸入信號，以產生比較信號，該加速信號通過加速該比較信號的翻轉來加速需要斷開的一路輸入電路的斷開。 較佳地，根據該比較信號產生與兩路輸入電路相對應的控制信號，以控制其中一路輸入電路導通，另一路輸入電路斷開。 較佳地，根據兩個該輸入電路的輸入信號以及對應的控制信號產生加速信號，以加速該比較信號的翻轉。 較佳地，若需要選擇輸入信號較大的一路輸入電路接入輸出端，則當較大的輸入信號與較小的輸入信號之差達到預定值時，且輸入信號較小的一路輸入電路仍未斷開時，開始產生該加速信號，以加速該比較信號的翻轉，直到輸入信號較小的一路輸入電路斷開時停止產生該加速信號的動作。 一種選擇電路，其特徵在於，包括兩路輸入電路和上述中任意一項所述的控制電路。 一種電源管理積體電路，其特徵在於，包括上述中任意一項所述的控制電路。 一種電源管理積體電路，其特徵在於，包括所述的選擇電路。 由上可見，依據本發明提供的控制電路，通過加速響應電路在需要需要斷開的輸入電路還來不及斷開時，加速比較信號的翻轉速度，以使得兩個輸入電路快速的進入所需的狀態，有效地減小了兩個輸入端的衝擊電流，增強了系統和晶片的穩定性。In view of this, the present invention provides a control circuit, a control method and a selection circuit, so that when the input signal is rapidly switched, the rapid inversion of the comparison signal is added to reduce the inherent delay time, so that each input circuit of the selection circuit is as fast as possible Enter the normal state. A control circuit for controlling the on-off state of two input circuits to select one of the input circuits to be connected to the output terminal, which is characterized by including an acceleration response circuit, When an input circuit that needs to be disconnected has not been opened, the acceleration response circuit outputs an acceleration signal to accelerate the disconnection of the input circuit that needs to be disconnected. Preferably, the control circuit further includes a comparison circuit. The comparison circuit is used to compare the input signals of the two input circuits to generate a comparison signal. The acceleration signal accelerates the path to be disconnected by accelerating the inversion of the comparison signal. Disconnection of the input circuit. Preferably, the control circuit further includes a logic circuit, characterized in that the logic circuit generates a control signal corresponding to the two input circuits according to the comparison signal to control one of the input circuits to be turned on and the other input circuit to be turned off open. Preferably, the comparison circuit includes a comparator, and the acceleration signal is used to increase the bias current of the comparator to reduce the output delay of the comparator to accelerate the inversion of the comparison signal. Preferably, the input signals corresponding to the two input circuits are respectively a first input signal and a second input signal, and the acceleration response circuit receives the first input signal, the second input signal and the corresponding control signal to generate the acceleration signal . Preferably, if an input circuit with a larger input signal needs to be selected and connected to the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value, and the input circuit with the smaller input signal is still When it is not disconnected, the acceleration response circuit starts to work to accelerate the flipping of the comparison signal until the input circuit with a smaller input signal is disconnected and stops working. Preferably, the acceleration response circuit includes a first error circuit and a second error circuit, When the value of the first input signal of the two input signals is greater than the first superimposed value, and the second input circuit corresponding to the second input signal of the two input signals is still open, the first error circuit works And generate a first error signal according to the difference between the value of the first input signal and the first superimposed value as the acceleration signal, the first superimposed value is the value of the second input signal and a predetermined value The superimposed value of When the value of the second input signal is greater than the second superimposed value, and the first input circuit is still not disconnected, the second error circuit operates, and according to the value of the second input signal and the second superimposed value The difference generates a second error signal as the acceleration signal, and the second superimposed value is the superimposed value of the value of the first input signal and the second predetermined value. Preferably, the third switch circuit is controlled by a second control signal for controlling the second input circuit. When the third switch circuit is turned on, the first error signal is transmitted to the comparison circuit as the acceleration signal, The fourth switch circuit is controlled by a first control signal for controlling the first input circuit. When the fourth switch circuit is turned on, the second error signal is transmitted to the comparison circuit as the acceleration signal. Preferably, the first error circuit includes a first transistor, a second transistor and a third transistor, The second error circuit includes a fourth transistor, a fifth transistor, and a sixth transistor, The third switching circuit includes a first inverter and a seventh transistor, The fourth switching circuit includes a second inverter and an eighth transistor, The first terminal of the first transistor receives the first input signal, the second terminal is connected to the second transistor through the seventh transistor, and the control terminal of the first transistor receives the second input signal, the first The second transistor and the third transistor constitute a first current mirror, and the second control signal is transmitted to the control terminal of the seventh transistor through the first inverter, The first end of the fourth transistor receives the second input signal, the second end is connected to the fifth transistor through the eighth transistor, and the control end of the fourth transistor receives the first input signal, the first The fifth transistor and the sixth transistor constitute a second current mirror, and the first control signal is transmitted to the control terminal of the eighth transistor through the second inverter, The first transistor is turned on when the value of the first input signal is greater than the first superimposed value, the seventh transistor is turned on during the valid period of the second control signal, when both the first transistor and the seventh transistor are turned on At this time, the first current mirror outputs the first error signal, the value of the threshold voltage of the first transistor is the first predetermined value, The fourth transistor is turned on when the value of the second input signal is greater than the second superimposed value, the eighth transistor is turned on during the valid period of the first control signal, when both the fourth transistor and the eighth transistor are turned on At this time, the second current mirror outputs the second error signal, and the value of the threshold voltage of the fourth transistor is the second predetermined value. Preferably, the first input circuit in the input circuit includes a first diode and a first switch, and the second input circuit in the input circuit includes a second diode and a second switch, The first diode is connected in parallel with the first switch, and the anode terminal of the first diode receives the first input signal, and the cathode terminal is connected to the cathode terminal of the second diode, The second diode is connected in parallel with the second switch, and the anode of the second diode receives the second input signal, The connecting end of the first diode and the second diode is used as the output end. Preferably, if an input circuit with a smaller input signal needs to be selected and connected to the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value, and the input circuit with a larger input signal is still When not disconnected, the acceleration response circuit starts to work to accelerate the flipping of the comparison signal until the input circuit with a larger input signal is disconnected and stops working. Preferably, the logic circuit generates the first control signal and the second control signal with the dead time information according to the comparison signal and the dead time of the first switch and the second switch, After the first input signal is greater than the second input signal, the first control signal controls the first switch to turn on, and the second control signal controls the second switch to turn off, After the second input signal is greater than the first input signal, the first control signal controls the first switch to turn off, and the second control signal controls the second switch to turn on. A control method for controlling the on-off state of two input circuits to select one of the input circuits to be connected to the output terminal, which is characterized by When the other input circuit that needs to be disconnected has not been disconnected, the disconnection of the input circuit that needs to be disconnected is accelerated. Preferably, the control method further includes comparing the input signals of the two input circuits to generate a comparison signal, and the acceleration signal accelerates the disconnection of the input circuit that needs to be disconnected by accelerating the reversal of the comparison signal. Preferably, a control signal corresponding to the two input circuits is generated according to the comparison signal to control one of the input circuits to be turned on and the other input circuit to be turned off. Preferably, an acceleration signal is generated according to two input signals of the input circuit and corresponding control signals to accelerate the inversion of the comparison signal. Preferably, if an input circuit with a larger input signal needs to be selected and connected to the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value, and the input circuit with the smaller input signal is still When it is not disconnected, the acceleration signal starts to be generated to accelerate the inversion of the comparison signal until the input signal with a smaller input signal is disconnected and the action of generating the acceleration signal is stopped. A selection circuit is characterized by comprising two input circuits and any of the control circuits described above. A power management integrated circuit is characterized by including the control circuit according to any one of the above. A power management integrated circuit is characterized by including the selection circuit. As can be seen from the above, according to the control circuit provided by the present invention, by accelerating the response circuit when the input circuit that needs to be disconnected is too late, the flipping speed of the comparison signal is accelerated, so that the two input circuits quickly enter the desired state , Effectively reducing the inrush current of the two input terminals, enhancing the stability of the system and the chip.

下面將結合本發明實施例中的圖式，對本發明實施例中的技術方案進行清楚、完整地描述，顯然，所描述的實施例僅僅是本發明一部分實施例，而不是全部的實施例。基於本發明中的實施例，本領域普通技術人員在沒有做出創造性勞動前提下所產生的所有其他實施例，都屬於本發明保護的範圍。此外需要說明的是，在具體實施方式這一項內容中“該…”是僅指本發明的中的技術屬於或特徵。 為了解決圖1所示的選擇電路中存在的比較器響應速度慢的問題，本發明提供了一種新的控制電路和控制方法，應用本發明提供的控制電路的選擇電路100的電路方塊圖如圖4所示。在本實施例中，選擇電路100為最大值選擇電路，其除了包括依據本發明提供的控制電路外，還包括兩路輸入電路，分別為第一輸入電路和第二輸入電路，該第一輸入電路的輸入端接收第一輸入信號Vin1，第二輸入電路的輸入端接收第二輸入信號Vin2，兩路輸入信號的輸出端公連接，以作為選擇電路100的輸出端Vmax輸出端，該控制電路用於控制該第一輸入電路和第二輸入電路的通斷狀態，以選擇其中一路輸入電路接入選擇電路的輸出端，如在本實施例中，是選擇輸入信號的值較大的一路輸入電路接入選擇電路的輸出端。所述的控制電路主要包括包括比較電路01、邏輯電路02以及加速響應電路03。 比較電路01用於比較第一輸入信號Vin1與第二輸入信號Vin2之間的大小關係，以產生比較信號S0。邏輯電路02根據比較信號S0產生與兩路輸入電路相對應的控制信號S1、S2，以控制其中一路輸入電路導通，另一路輸入電路斷開。在本實施例中，第一控制信號S1與第二控制信號S2均由比較信號S0觸發生成，並分別包含了第一輸入電路中的開關的死區時間資訊和包含了第一輸入電路中的開關的死區時間資訊。邏輯電路100的工作波形與也可以如圖2所示，當第二輸入信號Vin2上升至大於第一輸入信號Vin1後，比較信號S0翻轉，使得第一控制信號S1翻轉，以控制該第一輸入電路斷開，而第二控制信號S2需要經過一個死區時間後才翻轉，以控制該第二輸入電路導通。當第一輸入信號Vin1上升至大於第二輸入信號Vin2後，比較信號S0翻轉，使得第二控制信號S2翻轉，以控制該第二輸入電路斷開，而第一控制信號S1經過一個死區時間後翻轉，以控制該第一輸入電路導通。 然而，在實際應用中，在選擇電路工作的過程中，比較電路01是始終工作的，那麼為了降低功耗，比較電路01通常會選擇偏置電流較小的比較器CP來實現。低功耗的比較器CP在比較到兩個輸入信號的大小關係發生變化瞬間，其輸出的比較信號S0不會馬上翻轉，而是會經過比較器CP所存在的固有延時才翻轉，那麼第一控制信號S1和第二控制信號S2控制相應的輸入電路進入相應的狀態的時間也會出現延時，這就會出現需要斷開的一路輸入電路還來不及斷開的情況，這種情況可能使得兩路輸入電路的輸入端之間存在較大的電流而損壞晶片。例如，在最大值選擇電路中，當第一輸入信號Vin1跳變為大於第二輸入信號Vin2之後，則第二輸入信號Vin2對應的第二輸入電路需要斷開，而當第二輸入信號Vin2跳變為大於第一輸入信號Vin1之後，則第一輸入信號Vin1對應的第一輸入電路需要斷開。在最小值選擇電路中，當第一輸入信號Vin1跳變為小於第二輸入信號Vin2之後，則第二輸入信號Vin2對應的第二輸入電路需要斷開，而當第二輸入信號Vin2跳變為小於第一輸入信號Vin1之後，則第一輸入信號Vin1對應的第一輸入電路需要斷開。 然而，在本發明所提供的控制電路中還包括加速響應電路03，其主要用於在需要斷開的一路輸入電路還未斷開時輸出加速信號Ib_speed_up，以加速需要斷開的第一路輸入電路的斷開，即減小需要斷開的一路輸入電路由導通狀態切換至斷開狀態的時間，例如加速信號Ib_speed_up在本實施例中用以加速比較信號S0的翻轉，使得比較電路01在具有低功耗的同時還具有較快的響應速度，從而通過加速比較信號S0的翻轉來加速需要斷開的一路輸入電路的斷開。加速信號Ib_speed_up為電流信號，其被傳輸至比較器CP中，以增加比較器CP的偏置電流，減小比較器CP的輸出延時，從而加速比較信號S0的翻轉。如圖4所示，加速響應電路03接收第一輸入信號Vin1、第二輸入信號Vin2、第一控制信號S1以及第二控制信號S2，輸出加速信號Ib_speed_up。 繼續參考圖4所示，在本實施例中，選擇電路100為最大值選擇電路，其第一輸入電路包括第一二極體D1和第一開關K1，第二輸入電路包括第二二極體D2和第二開關K2。第一二極體D1與該第一開關K1並聯，且第一二極體D1的陽極端接收第一輸入信號Vin1，陰極端與第二二極體D2的陰極端相連，第二二極體D2與第二開關K2並聯，且第二二極體D2的陽極接收第二輸入信號Vin2， 第一二極體D1與第二二極體D2的相連端作為該輸出端。 當第一輸入信號Vin1與第二輸入信號Vin2中的較大者與較小者之差達到預定值，且輸入信號較小的一路輸入電路仍未斷開（即對應的控制信號仍處於有效狀態，如高位準狀態）時，加速響應電路03開始工作，以加速比較信號S0的翻轉，直到輸入信號較小的一路輸入電路斷開（對應的控制信號處於無效狀態，如低位準狀態）時停止工作。加速響應電路在本實施例中包括第一誤差電路和第二誤差電路，當第一輸入信號Vin1的值大於第一疊加值，且第一輸入電路仍未導通，與第二輸入電路仍未斷開時，該第一誤差電路開始工作，並根據第一輸入信號Vin1的值與所第一疊加值之間的差值產生第一誤差信號，以作為該加速信號Ib_speed_up，該第一疊加值為該第二輸入信號Vin2的值與一預定值Vt1的疊加值。第一預定值Vt1為第一誤差電路的失調電壓的值，在圖4中，第一誤差電路包括第一誤差放大器Gm1，第二誤差電路包括第二誤差放大器Gm2。第一誤差放大器輸出第一輸入信號Vin1與該第一疊加值的差值，在圖4中，第一誤差放大器Gm1的反相輸入端接收的第一預定值電壓Vt1並非指該反相輸入端與一個具有第一預定值Vt1的電壓電連接，而是示意該反相輸入端所接收的信號的值為第二輸入信號Vin2與第一預定值Vt1相疊加的第一疊加值。同樣，第二預定值Vt2為第二誤差電路的失調電壓的值。第二誤差放大器Gm2輸出第二輸入信號Vin2與第二疊加值的差值，在圖4中，第二誤差放大器Gm2的反相輸入端接收的第二預定值電壓Vt2並非指該反相輸入端與一個具有第二預定值Vt2的電壓電連接，而是示意該反相輸入端所接收的信號的值為第一輸入信號Vin1與第二預定值Vt2相疊加的第二疊加值。當第二輸入信號Vin2的值大於該第二疊加值，且第一輸入電路仍未斷開（第一控制信號S1仍處於有效狀態）時，該第二誤差電路開始工作，並根據第二輸入信號Vin2的值與所第二疊加值之間的差值產生第二誤差信號，以作為該加速信號Ib_speed_up。 加速響應電路03還包括由第二控制信號S2控制的開關電路，當該開關電路導通時，該第一誤差信號作為加速信號Ib_speed_up被傳輸至比較電路01，該由第二控制信號S2控制的第三開關電路包括開關K3。加速響應電路03還進一步包括由第一控制信號S1控制的第四開關電路，當該開關電路導通時，該第二誤差信號作為加速信號Ib_speed_up被傳輸至比較電路01，該由第一控制信號S1控制的開關電路包括開關K4。 圖5為依據本發明實施例提供的選擇電路200的電路方塊圖。在圖5所示的選擇電路200中示出加速響應電路03的具體實現電路，如圖5所示，該第一誤差電路包括第一電晶體MP1、第二電晶體MN1和第三電晶體MN2，該第二誤差電路包括第四電晶體MP2、第五電晶體MN3和第六電晶體MN4，該第三開關電路包括第一反相器N1和第七電晶體MP3，該第四開關電路包括第二反向器N2和第八電晶體MP4。第一電晶體MP1的第一端接收第一輸入信號Vin1，第二端通過第七電晶體MP3的與第二電晶體MN1相連，第一電晶體MP1的控制端接收第二輸入信號Vin2，第二電晶體MN1與第三電晶體MN2構成第一電流鏡，第二控制信號S2由經第一反相器N1被傳輸至第七電晶體MP3的控制端，第四電晶體MP2的第一端接收第二輸入信號Vin2，第二端通過第八電晶體MP4的與第五電晶體MN3相連，第四電晶體MP2的控制端接收第一輸入信號Vin1，第五電晶體MN3與第六電晶體MN4構成第二電流鏡，第一控制信號S1由經第二反相器N2被傳輸至第八電晶體MP4的控制端，第一電晶體MP1在第一輸入信號Vin1的值大於該第一疊加值時導通，第七電晶體MP3在第二控制信號S2有效期間導通，當第一電晶體MP1與第七電晶體MP3均導通時，該第一電流鏡輸出該第一誤差信號，第一電晶體MP1的開啟電壓的值為該第一預定值，第四電晶體MP2在第二輸入信號Vin2的值大於該第二疊加值時導通，第八電晶體MP4在第一控制信號S1有效期間導通，當第四電晶體MP2與第八電晶體MP4均導通時，該第二電流鏡輸出該第二誤差信號，第四電晶體MP2的開啟電壓的值為該第二預定值。其中，圖5中的第一反相器N1與第七電晶體MP3構成圖4中的開關K3，而第二反相器N2與第八電晶體MP4構成圖4中的開關K4。 以第一輸入信號Vin1向上跳變超過第二輸入信號Vin2，且各個開關均以高位準控制導通，低位準控制斷開（高位準有效）為例。當Vin1＜Vin2時，第二控制信號S2為高位準，開關K2導通，第一控制信號S1為低位準，開關K1斷開，第七電晶體MP3導通，第一電晶體MP1斷開，第二電晶體MN1、第三電晶體MN2構成的第一電流鏡不產生電流；第八電晶體MP4斷開，第五電晶體MN3、第六電晶體MN4構成的第二電流鏡也不產生電流。因此加速響應電路03不產生靜態功耗。當第一輸入信號Vin1快速超過第二輸入信號Vin2，且Vin1-Vin2＞Vtp1（Vtp1為第一電晶體MP1的開啟電壓，其值為該第一預定值）時，如果比較信號S0來不及翻轉，則此時第一控制信號S1仍為低，第八電晶體MP4斷開，第二控制信號S2仍為高位準，電晶體MP3仍導通，且此時第一電晶體MP1已被第一輸入信號Vin1和第二輸入信號Vin2的差值打開。因此，在該第一電流鏡上產生第一誤差信號，以作為加速信號Ib_speed_up，使比較器CP輸出的比較信號S0加速翻轉。當比較信號S0翻轉後，第二控制信號S2為低位準，第七電晶體MP3斷開，第一控制信號S1為高位準，第八電晶體MP4導通，但由於此時第四電晶體MP2被斷開，使得該第一電流鏡與第二電流鏡均無電流輸出，則加速響應電路03處於靜態無功耗狀態。 同樣，若第二輸入信號Vin2上升至超過第一輸入信號Vin1的過程中，在Vin2＜Vin1期間，該第一電流鏡和第二電流鏡均無電流輸出，加速響應電路03處於靜態無功耗狀態（即處於不工作狀態），當Vin2-Vin1＞Vtp2時（Vtp2為第四電晶體MP2的開啟電壓，該第二預定值）時，如果比較信號S0來不及翻轉，則此時該第一電流鏡不產生電流，但是該第二電流鏡產生電流以作為加速信號Ib_speed_up，使比較器CP輸出的比較信號S0加速翻轉，當比較信號S0翻轉後，該第一電流鏡和第二電流鏡均無電流輸出，加速響應電路03處於靜態無功耗狀態。該第一電流鏡和第二電流鏡的構成不局限於圖5所示的結構。 圖6為依據本發明具體實施例提供的選擇電路100或200的工作波形圖，如圖6所示，在第二輸入信號Vin2小於第一輸入信號Vin1期間，比較信號S0為高位準，第一控制信號S1為高位準，第二控制信號S2為低位準，所述的第一輸入電路導通，以被接入輸出端Vmax，該第二輸入電路斷開（反向阻斷），當第二輸入信號Vin2增加至超過Vin1+Vtp1後，加速響應電路使得比較信號S0快速翻轉為低位準，第一控制信號S1也快速變為低位準，而第二控制信號S2快速變為高位準，以控制該第一輸入電路快速切換至斷開狀態，而第二輸入信號快速切換至導通狀態。顯然，採用本發明提供的控制電路來控制選擇電路的過程中，比較器的輸出固有延時Td， 明顯得比現有技術中的比較器的固有延時Td小，從第二輸入端與第一輸入端之間的衝擊電流Iin2_1比較小。 選擇電路100與選擇電路200均為最大值選擇電路，然而，依據本發明實施例提供的該控制電路還可以用於最小值選擇電路。當選擇電路需要選擇輸入信號較小的一路輸入電路接入輸出端時，則該控制電路中的加速響應電路的工作過程為：當較大的輸入信號與較小的輸入信號之差達到預定值時，且輸入信號較大的一路輸入電路仍未斷開時，該加速響應電路開始工作，以加速該比較信號的翻轉，直到輸入信號較大的一路輸入電路斷開時停止工作。在在最小值選擇電路中，加速響應電路的具體實施方式與最大值選擇電路中的相似，在此不再累述。 此外，本發明還提供了一種控制方法，用於控制兩路輸入電路的通斷狀態，以選擇其中一路輸入電路接入輸出端，其主要包括比较兩個輸入電路的輸入信號，以產生比較信號，根據該比較信號產生與兩路輸入電路相對應的控制信號，以控制其中一路輸入電路導通，另一路輸入電路斷開，當需要斷開的一路輸入電路還未斷開時，加速該比較信號的翻轉。進一步的，可以根據兩個該輸入電路的輸入信號以及對應的控制信號產生加速信號，以加速該比較信號的翻轉。此外，若需要選擇輸入信號較大的一路輸入電路接入輸出端，則當較大的輸入信號與較小的輸入信號之差達到預定值時，且輸入信號較小的一路輸入電路仍未斷開時，開始產生該加速信號，以加速該比較信號的翻轉，直到輸入信號較小的一路輸入電路斷開時停止產生該加速信號的動作。 本發明還提供了一種電源管理積體電路（PMIC），該電路主要包括依據本發明提供的控制電路。另外，本發明還提供了另一種電源管理積體電路（PMIC），該電路主要包括依據本發明提供的選擇電路。本發明提供的電源管理積體電路具既具有較快的響應速度，又具有較低的功耗和較高的穩定性。 由上可見，依據本發明提供的控制電路，通過加速響應電路在需要斷開的輸入電路還來不及斷開時，加速比較信號的翻轉速度，以使得的兩個輸入電路快速的進入所需的狀態，有效的減小了兩個輸入端的衝擊電流，增強了系統和晶片的穩定性。 依照本發明的實施例如上文所述，這些實施例並沒有詳盡敘述所有的細節，也不限制該發明僅為所述的具體實施例。根據以上描述，可作很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本發明的原理和實際應用，從而使所屬技術領域技術人員能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍及其全部範圍和等效物的限制。The technical solutions in the embodiments of the present invention will be described clearly and completely in combination with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all the embodiments. Based on the embodiments of the present invention, all other embodiments produced by a person of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention. In addition, it should be noted that in the content of the specific implementation, "the..." refers only to the technical attribute or feature of the present invention. In order to solve the problem of the slow response speed of the comparator in the selection circuit shown in FIG. 1, the present invention provides a new control circuit and control method. The circuit block diagram of the selection circuit 100 applying the control circuit provided by the present invention is as shown in FIG. 4 is shown. In this embodiment, the selection circuit 100 is a maximum value selection circuit. In addition to the control circuit provided in accordance with the present invention, it also includes two input circuits, a first input circuit and a second input circuit, the first input The input end of the circuit receives the first input signal Vin1, the input end of the second input circuit receives the second input signal Vin2, and the output ends of the two input signals are male connected to serve as the output end Vmax of the selection circuit 100, the control circuit It is used to control the on and off states of the first input circuit and the second input circuit to select one of the input circuits to access the output of the selection circuit. As in this embodiment, it is to select the input with a larger value of the input signal The circuit is connected to the output of the selection circuit. The control circuit mainly includes a comparison circuit 01, a logic circuit 02 and an acceleration response circuit 03. The comparison circuit 01 is used to compare the magnitude relationship between the first input signal Vin1 and the second input signal Vin2 to generate a comparison signal S0. The logic circuit 02 generates control signals S1 and S2 corresponding to the two input circuits according to the comparison signal S0 to control one of the input circuits to be turned on and the other input circuit to be turned off. In this embodiment, the first control signal S1 and the second control signal S2 are both triggered and generated by the comparison signal S0, and respectively include the dead time information of the switch in the first input circuit and the first input circuit. Switch dead time information. The operating waveform of the logic circuit 100 can also be as shown in FIG. 2, when the second input signal Vin2 rises to be greater than the first input signal Vin1, the comparison signal S0 is inverted, so that the first control signal S1 is inverted to control the first input The circuit is disconnected, and the second control signal S2 needs to be turned over after a dead time to control the second input circuit to be turned on. When the first input signal Vin1 rises to be greater than the second input signal Vin2, the comparison signal S0 inverts, so that the second control signal S2 inverts to control the second input circuit to open, and the first control signal S1 passes a dead time It is reversed to control the first input circuit to turn on. However, in practical applications, the comparison circuit 01 always works during the selection circuit operation, so in order to reduce power consumption, the comparison circuit 01 usually selects the comparator CP with a smaller bias current to implement. When the comparator CP of the low power consumption compares the moment when the magnitude relationship between the two input signals changes, the comparison signal S0 output by it will not be flipped immediately, but will be flipped after the inherent delay of the comparator CP, then the first The time when the control signal S1 and the second control signal S2 control the corresponding input circuit to enter the corresponding state will also be delayed, which will cause the situation that the one input circuit that needs to be disconnected is too late to be disconnected. This situation may cause two channels There is a large current between the input terminals of the input circuit to damage the chip. For example, in the maximum value selection circuit, when the first input signal Vin1 jumps to be greater than the second input signal Vin2, the second input circuit corresponding to the second input signal Vin2 needs to be opened, and when the second input signal Vin2 jumps After it becomes greater than the first input signal Vin1, the first input circuit corresponding to the first input signal Vin1 needs to be opened. In the minimum value selection circuit, when the first input signal Vin1 jumps to be smaller than the second input signal Vin2, the second input circuit corresponding to the second input signal Vin2 needs to be disconnected, and when the second input signal Vin2 jumps to After being smaller than the first input signal Vin1, the first input circuit corresponding to the first input signal Vin1 needs to be opened. However, the control circuit provided by the present invention further includes an acceleration response circuit 03, which is mainly used to output an acceleration signal Ib_speed_up when an input circuit that needs to be disconnected has not been opened, to accelerate the first input that needs to be disconnected The disconnection of the circuit is to reduce the time for the input circuit that needs to be disconnected to switch from the on state to the off state. For example, the acceleration signal Ib_speed_up is used in this embodiment to accelerate the inversion of the comparison signal S0, so that the comparison circuit 01 has At the same time with low power consumption, it also has a faster response speed, so as to accelerate the opening of the input circuit that needs to be opened by accelerating the reversal of the comparison signal S0. The acceleration signal Ib_speed_up is a current signal, which is transmitted to the comparator CP to increase the bias current of the comparator CP and reduce the output delay of the comparator CP, thereby accelerating the inversion of the comparison signal S0. As shown in FIG. 4, the acceleration response circuit 03 receives the first input signal Vin1, the second input signal Vin2, the first control signal S1 and the second control signal S2, and outputs the acceleration signal Ib_speed_up. With continued reference to FIG. 4, in this embodiment, the selection circuit 100 is a maximum selection circuit, the first input circuit includes a first diode D1 and a first switch K1, and the second input circuit includes a second diode D2 and the second switch K2. The first diode D1 is connected in parallel with the first switch K1, and the anode terminal of the first diode D1 receives the first input signal Vin1, the cathode terminal is connected to the cathode terminal of the second diode D2, and the second diode D2 is connected in parallel with the second switch K2, and the anode of the second diode D2 receives the second input signal Vin2, and the connection terminal of the first diode D1 and the second diode D2 serves as the output terminal. When the difference between the larger and the smaller of the first input signal Vin1 and the second input signal Vin2 reaches a predetermined value, and the input circuit with the smaller input signal is still not disconnected (ie, the corresponding control signal is still in an active state , Such as high level state), the acceleration response circuit 03 starts to work to accelerate the flipping of the comparison signal S0 until the input circuit with a smaller input signal is disconnected (the corresponding control signal is in an invalid state, such as a low level state) and stops jobs. The acceleration response circuit includes a first error circuit and a second error circuit in this embodiment, when the value of the first input signal Vin1 is greater than the first superimposed value, and the first input circuit is still not turned on, and the second input circuit is still not disconnected When turned on, the first error circuit starts to work, and generates a first error signal according to the difference between the value of the first input signal Vin1 and the first superimposed value as the acceleration signal Ib_speed_up, the first superimposed value is The superimposed value of the value of the second input signal Vin2 and a predetermined value Vt1. The first predetermined value Vt1 is the value of the offset voltage of the first error circuit. In FIG. 4, the first error circuit includes a first error amplifier Gm1 and the second error circuit includes a second error amplifier Gm2. The first error amplifier outputs the difference between the first input signal Vin1 and the first superimposed value. In FIG. 4, the first predetermined value voltage Vt1 received by the inverting input terminal of the first error amplifier Gm1 does not refer to the inverting input terminal It is electrically connected to a voltage having a first predetermined value Vt1, but indicates that the value of the signal received at the inverting input terminal is the first superimposed value of the second input signal Vin2 superimposed on the first predetermined value Vt1. Similarly, the second predetermined value Vt2 is the value of the offset voltage of the second error circuit. The second error amplifier Gm2 outputs the difference between the second input signal Vin2 and the second superimposed value. In FIG. 4, the second predetermined value voltage Vt2 received at the inverting input terminal of the second error amplifier Gm2 does not refer to the inverting input terminal It is electrically connected to a voltage having a second predetermined value Vt2, but indicates that the value of the signal received at the inverting input terminal is a second superimposed value where the first input signal Vin1 and the second predetermined value Vt2 are superimposed. When the value of the second input signal Vin2 is greater than the second superimposed value, and the first input circuit is still not disconnected (the first control signal S1 is still in an active state), the second error circuit starts to work, and according to the second input The difference between the value of the signal Vin2 and the second superimposed value generates a second error signal as the acceleration signal Ib_speed_up. The acceleration response circuit 03 further includes a switch circuit controlled by the second control signal S2. When the switch circuit is turned on, the first error signal is transmitted to the comparison circuit 01 as the acceleration signal Ib_speed_up, and the first control signal controlled by the second control signal S2 The three-switch circuit includes a switch K3. The acceleration response circuit 03 further includes a fourth switch circuit controlled by the first control signal S1. When the switch circuit is turned on, the second error signal is transmitted to the comparison circuit 01 as the acceleration signal Ib_speed_up, which is controlled by the first control signal S1 The controlled switch circuit includes a switch K4. FIG. 5 is a circuit block diagram of the selection circuit 200 according to an embodiment of the present invention. A specific implementation circuit of the acceleration response circuit 03 is shown in the selection circuit 200 shown in FIG. 5, as shown in FIG. 5, the first error circuit includes a first transistor MP1, a second transistor MN1, and a third transistor MN2 The second error circuit includes a fourth transistor MP2, a fifth transistor MN3 and a sixth transistor MN4, the third switching circuit includes a first inverter N1 and a seventh transistor MP3, the fourth switching circuit includes The second inverter N2 and the eighth transistor MP4. The first terminal of the first transistor MP1 receives the first input signal Vin1, the second terminal is connected to the second transistor MN1 through the seventh transistor MP3, and the control terminal of the first transistor MP1 receives the second input signal Vin2, the first The second transistor MN1 and the third transistor MN2 form a first current mirror, the second control signal S2 is transmitted to the control terminal of the seventh transistor MP3 via the first inverter N1, and the first terminal of the fourth transistor MP2 Receive the second input signal Vin2, the second terminal is connected to the fifth transistor MN3 through the eighth transistor MP4, the control terminal of the fourth transistor MP2 receives the first input signal Vin1, the fifth transistor MN3 and the sixth transistor MN4 forms a second current mirror, the first control signal S1 is transmitted to the control terminal of the eighth transistor MP4 via the second inverter N2, the value of the first transistor MP1 at the first input signal Vin1 is greater than the first superposition When the value is on, the seventh transistor MP3 is on during the valid period of the second control signal S2. When both the first transistor MP1 and the seventh transistor MP3 are on, the first current mirror outputs the first error signal. The value of the turn-on voltage of the crystal MP1 is the first predetermined value, the fourth transistor MP2 is turned on when the value of the second input signal Vin2 is greater than the second superimposed value, and the eighth transistor MP4 is turned on during the effective period of the first control signal S1 When both the fourth transistor MP2 and the eighth transistor MP4 are turned on, the second current mirror outputs the second error signal, and the turn-on voltage value of the fourth transistor MP2 is the second predetermined value. Wherein, the first inverter N1 and the seventh transistor MP3 in FIG. 5 constitute the switch K3 in FIG. 4, and the second inverter N2 and the eighth transistor MP4 constitute the switch K4 in FIG. 4. Take an example in which the first input signal Vin1 jumps upwards beyond the second input signal Vin2, and each switch is turned on by the high level control and turned off by the low level control (the high level is valid). When Vin1<Vin2, the second control signal S2 is at a high level, the switch K2 is turned on, the first control signal S1 is at a low level, the switch K1 is turned off, the seventh transistor MP3 is turned on, the first transistor MP1 is turned off, the second The first current mirror composed of the transistor MN1 and the third transistor MN2 does not generate current; the eighth transistor MP4 is turned off, and the second current mirror composed of the fifth transistor MN3 and the sixth transistor MN4 also does not generate current. Therefore, the acceleration response circuit 03 does not generate static power consumption. When the first input signal Vin1 quickly exceeds the second input signal Vin2, and Vin1-Vin2>Vtp1 (Vtp1 is the turn-on voltage of the first transistor MP1, its value is the first predetermined value), if the comparison signal S0 is too late to reverse, At this time, the first control signal S1 is still low, the eighth transistor MP4 is off, the second control signal S2 is still high, the transistor MP3 is still on, and the first transistor MP1 has been input by the first input signal The difference between Vin1 and the second input signal Vin2 is turned on. Therefore, a first error signal is generated on the first current mirror as an acceleration signal Ib_speed_up, so that the comparison signal S0 output by the comparator CP is accelerated and inverted. When the comparison signal S0 is inverted, the second control signal S2 is at a low level, the seventh transistor MP3 is turned off, the first control signal S1 is at a high level, and the eighth transistor MP4 is turned on, but because the fourth transistor MP2 is turned off at this time When it is disconnected, so that neither the first current mirror nor the second current mirror has a current output, the acceleration response circuit 03 is in a static state without power consumption. Similarly, if the second input signal Vin2 rises to exceed the first input signal Vin1, during Vin2<Vin1, the first current mirror and the second current mirror have no current output, and the acceleration response circuit 03 is in a static state without power consumption In the state (that is, in an inoperative state), when Vin2-Vin1>Vtp2 (Vtp2 is the turn-on voltage of the fourth transistor MP2, the second predetermined value), if the comparison signal S0 is too late to reverse, then the first current The mirror does not generate current, but the second current mirror generates current as the acceleration signal Ib_speed_up, which accelerates and flips over the comparison signal S0 output by the comparator CP. When the comparison signal S0 is inverted, the first current mirror and the second current mirror have no Current output, acceleration response circuit 03 is in a static state without power consumption. The configuration of the first current mirror and the second current mirror is not limited to the structure shown in FIG. 5. FIG. 6 is an operation waveform diagram of the selection circuit 100 or 200 provided according to a specific embodiment of the present invention. As shown in FIG. 6, during the period when the second input signal Vin2 is less than the first input signal Vin1, the comparison signal S0 is at a high level, the first The control signal S1 is at a high level, the second control signal S2 is at a low level, the first input circuit is turned on to be connected to the output terminal Vmax, the second input circuit is disconnected (reverse blocking), when the second After the input signal Vin2 increases to exceed Vin1+Vtp1, the acceleration response circuit quickly turns the comparison signal S0 to a low level, the first control signal S1 also quickly changes to a low level, and the second control signal S2 quickly changes to a high level to control The first input circuit quickly switches to the off state, and the second input signal quickly switches to the on state. Obviously, using the process of the present invention provides a control circuit for controlling the selection circuit, the output of the comparator inherent delay time Td, significantly higher than the prior art comparator of small intrinsic delay time Td, the second input terminal and a first input terminal The inrush current Iin2_1 is relatively small. The selection circuit 100 and the selection circuit 200 are both maximum value selection circuits. However, the control circuit provided according to the embodiment of the present invention can also be used for the minimum value selection circuit. When the selection circuit needs to select an input circuit with a smaller input signal to connect to the output terminal, the working process of the acceleration response circuit in the control circuit is: when the difference between the larger input signal and the smaller input signal reaches a predetermined value When the input circuit with the larger input signal is still not disconnected, the acceleration response circuit starts to accelerate the flipping of the comparison signal until the input circuit with the larger input signal is disconnected and stops working. In the minimum value selection circuit, the specific implementation of the acceleration response circuit is similar to that in the maximum value selection circuit, and will not be repeated here. In addition, the present invention also provides a control method for controlling the on-off state of two input circuits to select one of the input circuits to access the output terminal, which mainly includes comparing the input signals of the two input circuits to generate a comparison signal , Generate control signals corresponding to the two input circuits according to the comparison signal to control one of the input circuits to be turned on, and the other input circuit to be disconnected. When the input circuit to be disconnected has not been disconnected, accelerate the comparison signal Flip. Further, an acceleration signal can be generated according to two input signals of the input circuit and corresponding control signals to accelerate the inversion of the comparison signal. In addition, if an input circuit with a larger input signal needs to be selected to be connected to the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value, and the input circuit with the smaller input signal is still open When it is on, the acceleration signal starts to be generated to accelerate the inversion of the comparison signal until the input signal with a smaller input signal is disconnected and the action of generating the acceleration signal is stopped. The present invention also provides a power management integrated circuit (PMIC), which mainly includes a control circuit provided according to the present invention. In addition, the present invention also provides another power management integrated circuit (PMIC), which mainly includes a selection circuit provided according to the present invention. The power management integrated circuit provided by the invention not only has a faster response speed, but also has lower power consumption and higher stability. It can be seen from the above that according to the control circuit provided by the present invention, the acceleration response circuit accelerates the flip speed of the comparison signal when the input circuit that needs to be disconnected is too late to disconnect, so that the two input circuits quickly enter the desired state , Effectively reduce the inrush current of the two input terminals, enhance the stability of the system and the chip. According to the embodiments of the present invention described above, these embodiments do not exhaustively describe all the details, nor limit the invention to the specific embodiments described. According to the above description, many modifications and changes can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications and uses based on the present invention. The present invention is only limited by the scope of the patent application and its full scope and equivalents.

100、200‧‧‧選擇電路 S0‧‧‧比較信號 S1‧‧‧第一控制信號 S2‧‧‧第二控制信號 Vmax‧‧‧輸出端 D1‧‧‧第一二極體 D2‧‧‧第二二極體 01‧‧‧比較電路 02‧‧‧邏輯電路 03‧‧‧加速響應電路 MP1‧‧‧第一電晶體 MP2‧‧‧第四電晶體 MP3‧‧‧第七電晶體 MP4‧‧‧第八電晶體 N1‧‧‧第一反相器 Iin2_1‧‧‧衝擊電流 Gm1‧‧‧第一誤差放大器 Gm2‧‧‧第二誤差放大器 Vin2‧‧‧第二輸入信號 Vin1‧‧‧第一輸入信號 Ib_speed_up‧‧‧加速信號 Vt1‧‧‧第一預定值 CP‧‧‧比較器 K1‧‧‧第一開關 K2‧‧‧第二開關 K3、K4‧‧‧開關 Vt2‧‧‧第二預定值 Vtp1‧‧‧第一電晶體MP1的開啟電壓 MN1‧‧‧第二電晶體 MN2‧‧‧第三電晶體 MN3‧‧‧第五電晶體 MN4‧‧‧第六電晶體 N2‧‧‧第二反相器 Td’‧‧‧輸出固有延時 Td‧‧‧固有延時 dt‧‧‧死區時間100、200‧‧‧selection circuit S0‧‧‧Comparison signal S1‧‧‧ First control signal S2‧‧‧Second control signal Vmax‧‧‧ output D1‧‧‧ First Diode D2‧‧‧ Second Diode 01‧‧‧Comparison circuit 02‧‧‧Logic circuit 03‧‧‧Accelerated response circuit MP1‧‧‧First transistor MP2‧‧‧ Fourth Transistor MP3‧‧‧The seventh transistor MP4‧‧‧Eighth transistor N1‧‧‧ First inverter Iin2_1‧‧‧rush current Gm1‧‧‧First error amplifier Gm2‧‧‧Second Error Amplifier Vin2‧‧‧Second input signal Vin1‧‧‧First input signal Ib_speed_up‧‧‧Acceleration signal Vt1‧‧‧First preset value CP‧‧‧Comparator K1‧‧‧ First switch K2‧‧‧Second switch K3, K4‧‧‧ switch Vt2‧‧‧Second predetermined value Vtp1‧‧‧Turn-on voltage of the first transistor MP1 MN1‧‧‧Second transistor MN2‧‧‧third transistor MN3 fifth transistor MN4 ‧‧‧ sixth transistor N2‧‧‧second inverter Td’‧‧‧ inherent delay in output Td‧‧‧Inherent delay dt‧‧‧dead time

圖1為現有的一種最大值選擇電路的結構示意圖； 圖2為圖1中邏輯電路的工作波形圖； 圖3為圖1所示的最大值選擇電路的工作波形圖； 圖4為應用本發明一實施例的控制電路的選擇電路的電路方塊圖； 圖5為應用本發明另一實施例的控制電路的選擇電路的電路圖； 圖6為本發明實施例的選擇電路的工作波形圖。FIG. 1 is a schematic structural diagram of an existing maximum value selection circuit; Figure 2 is a working waveform diagram of the logic circuit in Figure 1; Figure 3 is a working waveform diagram of the maximum value selection circuit shown in Figure 1; 4 is a circuit block diagram of a selection circuit applying a control circuit according to an embodiment of the invention; 5 is a circuit diagram of a selection circuit to which a control circuit of another embodiment of the present invention is applied; 6 is a working waveform diagram of a selection circuit according to an embodiment of the invention.

01‧‧‧比較電路 01‧‧‧Comparison circuit

02‧‧‧邏輯電路 02‧‧‧Logic circuit

03‧‧‧加速響應電路 03‧‧‧Accelerated response circuit

100‧‧‧選擇電路 100‧‧‧selection circuit

CP‧‧‧比較器 CP‧‧‧Comparator

D1‧‧‧第一二極體 D1‧‧‧ First Diode

D2‧‧‧第二二極體 D2‧‧‧ Second Diode

Gm1‧‧‧第一誤差放大器 Gm1‧‧‧First error amplifier

Gm2‧‧‧第二誤差放大器 Gm2‧‧‧Second Error Amplifier

Ib_speed_up‧‧‧加速信號 Ib_speed_up‧‧‧Acceleration signal

K1‧‧‧第一開關 K1‧‧‧ First switch

K2‧‧‧第二開關 K2‧‧‧Second switch

K3、K4‧‧‧開關 K3, K4‧‧‧ switch

S0‧‧‧比較信號 S0‧‧‧Comparison signal

S1‧‧‧第一控制信號 S1‧‧‧ First control signal

S2‧‧‧第二控制信號 S2‧‧‧Second control signal

Vin1‧‧‧第一輸入信號 Vin1‧‧‧First input signal

Vin2‧‧‧第二輸入信號 Vin2‧‧‧Second input signal

Vmax‧‧‧輸出端 Vmax‧‧‧ output

Vt1‧‧‧第一預定值 Vt1‧‧‧First preset value

Vt2‧‧‧第二預定值 Vt2‧‧‧Second predetermined value

Claims (20)

一種控制電路，用於控制兩路輸入電路的通斷狀態，以選擇其中一路輸入電路接入輸出端，其特徵在於，包括加速響應電路， 當需要斷開的一路輸入電路還未斷開時，該加速響應電路輸出加速信號，以加速需要斷開的一路輸入電路的斷開。A control circuit for controlling the on-off state of two input circuits to select one of the input circuits to be connected to the output terminal, which is characterized by including an acceleration response circuit, When an input circuit that needs to be disconnected has not been opened, the acceleration response circuit outputs an acceleration signal to accelerate the disconnection of the input circuit that needs to be disconnected. 根據請求項1所述的控制電路，其中，還包括比較電路，該比較電路用於比較兩個輸入電路的輸入信號，以產生比較信號，該加速信號通過加速該比較信號的翻轉來加速需要斷開的一路輸入電路的斷開。The control circuit according to claim 1, further comprising a comparison circuit for comparing the input signals of the two input circuits to generate a comparison signal, the acceleration signal is accelerated by accelerating the inversion of the comparison signal Disconnection of an open input circuit. 根據請求項2所述的控制電路，其中，還包括邏輯電路，其中，該邏輯電路根據該比較信號產生與兩路輸入電路相對應的控制信號，以控制其中一路輸入電路導通，另一路輸入電路斷開。The control circuit according to claim 2, further comprising a logic circuit, wherein the logic circuit generates a control signal corresponding to two input circuits according to the comparison signal to control one of the input circuits to be turned on and the other input circuit disconnect. 根據請求項2所述的控制電路，其中，該比較電路包括比較器，該加速信號用於增加該比較器的偏置電流，以減小該比較器的輸出延時，來加速該比較信號的翻轉。The control circuit according to claim 2, wherein the comparison circuit includes a comparator, and the acceleration signal is used to increase the bias current of the comparator to reduce the output delay of the comparator to accelerate the inversion of the comparison signal . 根據請求項3所述的控制電路，其中，兩個輸入電路所對應的輸入信號分別為第一輸入信號、第二輸入信號，該加速響應電路接收第一輸入信號、第二輸入信號以及對應的控制信號，以產生該加速信號。The control circuit according to claim 3, wherein the input signals corresponding to the two input circuits are a first input signal and a second input signal, respectively, and the acceleration response circuit receives the first input signal, the second input signal, and the corresponding Control signals to generate the acceleration signal. 根據請求項5所述的控制電路，其中，若需要選擇輸入信號較大的一路輸入電路接入輸出端，則當較大的輸入信號與較小的輸入信號之差達到預定值時，且輸入信號較小的一路輸入電路仍未斷開時，該加速響應電路開始工作，以加速該比較信號的翻轉，直到輸入信號較小的一路輸入電路斷開時停止工作。The control circuit according to claim 5, wherein if an input circuit with a larger input signal needs to be selected to be connected to the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value, and the input When the input circuit with the smaller signal is not disconnected, the acceleration response circuit starts to work to accelerate the reversal of the comparison signal until the input circuit with the smaller input signal is disconnected and stops working. 根據請求項6所述的控制電路，其中，該加速響應電路包括第一誤差電路、第二誤差電路， 當兩個該輸入信號中的第一輸入信號的值大於第一疊加值，且兩個該輸入信號中的第二輸入信號對應的第二輸入電路仍未斷開時，該第一誤差電路工作，並根據該第一輸入信號的值與該第一疊加值之間的差值產生第一誤差信號，以作為該加速信號，該第一疊加值為該第二輸入信號的值與一預定值的疊加值， 當該第二輸入信號的值大於第二疊加值，且該第一輸入電路仍未斷開時，該第二誤差電路工作，並根據該第二輸入信號的值與該第二疊加值之間的差值產生第二誤差信號，以作為該加速信號，該第二疊加值為該第一輸入信號的值與第二預定值的疊加值。The control circuit according to claim 6, wherein the acceleration response circuit includes a first error circuit and a second error circuit, When the value of the first input signal of the two input signals is greater than the first superimposed value, and the second input circuit corresponding to the second input signal of the two input signals is still open, the first error circuit works And generate a first error signal according to the difference between the value of the first input signal and the first superimposed value as the acceleration signal, the first superimposed value is the value of the second input signal and a predetermined value The superimposed value of When the value of the second input signal is greater than the second superimposed value, and the first input circuit is still not disconnected, the second error circuit operates, and according to the value of the second input signal and the second superimposed value The difference generates a second error signal as the acceleration signal, and the second superimposed value is the superimposed value of the value of the first input signal and the second predetermined value. 根據請求項7所述的控制電路，其中， 第三開關電路，由用於控制該第二輸入電路的第二控制信號控制，當該第三開關電路導通時，該第一誤差信號作為該加速信號被傳輸至該比較電路， 第四開關電路，由用於控制第一輸入電路的第一控制信號控制，當該第四開關電路導通時，該第二誤差信號作為該加速信號被傳輸至該比較電路。The control circuit according to claim 7, wherein, The third switch circuit is controlled by a second control signal for controlling the second input circuit. When the third switch circuit is turned on, the first error signal is transmitted to the comparison circuit as the acceleration signal, The fourth switch circuit is controlled by a first control signal for controlling the first input circuit. When the fourth switch circuit is turned on, the second error signal is transmitted to the comparison circuit as the acceleration signal. 根據請求項8所述的控制電路，其中， 該第一誤差電路包括第一電晶體、第二電晶體和第三電晶體， 該第二誤差電路包括第四電晶體、第五電晶體和第六電晶體， 該第三開關電路包括第一反相器和第七電晶體， 該第四開關電路包括第二反向器和第八電晶體， 該第一電晶體的第一端接收該第一輸入信號，第二端通過該第七電晶體與該第二電晶體相連，該第一電晶體的控制端接收該第二輸入信號，該第二電晶體與該第三電晶體構成第一電流鏡，該第二控制信號通過該第一反相器被傳輸至該第七電晶體的控制端， 該第四電晶體的第一端接收該第二輸入信號，第二端通過該第八電晶體與該第五電晶體相連，該第四電晶體的控制端接收該第一輸入信號，該第五電晶體與該第六電晶體構成第二電流鏡，該第一控制信號通過該第二反相器被傳輸至該第八電晶體的控制端， 該第一電晶體在該第一輸入信號的值大於該第一疊加值時導通，該第七電晶體在該第二控制信號有效期間導通，當該第一電晶體與第七電晶體均導通時，該第一電流鏡輸出該第一誤差信號，該第一電晶體的閾值電壓的值為該第一預定值， 該第四電晶體在該第二輸入信號的值大於該第二疊加值時導通，該第八電晶體在該第一控制信號有效期間導通，當該第四電晶體與第八電晶體均導通時，該第二電流鏡輸出該第二誤差信號，該第四電晶體的閾值電壓的值為該第二預定值。The control circuit according to claim 8, wherein, The first error circuit includes a first transistor, a second transistor, and a third transistor, The second error circuit includes a fourth transistor, a fifth transistor, and a sixth transistor, The third switching circuit includes a first inverter and a seventh transistor, The fourth switching circuit includes a second inverter and an eighth transistor, The first terminal of the first transistor receives the first input signal, the second terminal is connected to the second transistor through the seventh transistor, and the control terminal of the first transistor receives the second input signal, the first The second transistor and the third transistor constitute a first current mirror, and the second control signal is transmitted to the control terminal of the seventh transistor through the first inverter, The first end of the fourth transistor receives the second input signal, the second end is connected to the fifth transistor through the eighth transistor, and the control end of the fourth transistor receives the first input signal, the first The fifth transistor and the sixth transistor constitute a second current mirror, and the first control signal is transmitted to the control terminal of the eighth transistor through the second inverter, The first transistor is turned on when the value of the first input signal is greater than the first superimposed value, the seventh transistor is turned on during the valid period of the second control signal, when both the first transistor and the seventh transistor are turned on At this time, the first current mirror outputs the first error signal, the value of the threshold voltage of the first transistor is the first predetermined value, The fourth transistor is turned on when the value of the second input signal is greater than the second superimposed value, the eighth transistor is turned on during the valid period of the first control signal, when both the fourth transistor and the eighth transistor are turned on At this time, the second current mirror outputs the second error signal, and the value of the threshold voltage of the fourth transistor is the second predetermined value. 根據請求項7所述的控制電路，其中，該輸入電路中的第一輸入電路包括第一二極體和第一開關，該輸入電路中的第二輸入電路包括第二二極體和第二開關， 該第一二極體與該第一開關並聯，且該第一二極體的陽極端接收該第一輸入信號，陰極端與該第二二極體的陰極端相連， 該第二二極體與該第二開關並聯，且該第二二極體的陽極接收該第二輸入信號， 該第一二極體與第二二極體的相連端作為該輸出端。The control circuit according to claim 7, wherein the first input circuit in the input circuit includes a first diode and a first switch, and the second input circuit in the input circuit includes a second diode and a second switch, The first diode is connected in parallel with the first switch, and the anode terminal of the first diode receives the first input signal, and the cathode terminal is connected to the cathode terminal of the second diode, The second diode is connected in parallel with the second switch, and the anode of the second diode receives the second input signal, The connecting end of the first diode and the second diode is used as the output end. 根據請求項5所述的控制電路，其中，若需要選擇輸入信號較小的一路輸入電路接入輸出端，則當較大的輸入信號與較小的輸入信號之差達到預定值時，且輸入信號較大的一路輸入電路仍未斷開時，該加速響應電路開始工作，以加速該比較信號的翻轉，直到輸入信號較大的一路輸入電路斷開時停止工作。The control circuit according to claim 5, wherein if an input circuit with a smaller input signal needs to be selected to be connected to the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value, and the input When the input circuit with the larger signal is not disconnected, the acceleration response circuit starts to work to accelerate the flipping of the comparison signal until the input circuit with the larger input signal is disconnected and stops working. 根據請求項10所述的控制電路，其中，該邏輯電路根據該比較信號以及該第一開關與第二開關的死區時間，生成帶該死區時間資訊的該第一控制信號與第二控制信號， 該第一輸入信號大於該第二輸入信號後，該第一控制信號控制該第一開關導通，該第二控制信號控制該第二開關關斷， 該第二輸入信號大於該第一輸入信號後，該第一控制信號控制該第一開關關斷，該第二控制信號控制該第二開關導通。The control circuit according to claim 10, wherein the logic circuit generates the first control signal and the second control signal with the dead time information according to the comparison signal and the dead time of the first switch and the second switch , After the first input signal is greater than the second input signal, the first control signal controls the first switch to turn on, and the second control signal controls the second switch to turn off, After the second input signal is greater than the first input signal, the first control signal controls the first switch to turn off, and the second control signal controls the second switch to turn on. 一種控制方法，用於控制兩路輸入電路的通斷狀態，以選擇其中一路輸入電路接入輸出端，其特徵在於， 當需要斷開的一路輸入電路還未斷開時，加速需要斷開的一路輸入電路的斷開。A control method for controlling the on-off state of two input circuits to select one of the input circuits to be connected to the output terminal, which is characterized by When the input circuit that needs to be disconnected has not been disconnected, the disconnection of the input circuit that needs to be disconnected is accelerated. 根據請求項13所述的控制方法，其中，還包括，比較兩個輸入電路的輸入信號，以產生比較信號，該加速信號通過加速該比較信號的翻轉來加速需要斷開的一路輸入電路的斷開。The control method according to claim 13, further comprising comparing the input signals of the two input circuits to generate a comparison signal, and the acceleration signal accelerates the interruption of the input circuit to be disconnected by accelerating the inversion of the comparison signal open. 根據請求項14所述的控制電路，其中，根據該比較信號產生與兩路輸入電路相對應的控制信號，以控制其中一路輸入電路導通，另一路輸入電路斷開。The control circuit according to claim 14, wherein a control signal corresponding to two input circuits is generated according to the comparison signal to control one of the input circuits to be turned on and the other input circuit to be turned off. 根據請求項13所述的控制方法，其中，根據兩個該輸入電路的輸入信號以及對應的控制信號產生加速信號，以加速該比較信號的翻轉。The control method according to claim 13, wherein an acceleration signal is generated according to two input signals of the input circuit and corresponding control signals to accelerate the inversion of the comparison signal. 根據請求項16所述的控制方法，其中，若需要選擇輸入信號較大的一路輸入電路接入輸出端，則當較大的輸入信號與較小的輸入信號之差達到預定值時，且輸入信號較小的一路輸入電路仍未斷開時，開始產生該加速信號，以加速該比較信號的翻轉，直到輸入信號較小的一路輸入電路斷開時停止產生該加速信號的動作。The control method according to claim 16, wherein if an input circuit with a larger input signal needs to be selected to be connected to the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value, and the input When the input circuit with the smaller signal is not disconnected, the acceleration signal is generated to accelerate the reversal of the comparison signal until the input circuit with the smaller input signal is disconnected to stop generating the acceleration signal. 一種選擇電路，其特徵在於，包括兩路輸入電路和請求項1至12中任意一項所述的控制電路。A selection circuit is characterized by comprising two input circuits and a control circuit according to any one of the request items 1 to 12. 一種電源管理積體電路，其特徵在於，包括請求項1至12中任意一項所述的控制電路。A power management integrated circuit, characterized by comprising the control circuit according to any one of the request items 1 to 12. 一種電源管理積體電路，其特徵在於，包括請求項18所述的選擇電路。A power management integrated circuit is characterized by comprising the selection circuit described in claim 18.
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