CN108388302B - Control circuit, control method, selection circuit and power management integrated circuit - Google Patents
Control circuit, control method, selection circuit and power management integrated circuit Download PDFInfo
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- CN108388302B CN108388302B CN201810125408.XA CN201810125408A CN108388302B CN 108388302 B CN108388302 B CN 108388302B CN 201810125408 A CN201810125408 A CN 201810125408A CN 108388302 B CN108388302 B CN 108388302B
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Abstract
The invention provides a control circuit, a control method, a selection circuit and a power management integrated circuit, wherein when the control circuit controls the selection circuit, the control circuit accelerates the turning speed of a comparison signal by accelerating a response circuit when an input circuit needing to be disconnected is not disconnected in time, so that the two input circuits can rapidly enter a required state, the impact currents of the two input ends are effectively reduced, and the stability of a power management integrated circuit system and a power management integrated chip is enhanced.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a control circuit, a control method, a selection circuit and a power management integrated circuit.
Background
Fig. 1 is a schematic structural diagram of a conventional maximum value selection circuit, which mainly includes a first input circuit composed of a diode D1 and a switch K1, a second input circuit composed of a diode D2 and a switch K2, and a control circuit for controlling on-off states of the first input circuit and the second input circuit to select one of the first input circuit and the second input circuit, which receives a larger input signal, to be connected to an output terminal Vmax. The first input circuit receives a first input signal Vin1, the second input circuit receives a second input signal Vin2, and the first input circuit is commonly connected with the output end of the second input circuit to serve as the output end Vmax of the maximum value selection circuit. The control circuit mainly comprises a comparator and a logic circuit, wherein the comparator is used for comparing the magnitude of the first input signals Vin1 and Vin2 to output a comparison signal S0. As shown in the operation waveform diagram of the logic circuit of fig. 2, the logic circuit converts the comparison signal S0 into control signals S1, S2 with dead time dt of the switch K1 and the switch K2, respectively, to control the on-off states of the switch K1 and the switch K2, respectively, when the second input signal Vin2 rises to be greater than the first input signal Vin1, the comparator S0 flips and triggers the control signal S1 to flip to control the switch K1 to turn off, the control signal S2 flips after a dead time dt to control the switch K2 to turn on to block the first input circuit reversely, the second input circuit is connected to the output terminal Vmax, conversely, when the first input signal Vin1 rises to be greater than the second input signal Vin2, the comparator S0 flips and triggers the control signal S2 to flip to control the switch K2 to turn off, the control signal S1 flips after a dead time Vin1 to control the switch K1 to turn on to block the second input circuit reversely, the first input circuit is connected to the output terminal Vmax. The diodes D1 and D2 can ensure that the output terminal Vmax still has the maximum output signal (Vin1, Vin2) max-Vnp within the dead time dt, where Vnp is the turn-on voltage of the diode.
In such a maximum selection circuit as shown in fig. 1, when the input signals are switched rapidly, a large rush current problem may occur between the two input terminals. The reason for this is that, as shown in fig. 3, which is an operation waveform diagram of the maximum value selection circuit shown in fig. 1, when the second input signal Vin2 rapidly exceeds the sum of the first input signals Vin1 and Vnp, the comparator that is always operated has a non-negligible output delay Td due to the small bias current, so that the comparison signal S0 needs to be inverted after the inherent delay Td, and then a surge current Iin2_1 from the input terminal of the second input signal Vin2 to the input terminal of the first input signal Vin1 through the diode D2 and the K1 that is not turned off too soon will be generated within the inherent delay Td. If the difference between the second input signal Vin2 and the first input signal Vin1 increases during the inherent delay time Td, Iin2_1 also increases continuously, which is disadvantageous in two aspects. First, the first input signal Vin2 will bring the voltage at the input of the first input signal Vin1 high, causing a front-end system overvoltage at the input of the first input signal Vin 1. Second, in the chip, a large current flows through the diode D2, and thus the chip is easily damaged by local overheating or a nearby parasitic device is excited to cause latch-up, which causes chip damage.
Disclosure of Invention
In view of the above, the present invention provides a control circuit, a control method and a selection circuit, so as to reduce the inherent delay time by adding the fast inversion of the comparison signal when the input signal is switched fast, so that each input circuit of the selection circuit enters the normal state as fast as possible.
A control circuit is used for controlling the on-off state of two input circuits so as to select one input circuit to be connected with an output end, and is characterized by comprising an acceleration response circuit,
when one path of input circuit needing to be disconnected is not disconnected, the acceleration response circuit outputs an acceleration signal so as to accelerate the disconnection of the path of input circuit needing to be disconnected.
Preferably, the control circuit further comprises a comparison circuit, the comparison circuit is used for comparing input signals of two input circuits to generate a comparison signal, and the acceleration signal accelerates the disconnection of one input circuit to be disconnected by accelerating the inversion of the comparison signal.
Preferably, the control circuit further includes a logic circuit, and is characterized in that the logic circuit generates a control signal corresponding to the two input circuits according to the comparison signal to control one input circuit to be turned on and the other input circuit to be turned off
Preferably, the comparison circuit comprises a comparator, and the acceleration signal is used for increasing the bias current of the comparator to reduce the output delay of the comparator so as to accelerate the inversion of the comparison signal.
Preferably, the input signals corresponding to the two input circuits are a first input signal and a second input signal respectively, and the acceleration response circuit receives the first input signal, the second input signal and a corresponding control signal to generate the acceleration signal.
Preferably, if it is required to select one of the input circuits with a larger input signal to access the output terminal, when a difference between the larger input signal and the smaller input signal reaches a predetermined value and the one of the input circuits with the smaller input signal is still not disconnected, the accelerated response circuit starts to operate to accelerate the inversion of the comparison signal until the one of the input circuits with the smaller input signal is disconnected.
Preferably, the accelerated response circuit includes a first error circuit, a second error circuit,
when the value of a first input signal of the two input signals is larger than a first superposition value and a second input circuit corresponding to a second input signal of the two input signals is not disconnected, the first error circuit works and generates a first error signal according to the difference between the value of the first input signal and the first superposition value to serve as the acceleration signal, wherein the first superposition value is the superposition value of the second input signal and a preset value,
when the value of the second input signal is greater than a second overlap value, which is a value of the first input signal and a second predetermined value, and the first input circuit is not yet turned off, the second error circuit operates and generates a second error signal as the acceleration signal according to a difference between the value of the second input signal and the second overlap value.
Preferably, a third switching circuit controlled by a second control signal for controlling the second input circuit, the first error signal being transmitted to the comparison circuit as the acceleration signal when the third switching circuit is turned on,
a fourth switch circuit controlled by a first control signal for controlling the first input circuit, the second error signal being transmitted to the comparison circuit as the acceleration signal when the fourth switch circuit is turned on.
Preferably, the first error circuit includes a first transistor, a second transistor, and a third transistor,
the second error circuit includes a fourth transistor, a fifth transistor and a sixth transistor,
the third switching circuit includes a first inverter and a seventh transistor,
the fourth switching circuit includes a second inverter and an eighth transistor,
a first terminal of the first transistor receives the first input signal, a second terminal of the first transistor is connected to the second transistor through the seventh transistor, a control terminal of the first transistor receives the second input signal, the second transistor and the third transistor form a first current mirror, and the second control signal is transmitted to a control terminal of the seventh transistor through the first inverter,
a first terminal of the fourth transistor receives the second input signal, a second terminal of the fourth transistor is connected to the fifth transistor through the eighth transistor, a control terminal of the fourth transistor receives the first input signal, the fifth transistor and the sixth transistor form a second current mirror, and the first control signal is transmitted to the control terminal of the eighth transistor through the second inverter,
the first transistor is turned on when the value of the first input signal is larger than the first superposition value, the seventh transistor is turned on during the period when the second control signal is active, the first current mirror outputs the first error signal when both the first transistor and the seventh transistor are turned on, the value of the threshold voltage of the first transistor is the first predetermined value,
the fourth transistor is turned on when the value of the second input signal is greater than the second superposition value, the eighth transistor is turned on during the period when the first control signal is active, the second current mirror outputs the second error signal when both the fourth transistor and the eighth transistor are turned on, and the value of the threshold voltage of the fourth transistor is the second predetermined value.
Preferably, a first one of the input circuits comprises a first diode and a first switch, a second one of the input circuits comprises a second diode and a second switch,
the first diode is connected with the first switch in parallel, the anode end of the first diode receives the first input signal, the cathode end of the first diode is connected with the cathode end of the second diode,
the second diode is connected in parallel with the second switch, and an anode of the second diode receives the second input signal,
and the connection end of the first diode and the second diode is used as the output end.
Preferably, if it is required to select one input circuit with a smaller input signal to access the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value and the input circuit with the larger input signal is still not disconnected, the accelerated response circuit starts to operate to accelerate the inversion of the comparison signal until the input circuit with the larger input signal is disconnected.
Preferably, the logic circuit generates the first and second control signals with the dead time information according to the comparison signal and the dead time of the first and second switches,
when the first input signal is greater than the second input signal, the first control signal controls the first switch to be switched on, and the second control signal controls the second switch to be switched off,
after the second input signal is greater than the first input signal, the first control signal controls the first switch to be turned off, and the second control signal controls the second switch to be turned on.
A control method is used for controlling the on-off state of two input circuits to select one input circuit to be connected with an output end,
when the other input circuit needing to be disconnected is not disconnected, the disconnection of the input circuit needing to be disconnected is accelerated.
Preferably, the control method further includes comparing the input signals of the two input circuits to generate a comparison signal, and the acceleration signal accelerates the disconnection of the input circuit to be disconnected by accelerating the inversion of the comparison signal.
Preferably, the control signal corresponding to the two input circuits is generated according to the comparison signal to control one input circuit to be switched on and the other input circuit to be switched off.
Preferably, an acceleration signal is generated according to input signals of two input circuits and corresponding control signals to accelerate the inversion of the comparison signal.
Preferably, if it is required to select one of the input circuits with a larger input signal to access the output terminal, when a difference between the larger input signal and the smaller input signal reaches a predetermined value and the one of the input circuits with the smaller input signal is still not disconnected, the acceleration signal is generated to accelerate the inversion of the comparison signal, and the generation of the acceleration signal is stopped until the one of the input circuits with the smaller input signal is disconnected.
A selection circuit is characterized by comprising two input circuits and the control circuit in any one of the two input circuits.
A power management integrated circuit comprising the control circuit of any preceding claim.
A power management integrated circuit comprises the selection circuit.
Therefore, according to the control circuit provided by the invention, when the input circuit needing to be disconnected is not ready to be disconnected, the response acceleration circuit accelerates the turning speed of the comparison signal, so that the two input circuits can rapidly enter the required state, the impact current of the two input ends is effectively reduced, and the stability of a system and a chip is enhanced.
Drawings
Fig. 1 is a schematic diagram of a conventional maximum value selection circuit;
FIG. 2 is a waveform diagram illustrating operation of the logic circuit of FIG. 1;
FIG. 3 is a waveform diagram illustrating the operation of the maximum selection circuit shown in FIG. 1;
FIG. 4 is a block diagram of a selection circuit to which the control circuit of one embodiment of the present invention is applied;
FIG. 5 is a circuit diagram of a selection circuit to which a control circuit according to another embodiment of the present invention is applied;
fig. 6 is a waveform diagram illustrating the operation of the selection circuit according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any creative effort, shall fall within the protection scope of the present invention. It should be noted that "…" in this description of the preferred embodiment is only for technical attributes or features of the present invention.
In order to solve the problem of slow response speed of the comparator in the selection circuit shown in fig. 1, the present invention provides a new control circuit and control method, and a circuit block diagram of the selection circuit 100 using the control circuit provided by the present invention is shown in fig. 4. In this embodiment, the selecting circuit 100 is a maximum value selecting circuit, and includes, in addition to the control circuit provided according to the present invention, two input circuits, namely a first input circuit and a second input circuit, an input end of the first input circuit receives the first input signal Vin1, an input end of the second input circuit receives the second input signal Vin2, output ends of the two input circuits are commonly connected to serve as an output end Vmax of the selecting circuit 100, and the control circuit is configured to control on-off states of the first input circuit and the second input circuit to select one of the input circuits to be connected to an output end of the selecting circuit, for example, in this embodiment, the input circuit with a larger value of the input signal is selected to be connected to the output end of the selecting circuit. The control circuit mainly comprises a comparison circuit 01, a logic circuit 02 and an acceleration response circuit 03.
The comparison circuit 01 is used for comparing the magnitude relationship between the first input signal Vin1 and the second input signal Vin2 to generate a comparison signal S0. The logic circuit 02 generates control signals S1, S2 corresponding to the two input circuits according to the comparison signal S0 to control one input circuit to be turned on and the other input circuit to be turned off. In the present embodiment, the first control signal S1 and the second control signal S2 are generated by triggering the comparison signal S0 and respectively include dead time information of the switches in the first input circuit and dead time information of the switches in the first input circuit. As shown in fig. 2, when the second input signal Vin2 rises to be greater than the first input signal Vin1, the comparison signal S0 is inverted, so that the first control signal S1 is inverted to control the first input circuit to turn off, and the second control signal S2 is inverted after a dead time to control the second input circuit to turn on. When the first input signal Vin1 rises to be greater than the second input signal Vin2, the comparison signal S0 is inverted, such that the second control signal S2 is inverted to control the second input circuit to be turned off, and the first control signal S1 is inverted after a dead time to control the first input circuit to be turned on.
However, in practical applications, the comparator circuit 01 is always operated during the operation of the selection circuit, and then the comparator circuit 01 is usually implemented by selecting the comparator CP with a smaller bias current in order to reduce power consumption. When the comparator CP with low power consumption compares that the magnitude relationship of two input signals changes, the comparison signal S0 output by the comparator CP does not immediately turn over, but turns over only after the inherent delay of the comparator CP, so that the time when the first control signal S1 and the second control signal S2 control the corresponding input circuits to enter the corresponding states also delays, which may cause that one input circuit to be disconnected is not ready to be disconnected, and this may cause a large current to exist between the input ends of the two input circuits to damage the chip. For example, in the maximum value selection circuit, after the first input signal Vin1 jumps to be greater than the second input signal Vin2, the second input circuit corresponding to the second input signal Vin2 needs to be turned off, and after the second input signal Vin2 jumps to be greater than the first input signal Vin1, the first input circuit corresponding to the first input signal Vin1 needs to be turned off. In the minimum value selection circuit, after the first input signal Vin1 jumps to be less than the second input signal Vin2, the second input circuit corresponding to the second input signal Vin2 needs to be turned off, and after the second input signal Vin2 jumps to be less than the first input signal Vin1, the first input circuit corresponding to the first input signal Vin1 needs to be turned off.
However, the control circuit provided by the present invention further includes an acceleration response circuit 03, which is mainly configured to output an acceleration signal Ib _ speed _ up when one of the input circuits to be disconnected is not yet disconnected, so as to accelerate the disconnection of the first input circuit to be disconnected, that is, reduce the time for switching the on state of the one of the input circuits to be disconnected to the off state, for example, the acceleration signal Ib _ speed _ up is used in this embodiment to accelerate the inversion of the comparison signal S0, so that the comparison circuit 01 has a faster response speed while having low power consumption, and thus accelerates the disconnection of the one of the input circuits to be disconnected by accelerating the inversion of the comparison signal S0. The acceleration signal Ib _ speed _ up is a current signal, which is transmitted to the comparator CP to increase the bias current of the comparator CP and reduce the output delay of the comparator CP, thereby accelerating the inversion of the comparison signal S0. As shown in fig. 4, the acceleration response circuit 03 receives the first input signal Vin1, the second input signal Vin2, the first control signal S1 and the second control signal S2, and outputs an acceleration signal Ib _ speed _ up.
With continued reference to fig. 4, in the present embodiment, the selection circuit 100 is a maximum value selection circuit, and the first input circuit thereof includes a first diode D1 and a first switch K1, and the second input circuit includes a second diode D2 and a second switch K2. The first diode D1 is connected in parallel with the first switch K1, an anode terminal of the first diode D1 receives the first input signal Vin1, a cathode terminal of the first diode D1 is connected to a cathode terminal of the second diode D2, the second diode D2 is connected in parallel with the second switch K2, an anode terminal of the second diode D2 receives the second input signal Vin2, and a connection terminal of the first diode D1 and the second diode D2 serves as the output terminal.
When the difference between the larger and the smaller of the first input signal Vin1 and the second input signal Vin2 reaches a predetermined value and one input circuit with a smaller input signal is still not disconnected (i.e., the corresponding control signal is still in an active state, such as a high state), the accelerated response circuit 03 starts to operate to accelerate the inversion of the comparison signal S0 until the input circuit with a smaller input signal is disconnected (the corresponding control signal is in an inactive state, such as a low state). The accelerated response circuit in this embodiment comprises a first error circuit and a second error circuit, when the value of the first input signal Vin1 is greater than a first superposition value, and the first input circuit is not turned on yet and is not turned off yet, the first error circuit starts to operate and generates a first error signal according to the difference between the value of the first input signal Vin1 and the first superposition value as the accelerated signal Ib _ speed _ up, wherein the first superposition value is the superposition value of the second input signal Vin2 and a predetermined value Vt 1. The first predetermined value Vt1 is the value of the offset voltage of the first error circuit, which includes the first error amplifier Gm1 and the second error circuit includes the second error amplifier Gm2 in fig. 4. The first error amplifier outputs the difference between the first input signal Vin1 and the first superposition value, and in fig. 4, the first predetermined value voltage Vt1 received at the inverting input terminal of the first error amplifier Gm1 does not mean that the inverting input terminal is electrically connected to a voltage having the first predetermined value Vt1, but indicates that the value of the signal received at the inverting input terminal is the first superposition value obtained by superposing the second input signal Vin2 and the first predetermined value Vt 1. Similarly, the second predetermined value Vt2 is the offset voltage of the second error circuit. The second error amplifier Gm2 outputs the difference between the second input signal Vin2 and the second superposition value, and in fig. 4, the second predetermined value voltage Vt2 received by the inverting input terminal of the second error amplifier Gm2 does not mean that the inverting input terminal is electrically connected to a voltage having the second predetermined value Vt2, but indicates that the value of the signal received by the inverting input terminal is the second superposition value obtained by superimposing the first input signal Vin1 and the second predetermined value Vt 2. When the value of the second input signal Vin2 is greater than the second superimposed value and the first input circuit is still not turned off (the first control signal S1 is still in an active state), the second error circuit starts to operate and generates a second error signal according to the difference between the value of the second input signal Vin2 and the second superimposed value, as the acceleration signal Ib _ speed _ up.
The speed-up response circuit 03 further comprises a switching circuit controlled by a second control signal S2, the first error signal being transmitted as a speed-up signal Ib _ speed _ up to the comparison circuit 01 when the switching circuit is switched on, the third switching circuit controlled by a second control signal S2 comprising a switch K3. The speed-up response circuit 03 further comprises a fourth switching circuit controlled by the first control signal S1, which second error signal is transmitted as the speed-up signal Ib _ speed _ up to the comparing circuit 01 when the switching circuit is switched on, which switching circuit controlled by the first control signal S1 comprises the switch K4.
Fig. 5 is a circuit block diagram of a selection circuit 200 according to an embodiment of the invention. A specific implementation circuit of the acceleration response circuit 03 is shown in the selection circuit 200 shown in fig. 5, and as shown in fig. 5, the first error circuit includes a first transistor MP1, a second transistor MN1, and a third transistor MN2, the second error circuit includes a fourth transistor MP2, a fifth transistor MN3, and a sixth transistor MN4, the third switch circuit includes a first inverter N1 and a seventh transistor MP3, and the fourth switch circuit includes a second inverter N2 and an eighth transistor MP 4. A first terminal of the first transistor MP1 receives the first input signal Vin1, a second terminal is connected to the second transistor MN1 through a seventh transistor MP3, a control terminal of the first transistor MP1 receives the second input signal Vin2, the second transistor MN1 and the third transistor MN2 form a first current mirror, the second control signal S2 is transmitted to a control terminal of the seventh transistor MP3 through a first inverter N1, a first terminal of the fourth transistor MP2 receives the second input signal Vin2, a second terminal is connected to the fifth transistor MN3 through an eighth transistor MP4, a control terminal of the fourth transistor MP2 receives the first input signal Vin1, the fifth transistor MN3 and the sixth transistor MN4 form a second current mirror, the first control signal S367 is transmitted to a control terminal of the eighth transistor MP4 through a second inverter N2, the first transistor MP4 turns on the second control signal 4 when the value of the first input signal Vin 4 is greater than the second input signal MP4, the second transistor MN 36 12 is active, when the first transistor MP1 and the seventh transistor MP3 are both turned on, the first current mirror outputs the first error signal, the value of the turn-on voltage of the first transistor MP1 is the first predetermined value, the fourth transistor MP2 is turned on when the value of the second input signal Vin2 is greater than the second superimposed value, the eighth transistor MP4 is turned on during the active period of the first control signal S1, the second current mirror outputs the second error signal when the fourth transistor MP2 and the eighth transistor MP4 are both turned on, and the value of the turn-on voltage of the fourth transistor MP2 is the second predetermined value. Among them, the first inverter N1 and the seventh transistor MP3 in fig. 5 constitute the switch K3 in fig. 4, and the second inverter N2 and the eighth transistor MP4 constitute the switch K4 in fig. 4.
Take the first input signal Vin1 jumping upwards to exceed the second input signal Vin2, and each switch is turned on by high control and turned off by low control (active high). When Vin1< Vin2, the second control signal S2 is at a high level, the switch K2 is turned on, the first control signal S1 is at a low level, the switch K1 is turned off, the seventh transistor MP3 is turned on, the first transistor MP1 is turned off, and no current is generated by the first current mirror formed by the second transistor MN1 and the third transistor MN 2; the eighth transistor MP4 is turned off, and the second current mirror formed by the fifth transistor MN3 and the sixth transistor MN4 does not generate current. The accelerated response circuit 03 does not generate static power consumption. When the first input signal Vin1 rapidly exceeds the second input signal Vin2, and Vin1-Vin2> Vtp1(Vtp1 is the turn-on voltage of the first transistor MP1, and the value thereof is the first predetermined value), if the comparison signal S0 is not ready to flip over, then the first control signal S1 is still low, the eighth transistor MP4 is turned off, the second control signal S2 is still high, the transistor MP3 is still turned on, and at this time the first transistor MP1 is already turned on by the difference between the first input signal Vin1 and the second input signal Vin 2. Therefore, a first error signal is generated on the first current mirror as an acceleration signal Ib _ speed _ up to accelerate the inversion of the comparison signal S0 output by the comparator CP. When the comparison signal S0 is inverted, the second control signal S2 is at a low level, the seventh transistor MP3 is turned off, the first control signal S1 is at a high level, and the eighth transistor MP4 is turned on, but since the fourth transistor MP2 is turned off at this time, neither the first current mirror nor the second current mirror outputs current, the acceleration response circuit 03 is in a static state without power consumption.
Similarly, if the second input signal Vin2 rises to exceed the first input signal Vin1, during the period of Vin2< Vin1, the first current mirror and the second current mirror are both not outputting current, the accelerated response circuit 03 is in a static power-free state (i.e. in a non-operating state), when Vin2-Vin1> Vtp2 (Vtp2 is the turn-on voltage of the fourth transistor MP2, and the second predetermined value), if the comparison signal S0 is not ready to be inverted, the first current mirror does not generate current, but the second current mirror generates current as the acceleration signal Ib _ speed _ up, so that the comparison signal S0 output by the comparator CP is accelerated to be inverted, and when the comparison signal S0 is inverted, the first current mirror and the second current mirror are both outputting current, so that the accelerated response circuit 03 is in the static power-free state. The configuration of the first current mirror and the second current mirror is not limited to the configuration shown in fig. 5.
Fig. 6 is a waveform diagram illustrating operation of the selection circuit 100 or 200 according to an embodiment of the invention, as shown in fig. 6, during a period when the second input signal Vin2 is smaller than the first input signal Vin1, the comparison signal S0 is at a high level, the first control signal S1 is at a high level, the second control signal S2 is at a low level, the first input circuit is turned on to be connected to the output terminal Vmax, the second input circuit is turned off (reverse blocking), when the second input signal Vin2 increases to exceed Vin1+ Vtp1, the accelerated response circuit makes the comparison signal S0 rapidly turn to a low level, the first control signal S1 also rapidly turns to a low level, and the second control signal S2 rapidly turns to a high level to control the first input circuit to rapidly switch to an off state and the second input signal to rapidly switch to an on state. Obviously, in the process of controlling the selection circuit by using the control circuit provided by the present invention, the inherent delay Td of the output of the comparator is obviously smaller than the inherent delay Td of the comparator in the prior art, and the impact current Iin2_1 between the second input end and the first input end is relatively small.
The selection circuit 100 and the selection circuit 200 are both maximum value selection circuits, however, the control circuit provided according to the embodiment of the present invention can also be used for minimum value selection circuits. When the selection circuit needs to select one input circuit with a smaller input signal to access the output end, the working process of the accelerated response circuit in the control circuit is as follows: when the difference between the larger input signal and the smaller input signal reaches a preset value and one path of input circuit with the larger input signal is still not disconnected, the acceleration response circuit starts to work to accelerate the inversion of the comparison signal until the path of input circuit with the larger input signal is disconnected. In the minimum value selection circuit, the specific implementation of the accelerated response circuit is similar to that in the maximum value selection circuit, and will not be described in detail here.
In addition, the invention also provides a control method for controlling the on-off state of the two input circuits so as to select one input circuit to be connected with the output end, which mainly comprises the steps of comparing the input signals of the two input circuits to generate a comparison signal, generating a control signal corresponding to the two input circuits according to the comparison signal so as to control the on-off of one input circuit and the off-off of the other input circuit, and accelerating the turnover of the comparison signal when the input circuit needing to be switched off is not switched off. Further, an acceleration signal may be generated according to the input signals of the two input circuits and the corresponding control signals to accelerate the inversion of the comparison signal. In addition, if it is required to select the input circuit with the larger input signal to access the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value and the input circuit with the smaller input signal is still not disconnected, the acceleration signal is generated to accelerate the inversion of the comparison signal, and the generation of the acceleration signal is stopped until the input circuit with the smaller input signal is disconnected.
The invention also provides a Power Management Integrated Circuit (PMIC), which mainly comprises the control circuit provided by the invention. In addition, the invention also provides another Power Management Integrated Circuit (PMIC), which mainly comprises the selection circuit provided by the invention. The power management integrated circuit provided by the invention has the advantages of higher response speed, lower power consumption and higher stability.
Therefore, according to the control circuit provided by the invention, when the input circuit needing to be disconnected is not ready to be disconnected, the response acceleration circuit accelerates the turning speed of the comparison signal, so that the two input circuits can rapidly enter the required state, the impact current of the two input ends is effectively reduced, and the stability of a system and a chip is enhanced.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (20)
1. A control circuit is used for controlling the on-off state of two input circuits so as to select one input circuit to be connected with an output end, and is characterized by comprising an acceleration response circuit,
when one path of input circuit needing to be disconnected is not disconnected, the acceleration response circuit outputs an acceleration signal so as to accelerate the disconnection of one path of input circuit needing to be disconnected;
if one of the input circuits needs to be selected to be connected to the output end, when the difference between the two input signals reaches a preset value and the other input circuit is not disconnected, the acceleration response circuit starts to work until the other input circuit is disconnected.
2. The control circuit of claim 1, further comprising a comparison circuit for comparing input signals of two input circuits to generate a comparison signal, wherein the acceleration signal accelerates the disconnection of one input circuit to be disconnected by accelerating the inversion of the comparison signal.
3. The control circuit of claim 2, further comprising a logic circuit, wherein the logic circuit generates a control signal corresponding to the two input circuits according to the comparison signal to control one of the input circuits to be turned on and the other input circuit to be turned off.
4. The control circuit of claim 2, wherein the comparison circuit comprises a comparator, and the acceleration signal is configured to increase a bias current of the comparator to reduce an output delay of the comparator to accelerate the inversion of the comparison signal.
5. The control circuit of claim 3, wherein the input signals corresponding to the two input circuits are a first input signal and a second input signal, respectively, and the acceleration response circuit receives the first input signal, the second input signal and a corresponding control signal to generate the acceleration signal.
6. The control circuit of claim 5, wherein if it is required to select the input circuit with the larger input signal to access the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value and the input circuit with the smaller input signal is still not disconnected, the speed-up response circuit starts to operate to speed up the inversion of the comparison signal until the input circuit with the smaller input signal is disconnected.
7. The control circuit of claim 6, wherein the accelerated response circuit comprises a first error circuit, a second error circuit,
when the value of a first input signal of the two input signals is larger than a first superposition value and a second input circuit corresponding to a second input signal of the two input signals is not disconnected, the first error circuit works and generates a first error signal according to the difference between the value of the first input signal and the first superposition value to serve as the acceleration signal, wherein the first superposition value is the superposition value of the second input signal and a preset value,
when the value of the second input signal is greater than a second overlap value, which is a value of the first input signal and a second predetermined value, and the first input circuit is not yet turned off, the second error circuit operates and generates a second error signal as the acceleration signal according to a difference between the value of the second input signal and the second overlap value.
8. The control circuit of claim 7,
a third switch circuit controlled by a second control signal for controlling the second input circuit, the first error signal being transmitted to the comparison circuit as the acceleration signal when the third switch circuit is turned on,
a fourth switch circuit controlled by a first control signal for controlling the first input circuit, the second error signal being transmitted to the comparison circuit as the acceleration signal when the fourth switch circuit is turned on.
9. The control circuit of claim 8,
the first error circuit includes a first transistor, a second transistor, and a third transistor, the second error circuit includes a fourth transistor, a fifth transistor, and a sixth transistor, the third switch circuit includes a first inverter and a seventh transistor,
the fourth switching circuit includes a second inverter and an eighth transistor,
a first terminal of the first transistor receives the first input signal, a second terminal of the first transistor is connected to the second transistor through the seventh transistor, a control terminal of the first transistor receives the second input signal, the second transistor and the third transistor form a first current mirror, and the second control signal is transmitted to a control terminal of the seventh transistor through the first inverter,
a first terminal of the fourth transistor receives the second input signal, a second terminal of the fourth transistor is connected to the fifth transistor through the eighth transistor, a control terminal of the fourth transistor receives the first input signal, the fifth transistor and the sixth transistor form a second current mirror, and the first control signal is transmitted to the control terminal of the eighth transistor through the second inverter,
the first transistor is turned on when the value of the first input signal is larger than the first superposition value, the seventh transistor is turned on during the period when the second control signal is active, the first current mirror outputs the first error signal when both the first transistor and the seventh transistor are turned on, the value of the threshold voltage of the first transistor is a first predetermined value,
the fourth transistor is turned on when the value of the second input signal is greater than the second superposition value, the eighth transistor is turned on during the period when the first control signal is active, the second current mirror outputs the second error signal when both the fourth transistor and the eighth transistor are turned on, and the value of the threshold voltage of the fourth transistor is a second predetermined value.
10. The control circuit of claim 7, wherein a first one of the input circuits comprises a first diode and a first switch, wherein a second one of the input circuits comprises a second diode and a second switch,
the first diode is connected with the first switch in parallel, the anode end of the first diode receives the first input signal, the cathode end of the first diode is connected with the cathode end of the second diode,
the second diode is connected in parallel with the second switch, and an anode of the second diode receives the second input signal,
and the connection end of the first diode and the second diode is used as the output end.
11. The control circuit of claim 5, wherein if it is required to select one of the input circuits with smaller input signal to access the output terminal, when the difference between the larger input signal and the smaller input signal reaches a predetermined value and the one of the input circuits with larger input signal is still not disconnected, the speed-up response circuit starts to operate to speed up the inversion of the comparison signal until the one of the input circuits with larger input signal is disconnected.
12. The control circuit of claim 10, wherein the logic circuit generates first and second control signals with the dead time information based on the comparison signal and dead times of the first and second switches,
when the first input signal is greater than the second input signal, the first control signal controls the first switch to be switched on, and the second control signal controls the second switch to be switched off,
after the second input signal is greater than the first input signal, the first control signal controls the first switch to be turned off, and the second control signal controls the second switch to be turned on.
13. A control method is used for controlling the on-off state of two input circuits to select one input circuit to be connected with an output end,
when one path of input circuit needing to be disconnected is not disconnected, an acceleration signal is generated through the acceleration response circuit to accelerate the disconnection of the path of input circuit needing to be disconnected;
if one of the input circuits needs to be selected to be connected to the output end, when the difference between the two input signals reaches a preset value and the other input circuit is not disconnected, the acceleration response circuit starts to work until the other input circuit is disconnected.
14. The control method according to claim 13, further comprising comparing the input signals of the two input circuits to generate a comparison signal, wherein the acceleration signal accelerates the disconnection of the input circuit to be disconnected by accelerating the inversion of the comparison signal.
15. The control method according to claim 14, wherein the comparison signal is used to generate a control signal corresponding to the two input circuits to control one input circuit to be turned on and the other input circuit to be turned off.
16. The control method according to claim 14, wherein an acceleration signal is generated according to the input signals of the two input circuits and the corresponding control signals to accelerate the inversion of the comparison signal.
17. The control method according to claim 16, wherein if it is required to select the input circuit with a larger input signal to access the output terminal, when a difference between the larger input signal and the smaller input signal reaches a predetermined value and the input circuit with the smaller input signal is not disconnected, the generation of the acceleration signal is started to accelerate the inversion of the comparison signal until the input circuit with the smaller input signal is disconnected, and the generation of the acceleration signal is stopped.
18. A selection circuit comprising a two-way input circuit and a control circuit as claimed in any one of claims 1 to 12.
19. A power management integrated circuit comprising the control circuit of any of claims 1 to 12.
20. A power management integrated circuit comprising the selection circuit of claim 18.
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| Application Number | Priority Date | Filing Date | Title |
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| TW107137523A TWI683538B (en) | 2018-01-22 | 2018-10-24 | Control circuit, control method, selection circuit and power management integrated circuit |
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| CN201810060074 | 2018-01-22 | ||
| CN2018100600742 | 2018-01-22 |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108388302A (en) | 2018-08-10 |
| TWI683538B (en) | 2020-01-21 |
| TW201933771A (en) | 2019-08-16 |
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